diff options
author | Steve Wise <swise@opengridcomputing.com> | 2008-07-15 02:48:45 -0400 |
---|---|---|
committer | Roland Dreier <rolandd@cisco.com> | 2008-07-15 02:48:45 -0400 |
commit | e7e55829999deaab3f43e201a087731c02c54cf9 (patch) | |
tree | 665f2ff291045af9469bbb929f99224e9707965b /drivers/infiniband/hw/cxgb3/cxio_hal.c | |
parent | 00f7ec36c9324928e4cd23f02e6d8550f30c32ca (diff) |
RDMA/cxgb3: MEM_MGT_EXTENSIONS support
- set IB_DEVICE_MEM_MGT_EXTENSIONS capability bit if fw supports it.
- set max_fast_reg_page_list_len device attribute.
- add iwch_alloc_fast_reg_mr function.
- add iwch_alloc_fastreg_pbl
- add iwch_free_fastreg_pbl
- adjust the WQ depth for kernel mode work queues to account for
fastreg possibly taking 2 WR slots.
- add fastreg_mr work request support.
- add local_inv work request support.
- add send_with_inv and send_with_se_inv work request support.
- removed useless duplicate enums/defines for TPT/MW/MR stuff.
Signed-off-by: Steve Wise <swise@opengridcomputing.com>
Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'drivers/infiniband/hw/cxgb3/cxio_hal.c')
-rw-r--r-- | drivers/infiniband/hw/cxgb3/cxio_hal.c | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/drivers/infiniband/hw/cxgb3/cxio_hal.c b/drivers/infiniband/hw/cxgb3/cxio_hal.c index 3f441fc57c17..340e4181c761 100644 --- a/drivers/infiniband/hw/cxgb3/cxio_hal.c +++ b/drivers/infiniband/hw/cxgb3/cxio_hal.c | |||
@@ -145,7 +145,9 @@ static int cxio_hal_clear_qp_ctx(struct cxio_rdev *rdev_p, u32 qpid) | |||
145 | } | 145 | } |
146 | wqe = (struct t3_modify_qp_wr *) skb_put(skb, sizeof(*wqe)); | 146 | wqe = (struct t3_modify_qp_wr *) skb_put(skb, sizeof(*wqe)); |
147 | memset(wqe, 0, sizeof(*wqe)); | 147 | memset(wqe, 0, sizeof(*wqe)); |
148 | build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD, 3, 0, qpid, 7); | 148 | build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD, |
149 | T3_COMPLETION_FLAG | T3_NOTIFY_FLAG, 0, qpid, 7, | ||
150 | T3_SOPEOP); | ||
149 | wqe->flags = cpu_to_be32(MODQP_WRITE_EC); | 151 | wqe->flags = cpu_to_be32(MODQP_WRITE_EC); |
150 | sge_cmd = qpid << 8 | 3; | 152 | sge_cmd = qpid << 8 | 3; |
151 | wqe->sge_cmd = cpu_to_be64(sge_cmd); | 153 | wqe->sge_cmd = cpu_to_be64(sge_cmd); |
@@ -558,7 +560,7 @@ static int cxio_hal_init_ctrl_qp(struct cxio_rdev *rdev_p) | |||
558 | wqe = (struct t3_modify_qp_wr *) skb_put(skb, sizeof(*wqe)); | 560 | wqe = (struct t3_modify_qp_wr *) skb_put(skb, sizeof(*wqe)); |
559 | memset(wqe, 0, sizeof(*wqe)); | 561 | memset(wqe, 0, sizeof(*wqe)); |
560 | build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD, 0, 0, | 562 | build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_QP_MOD, 0, 0, |
561 | T3_CTL_QP_TID, 7); | 563 | T3_CTL_QP_TID, 7, T3_SOPEOP); |
562 | wqe->flags = cpu_to_be32(MODQP_WRITE_EC); | 564 | wqe->flags = cpu_to_be32(MODQP_WRITE_EC); |
563 | sge_cmd = (3ULL << 56) | FW_RI_SGEEC_START << 8 | 3; | 565 | sge_cmd = (3ULL << 56) | FW_RI_SGEEC_START << 8 | 3; |
564 | wqe->sge_cmd = cpu_to_be64(sge_cmd); | 566 | wqe->sge_cmd = cpu_to_be64(sge_cmd); |
@@ -674,7 +676,7 @@ static int cxio_hal_ctrl_qp_write_mem(struct cxio_rdev *rdev_p, u32 addr, | |||
674 | build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_BP, flag, | 676 | build_fw_riwrh((struct fw_riwrh *) wqe, T3_WR_BP, flag, |
675 | Q_GENBIT(rdev_p->ctrl_qp.wptr, | 677 | Q_GENBIT(rdev_p->ctrl_qp.wptr, |
676 | T3_CTRL_QP_SIZE_LOG2), T3_CTRL_QP_ID, | 678 | T3_CTRL_QP_SIZE_LOG2), T3_CTRL_QP_ID, |
677 | wr_len); | 679 | wr_len, T3_SOPEOP); |
678 | if (flag == T3_COMPLETION_FLAG) | 680 | if (flag == T3_COMPLETION_FLAG) |
679 | ring_doorbell(rdev_p->ctrl_qp.doorbell, T3_CTRL_QP_ID); | 681 | ring_doorbell(rdev_p->ctrl_qp.doorbell, T3_CTRL_QP_ID); |
680 | len -= 96; | 682 | len -= 96; |
@@ -816,6 +818,13 @@ int cxio_deallocate_window(struct cxio_rdev *rdev_p, u32 stag) | |||
816 | 0, 0); | 818 | 0, 0); |
817 | } | 819 | } |
818 | 820 | ||
821 | int cxio_allocate_stag(struct cxio_rdev *rdev_p, u32 *stag, u32 pdid, u32 pbl_size, u32 pbl_addr) | ||
822 | { | ||
823 | *stag = T3_STAG_UNSET; | ||
824 | return __cxio_tpt_op(rdev_p, 0, stag, 0, pdid, TPT_NON_SHARED_MR, | ||
825 | 0, 0, 0ULL, 0, 0, pbl_size, pbl_addr); | ||
826 | } | ||
827 | |||
819 | int cxio_rdma_init(struct cxio_rdev *rdev_p, struct t3_rdma_init_attr *attr) | 828 | int cxio_rdma_init(struct cxio_rdev *rdev_p, struct t3_rdma_init_attr *attr) |
820 | { | 829 | { |
821 | struct t3_rdma_init_wr *wqe; | 830 | struct t3_rdma_init_wr *wqe; |