diff options
author | Steve Wise <swise@opengridcomputing.com> | 2008-05-02 12:17:41 -0400 |
---|---|---|
committer | Roland Dreier <rolandd@cisco.com> | 2008-05-02 13:56:57 -0400 |
commit | c8286944b802c5ce4063ec3c334b38c6757a9434 (patch) | |
tree | f1cbf7c3baa83cc2e4e92ad43cf5083cd956ad32 /drivers/infiniband/hw/cxgb3/cxio_hal.c | |
parent | 57ce41d1d18279cc90223f3deadca70c7de1cfca (diff) |
RDMA/cxgb3: QP flush fixes
- Flush the QP only after the HW disables the connection. Currently
we flush the QP when transitioning to CLOSING. This exposes a race
condition where the HW can complete a RECV WR, for instance, -and-
the SW can flush that same WR.
- Only call CQ event handlers on flush IFF we actually flushed something.
Signed-off-by: Steve Wise <swise@opengridcomputing.com>
Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'drivers/infiniband/hw/cxgb3/cxio_hal.c')
-rw-r--r-- | drivers/infiniband/hw/cxgb3/cxio_hal.c | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/drivers/infiniband/hw/cxgb3/cxio_hal.c b/drivers/infiniband/hw/cxgb3/cxio_hal.c index ed2ee4ba4b7c..5fd8506a8657 100644 --- a/drivers/infiniband/hw/cxgb3/cxio_hal.c +++ b/drivers/infiniband/hw/cxgb3/cxio_hal.c | |||
@@ -359,9 +359,10 @@ static void insert_recv_cqe(struct t3_wq *wq, struct t3_cq *cq) | |||
359 | cq->sw_wptr++; | 359 | cq->sw_wptr++; |
360 | } | 360 | } |
361 | 361 | ||
362 | void cxio_flush_rq(struct t3_wq *wq, struct t3_cq *cq, int count) | 362 | int cxio_flush_rq(struct t3_wq *wq, struct t3_cq *cq, int count) |
363 | { | 363 | { |
364 | u32 ptr; | 364 | u32 ptr; |
365 | int flushed = 0; | ||
365 | 366 | ||
366 | PDBG("%s wq %p cq %p\n", __func__, wq, cq); | 367 | PDBG("%s wq %p cq %p\n", __func__, wq, cq); |
367 | 368 | ||
@@ -369,8 +370,11 @@ void cxio_flush_rq(struct t3_wq *wq, struct t3_cq *cq, int count) | |||
369 | PDBG("%s rq_rptr %u rq_wptr %u skip count %u\n", __func__, | 370 | PDBG("%s rq_rptr %u rq_wptr %u skip count %u\n", __func__, |
370 | wq->rq_rptr, wq->rq_wptr, count); | 371 | wq->rq_rptr, wq->rq_wptr, count); |
371 | ptr = wq->rq_rptr + count; | 372 | ptr = wq->rq_rptr + count; |
372 | while (ptr++ != wq->rq_wptr) | 373 | while (ptr++ != wq->rq_wptr) { |
373 | insert_recv_cqe(wq, cq); | 374 | insert_recv_cqe(wq, cq); |
375 | flushed++; | ||
376 | } | ||
377 | return flushed; | ||
374 | } | 378 | } |
375 | 379 | ||
376 | static void insert_sq_cqe(struct t3_wq *wq, struct t3_cq *cq, | 380 | static void insert_sq_cqe(struct t3_wq *wq, struct t3_cq *cq, |
@@ -394,9 +398,10 @@ static void insert_sq_cqe(struct t3_wq *wq, struct t3_cq *cq, | |||
394 | cq->sw_wptr++; | 398 | cq->sw_wptr++; |
395 | } | 399 | } |
396 | 400 | ||
397 | void cxio_flush_sq(struct t3_wq *wq, struct t3_cq *cq, int count) | 401 | int cxio_flush_sq(struct t3_wq *wq, struct t3_cq *cq, int count) |
398 | { | 402 | { |
399 | __u32 ptr; | 403 | __u32 ptr; |
404 | int flushed = 0; | ||
400 | struct t3_swsq *sqp = wq->sq + Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2); | 405 | struct t3_swsq *sqp = wq->sq + Q_PTR2IDX(wq->sq_rptr, wq->sq_size_log2); |
401 | 406 | ||
402 | ptr = wq->sq_rptr + count; | 407 | ptr = wq->sq_rptr + count; |
@@ -405,7 +410,9 @@ void cxio_flush_sq(struct t3_wq *wq, struct t3_cq *cq, int count) | |||
405 | insert_sq_cqe(wq, cq, sqp); | 410 | insert_sq_cqe(wq, cq, sqp); |
406 | sqp++; | 411 | sqp++; |
407 | ptr++; | 412 | ptr++; |
413 | flushed++; | ||
408 | } | 414 | } |
415 | return flushed; | ||
409 | } | 416 | } |
410 | 417 | ||
411 | /* | 418 | /* |