diff options
author | Abhilash Kesavan <a.kesavan@samsung.com> | 2014-11-01 00:00:43 -0400 |
---|---|---|
committer | Jonathan Cameron <jic23@kernel.org> | 2014-11-05 10:38:25 -0500 |
commit | c1b501564c98a94b48f4ed936737403108dc7300 (patch) | |
tree | f099f3c59337f23e1012954e5187b00d86d35a84 /drivers/iio/adc/exynos_adc.c | |
parent | db9bf4d6577f23b9a9ee4f70c07a51946ed111a7 (diff) |
iio: adc: exynos_adc: Add support for exynos7
The ADC on exynos7 is quite similar to ADCv2. The differences are as
follows:
- exynos7-adc has 8 input channels (as against 10 in ADCv2).
- exynos7 does not include an ADC PHY control register.
- Some ADC_CON2 register bits being used in ADCv2 are listed as
reserved in exynos7-adc. This results in a different init_hw
function for exynos7.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Diffstat (limited to 'drivers/iio/adc/exynos_adc.c')
-rw-r--r-- | drivers/iio/adc/exynos_adc.c | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c index fe0317745436..3a2dbb3b4926 100644 --- a/drivers/iio/adc/exynos_adc.c +++ b/drivers/iio/adc/exynos_adc.c | |||
@@ -390,6 +390,35 @@ static const struct exynos_adc_data exynos3250_adc_data = { | |||
390 | .start_conv = exynos_adc_v2_start_conv, | 390 | .start_conv = exynos_adc_v2_start_conv, |
391 | }; | 391 | }; |
392 | 392 | ||
393 | static void exynos_adc_exynos7_init_hw(struct exynos_adc *info) | ||
394 | { | ||
395 | u32 con1, con2; | ||
396 | |||
397 | if (info->data->needs_adc_phy) | ||
398 | regmap_write(info->pmu_map, info->data->phy_offset, 1); | ||
399 | |||
400 | con1 = ADC_V2_CON1_SOFT_RESET; | ||
401 | writel(con1, ADC_V2_CON1(info->regs)); | ||
402 | |||
403 | con2 = readl(ADC_V2_CON2(info->regs)); | ||
404 | con2 &= ~ADC_V2_CON2_C_TIME(7); | ||
405 | con2 |= ADC_V2_CON2_C_TIME(0); | ||
406 | writel(con2, ADC_V2_CON2(info->regs)); | ||
407 | |||
408 | /* Enable interrupts */ | ||
409 | writel(1, ADC_V2_INT_EN(info->regs)); | ||
410 | } | ||
411 | |||
412 | static const struct exynos_adc_data exynos7_adc_data = { | ||
413 | .num_channels = MAX_ADC_V1_CHANNELS, | ||
414 | .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ | ||
415 | |||
416 | .init_hw = exynos_adc_exynos7_init_hw, | ||
417 | .exit_hw = exynos_adc_v2_exit_hw, | ||
418 | .clear_irq = exynos_adc_v2_clear_irq, | ||
419 | .start_conv = exynos_adc_v2_start_conv, | ||
420 | }; | ||
421 | |||
393 | static const struct of_device_id exynos_adc_match[] = { | 422 | static const struct of_device_id exynos_adc_match[] = { |
394 | { | 423 | { |
395 | .compatible = "samsung,s3c2410-adc", | 424 | .compatible = "samsung,s3c2410-adc", |
@@ -415,6 +444,9 @@ static const struct of_device_id exynos_adc_match[] = { | |||
415 | }, { | 444 | }, { |
416 | .compatible = "samsung,exynos3250-adc", | 445 | .compatible = "samsung,exynos3250-adc", |
417 | .data = &exynos3250_adc_data, | 446 | .data = &exynos3250_adc_data, |
447 | }, { | ||
448 | .compatible = "samsung,exynos7-adc", | ||
449 | .data = &exynos7_adc_data, | ||
418 | }, | 450 | }, |
419 | {}, | 451 | {}, |
420 | }; | 452 | }; |