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authorStefan Richter <stefanr@s5r6.in-berlin.de>2006-03-28 19:57:34 -0500
committerJody McIntyre <scjody@modernduck.com>2006-03-28 19:57:34 -0500
commit180a43044faeaa9bfe0c604d472023a6446430b5 (patch)
tree81025e588cd49c5b69501773e58afbf31ba8b176 /drivers/ieee1394/ohci1394.c
parentc1d08eb6cd06c225d825c8981e05729389fd51a9 (diff)
ohci1394: clean up asynchronous and physical request filters programming
Various cleanups of how ohci1394 programs AsynchronousRequestFilter, PhysicalRequestFilter, and physUpperBoundOffset. In particular, do not rewrite registers within the bus reset interrupt handler if bus resets do not affect the registers in the first place. Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de> Signed-off-by: Jody McIntyre <scjody@modernduck.com>
Diffstat (limited to 'drivers/ieee1394/ohci1394.c')
-rw-r--r--drivers/ieee1394/ohci1394.c37
1 files changed, 19 insertions, 18 deletions
diff --git a/drivers/ieee1394/ohci1394.c b/drivers/ieee1394/ohci1394.c
index eb329a875099..24d045c353e5 100644
--- a/drivers/ieee1394/ohci1394.c
+++ b/drivers/ieee1394/ohci1394.c
@@ -544,12 +544,19 @@ static void ohci_initialize(struct ti_ohci *ohci)
544 /* Initialize IR Legacy DMA channel mask */ 544 /* Initialize IR Legacy DMA channel mask */
545 ohci->ir_legacy_channels = 0; 545 ohci->ir_legacy_channels = 0;
546 546
547 /* 547 /* Accept AR requests from all nodes */
548 * Accept AT requests from all nodes. This probably 548 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
549 * will have to be controlled from the subsystem 549
550 * on a per node basis. 550 /* Set the address range of the physical response unit.
551 */ 551 * Most controllers do not implement it as a writable register though.
552 reg_write(ohci,OHCI1394_AsReqFilterHiSet, 0x80000000); 552 * They will keep a hardwired offset of 0x00010000 and show 0x0 as
553 * register content.
554 * To actually enable physical responses is the job of our interrupt
555 * handler which programs the physical request filter. */
556 reg_write(ohci, OHCI1394_PhyUpperBound, 0xffff0000);
557
558 DBGMSG("physUpperBoundOffset=%08x",
559 reg_read(ohci, OHCI1394_PhyUpperBound));
553 560
554 /* Specify AT retries */ 561 /* Specify AT retries */
555 reg_write(ohci, OHCI1394_ATRetries, 562 reg_write(ohci, OHCI1394_ATRetries,
@@ -2516,26 +2523,20 @@ static irqreturn_t ohci_irq_handler(int irq, void *dev_id,
2516 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset); 2523 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
2517 spin_unlock_irqrestore(&ohci->event_lock, flags); 2524 spin_unlock_irqrestore(&ohci->event_lock, flags);
2518 2525
2519 /* Accept Physical requests from all nodes. */
2520 reg_write(ohci,OHCI1394_AsReqFilterHiSet, 0xffffffff);
2521 reg_write(ohci,OHCI1394_AsReqFilterLoSet, 0xffffffff);
2522
2523 /* Turn on phys dma reception. 2526 /* Turn on phys dma reception.
2524 * 2527 *
2525 * TODO: Enable some sort of filtering management. 2528 * TODO: Enable some sort of filtering management.
2526 */ 2529 */
2527 if (phys_dma) { 2530 if (phys_dma) {
2528 reg_write(ohci,OHCI1394_PhyReqFilterHiSet, 0xffffffff); 2531 reg_write(ohci, OHCI1394_PhyReqFilterHiSet,
2529 reg_write(ohci,OHCI1394_PhyReqFilterLoSet, 0xffffffff); 2532 0xffffffff);
2530 reg_write(ohci,OHCI1394_PhyUpperBound, 0xffff0000); 2533 reg_write(ohci, OHCI1394_PhyReqFilterLoSet,
2531 } else { 2534 0xffffffff);
2532 reg_write(ohci,OHCI1394_PhyReqFilterHiSet, 0x00000000);
2533 reg_write(ohci,OHCI1394_PhyReqFilterLoSet, 0x00000000);
2534 } 2535 }
2535 2536
2536 DBGMSG("PhyReqFilter=%08x%08x", 2537 DBGMSG("PhyReqFilter=%08x%08x",
2537 reg_read(ohci,OHCI1394_PhyReqFilterHiSet), 2538 reg_read(ohci, OHCI1394_PhyReqFilterHiSet),
2538 reg_read(ohci,OHCI1394_PhyReqFilterLoSet)); 2539 reg_read(ohci, OHCI1394_PhyReqFilterLoSet));
2539 2540
2540 hpsb_selfid_complete(host, phyid, isroot); 2541 hpsb_selfid_complete(host, phyid, isroot);
2541 } else 2542 } else