Merge v2.6.37-rc8 into powerpc/next

1 files changed, 70 insertions, 89 deletions

diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
index 03d202b1ff27..c131d58bcb50 100755..100644
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@ -59,33 +59,24 @@
 #include <linux/hrtimer.h>      /* ktime_get_real() */
 #include <trace/events/power.h>
 #include <linux/sched.h>
+#include <asm/mwait.h>
 
 #define INTEL_IDLE_VERSION "0.4"
 #define PREFIX "intel_idle: "
 
-#define MWAIT_SUBSTATE_MASK     (0xf)
-#define MWAIT_CSTATE_MASK       (0xf)
-#define MWAIT_SUBSTATE_SIZE     (4)
-#define MWAIT_MAX_NUM_CSTATES   8
-#define CPUID_MWAIT_LEAF (5)
-#define CPUID5_ECX_EXTENSIONS_SUPPORTED (0x1)
-#define CPUID5_ECX_INTERRUPT_BREAK      (0x2)
-
 static struct cpuidle_driver intel_idle_driver = {
         .name = "intel_idle",
         .owner = THIS_MODULE,
 };
 /* intel_idle.max_cstate=0 disables driver */
 static int max_cstate = MWAIT_MAX_NUM_CSTATES - 1;
-static int power_policy = 7; /* 0 = max perf; 15 = max powersave */
 
-static unsigned int substates;
-static int (*choose_substate)(int);
+static unsigned int mwait_substates;
 
 /* Reliable LAPIC Timer States, bit 1 for C1 etc.  */
-static unsigned int lapic_timer_reliable_states;
+static unsigned int lapic_timer_reliable_states = (1 << 1);      /* Default to only C1 */
 
-static struct cpuidle_device *intel_idle_cpuidle_devices;
+static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
 static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state);
 
 static struct cpuidle_state *cpuidle_state_table;
@@ -103,29 +94,62 @@ static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = {
                 .driver_data = (void *) 0x00,
                 .flags = CPUIDLE_FLAG_TIME_VALID,
                 .exit_latency = 3,
-                .power_usage = 1000,
                 .target_residency = 6,
                 .enter = &intel_idle },
         { /* MWAIT C2 */
                 .name = "NHM-C3",
                 .desc = "MWAIT 0x10",
                 .driver_data = (void *) 0x10,
-                .flags = CPUIDLE_FLAG_TIME_VALID,
+                .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
                 .exit_latency = 20,
-                .power_usage = 500,
                 .target_residency = 80,
                 .enter = &intel_idle },
         { /* MWAIT C3 */
                 .name = "NHM-C6",
                 .desc = "MWAIT 0x20",
                 .driver_data = (void *) 0x20,
-                .flags = CPUIDLE_FLAG_TIME_VALID,
+                .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
                 .exit_latency = 200,
-                .power_usage = 350,
                 .target_residency = 800,
                 .enter = &intel_idle },
 };
 
+static struct cpuidle_state snb_cstates[MWAIT_MAX_NUM_CSTATES] = {
+        { /* MWAIT C0 */ },
+        { /* MWAIT C1 */
+                .name = "SNB-C1",
+                .desc = "MWAIT 0x00",
+                .driver_data = (void *) 0x00,
+                .flags = CPUIDLE_FLAG_TIME_VALID,
+                .exit_latency = 1,
+                .target_residency = 4,
+                .enter = &intel_idle },
+        { /* MWAIT C2 */
+                .name = "SNB-C3",
+                .desc = "MWAIT 0x10",
+                .driver_data = (void *) 0x10,
+                .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
+                .exit_latency = 80,
+                .target_residency = 160,
+                .enter = &intel_idle },
+        { /* MWAIT C3 */
+                .name = "SNB-C6",
+                .desc = "MWAIT 0x20",
+                .driver_data = (void *) 0x20,
+                .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
+                .exit_latency = 104,
+                .target_residency = 208,
+                .enter = &intel_idle },
+        { /* MWAIT C4 */
+                .name = "SNB-C7",
+                .desc = "MWAIT 0x30",
+                .driver_data = (void *) 0x30,
+                .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
+                .exit_latency = 109,
+                .target_residency = 300,
+                .enter = &intel_idle },
+};
+
 static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
         { /* MWAIT C0 */ },
         { /* MWAIT C1 */
@@ -134,7 +158,6 @@ static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
                 .driver_data = (void *) 0x00,
                 .flags = CPUIDLE_FLAG_TIME_VALID,
                 .exit_latency = 1,
-                .power_usage = 1000,
                 .target_residency = 4,
                 .enter = &intel_idle },
         { /* MWAIT C2 */
@@ -143,7 +166,6 @@ static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
                 .driver_data = (void *) 0x10,
                 .flags = CPUIDLE_FLAG_TIME_VALID,
                 .exit_latency = 20,
-                .power_usage = 500,
                 .target_residency = 80,
                 .enter = &intel_idle },
         { /* MWAIT C3 */ },
@@ -151,58 +173,21 @@ static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
                 .name = "ATM-C4",
                 .desc = "MWAIT 0x30",
                 .driver_data = (void *) 0x30,
-                .flags = CPUIDLE_FLAG_TIME_VALID,
+                .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
                 .exit_latency = 100,
-                .power_usage = 250,
                 .target_residency = 400,
                 .enter = &intel_idle },
         { /* MWAIT C5 */ },
         { /* MWAIT C6 */
                 .name = "ATM-C6",
-                .desc = "MWAIT 0x40",
-                .driver_data = (void *) 0x40,
-                .flags = CPUIDLE_FLAG_TIME_VALID,
-                .exit_latency = 200,
-                .power_usage = 150,
-                .target_residency = 800,
-                .enter = NULL },        /* disabled */
+                .desc = "MWAIT 0x52",
+                .driver_data = (void *) 0x52,
+                .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
+                .exit_latency = 140,
+                .target_residency = 560,
+                .enter = &intel_idle },
 };
 
-/*
- * choose_tunable_substate()
- *
- * Run-time decision on which C-state substate to invoke
- * If power_policy = 0, choose shallowest substate (0)
- * If power_policy = 15, choose deepest substate
- * If power_policy = middle, choose middle substate etc.
- */
-static int choose_tunable_substate(int cstate)
-{
-        unsigned int num_substates;
-        unsigned int substate_choice;
-
-        power_policy &= 0xF;    /* valid range: 0-15 */
-        cstate &= 7;    /* valid range: 0-7 */
-
-        num_substates = (substates >> ((cstate) * 4)) & MWAIT_SUBSTATE_MASK;
-
-        if (num_substates <= 1)
-                return 0;
-
-        substate_choice = ((power_policy + (power_policy + 1) *
-                                (num_substates - 1)) / 16);
-
-        return substate_choice;
-}
-
-/*
- * choose_zero_substate()
- */
-static int choose_zero_substate(int cstate)
-{
-        return 0;
-}
-
 /**
  * intel_idle
  * @dev: cpuidle_device
@@ -220,10 +205,15 @@ static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state)
 
         cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
 
-        eax = eax + (choose_substate)(cstate);
-
         local_irq_disable();
 
+        /*
+         * leave_mm() to avoid costly and often unnecessary wakeups
+         * for flushing the user TLB's associated with the active mm.
+         */
+        if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
+                leave_mm(cpu);
+
         if (!(lapic_timer_reliable_states & (1 << (cstate))))
                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
 
@@ -259,7 +249,7 @@ static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state)
  */
 static int intel_idle_probe(void)
 {
-        unsigned int eax, ebx, ecx, edx;
+        unsigned int eax, ebx, ecx;
 
         if (max_cstate == 0) {
                 pr_debug(PREFIX "disabled\n");
@@ -275,20 +265,14 @@ static int intel_idle_probe(void)
         if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
                 return -ENODEV;
 
-        cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx);
+        cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
 
         if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
                 !(ecx & CPUID5_ECX_INTERRUPT_BREAK))
                         return -ENODEV;
-#ifdef DEBUG
-        if (substates == 0)     /* can over-ride via modparam */
-#endif
-                substates = edx;
 
-        pr_debug(PREFIX "MWAIT substates: 0x%x\n", substates);
+        pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);
 
-        if (boot_cpu_has(X86_FEATURE_ARAT))     /* Always Reliable APIC Timer */
-                lapic_timer_reliable_states = 0xFFFFFFFF;
 
         if (boot_cpu_data.x86 != 6)     /* family 6 */
                 return -ENODEV;
@@ -299,23 +283,21 @@ static int intel_idle_probe(void)
         case 0x1E:      /* Core i7 and i5 Processor - Lynnfield Jasper Forest */
         case 0x1F:      /* Core i7 and i5 Processor - Nehalem */
         case 0x2E:      /* Nehalem-EX Xeon */
-                lapic_timer_reliable_states = (1 << 1);  /* C1 */
-
+        case 0x2F:      /* Westmere-EX Xeon */
         case 0x25:      /* Westmere */
         case 0x2C:      /* Westmere */
                 cpuidle_state_table = nehalem_cstates;
-                choose_substate = choose_tunable_substate;
                 break;
 
         case 0x1C:      /* 28 - Atom Processor */
-                lapic_timer_reliable_states = (1 << 2) | (1 << 1); /* C2, C1 */
+        case 0x26:      /* 38 - Lincroft Atom Processor */
                 cpuidle_state_table = atom_cstates;
-                choose_substate = choose_zero_substate;
                 break;
-#ifdef FUTURE_USE
-        case 0x17:      /* 23 - Core 2 Duo */
-                lapic_timer_reliable_states = (1 << 2) | (1 << 1); /* C2, C1 */
-#endif
+
+        case 0x2A:      /* SNB */
+        case 0x2D:      /* SNB Xeon */
+                cpuidle_state_table = snb_cstates;
+                break;
 
         default:
                 pr_debug(PREFIX "does not run on family %d model %d\n",
@@ -323,6 +305,9 @@ static int intel_idle_probe(void)
                 return -ENODEV;
         }
 
+        if (boot_cpu_has(X86_FEATURE_ARAT))     /* Always Reliable APIC Timer */
+                lapic_timer_reliable_states = 0xFFFFFFFF;
+
         pr_debug(PREFIX "v" INTEL_IDLE_VERSION
                 " model 0x%X\n", boot_cpu_data.x86_model);
 
@@ -376,7 +361,7 @@ static int intel_idle_cpuidle_devices_init(void)
                         }
 
                         /* does the state exist in CPUID.MWAIT? */
-                        num_substates = (substates >> ((cstate) * 4))
+                        num_substates = (mwait_substates >> ((cstate) * 4))
                                                 & MWAIT_SUBSTATE_MASK;
                         if (num_substates == 0)
                                 continue;
@@ -450,11 +435,7 @@ static void __exit intel_idle_exit(void)
 module_init(intel_idle_init);
 module_exit(intel_idle_exit);
 
-module_param(power_policy, int, 0644);
 module_param(max_cstate, int, 0444);
-#ifdef DEBUG
-module_param(substates, int, 0444);
-#endif
 
 MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
 MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);