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authorSergei Shtylyov <sshtylyov@ru.mvista.com>2007-06-08 09:14:32 -0400
committerBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2007-06-08 09:14:32 -0400
commit278978e953a35a2ddf27f197003b29da54e31908 (patch)
treed9868d4ca528da6aa903a616c9b15b4fbe6d5e49 /drivers/ide
parentea30759643b423933ced48acdd78e5299f05295b (diff)
hpt366: disallow Ultra133 for HPT374
Eliminate UltraATA/133 support for HPT374 -- the chip isn't capable of this mode according to the manual, and doesn't even seem to tolerate 66 MHz DPLL clock... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Cc: Geller Sandor <wildy@petra.hos.u-szeged.hu> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Diffstat (limited to 'drivers/ide')
-rw-r--r--drivers/ide/pci/hpt366.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/ide/pci/hpt366.c b/drivers/ide/pci/hpt366.c
index fcbc5605b38e..ce8a5449a574 100644
--- a/drivers/ide/pci/hpt366.c
+++ b/drivers/ide/pci/hpt366.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/drivers/ide/pci/hpt366.c Version 1.03 May 4, 2007 2 * linux/drivers/ide/pci/hpt366.c Version 1.04 Jun 4, 2007
3 * 3 *
4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> 4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
5 * Portions Copyright (C) 2001 Sun Microsystems, Inc. 5 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
@@ -106,7 +106,8 @@
106 * switch to calculating PCI clock frequency based on the chip's base DPLL 106 * switch to calculating PCI clock frequency based on the chip's base DPLL
107 * frequency 107 * frequency
108 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on 108 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
109 * anything newer than HPT370/A 109 * anything newer than HPT370/A (except HPT374 that is not capable of this
110 * mode according to the manual)
110 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(), 111 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
111 * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips; 112 * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
112 * unify HPT36x/37x timing setup code and the speedproc handlers by joining 113 * unify HPT36x/37x timing setup code and the speedproc handlers by joining
@@ -365,7 +366,6 @@ static u32 sixty_six_base_hpt37x[] = {
365}; 366};
366 367
367#define HPT366_DEBUG_DRIVE_INFO 0 368#define HPT366_DEBUG_DRIVE_INFO 0
368#define HPT374_ALLOW_ATA133_6 1
369#define HPT371_ALLOW_ATA133_6 1 369#define HPT371_ALLOW_ATA133_6 1
370#define HPT302_ALLOW_ATA133_6 1 370#define HPT302_ALLOW_ATA133_6 1
371#define HPT372_ALLOW_ATA133_6 1 371#define HPT372_ALLOW_ATA133_6 1
@@ -450,7 +450,7 @@ static struct hpt_info hpt370a __devinitdata = {
450 450
451static struct hpt_info hpt374 __devinitdata = { 451static struct hpt_info hpt374 __devinitdata = {
452 .chip_type = HPT374, 452 .chip_type = HPT374,
453 .max_mode = HPT374_ALLOW_ATA133_6 ? 4 : 3, 453 .max_mode = 3,
454 .dpll_clk = 48, 454 .dpll_clk = 48,
455 .settings = hpt37x_settings 455 .settings = hpt37x_settings
456}; 456};