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authorBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2010-01-18 02:21:19 -0500
committerDavid S. Miller <davem@davemloft.net>2010-01-19 04:52:31 -0500
commita345c7856e52bf8b21a5ae6a24fb824bfedefbe9 (patch)
treeb4e2b8a570a03ca320763c07f2512972b98fc876 /drivers/ide
parent5740345b877e2c8745cdf454674b45919679f231 (diff)
alim15x3: fix handling of DMA timings
Stop depending on the BIOS setup. Based on libata pata_ali host driver. Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/ide')
-rw-r--r--drivers/ide/alim15x3.c55
1 files changed, 39 insertions, 16 deletions
diff --git a/drivers/ide/alim15x3.c b/drivers/ide/alim15x3.c
index 529f8e2218ac..3ba7d0bdd25d 100644
--- a/drivers/ide/alim15x3.c
+++ b/drivers/ide/alim15x3.c
@@ -61,6 +61,25 @@ static void ali_fifo_control(ide_hwif_t *hwif, ide_drive_t *drive, int on)
61 pci_write_config_byte(pdev, pio_fifo, fifo); 61 pci_write_config_byte(pdev, pio_fifo, fifo);
62} 62}
63 63
64static void ali_program_timings(ide_hwif_t *hwif, ide_drive_t *drive,
65 struct ide_timing *t)
66{
67 struct pci_dev *dev = to_pci_dev(hwif->dev);
68 int port = hwif->channel ? 0x5c : 0x58;
69 u8 unit = drive->dn & 1;
70
71 t->setup = clamp_val(t->setup, 1, 8) & 7;
72 t->act8b = clamp_val(t->act8b, 1, 8) & 7;
73 t->rec8b = clamp_val(t->rec8b, 1, 16) & 15;
74 t->active = clamp_val(t->active, 1, 8) & 7;
75 t->recover = clamp_val(t->recover, 1, 16) & 15;
76
77 pci_write_config_byte(dev, port, t->setup);
78 pci_write_config_byte(dev, port + 1, (t->act8b << 4) | t->rec8b);
79 pci_write_config_byte(dev, port + unit + 2,
80 (t->active << 4) | t->recover);
81}
82
64/** 83/**
65 * ali_set_pio_mode - set host controller for PIO mode 84 * ali_set_pio_mode - set host controller for PIO mode
66 * @hwif: port 85 * @hwif: port
@@ -71,12 +90,9 @@ static void ali_fifo_control(ide_hwif_t *hwif, ide_drive_t *drive, int on)
71 90
72static void ali_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) 91static void ali_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
73{ 92{
74 struct pci_dev *dev = to_pci_dev(hwif->dev);
75 ide_drive_t *pair = ide_get_pair_dev(drive); 93 ide_drive_t *pair = ide_get_pair_dev(drive);
76 int bus_speed = ide_pci_clk ? ide_pci_clk : 33; 94 int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
77 unsigned long T = 1000000 / bus_speed; /* PCI clock based */ 95 unsigned long T = 1000000 / bus_speed; /* PCI clock based */
78 int port = hwif->channel ? 0x5c : 0x58;
79 u8 unit = drive->dn & 1;
80 struct ide_timing t; 96 struct ide_timing t;
81 97
82 ide_timing_compute(drive, drive->pio_mode, &t, T, 1); 98 ide_timing_compute(drive, drive->pio_mode, &t, T, 1);
@@ -93,21 +109,12 @@ static void ali_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
93 } 109 }
94 } 110 }
95 111
96 t.setup = clamp_val(t.setup, 1, 8) & 7;
97 t.act8b = clamp_val(t.act8b, 1, 8) & 7;
98 t.rec8b = clamp_val(t.rec8b, 1, 16) & 15;
99 t.active = clamp_val(t.active, 1, 8) & 7;
100 t.recover = clamp_val(t.recover, 1, 16) & 15;
101
102 /* 112 /*
103 * PIO mode => ATA FIFO on, ATAPI FIFO off 113 * PIO mode => ATA FIFO on, ATAPI FIFO off
104 */ 114 */
105 ali_fifo_control(hwif, drive, (drive->media == ide_disk) ? 0x05 : 0x00); 115 ali_fifo_control(hwif, drive, (drive->media == ide_disk) ? 0x05 : 0x00);
106 116
107 pci_write_config_byte(dev, port, t.setup); 117 ali_program_timings(hwif, drive, &t);
108 pci_write_config_byte(dev, port + 1, (t.act8b << 4) | t.rec8b);
109 pci_write_config_byte(dev, port + unit + 2,
110 (t.active << 4) | t.recover);
111} 118}
112 119
113/** 120/**
@@ -146,11 +153,15 @@ static u8 ali_udma_filter(ide_drive_t *drive)
146static void ali_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) 153static void ali_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
147{ 154{
148 struct pci_dev *dev = to_pci_dev(hwif->dev); 155 struct pci_dev *dev = to_pci_dev(hwif->dev);
156 ide_drive_t *pair = ide_get_pair_dev(drive);
157 int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
158 unsigned long T = 1000000 / bus_speed; /* PCI clock based */
149 const u8 speed = drive->dma_mode; 159 const u8 speed = drive->dma_mode;
150 u8 speed1 = speed; 160 u8 speed1 = speed;
151 u8 unit = drive->dn & 1; 161 u8 unit = drive->dn & 1;
152 u8 tmpbyte = 0x00; 162 u8 tmpbyte = 0x00;
153 int m5229_udma = (hwif->channel) ? 0x57 : 0x56; 163 int m5229_udma = (hwif->channel) ? 0x57 : 0x56;
164 struct ide_timing t;
154 165
155 if (speed == XFER_UDMA_6) 166 if (speed == XFER_UDMA_6)
156 speed1 = 0x47; 167 speed1 = 0x47;
@@ -164,9 +175,21 @@ static void ali_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
164 tmpbyte &= ultra_enable; 175 tmpbyte &= ultra_enable;
165 pci_write_config_byte(dev, m5229_udma, tmpbyte); 176 pci_write_config_byte(dev, m5229_udma, tmpbyte);
166 177
167 /* 178 ide_timing_compute(drive, drive->dma_mode, &t, T, 1);
168 * FIXME: Oh, my... DMA timings are never set. 179 if (pair) {
169 */ 180 struct ide_timing p;
181
182 ide_timing_compute(pair, pair->pio_mode, &p, T, 1);
183 ide_timing_merge(&p, &t, &t,
184 IDE_TIMING_SETUP | IDE_TIMING_8BIT);
185 if (pair->dma_mode) {
186 ide_timing_compute(pair, pair->dma_mode,
187 &p, T, 1);
188 ide_timing_merge(&p, &t, &t,
189 IDE_TIMING_SETUP | IDE_TIMING_8BIT);
190 }
191 }
192 ali_program_timings(hwif, drive, &t);
170 } else { 193 } else {
171 pci_read_config_byte(dev, m5229_udma, &tmpbyte); 194 pci_read_config_byte(dev, m5229_udma, &tmpbyte);
172 tmpbyte &= (0x0f << ((1-unit) << 2)); 195 tmpbyte &= (0x0f << ((1-unit) << 2));