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authorBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2010-01-18 02:18:47 -0500
committerDavid S. Miller <davem@davemloft.net>2010-01-19 04:24:59 -0500
commit4d6b328943e87258efdc30110335a681f52d8367 (patch)
tree6617fc61a23f2071f1b7ca7d4ab39cc3cd19112c /drivers/ide
parent22cabc2619a58d3e5f95bb8df823da535e103bf4 (diff)
cy82c693: fix PIO timings calculations
Just use the standard ide_timing_compute() helper to calculate PIO timings. This fixes many issues with the open-coded version like using 16-bit timings when 8-bit ones should be used or not accounting for the enhanced cycle time specified by the device. Based on libata pata_cypress host driver. Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/ide')
-rw-r--r--drivers/ide/cy82c693.c106
1 files changed, 20 insertions, 86 deletions
diff --git a/drivers/ide/cy82c693.c b/drivers/ide/cy82c693.c
index d6e2cbbc53a0..49dfb8d40dcf 100644
--- a/drivers/ide/cy82c693.c
+++ b/drivers/ide/cy82c693.c
@@ -1,6 +1,7 @@
1/* 1/*
2 * Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer 2 * Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer
3 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator 3 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator
4 * Copyright (C) 2007-2010 Bartlomiej Zolnierkiewicz
4 * 5 *
5 * CYPRESS CY82C693 chipset IDE controller 6 * CYPRESS CY82C693 chipset IDE controller
6 * 7 *
@@ -81,80 +82,6 @@
81#define CY82_INDEX_CHANNEL1 0x31 82#define CY82_INDEX_CHANNEL1 0x31
82#define CY82_INDEX_TIMEOUT 0x32 83#define CY82_INDEX_TIMEOUT 0x32
83 84
84/* the min and max PCI bus speed in MHz - from datasheet */
85#define CY82C963_MIN_BUS_SPEED 25
86#define CY82C963_MAX_BUS_SPEED 33
87
88/* the struct for the PIO mode timings */
89typedef struct pio_clocks_s {
90 u8 address_time; /* Address setup (clocks) */
91 u8 time_16r; /* clocks for 16bit IOR (0xF0=Active/data, 0x0F=Recovery) */
92 u8 time_16w; /* clocks for 16bit IOW (0xF0=Active/data, 0x0F=Recovery) */
93 u8 time_8; /* clocks for 8bit (0xF0=Active/data, 0x0F=Recovery) */
94} pio_clocks_t;
95
96/*
97 * calc clocks using bus_speed
98 * returns (rounded up) time in bus clocks for time in ns
99 */
100static int calc_clk(int time, int bus_speed)
101{
102 int clocks;
103
104 clocks = (time*bus_speed+999)/1000 - 1;
105
106 if (clocks < 0)
107 clocks = 0;
108
109 if (clocks > 0x0F)
110 clocks = 0x0F;
111
112 return clocks;
113}
114
115/*
116 * compute the values for the clock registers for PIO
117 * mode and pci_clk [MHz] speed
118 *
119 * NOTE: for mode 0,1 and 2 drives 8-bit IDE command control registers are used
120 * for mode 3 and 4 drives 8 and 16-bit timings are the same
121 *
122 */
123static void compute_clocks(u8 pio, pio_clocks_t *p_pclk)
124{
125 struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
126 int clk1, clk2;
127 int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
128
129 /* we don't check against CY82C693's min and max speed,
130 * so you can play with the idebus=xx parameter
131 */
132
133 /* let's calc the address setup time clocks */
134 p_pclk->address_time = (u8)calc_clk(t->setup, bus_speed);
135
136 /* let's calc the active and recovery time clocks */
137 clk1 = calc_clk(t->active, bus_speed);
138
139 /* calc recovery timing */
140 clk2 = t->cycle - t->active - t->setup;
141
142 clk2 = calc_clk(clk2, bus_speed);
143
144 clk1 = (clk1<<4)|clk2; /* combine active and recovery clocks */
145
146 /* note: we use the same values for 16bit IOR and IOW
147 * those are all the same, since I don't have other
148 * timings than those from ide-lib.c
149 */
150
151 p_pclk->time_16r = (u8)clk1;
152 p_pclk->time_16w = (u8)clk1;
153
154 /* what are good values for 8bit ?? */
155 p_pclk->time_8 = (u8)clk1;
156}
157
158/* 85/*
159 * set DMA mode a specific channel for CY82C693 86 * set DMA mode a specific channel for CY82C693
160 */ 87 */
@@ -190,8 +117,11 @@ static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio)
190{ 117{
191 ide_hwif_t *hwif = drive->hwif; 118 ide_hwif_t *hwif = drive->hwif;
192 struct pci_dev *dev = to_pci_dev(hwif->dev); 119 struct pci_dev *dev = to_pci_dev(hwif->dev);
193 pio_clocks_t pclk; 120 int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
121 const unsigned long T = 1000000 / bus_speed;
194 unsigned int addrCtrl; 122 unsigned int addrCtrl;
123 struct ide_timing t;
124 u8 time_16, time_8;
195 125
196 /* select primary or secondary channel */ 126 /* select primary or secondary channel */
197 if (hwif->index > 0) { /* drive is on the secondary channel */ 127 if (hwif->index > 0) { /* drive is on the secondary channel */
@@ -204,8 +134,12 @@ static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio)
204 } 134 }
205 } 135 }
206 136
207 /* let's calc the values for this PIO mode */ 137 ide_timing_compute(drive, XFER_PIO_0 + pio, &t, T, 1);
208 compute_clocks(pio, &pclk); 138
139 time_16 = clamp_val(t.recover - 1, 0, 15) |
140 (clamp_val(t.active - 1, 0, 15) << 4);
141 time_8 = clamp_val(t.act8b - 1, 0, 15) |
142 (clamp_val(t.rec8b - 1, 0, 15) << 4);
209 143
210 /* now let's write the clocks registers */ 144 /* now let's write the clocks registers */
211 if ((drive->dn & 1) == 0) { 145 if ((drive->dn & 1) == 0) {
@@ -217,13 +151,13 @@ static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio)
217 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl); 151 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
218 152
219 addrCtrl &= (~0xF); 153 addrCtrl &= (~0xF);
220 addrCtrl |= (unsigned int)pclk.address_time; 154 addrCtrl |= clamp_val(t.setup - 1, 0, 15);
221 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl); 155 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
222 156
223 /* now let's set the remaining registers */ 157 /* now let's set the remaining registers */
224 pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, pclk.time_16r); 158 pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, time_16);
225 pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, pclk.time_16w); 159 pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, time_16);
226 pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, pclk.time_8); 160 pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, time_8);
227 } else { 161 } else {
228 /* 162 /*
229 * set slave drive 163 * set slave drive
@@ -233,13 +167,13 @@ static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio)
233 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl); 167 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
234 168
235 addrCtrl &= (~0xF0); 169 addrCtrl &= (~0xF0);
236 addrCtrl |= ((unsigned int)pclk.address_time<<4); 170 addrCtrl |= (clamp_val(t.setup - 1, 0, 15) << 4);
237 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl); 171 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
238 172
239 /* now let's set the remaining registers */ 173 /* now let's set the remaining registers */
240 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, pclk.time_16r); 174 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, time_16);
241 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, pclk.time_16w); 175 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, time_16);
242 pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, pclk.time_8); 176 pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, time_8);
243 } 177 }
244} 178}
245 179
@@ -325,6 +259,6 @@ static void __exit cy82c693_ide_exit(void)
325module_init(cy82c693_ide_init); 259module_init(cy82c693_ide_init);
326module_exit(cy82c693_ide_exit); 260module_exit(cy82c693_ide_exit);
327 261
328MODULE_AUTHOR("Andreas Krebs, Andre Hedrick"); 262MODULE_AUTHOR("Andreas Krebs, Andre Hedrick, Bartlomiej Zolnierkiewicz");
329MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE"); 263MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE");
330MODULE_LICENSE("GPL"); 264MODULE_LICENSE("GPL");