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authorSergei Shtylyov <sshtylyov@ru.mvista.com>2007-12-12 17:31:58 -0500
committerBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2007-12-12 17:31:58 -0500
commit809b53c4ef7188dc284498ef6e4ec2d4d587a275 (patch)
tree97f7ccd0330c67de092f0c2e84141dd68d94700f /drivers/ide
parenteadb6ecf761166aa55ad44f05b7a29b10ddaba34 (diff)
hpt366: fix HPT37x PIO mode timings (take 2)
After looking into the HPT370 manual (now that I have it) and re-checking all the timing tables, here's what I have discovered: - at 33 MHz clock, PIO mode 0 timings turned to be overclocked, and all other PIO modes underclocked; - at 50 MHz clock, PIO modes 0 to 2 turned to be overclocked; - at 66 MHz clock, PIO mode 0 was overclocked too. Finally, the taskfile timing (matching PIO mode 0) turned to be overclocked at all clock frequencies (and in all manuals)... The new timings have been tested on HPT370 chip (at 33 MHz PCI clock) and on HPT371N chip (at both 50 and 66 MHz DPLL clock). Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Diffstat (limited to 'drivers/ide')
-rw-r--r--drivers/ide/pci/hpt366.c71
1 files changed, 70 insertions, 1 deletions
diff --git a/drivers/ide/pci/hpt366.c b/drivers/ide/pci/hpt366.c
index 5682895d36d9..9fce25bdec8a 100644
--- a/drivers/ide/pci/hpt366.c
+++ b/drivers/ide/pci/hpt366.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/drivers/ide/pci/hpt366.c Version 1.21 Oct 23, 2007 2 * linux/drivers/ide/pci/hpt366.c Version 1.22 Dec 4, 2007
3 * 3 *
4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> 4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
5 * Portions Copyright (C) 2001 Sun Microsystems, Inc. 5 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
@@ -310,6 +310,8 @@ static u32 twenty_five_base_hpt36x[] = {
310 /* XFER_PIO_0 */ 0xc0d08585 310 /* XFER_PIO_0 */ 0xc0d08585
311}; 311};
312 312
313#if 0
314/* These are the timing tables from the HighPoint open source drivers... */
313static u32 thirty_three_base_hpt37x[] = { 315static u32 thirty_three_base_hpt37x[] = {
314 /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */ 316 /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */
315 /* XFER_UDMA_5 */ 0x12446231, 317 /* XFER_UDMA_5 */ 0x12446231,
@@ -369,6 +371,73 @@ static u32 sixty_six_base_hpt37x[] = {
369 /* XFER_PIO_1 */ 0x0d029d26, 371 /* XFER_PIO_1 */ 0x0d029d26,
370 /* XFER_PIO_0 */ 0x0d029d5e 372 /* XFER_PIO_0 */ 0x0d029d5e
371}; 373};
374#else
375/*
376 * The following are the new timing tables with PIO mode data/taskfile transfer
377 * overclocking fixed...
378 */
379
380/* This table is taken from the HPT370 data manual rev. 1.02 */
381static u32 thirty_three_base_hpt37x[] = {
382 /* XFER_UDMA_6 */ 0x16455031, /* 0x16655031 ?? */
383 /* XFER_UDMA_5 */ 0x16455031,
384 /* XFER_UDMA_4 */ 0x16455031,
385 /* XFER_UDMA_3 */ 0x166d5031,
386 /* XFER_UDMA_2 */ 0x16495031,
387 /* XFER_UDMA_1 */ 0x164d5033,
388 /* XFER_UDMA_0 */ 0x16515097,
389
390 /* XFER_MW_DMA_2 */ 0x26515031,
391 /* XFER_MW_DMA_1 */ 0x26515033,
392 /* XFER_MW_DMA_0 */ 0x26515097,
393
394 /* XFER_PIO_4 */ 0x06515021,
395 /* XFER_PIO_3 */ 0x06515022,
396 /* XFER_PIO_2 */ 0x06515033,
397 /* XFER_PIO_1 */ 0x06915065,
398 /* XFER_PIO_0 */ 0x06d1508a
399};
400
401static u32 fifty_base_hpt37x[] = {
402 /* XFER_UDMA_6 */ 0x1a861842,
403 /* XFER_UDMA_5 */ 0x1a861842,
404 /* XFER_UDMA_4 */ 0x1aae1842,
405 /* XFER_UDMA_3 */ 0x1a8e1842,
406 /* XFER_UDMA_2 */ 0x1a0e1842,
407 /* XFER_UDMA_1 */ 0x1a161854,
408 /* XFER_UDMA_0 */ 0x1a1a18ea,
409
410 /* XFER_MW_DMA_2 */ 0x2a821842,
411 /* XFER_MW_DMA_1 */ 0x2a821854,
412 /* XFER_MW_DMA_0 */ 0x2a8218ea,
413
414 /* XFER_PIO_4 */ 0x0a821842,
415 /* XFER_PIO_3 */ 0x0a821843,
416 /* XFER_PIO_2 */ 0x0a821855,
417 /* XFER_PIO_1 */ 0x0ac218a8,
418 /* XFER_PIO_0 */ 0x0b02190c
419};
420
421static u32 sixty_six_base_hpt37x[] = {
422 /* XFER_UDMA_6 */ 0x1c86fe62,
423 /* XFER_UDMA_5 */ 0x1caefe62, /* 0x1c8afe62 */
424 /* XFER_UDMA_4 */ 0x1c8afe62,
425 /* XFER_UDMA_3 */ 0x1c8efe62,
426 /* XFER_UDMA_2 */ 0x1c92fe62,
427 /* XFER_UDMA_1 */ 0x1c9afe62,
428 /* XFER_UDMA_0 */ 0x1c82fe62,
429
430 /* XFER_MW_DMA_2 */ 0x2c82fe62,
431 /* XFER_MW_DMA_1 */ 0x2c82fe66,
432 /* XFER_MW_DMA_0 */ 0x2c82ff2e,
433
434 /* XFER_PIO_4 */ 0x0c82fe62,
435 /* XFER_PIO_3 */ 0x0c82fe84,
436 /* XFER_PIO_2 */ 0x0c82fea6,
437 /* XFER_PIO_1 */ 0x0d02ff26,
438 /* XFER_PIO_0 */ 0x0d42ff7f
439};
440#endif
372 441
373#define HPT366_DEBUG_DRIVE_INFO 0 442#define HPT366_DEBUG_DRIVE_INFO 0
374#define HPT371_ALLOW_ATA133_6 1 443#define HPT371_ALLOW_ATA133_6 1