aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/ide/ppc
diff options
context:
space:
mode:
authorBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2007-10-13 11:47:48 -0400
committerBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2007-10-13 11:47:48 -0400
commit90f72eca36e92d5756cf312535d94d7f21f34d2e (patch)
tree2c2eb317911df95628802b35fa8a6b4aad9e4965 /drivers/ide/ppc
parent085798b12ffebd69c13c8ce05fabc8ed5ac43e63 (diff)
ide-pmac: fix set_timings_mdma()
* Move adjusting of cycle time for devices providing explicit DMA cycle time from pmac_ide_mdma_enable() to set_timings_mdma(). * Remove no longer needed drive_cycle_time argument. * BUG() if unsupported speed argument value is passed (shouldn't happen). * Matching access/recovery timings always exist so remove redundant check. * Make set_timings_mdma() void. * Update pmac_ide_tune_chipset()'s comment. Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Diffstat (limited to 'drivers/ide/ppc')
-rw-r--r--drivers/ide/ppc/pmac.c40
1 files changed, 12 insertions, 28 deletions
diff --git a/drivers/ide/ppc/pmac.c b/drivers/ide/ppc/pmac.c
index cfbe5690ca88..b24e905ddcdd 100644
--- a/drivers/ide/ppc/pmac.c
+++ b/drivers/ide/ppc/pmac.c
@@ -770,12 +770,13 @@ set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed)
770/* 770/*
771 * Calculate MDMA timings for all cells 771 * Calculate MDMA timings for all cells
772 */ 772 */
773static int 773static void
774set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2, 774set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
775 u8 speed, int drive_cycle_time) 775 u8 speed)
776{ 776{
777 int cycleTime, accessTime = 0, recTime = 0; 777 int cycleTime, accessTime = 0, recTime = 0;
778 unsigned accessTicks, recTicks; 778 unsigned accessTicks, recTicks;
779 struct hd_driveid *id = drive->id;
779 struct mdma_timings_t* tm = NULL; 780 struct mdma_timings_t* tm = NULL;
780 int i; 781 int i;
781 782
@@ -785,11 +786,14 @@ set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
785 case 1: cycleTime = 150; break; 786 case 1: cycleTime = 150; break;
786 case 2: cycleTime = 120; break; 787 case 2: cycleTime = 120; break;
787 default: 788 default:
788 return 1; 789 BUG();
790 break;
789 } 791 }
790 /* Adjust for drive */ 792
791 if (drive_cycle_time && drive_cycle_time > cycleTime) 793 /* Check if drive provides explicit DMA cycle time */
792 cycleTime = drive_cycle_time; 794 if ((id->field_valid & 2) && id->eide_dma_time)
795 cycleTime = max_t(int, id->eide_dma_time, cycleTime);
796
793 /* OHare limits according to some old Apple sources */ 797 /* OHare limits according to some old Apple sources */
794 if ((intf_type == controller_ohare) && (cycleTime < 150)) 798 if ((intf_type == controller_ohare) && (cycleTime < 150))
795 cycleTime = 150; 799 cycleTime = 150;
@@ -817,8 +821,6 @@ set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
817 break; 821 break;
818 i++; 822 i++;
819 } 823 }
820 if (i < 0)
821 return 1;
822 cycleTime = tm[i].cycleTime; 824 cycleTime = tm[i].cycleTime;
823 accessTime = tm[i].accessTime; 825 accessTime = tm[i].accessTime;
824 recTime = tm[i].recoveryTime; 826 recTime = tm[i].recoveryTime;
@@ -900,16 +902,12 @@ set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
900 printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n", 902 printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
901 drive->name, speed & 0xf, *timings); 903 drive->name, speed & 0xf, *timings);
902#endif 904#endif
903 return 0;
904} 905}
905#endif /* #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC */ 906#endif /* #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC */
906 907
907/* 908/*
908 * Speedproc. This function is called by the core to set any of the standard 909 * Speedproc. This function is called by the core to set any of the standard
909 * DMA timing (MDMA or UDMA) to both the drive and the controller. 910 * DMA timing (MDMA or UDMA) to both the drive and the controller.
910 * You may notice we don't use this function on normal "dma check" operation,
911 * our dedicated function is more precise as it uses the drive provided
912 * cycle time value. We should probably fix this one to deal with that too...
913 */ 911 */
914static int pmac_ide_tune_chipset(ide_drive_t *drive, const u8 speed) 912static int pmac_ide_tune_chipset(ide_drive_t *drive, const u8 speed)
915{ 913{
@@ -947,7 +945,7 @@ static int pmac_ide_tune_chipset(ide_drive_t *drive, const u8 speed)
947 case XFER_MW_DMA_2: 945 case XFER_MW_DMA_2:
948 case XFER_MW_DMA_1: 946 case XFER_MW_DMA_1:
949 case XFER_MW_DMA_0: 947 case XFER_MW_DMA_0:
950 ret = set_timings_mdma(drive, pmif->kind, &tl[0], &tl[1], speed, 0); 948 set_timings_mdma(drive, pmif->kind, &tl[0], &tl[1], speed);
951 break; 949 break;
952 case XFER_SW_DMA_2: 950 case XFER_SW_DMA_2:
953 case XFER_SW_DMA_1: 951 case XFER_SW_DMA_1:
@@ -1680,8 +1678,6 @@ pmac_ide_mdma_enable(ide_drive_t *drive, u16 mode)
1680{ 1678{
1681 ide_hwif_t *hwif = HWIF(drive); 1679 ide_hwif_t *hwif = HWIF(drive);
1682 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data; 1680 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1683 int drive_cycle_time;
1684 struct hd_driveid *id = drive->id;
1685 u32 *timings, *timings2; 1681 u32 *timings, *timings2;
1686 u32 timing_local[2]; 1682 u32 timing_local[2];
1687 int ret; 1683 int ret;
@@ -1690,24 +1686,12 @@ pmac_ide_mdma_enable(ide_drive_t *drive, u16 mode)
1690 timings = &pmif->timings[drive->select.b.unit & 0x01]; 1686 timings = &pmif->timings[drive->select.b.unit & 0x01];
1691 timings2 = &pmif->timings[(drive->select.b.unit & 0x01) + 2]; 1687 timings2 = &pmif->timings[(drive->select.b.unit & 0x01) + 2];
1692 1688
1693 /* Check if drive provide explicit cycle time */
1694 if ((id->field_valid & 2) && (id->eide_dma_time))
1695 drive_cycle_time = id->eide_dma_time;
1696 else
1697 drive_cycle_time = 0;
1698
1699 /* Copy timings to local image */ 1689 /* Copy timings to local image */
1700 timing_local[0] = *timings; 1690 timing_local[0] = *timings;
1701 timing_local[1] = *timings2; 1691 timing_local[1] = *timings2;
1702 1692
1703 /* Calculate controller timings */ 1693 /* Calculate controller timings */
1704 ret = set_timings_mdma( drive, pmif->kind, 1694 set_timings_mdma(drive, pmif->kind, &timing_local[0], &timing_local[1], mode);
1705 &timing_local[0],
1706 &timing_local[1],
1707 mode,
1708 drive_cycle_time);
1709 if (ret)
1710 return 0;
1711 1695
1712 /* Set feature on drive */ 1696 /* Set feature on drive */
1713 printk(KERN_INFO "%s: Enabling MultiWord DMA %d\n", drive->name, mode & 0xf); 1697 printk(KERN_INFO "%s: Enabling MultiWord DMA %d\n", drive->name, mode & 0xf);