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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/ide/ppc/pmac.c
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/ide/ppc/pmac.c')
-rw-r--r--drivers/ide/ppc/pmac.c2208
1 files changed, 2208 insertions, 0 deletions
diff --git a/drivers/ide/ppc/pmac.c b/drivers/ide/ppc/pmac.c
new file mode 100644
index 000000000000..6dc273a81327
--- /dev/null
+++ b/drivers/ide/ppc/pmac.c
@@ -0,0 +1,2208 @@
1/*
2 * linux/drivers/ide/ide-pmac.c
3 *
4 * Support for IDE interfaces on PowerMacs.
5 * These IDE interfaces are memory-mapped and have a DBDMA channel
6 * for doing DMA.
7 *
8 * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 *
15 * Some code taken from drivers/ide/ide-dma.c:
16 *
17 * Copyright (c) 1995-1998 Mark Lord
18 *
19 * TODO: - Use pre-calculated (kauai) timing tables all the time and
20 * get rid of the "rounded" tables used previously, so we have the
21 * same table format for all controllers and can then just have one
22 * big table
23 *
24 */
25#include <linux/config.h>
26#include <linux/types.h>
27#include <linux/kernel.h>
28#include <linux/sched.h>
29#include <linux/init.h>
30#include <linux/delay.h>
31#include <linux/ide.h>
32#include <linux/notifier.h>
33#include <linux/reboot.h>
34#include <linux/pci.h>
35#include <linux/adb.h>
36#include <linux/pmu.h>
37#include <linux/scatterlist.h>
38
39#include <asm/prom.h>
40#include <asm/io.h>
41#include <asm/dbdma.h>
42#include <asm/ide.h>
43#include <asm/pci-bridge.h>
44#include <asm/machdep.h>
45#include <asm/pmac_feature.h>
46#include <asm/sections.h>
47#include <asm/irq.h>
48
49#ifndef CONFIG_PPC64
50#include <asm/mediabay.h>
51#endif
52
53#include "ide-timing.h"
54
55#undef IDE_PMAC_DEBUG
56
57#define DMA_WAIT_TIMEOUT 50
58
59typedef struct pmac_ide_hwif {
60 unsigned long regbase;
61 int irq;
62 int kind;
63 int aapl_bus_id;
64 unsigned cable_80 : 1;
65 unsigned mediabay : 1;
66 unsigned broken_dma : 1;
67 unsigned broken_dma_warn : 1;
68 struct device_node* node;
69 struct macio_dev *mdev;
70 u32 timings[4];
71 volatile u32 __iomem * *kauai_fcr;
72#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
73 /* Those fields are duplicating what is in hwif. We currently
74 * can't use the hwif ones because of some assumptions that are
75 * beeing done by the generic code about the kind of dma controller
76 * and format of the dma table. This will have to be fixed though.
77 */
78 volatile struct dbdma_regs __iomem * dma_regs;
79 struct dbdma_cmd* dma_table_cpu;
80#endif
81
82} pmac_ide_hwif_t;
83
84static pmac_ide_hwif_t pmac_ide[MAX_HWIFS] __pmacdata;
85static int pmac_ide_count;
86
87enum {
88 controller_ohare, /* OHare based */
89 controller_heathrow, /* Heathrow/Paddington */
90 controller_kl_ata3, /* KeyLargo ATA-3 */
91 controller_kl_ata4, /* KeyLargo ATA-4 */
92 controller_un_ata6, /* UniNorth2 ATA-6 */
93 controller_k2_ata6, /* K2 ATA-6 */
94 controller_sh_ata6, /* Shasta ATA-6 */
95};
96
97static const char* model_name[] = {
98 "OHare ATA", /* OHare based */
99 "Heathrow ATA", /* Heathrow/Paddington */
100 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
101 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
102 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
103 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
104 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
105};
106
107/*
108 * Extra registers, both 32-bit little-endian
109 */
110#define IDE_TIMING_CONFIG 0x200
111#define IDE_INTERRUPT 0x300
112
113/* Kauai (U2) ATA has different register setup */
114#define IDE_KAUAI_PIO_CONFIG 0x200
115#define IDE_KAUAI_ULTRA_CONFIG 0x210
116#define IDE_KAUAI_POLL_CONFIG 0x220
117
118/*
119 * Timing configuration register definitions
120 */
121
122/* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
123#define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
124#define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
125#define IDE_SYSCLK_NS 30 /* 33Mhz cell */
126#define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
127
128/* 133Mhz cell, found in shasta.
129 * See comments about 100 Mhz Uninorth 2...
130 * Note that PIO_MASK and MDMA_MASK seem to overlap
131 */
132#define TR_133_PIOREG_PIO_MASK 0xff000fff
133#define TR_133_PIOREG_MDMA_MASK 0x00fff800
134#define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
135#define TR_133_UDMAREG_UDMA_EN 0x00000001
136
137/* 100Mhz cell, found in Uninorth 2. I don't have much infos about
138 * this one yet, it appears as a pci device (106b/0033) on uninorth
139 * internal PCI bus and it's clock is controlled like gem or fw. It
140 * appears to be an evolution of keylargo ATA4 with a timing register
141 * extended to 2 32bits registers and a similar DBDMA channel. Other
142 * registers seem to exist but I can't tell much about them.
143 *
144 * So far, I'm using pre-calculated tables for this extracted from
145 * the values used by the MacOS X driver.
146 *
147 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
148 * register controls the UDMA timings. At least, it seems bit 0
149 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
150 * cycle time in units of 10ns. Bits 8..15 are used by I don't
151 * know their meaning yet
152 */
153#define TR_100_PIOREG_PIO_MASK 0xff000fff
154#define TR_100_PIOREG_MDMA_MASK 0x00fff000
155#define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
156#define TR_100_UDMAREG_UDMA_EN 0x00000001
157
158
159/* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
160 * 40 connector cable and to 4 on 80 connector one.
161 * Clock unit is 15ns (66Mhz)
162 *
163 * 3 Values can be programmed:
164 * - Write data setup, which appears to match the cycle time. They
165 * also call it DIOW setup.
166 * - Ready to pause time (from spec)
167 * - Address setup. That one is weird. I don't see where exactly
168 * it fits in UDMA cycles, I got it's name from an obscure piece
169 * of commented out code in Darwin. They leave it to 0, we do as
170 * well, despite a comment that would lead to think it has a
171 * min value of 45ns.
172 * Apple also add 60ns to the write data setup (or cycle time ?) on
173 * reads.
174 */
175#define TR_66_UDMA_MASK 0xfff00000
176#define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
177#define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */
178#define TR_66_UDMA_ADDRSETUP_SHIFT 29
179#define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
180#define TR_66_UDMA_RDY2PAUS_SHIFT 25
181#define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
182#define TR_66_UDMA_WRDATASETUP_SHIFT 21
183#define TR_66_MDMA_MASK 0x000ffc00
184#define TR_66_MDMA_RECOVERY_MASK 0x000f8000
185#define TR_66_MDMA_RECOVERY_SHIFT 15
186#define TR_66_MDMA_ACCESS_MASK 0x00007c00
187#define TR_66_MDMA_ACCESS_SHIFT 10
188#define TR_66_PIO_MASK 0x000003ff
189#define TR_66_PIO_RECOVERY_MASK 0x000003e0
190#define TR_66_PIO_RECOVERY_SHIFT 5
191#define TR_66_PIO_ACCESS_MASK 0x0000001f
192#define TR_66_PIO_ACCESS_SHIFT 0
193
194/* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
195 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
196 *
197 * The access time and recovery time can be programmed. Some older
198 * Darwin code base limit OHare to 150ns cycle time. I decided to do
199 * the same here fore safety against broken old hardware ;)
200 * The HalfTick bit, when set, adds half a clock (15ns) to the access
201 * time and removes one from recovery. It's not supported on KeyLargo
202 * implementation afaik. The E bit appears to be set for PIO mode 0 and
203 * is used to reach long timings used in this mode.
204 */
205#define TR_33_MDMA_MASK 0x003ff800
206#define TR_33_MDMA_RECOVERY_MASK 0x001f0000
207#define TR_33_MDMA_RECOVERY_SHIFT 16
208#define TR_33_MDMA_ACCESS_MASK 0x0000f800
209#define TR_33_MDMA_ACCESS_SHIFT 11
210#define TR_33_MDMA_HALFTICK 0x00200000
211#define TR_33_PIO_MASK 0x000007ff
212#define TR_33_PIO_E 0x00000400
213#define TR_33_PIO_RECOVERY_MASK 0x000003e0
214#define TR_33_PIO_RECOVERY_SHIFT 5
215#define TR_33_PIO_ACCESS_MASK 0x0000001f
216#define TR_33_PIO_ACCESS_SHIFT 0
217
218/*
219 * Interrupt register definitions
220 */
221#define IDE_INTR_DMA 0x80000000
222#define IDE_INTR_DEVICE 0x40000000
223
224/*
225 * FCR Register on Kauai. Not sure what bit 0x4 is ...
226 */
227#define KAUAI_FCR_UATA_MAGIC 0x00000004
228#define KAUAI_FCR_UATA_RESET_N 0x00000002
229#define KAUAI_FCR_UATA_ENABLE 0x00000001
230
231#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
232
233/* Rounded Multiword DMA timings
234 *
235 * I gave up finding a generic formula for all controller
236 * types and instead, built tables based on timing values
237 * used by Apple in Darwin's implementation.
238 */
239struct mdma_timings_t {
240 int accessTime;
241 int recoveryTime;
242 int cycleTime;
243};
244
245struct mdma_timings_t mdma_timings_33[] __pmacdata =
246{
247 { 240, 240, 480 },
248 { 180, 180, 360 },
249 { 135, 135, 270 },
250 { 120, 120, 240 },
251 { 105, 105, 210 },
252 { 90, 90, 180 },
253 { 75, 75, 150 },
254 { 75, 45, 120 },
255 { 0, 0, 0 }
256};
257
258struct mdma_timings_t mdma_timings_33k[] __pmacdata =
259{
260 { 240, 240, 480 },
261 { 180, 180, 360 },
262 { 150, 150, 300 },
263 { 120, 120, 240 },
264 { 90, 120, 210 },
265 { 90, 90, 180 },
266 { 90, 60, 150 },
267 { 90, 30, 120 },
268 { 0, 0, 0 }
269};
270
271struct mdma_timings_t mdma_timings_66[] __pmacdata =
272{
273 { 240, 240, 480 },
274 { 180, 180, 360 },
275 { 135, 135, 270 },
276 { 120, 120, 240 },
277 { 105, 105, 210 },
278 { 90, 90, 180 },
279 { 90, 75, 165 },
280 { 75, 45, 120 },
281 { 0, 0, 0 }
282};
283
284/* KeyLargo ATA-4 Ultra DMA timings (rounded) */
285struct {
286 int addrSetup; /* ??? */
287 int rdy2pause;
288 int wrDataSetup;
289} kl66_udma_timings[] __pmacdata =
290{
291 { 0, 180, 120 }, /* Mode 0 */
292 { 0, 150, 90 }, /* 1 */
293 { 0, 120, 60 }, /* 2 */
294 { 0, 90, 45 }, /* 3 */
295 { 0, 90, 30 } /* 4 */
296};
297
298/* UniNorth 2 ATA/100 timings */
299struct kauai_timing {
300 int cycle_time;
301 u32 timing_reg;
302};
303
304static struct kauai_timing kauai_pio_timings[] __pmacdata =
305{
306 { 930 , 0x08000fff },
307 { 600 , 0x08000a92 },
308 { 383 , 0x0800060f },
309 { 360 , 0x08000492 },
310 { 330 , 0x0800048f },
311 { 300 , 0x080003cf },
312 { 270 , 0x080003cc },
313 { 240 , 0x0800038b },
314 { 239 , 0x0800030c },
315 { 180 , 0x05000249 },
316 { 120 , 0x04000148 }
317};
318
319static struct kauai_timing kauai_mdma_timings[] __pmacdata =
320{
321 { 1260 , 0x00fff000 },
322 { 480 , 0x00618000 },
323 { 360 , 0x00492000 },
324 { 270 , 0x0038e000 },
325 { 240 , 0x0030c000 },
326 { 210 , 0x002cb000 },
327 { 180 , 0x00249000 },
328 { 150 , 0x00209000 },
329 { 120 , 0x00148000 },
330 { 0 , 0 },
331};
332
333static struct kauai_timing kauai_udma_timings[] __pmacdata =
334{
335 { 120 , 0x000070c0 },
336 { 90 , 0x00005d80 },
337 { 60 , 0x00004a60 },
338 { 45 , 0x00003a50 },
339 { 30 , 0x00002a30 },
340 { 20 , 0x00002921 },
341 { 0 , 0 },
342};
343
344static struct kauai_timing shasta_pio_timings[] __pmacdata =
345{
346 { 930 , 0x08000fff },
347 { 600 , 0x0A000c97 },
348 { 383 , 0x07000712 },
349 { 360 , 0x040003cd },
350 { 330 , 0x040003cd },
351 { 300 , 0x040003cd },
352 { 270 , 0x040003cd },
353 { 240 , 0x040003cd },
354 { 239 , 0x040003cd },
355 { 180 , 0x0400028b },
356 { 120 , 0x0400010a }
357};
358
359static struct kauai_timing shasta_mdma_timings[] __pmacdata =
360{
361 { 1260 , 0x00fff000 },
362 { 480 , 0x00820800 },
363 { 360 , 0x00820800 },
364 { 270 , 0x00820800 },
365 { 240 , 0x00820800 },
366 { 210 , 0x00820800 },
367 { 180 , 0x00820800 },
368 { 150 , 0x0028b000 },
369 { 120 , 0x001ca000 },
370 { 0 , 0 },
371};
372
373static struct kauai_timing shasta_udma133_timings[] __pmacdata =
374{
375 { 120 , 0x00035901, },
376 { 90 , 0x000348b1, },
377 { 60 , 0x00033881, },
378 { 45 , 0x00033861, },
379 { 30 , 0x00033841, },
380 { 20 , 0x00033031, },
381 { 15 , 0x00033021, },
382 { 0 , 0 },
383};
384
385
386static inline u32
387kauai_lookup_timing(struct kauai_timing* table, int cycle_time)
388{
389 int i;
390
391 for (i=0; table[i].cycle_time; i++)
392 if (cycle_time > table[i+1].cycle_time)
393 return table[i].timing_reg;
394 return 0;
395}
396
397/* allow up to 256 DBDMA commands per xfer */
398#define MAX_DCMDS 256
399
400/*
401 * Wait 1s for disk to answer on IDE bus after a hard reset
402 * of the device (via GPIO/FCR).
403 *
404 * Some devices seem to "pollute" the bus even after dropping
405 * the BSY bit (typically some combo drives slave on the UDMA
406 * bus) after a hard reset. Since we hard reset all drives on
407 * KeyLargo ATA66, we have to keep that delay around. I may end
408 * up not hard resetting anymore on these and keep the delay only
409 * for older interfaces instead (we have to reset when coming
410 * from MacOS...) --BenH.
411 */
412#define IDE_WAKEUP_DELAY (1*HZ)
413
414static void pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif);
415static int pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq);
416static int pmac_ide_tune_chipset(ide_drive_t *drive, u8 speed);
417static void pmac_ide_tuneproc(ide_drive_t *drive, u8 pio);
418static void pmac_ide_selectproc(ide_drive_t *drive);
419static void pmac_ide_kauai_selectproc(ide_drive_t *drive);
420
421#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
422
423/*
424 * Below is the code for blinking the laptop LED along with hard
425 * disk activity.
426 */
427
428#ifdef CONFIG_BLK_DEV_IDE_PMAC_BLINK
429
430/* Set to 50ms minimum led-on time (also used to limit frequency
431 * of requests sent to the PMU
432 */
433#define PMU_HD_BLINK_TIME (HZ/50)
434
435static struct adb_request pmu_blink_on, pmu_blink_off;
436static spinlock_t pmu_blink_lock;
437static unsigned long pmu_blink_stoptime;
438static int pmu_blink_ledstate;
439static struct timer_list pmu_blink_timer;
440static int pmu_ide_blink_enabled;
441
442
443static void
444pmu_hd_blink_timeout(unsigned long data)
445{
446 unsigned long flags;
447
448 spin_lock_irqsave(&pmu_blink_lock, flags);
449
450 /* We may have been triggered again in a racy way, check
451 * that we really want to switch it off
452 */
453 if (time_after(pmu_blink_stoptime, jiffies))
454 goto done;
455
456 /* Previous req. not complete, try 100ms more */
457 if (pmu_blink_off.complete == 0)
458 mod_timer(&pmu_blink_timer, jiffies + PMU_HD_BLINK_TIME);
459 else if (pmu_blink_ledstate) {
460 pmu_request(&pmu_blink_off, NULL, 4, 0xee, 4, 0, 0);
461 pmu_blink_ledstate = 0;
462 }
463done:
464 spin_unlock_irqrestore(&pmu_blink_lock, flags);
465}
466
467static void
468pmu_hd_kick_blink(void *data, int rw)
469{
470 unsigned long flags;
471
472 pmu_blink_stoptime = jiffies + PMU_HD_BLINK_TIME;
473 wmb();
474 mod_timer(&pmu_blink_timer, pmu_blink_stoptime);
475 /* Fast path when LED is already ON */
476 if (pmu_blink_ledstate == 1)
477 return;
478 spin_lock_irqsave(&pmu_blink_lock, flags);
479 if (pmu_blink_on.complete && !pmu_blink_ledstate) {
480 pmu_request(&pmu_blink_on, NULL, 4, 0xee, 4, 0, 1);
481 pmu_blink_ledstate = 1;
482 }
483 spin_unlock_irqrestore(&pmu_blink_lock, flags);
484}
485
486static int
487pmu_hd_blink_init(void)
488{
489 struct device_node *dt;
490 const char *model;
491
492 /* Currently, I only enable this feature on KeyLargo based laptops,
493 * older laptops may support it (at least heathrow/paddington) but
494 * I don't feel like loading those venerable old machines with so
495 * much additional interrupt & PMU activity...
496 */
497 if (pmu_get_model() != PMU_KEYLARGO_BASED)
498 return 0;
499
500 dt = find_devices("device-tree");
501 if (dt == NULL)
502 return 0;
503 model = (const char *)get_property(dt, "model", NULL);
504 if (model == NULL)
505 return 0;
506 if (strncmp(model, "PowerBook", strlen("PowerBook")) != 0 &&
507 strncmp(model, "iBook", strlen("iBook")) != 0)
508 return 0;
509
510 pmu_blink_on.complete = 1;
511 pmu_blink_off.complete = 1;
512 spin_lock_init(&pmu_blink_lock);
513 init_timer(&pmu_blink_timer);
514 pmu_blink_timer.function = pmu_hd_blink_timeout;
515
516 return 1;
517}
518
519#endif /* CONFIG_BLK_DEV_IDE_PMAC_BLINK */
520
521/*
522 * N.B. this can't be an initfunc, because the media-bay task can
523 * call ide_[un]register at any time.
524 */
525void __pmac
526pmac_ide_init_hwif_ports(hw_regs_t *hw,
527 unsigned long data_port, unsigned long ctrl_port,
528 int *irq)
529{
530 int i, ix;
531
532 if (data_port == 0)
533 return;
534
535 for (ix = 0; ix < MAX_HWIFS; ++ix)
536 if (data_port == pmac_ide[ix].regbase)
537 break;
538
539 if (ix >= MAX_HWIFS) {
540 /* Probably a PCI interface... */
541 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; ++i)
542 hw->io_ports[i] = data_port + i - IDE_DATA_OFFSET;
543 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
544 return;
545 }
546
547 for (i = 0; i < 8; ++i)
548 hw->io_ports[i] = data_port + i * 0x10;
549 hw->io_ports[8] = data_port + 0x160;
550
551 if (irq != NULL)
552 *irq = pmac_ide[ix].irq;
553}
554
555#define PMAC_IDE_REG(x) ((void __iomem *)(IDE_DATA_REG+(x)))
556
557/*
558 * Apply the timings of the proper unit (master/slave) to the shared
559 * timing register when selecting that unit. This version is for
560 * ASICs with a single timing register
561 */
562static void __pmac
563pmac_ide_selectproc(ide_drive_t *drive)
564{
565 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
566
567 if (pmif == NULL)
568 return;
569
570 if (drive->select.b.unit & 0x01)
571 writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG));
572 else
573 writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG));
574 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
575}
576
577/*
578 * Apply the timings of the proper unit (master/slave) to the shared
579 * timing register when selecting that unit. This version is for
580 * ASICs with a dual timing register (Kauai)
581 */
582static void __pmac
583pmac_ide_kauai_selectproc(ide_drive_t *drive)
584{
585 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
586
587 if (pmif == NULL)
588 return;
589
590 if (drive->select.b.unit & 0x01) {
591 writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
592 writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
593 } else {
594 writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
595 writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
596 }
597 (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
598}
599
600/*
601 * Force an update of controller timing values for a given drive
602 */
603static void __pmac
604pmac_ide_do_update_timings(ide_drive_t *drive)
605{
606 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
607
608 if (pmif == NULL)
609 return;
610
611 if (pmif->kind == controller_sh_ata6 ||
612 pmif->kind == controller_un_ata6 ||
613 pmif->kind == controller_k2_ata6)
614 pmac_ide_kauai_selectproc(drive);
615 else
616 pmac_ide_selectproc(drive);
617}
618
619static void
620pmac_outbsync(ide_drive_t *drive, u8 value, unsigned long port)
621{
622 u32 tmp;
623
624 writeb(value, (void __iomem *) port);
625 tmp = readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
626}
627
628/*
629 * Send the SET_FEATURE IDE command to the drive and update drive->id with
630 * the new state. We currently don't use the generic routine as it used to
631 * cause various trouble, especially with older mediabays.
632 * This code is sometimes triggering a spurrious interrupt though, I need
633 * to sort that out sooner or later and see if I can finally get the
634 * common version to work properly in all cases
635 */
636static int __pmac
637pmac_ide_do_setfeature(ide_drive_t *drive, u8 command)
638{
639 ide_hwif_t *hwif = HWIF(drive);
640 int result = 1;
641
642 disable_irq_nosync(hwif->irq);
643 udelay(1);
644 SELECT_DRIVE(drive);
645 SELECT_MASK(drive, 0);
646 udelay(1);
647 /* Get rid of pending error state */
648 (void) hwif->INB(IDE_STATUS_REG);
649 /* Timeout bumped for some powerbooks */
650 if (wait_for_ready(drive, 2000)) {
651 /* Timeout bumped for some powerbooks */
652 printk(KERN_ERR "%s: pmac_ide_do_setfeature disk not ready "
653 "before SET_FEATURE!\n", drive->name);
654 goto out;
655 }
656 udelay(10);
657 hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG);
658 hwif->OUTB(command, IDE_NSECTOR_REG);
659 hwif->OUTB(SETFEATURES_XFER, IDE_FEATURE_REG);
660 hwif->OUTBSYNC(drive, WIN_SETFEATURES, IDE_COMMAND_REG);
661 udelay(1);
662 /* Timeout bumped for some powerbooks */
663 result = wait_for_ready(drive, 2000);
664 hwif->OUTB(drive->ctl, IDE_CONTROL_REG);
665 if (result)
666 printk(KERN_ERR "%s: pmac_ide_do_setfeature disk not ready "
667 "after SET_FEATURE !\n", drive->name);
668out:
669 SELECT_MASK(drive, 0);
670 if (result == 0) {
671 drive->id->dma_ultra &= ~0xFF00;
672 drive->id->dma_mword &= ~0x0F00;
673 drive->id->dma_1word &= ~0x0F00;
674 switch(command) {
675 case XFER_UDMA_7:
676 drive->id->dma_ultra |= 0x8080; break;
677 case XFER_UDMA_6:
678 drive->id->dma_ultra |= 0x4040; break;
679 case XFER_UDMA_5:
680 drive->id->dma_ultra |= 0x2020; break;
681 case XFER_UDMA_4:
682 drive->id->dma_ultra |= 0x1010; break;
683 case XFER_UDMA_3:
684 drive->id->dma_ultra |= 0x0808; break;
685 case XFER_UDMA_2:
686 drive->id->dma_ultra |= 0x0404; break;
687 case XFER_UDMA_1:
688 drive->id->dma_ultra |= 0x0202; break;
689 case XFER_UDMA_0:
690 drive->id->dma_ultra |= 0x0101; break;
691 case XFER_MW_DMA_2:
692 drive->id->dma_mword |= 0x0404; break;
693 case XFER_MW_DMA_1:
694 drive->id->dma_mword |= 0x0202; break;
695 case XFER_MW_DMA_0:
696 drive->id->dma_mword |= 0x0101; break;
697 case XFER_SW_DMA_2:
698 drive->id->dma_1word |= 0x0404; break;
699 case XFER_SW_DMA_1:
700 drive->id->dma_1word |= 0x0202; break;
701 case XFER_SW_DMA_0:
702 drive->id->dma_1word |= 0x0101; break;
703 default: break;
704 }
705 }
706 enable_irq(hwif->irq);
707 return result;
708}
709
710/*
711 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
712 */
713static void __pmac
714pmac_ide_tuneproc(ide_drive_t *drive, u8 pio)
715{
716 ide_pio_data_t d;
717 u32 *timings;
718 unsigned accessTicks, recTicks;
719 unsigned accessTime, recTime;
720 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
721
722 if (pmif == NULL)
723 return;
724
725 /* which drive is it ? */
726 timings = &pmif->timings[drive->select.b.unit & 0x01];
727
728 pio = ide_get_best_pio_mode(drive, pio, 4, &d);
729
730 switch (pmif->kind) {
731 case controller_sh_ata6: {
732 /* 133Mhz cell */
733 u32 tr = kauai_lookup_timing(shasta_pio_timings, d.cycle_time);
734 if (tr == 0)
735 return;
736 *timings = ((*timings) & ~TR_133_PIOREG_PIO_MASK) | tr;
737 break;
738 }
739 case controller_un_ata6:
740 case controller_k2_ata6: {
741 /* 100Mhz cell */
742 u32 tr = kauai_lookup_timing(kauai_pio_timings, d.cycle_time);
743 if (tr == 0)
744 return;
745 *timings = ((*timings) & ~TR_100_PIOREG_PIO_MASK) | tr;
746 break;
747 }
748 case controller_kl_ata4:
749 /* 66Mhz cell */
750 recTime = d.cycle_time - ide_pio_timings[pio].active_time
751 - ide_pio_timings[pio].setup_time;
752 recTime = max(recTime, 150U);
753 accessTime = ide_pio_timings[pio].active_time;
754 accessTime = max(accessTime, 150U);
755 accessTicks = SYSCLK_TICKS_66(accessTime);
756 accessTicks = min(accessTicks, 0x1fU);
757 recTicks = SYSCLK_TICKS_66(recTime);
758 recTicks = min(recTicks, 0x1fU);
759 *timings = ((*timings) & ~TR_66_PIO_MASK) |
760 (accessTicks << TR_66_PIO_ACCESS_SHIFT) |
761 (recTicks << TR_66_PIO_RECOVERY_SHIFT);
762 break;
763 default: {
764 /* 33Mhz cell */
765 int ebit = 0;
766 recTime = d.cycle_time - ide_pio_timings[pio].active_time
767 - ide_pio_timings[pio].setup_time;
768 recTime = max(recTime, 150U);
769 accessTime = ide_pio_timings[pio].active_time;
770 accessTime = max(accessTime, 150U);
771 accessTicks = SYSCLK_TICKS(accessTime);
772 accessTicks = min(accessTicks, 0x1fU);
773 accessTicks = max(accessTicks, 4U);
774 recTicks = SYSCLK_TICKS(recTime);
775 recTicks = min(recTicks, 0x1fU);
776 recTicks = max(recTicks, 5U) - 4;
777 if (recTicks > 9) {
778 recTicks--; /* guess, but it's only for PIO0, so... */
779 ebit = 1;
780 }
781 *timings = ((*timings) & ~TR_33_PIO_MASK) |
782 (accessTicks << TR_33_PIO_ACCESS_SHIFT) |
783 (recTicks << TR_33_PIO_RECOVERY_SHIFT);
784 if (ebit)
785 *timings |= TR_33_PIO_E;
786 break;
787 }
788 }
789
790#ifdef IDE_PMAC_DEBUG
791 printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n",
792 drive->name, pio, *timings);
793#endif
794
795 if (drive->select.all == HWIF(drive)->INB(IDE_SELECT_REG))
796 pmac_ide_do_update_timings(drive);
797}
798
799#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
800
801/*
802 * Calculate KeyLargo ATA/66 UDMA timings
803 */
804static int __pmac
805set_timings_udma_ata4(u32 *timings, u8 speed)
806{
807 unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks;
808
809 if (speed > XFER_UDMA_4)
810 return 1;
811
812 rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause);
813 wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup);
814 addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup);
815
816 *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) |
817 (wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) |
818 (rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) |
819 (addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) |
820 TR_66_UDMA_EN;
821#ifdef IDE_PMAC_DEBUG
822 printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
823 speed & 0xf, *timings);
824#endif
825
826 return 0;
827}
828
829/*
830 * Calculate Kauai ATA/100 UDMA timings
831 */
832static int __pmac
833set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed)
834{
835 struct ide_timing *t = ide_timing_find_mode(speed);
836 u32 tr;
837
838 if (speed > XFER_UDMA_5 || t == NULL)
839 return 1;
840 tr = kauai_lookup_timing(kauai_udma_timings, (int)t->udma);
841 if (tr == 0)
842 return 1;
843 *ultra_timings = ((*ultra_timings) & ~TR_100_UDMAREG_UDMA_MASK) | tr;
844 *ultra_timings = (*ultra_timings) | TR_100_UDMAREG_UDMA_EN;
845
846 return 0;
847}
848
849/*
850 * Calculate Shasta ATA/133 UDMA timings
851 */
852static int __pmac
853set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed)
854{
855 struct ide_timing *t = ide_timing_find_mode(speed);
856 u32 tr;
857
858 if (speed > XFER_UDMA_6 || t == NULL)
859 return 1;
860 tr = kauai_lookup_timing(shasta_udma133_timings, (int)t->udma);
861 if (tr == 0)
862 return 1;
863 *ultra_timings = ((*ultra_timings) & ~TR_133_UDMAREG_UDMA_MASK) | tr;
864 *ultra_timings = (*ultra_timings) | TR_133_UDMAREG_UDMA_EN;
865
866 return 0;
867}
868
869/*
870 * Calculate MDMA timings for all cells
871 */
872static int __pmac
873set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
874 u8 speed, int drive_cycle_time)
875{
876 int cycleTime, accessTime = 0, recTime = 0;
877 unsigned accessTicks, recTicks;
878 struct mdma_timings_t* tm = NULL;
879 int i;
880
881 /* Get default cycle time for mode */
882 switch(speed & 0xf) {
883 case 0: cycleTime = 480; break;
884 case 1: cycleTime = 150; break;
885 case 2: cycleTime = 120; break;
886 default:
887 return 1;
888 }
889 /* Adjust for drive */
890 if (drive_cycle_time && drive_cycle_time > cycleTime)
891 cycleTime = drive_cycle_time;
892 /* OHare limits according to some old Apple sources */
893 if ((intf_type == controller_ohare) && (cycleTime < 150))
894 cycleTime = 150;
895 /* Get the proper timing array for this controller */
896 switch(intf_type) {
897 case controller_sh_ata6:
898 case controller_un_ata6:
899 case controller_k2_ata6:
900 break;
901 case controller_kl_ata4:
902 tm = mdma_timings_66;
903 break;
904 case controller_kl_ata3:
905 tm = mdma_timings_33k;
906 break;
907 default:
908 tm = mdma_timings_33;
909 break;
910 }
911 if (tm != NULL) {
912 /* Lookup matching access & recovery times */
913 i = -1;
914 for (;;) {
915 if (tm[i+1].cycleTime < cycleTime)
916 break;
917 i++;
918 }
919 if (i < 0)
920 return 1;
921 cycleTime = tm[i].cycleTime;
922 accessTime = tm[i].accessTime;
923 recTime = tm[i].recoveryTime;
924
925#ifdef IDE_PMAC_DEBUG
926 printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
927 drive->name, cycleTime, accessTime, recTime);
928#endif
929 }
930 switch(intf_type) {
931 case controller_sh_ata6: {
932 /* 133Mhz cell */
933 u32 tr = kauai_lookup_timing(shasta_mdma_timings, cycleTime);
934 if (tr == 0)
935 return 1;
936 *timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr;
937 *timings2 = (*timings2) & ~TR_133_UDMAREG_UDMA_EN;
938 }
939 case controller_un_ata6:
940 case controller_k2_ata6: {
941 /* 100Mhz cell */
942 u32 tr = kauai_lookup_timing(kauai_mdma_timings, cycleTime);
943 if (tr == 0)
944 return 1;
945 *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr;
946 *timings2 = (*timings2) & ~TR_100_UDMAREG_UDMA_EN;
947 }
948 break;
949 case controller_kl_ata4:
950 /* 66Mhz cell */
951 accessTicks = SYSCLK_TICKS_66(accessTime);
952 accessTicks = min(accessTicks, 0x1fU);
953 accessTicks = max(accessTicks, 0x1U);
954 recTicks = SYSCLK_TICKS_66(recTime);
955 recTicks = min(recTicks, 0x1fU);
956 recTicks = max(recTicks, 0x3U);
957 /* Clear out mdma bits and disable udma */
958 *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) |
959 (accessTicks << TR_66_MDMA_ACCESS_SHIFT) |
960 (recTicks << TR_66_MDMA_RECOVERY_SHIFT);
961 break;
962 case controller_kl_ata3:
963 /* 33Mhz cell on KeyLargo */
964 accessTicks = SYSCLK_TICKS(accessTime);
965 accessTicks = max(accessTicks, 1U);
966 accessTicks = min(accessTicks, 0x1fU);
967 accessTime = accessTicks * IDE_SYSCLK_NS;
968 recTicks = SYSCLK_TICKS(recTime);
969 recTicks = max(recTicks, 1U);
970 recTicks = min(recTicks, 0x1fU);
971 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
972 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
973 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
974 break;
975 default: {
976 /* 33Mhz cell on others */
977 int halfTick = 0;
978 int origAccessTime = accessTime;
979 int origRecTime = recTime;
980
981 accessTicks = SYSCLK_TICKS(accessTime);
982 accessTicks = max(accessTicks, 1U);
983 accessTicks = min(accessTicks, 0x1fU);
984 accessTime = accessTicks * IDE_SYSCLK_NS;
985 recTicks = SYSCLK_TICKS(recTime);
986 recTicks = max(recTicks, 2U) - 1;
987 recTicks = min(recTicks, 0x1fU);
988 recTime = (recTicks + 1) * IDE_SYSCLK_NS;
989 if ((accessTicks > 1) &&
990 ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) &&
991 ((recTime - IDE_SYSCLK_NS/2) >= origRecTime)) {
992 halfTick = 1;
993 accessTicks--;
994 }
995 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
996 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
997 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
998 if (halfTick)
999 *timings |= TR_33_MDMA_HALFTICK;
1000 }
1001 }
1002#ifdef IDE_PMAC_DEBUG
1003 printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
1004 drive->name, speed & 0xf, *timings);
1005#endif
1006 return 0;
1007}
1008#endif /* #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC */
1009
1010/*
1011 * Speedproc. This function is called by the core to set any of the standard
1012 * timing (PIO, MDMA or UDMA) to both the drive and the controller.
1013 * You may notice we don't use this function on normal "dma check" operation,
1014 * our dedicated function is more precise as it uses the drive provided
1015 * cycle time value. We should probably fix this one to deal with that too...
1016 */
1017static int __pmac
1018pmac_ide_tune_chipset (ide_drive_t *drive, byte speed)
1019{
1020 int unit = (drive->select.b.unit & 0x01);
1021 int ret = 0;
1022 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1023 u32 *timings, *timings2;
1024
1025 if (pmif == NULL)
1026 return 1;
1027
1028 timings = &pmif->timings[unit];
1029 timings2 = &pmif->timings[unit+2];
1030
1031 switch(speed) {
1032#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1033 case XFER_UDMA_6:
1034 if (pmif->kind != controller_sh_ata6)
1035 return 1;
1036 case XFER_UDMA_5:
1037 if (pmif->kind != controller_un_ata6 &&
1038 pmif->kind != controller_k2_ata6 &&
1039 pmif->kind != controller_sh_ata6)
1040 return 1;
1041 case XFER_UDMA_4:
1042 case XFER_UDMA_3:
1043 if (HWIF(drive)->udma_four == 0)
1044 return 1;
1045 case XFER_UDMA_2:
1046 case XFER_UDMA_1:
1047 case XFER_UDMA_0:
1048 if (pmif->kind == controller_kl_ata4)
1049 ret = set_timings_udma_ata4(timings, speed);
1050 else if (pmif->kind == controller_un_ata6
1051 || pmif->kind == controller_k2_ata6)
1052 ret = set_timings_udma_ata6(timings, timings2, speed);
1053 else if (pmif->kind == controller_sh_ata6)
1054 ret = set_timings_udma_shasta(timings, timings2, speed);
1055 else
1056 ret = 1;
1057 break;
1058 case XFER_MW_DMA_2:
1059 case XFER_MW_DMA_1:
1060 case XFER_MW_DMA_0:
1061 ret = set_timings_mdma(drive, pmif->kind, timings, timings2, speed, 0);
1062 break;
1063 case XFER_SW_DMA_2:
1064 case XFER_SW_DMA_1:
1065 case XFER_SW_DMA_0:
1066 return 1;
1067#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1068 case XFER_PIO_4:
1069 case XFER_PIO_3:
1070 case XFER_PIO_2:
1071 case XFER_PIO_1:
1072 case XFER_PIO_0:
1073 pmac_ide_tuneproc(drive, speed & 0x07);
1074 break;
1075 default:
1076 ret = 1;
1077 }
1078 if (ret)
1079 return ret;
1080
1081 ret = pmac_ide_do_setfeature(drive, speed);
1082 if (ret)
1083 return ret;
1084
1085 pmac_ide_do_update_timings(drive);
1086 drive->current_speed = speed;
1087
1088 return 0;
1089}
1090
1091/*
1092 * Blast some well known "safe" values to the timing registers at init or
1093 * wakeup from sleep time, before we do real calculation
1094 */
1095static void __pmac
1096sanitize_timings(pmac_ide_hwif_t *pmif)
1097{
1098 unsigned int value, value2 = 0;
1099
1100 switch(pmif->kind) {
1101 case controller_sh_ata6:
1102 value = 0x0a820c97;
1103 value2 = 0x00033031;
1104 break;
1105 case controller_un_ata6:
1106 case controller_k2_ata6:
1107 value = 0x08618a92;
1108 value2 = 0x00002921;
1109 break;
1110 case controller_kl_ata4:
1111 value = 0x0008438c;
1112 break;
1113 case controller_kl_ata3:
1114 value = 0x00084526;
1115 break;
1116 case controller_heathrow:
1117 case controller_ohare:
1118 default:
1119 value = 0x00074526;
1120 break;
1121 }
1122 pmif->timings[0] = pmif->timings[1] = value;
1123 pmif->timings[2] = pmif->timings[3] = value2;
1124}
1125
1126unsigned long __pmac
1127pmac_ide_get_base(int index)
1128{
1129 return pmac_ide[index].regbase;
1130}
1131
1132int __pmac
1133pmac_ide_check_base(unsigned long base)
1134{
1135 int ix;
1136
1137 for (ix = 0; ix < MAX_HWIFS; ++ix)
1138 if (base == pmac_ide[ix].regbase)
1139 return ix;
1140 return -1;
1141}
1142
1143int __pmac
1144pmac_ide_get_irq(unsigned long base)
1145{
1146 int ix;
1147
1148 for (ix = 0; ix < MAX_HWIFS; ++ix)
1149 if (base == pmac_ide[ix].regbase)
1150 return pmac_ide[ix].irq;
1151 return 0;
1152}
1153
1154static int ide_majors[] __pmacdata = { 3, 22, 33, 34, 56, 57 };
1155
1156dev_t __init
1157pmac_find_ide_boot(char *bootdevice, int n)
1158{
1159 int i;
1160
1161 /*
1162 * Look through the list of IDE interfaces for this one.
1163 */
1164 for (i = 0; i < pmac_ide_count; ++i) {
1165 char *name;
1166 if (!pmac_ide[i].node || !pmac_ide[i].node->full_name)
1167 continue;
1168 name = pmac_ide[i].node->full_name;
1169 if (memcmp(name, bootdevice, n) == 0 && name[n] == 0) {
1170 /* XXX should cope with the 2nd drive as well... */
1171 return MKDEV(ide_majors[i], 0);
1172 }
1173 }
1174
1175 return 0;
1176}
1177
1178/* Suspend call back, should be called after the child devices
1179 * have actually been suspended
1180 */
1181static int
1182pmac_ide_do_suspend(ide_hwif_t *hwif)
1183{
1184 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1185
1186 /* We clear the timings */
1187 pmif->timings[0] = 0;
1188 pmif->timings[1] = 0;
1189
1190#ifdef CONFIG_BLK_DEV_IDE_PMAC_BLINK
1191 /* Note: This code will be called for every hwif, thus we'll
1192 * try several time to stop the LED blinker timer, but that
1193 * should be harmless
1194 */
1195 if (pmu_ide_blink_enabled) {
1196 unsigned long flags;
1197
1198 /* Make sure we don't hit the PMU blink */
1199 spin_lock_irqsave(&pmu_blink_lock, flags);
1200 if (pmu_blink_ledstate)
1201 del_timer(&pmu_blink_timer);
1202 pmu_blink_ledstate = 0;
1203 spin_unlock_irqrestore(&pmu_blink_lock, flags);
1204 }
1205#endif /* CONFIG_BLK_DEV_IDE_PMAC_BLINK */
1206
1207 /* The media bay will handle itself just fine */
1208 if (pmif->mediabay)
1209 return 0;
1210
1211 /* Kauai has bus control FCRs directly here */
1212 if (pmif->kauai_fcr) {
1213 u32 fcr = readl(pmif->kauai_fcr);
1214 fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
1215 writel(fcr, pmif->kauai_fcr);
1216 }
1217
1218 /* Disable the bus on older machines and the cell on kauai */
1219 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id,
1220 0);
1221
1222 return 0;
1223}
1224
1225/* Resume call back, should be called before the child devices
1226 * are resumed
1227 */
1228static int
1229pmac_ide_do_resume(ide_hwif_t *hwif)
1230{
1231 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1232
1233 /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
1234 if (!pmif->mediabay) {
1235 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1);
1236 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1);
1237 msleep(10);
1238 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0);
1239 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1240
1241 /* Kauai has it different */
1242 if (pmif->kauai_fcr) {
1243 u32 fcr = readl(pmif->kauai_fcr);
1244 fcr |= KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE;
1245 writel(fcr, pmif->kauai_fcr);
1246 }
1247 }
1248
1249 /* Sanitize drive timings */
1250 sanitize_timings(pmif);
1251
1252 return 0;
1253}
1254
1255/*
1256 * Setup, register & probe an IDE channel driven by this driver, this is
1257 * called by one of the 2 probe functions (macio or PCI). Note that a channel
1258 * that ends up beeing free of any device is not kept around by this driver
1259 * (it is kept in 2.4). This introduce an interface numbering change on some
1260 * rare machines unfortunately, but it's better this way.
1261 */
1262static int
1263pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif)
1264{
1265 struct device_node *np = pmif->node;
1266 int *bidp, i;
1267
1268 pmif->cable_80 = 0;
1269 pmif->broken_dma = pmif->broken_dma_warn = 0;
1270 if (device_is_compatible(np, "shasta-ata"))
1271 pmif->kind = controller_sh_ata6;
1272 else if (device_is_compatible(np, "kauai-ata"))
1273 pmif->kind = controller_un_ata6;
1274 else if (device_is_compatible(np, "K2-UATA"))
1275 pmif->kind = controller_k2_ata6;
1276 else if (device_is_compatible(np, "keylargo-ata")) {
1277 if (strcmp(np->name, "ata-4") == 0)
1278 pmif->kind = controller_kl_ata4;
1279 else
1280 pmif->kind = controller_kl_ata3;
1281 } else if (device_is_compatible(np, "heathrow-ata"))
1282 pmif->kind = controller_heathrow;
1283 else {
1284 pmif->kind = controller_ohare;
1285 pmif->broken_dma = 1;
1286 }
1287
1288 bidp = (int *)get_property(np, "AAPL,bus-id", NULL);
1289 pmif->aapl_bus_id = bidp ? *bidp : 0;
1290
1291 /* Get cable type from device-tree */
1292 if (pmif->kind == controller_kl_ata4 || pmif->kind == controller_un_ata6
1293 || pmif->kind == controller_k2_ata6
1294 || pmif->kind == controller_sh_ata6) {
1295 char* cable = get_property(np, "cable-type", NULL);
1296 if (cable && !strncmp(cable, "80-", 3))
1297 pmif->cable_80 = 1;
1298 }
1299 /* G5's seem to have incorrect cable type in device-tree. Let's assume
1300 * they have a 80 conductor cable, this seem to be always the case unless
1301 * the user mucked around
1302 */
1303 if (device_is_compatible(np, "K2-UATA") ||
1304 device_is_compatible(np, "shasta-ata"))
1305 pmif->cable_80 = 1;
1306
1307 /* On Kauai-type controllers, we make sure the FCR is correct */
1308 if (pmif->kauai_fcr)
1309 writel(KAUAI_FCR_UATA_MAGIC |
1310 KAUAI_FCR_UATA_RESET_N |
1311 KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr);
1312
1313 pmif->mediabay = 0;
1314
1315 /* Make sure we have sane timings */
1316 sanitize_timings(pmif);
1317
1318#ifndef CONFIG_PPC64
1319 /* XXX FIXME: Media bay stuff need re-organizing */
1320 if (np->parent && np->parent->name
1321 && strcasecmp(np->parent->name, "media-bay") == 0) {
1322#ifdef CONFIG_PMAC_PBOOK
1323 media_bay_set_ide_infos(np->parent, pmif->regbase, pmif->irq, hwif->index);
1324#endif /* CONFIG_PMAC_PBOOK */
1325 pmif->mediabay = 1;
1326 if (!bidp)
1327 pmif->aapl_bus_id = 1;
1328 } else if (pmif->kind == controller_ohare) {
1329 /* The code below is having trouble on some ohare machines
1330 * (timing related ?). Until I can put my hand on one of these
1331 * units, I keep the old way
1332 */
1333 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1);
1334 } else
1335#endif
1336 {
1337 /* This is necessary to enable IDE when net-booting */
1338 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1);
1339 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1);
1340 msleep(10);
1341 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0);
1342 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1343 }
1344
1345 /* Setup MMIO ops */
1346 default_hwif_mmiops(hwif);
1347 hwif->OUTBSYNC = pmac_outbsync;
1348
1349 /* Tell common code _not_ to mess with resources */
1350 hwif->mmio = 2;
1351 hwif->hwif_data = pmif;
1352 pmac_ide_init_hwif_ports(&hwif->hw, pmif->regbase, 0, &hwif->irq);
1353 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
1354 hwif->chipset = ide_pmac;
1355 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET] || pmif->mediabay;
1356 hwif->hold = pmif->mediabay;
1357 hwif->udma_four = pmif->cable_80;
1358 hwif->drives[0].unmask = 1;
1359 hwif->drives[1].unmask = 1;
1360 hwif->tuneproc = pmac_ide_tuneproc;
1361 if (pmif->kind == controller_un_ata6
1362 || pmif->kind == controller_k2_ata6
1363 || pmif->kind == controller_sh_ata6)
1364 hwif->selectproc = pmac_ide_kauai_selectproc;
1365 else
1366 hwif->selectproc = pmac_ide_selectproc;
1367 hwif->speedproc = pmac_ide_tune_chipset;
1368
1369#ifdef CONFIG_BLK_DEV_IDE_PMAC_BLINK
1370 pmu_ide_blink_enabled = pmu_hd_blink_init();
1371
1372 if (pmu_ide_blink_enabled)
1373 hwif->led_act = pmu_hd_kick_blink;
1374#endif
1375
1376 printk(KERN_INFO "ide%d: Found Apple %s controller, bus ID %d%s, irq %d\n",
1377 hwif->index, model_name[pmif->kind], pmif->aapl_bus_id,
1378 pmif->mediabay ? " (mediabay)" : "", hwif->irq);
1379
1380#ifdef CONFIG_PMAC_PBOOK
1381 if (pmif->mediabay && check_media_bay_by_base(pmif->regbase, MB_CD) == 0)
1382 hwif->noprobe = 0;
1383#endif /* CONFIG_PMAC_PBOOK */
1384
1385 hwif->sg_max_nents = MAX_DCMDS;
1386
1387#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1388 /* has a DBDMA controller channel */
1389 if (pmif->dma_regs)
1390 pmac_ide_setup_dma(pmif, hwif);
1391#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1392
1393 /* We probe the hwif now */
1394 probe_hwif_init(hwif);
1395
1396 /* The code IDE code will have set hwif->present if we have devices attached,
1397 * if we don't, the discard the interface except if we are on a media bay slot
1398 */
1399 if (!hwif->present && !pmif->mediabay) {
1400 printk(KERN_INFO "ide%d: Bus empty, interface released.\n",
1401 hwif->index);
1402 default_hwif_iops(hwif);
1403 for (i = IDE_DATA_OFFSET; i <= IDE_CONTROL_OFFSET; ++i)
1404 hwif->io_ports[i] = 0;
1405 hwif->chipset = ide_unknown;
1406 hwif->noprobe = 1;
1407 return -ENODEV;
1408 }
1409
1410 return 0;
1411}
1412
1413/*
1414 * Attach to a macio probed interface
1415 */
1416static int __devinit
1417pmac_ide_macio_attach(struct macio_dev *mdev, const struct of_match *match)
1418{
1419 void __iomem *base;
1420 unsigned long regbase;
1421 int irq;
1422 ide_hwif_t *hwif;
1423 pmac_ide_hwif_t *pmif;
1424 int i, rc;
1425
1426 i = 0;
1427 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1428 || pmac_ide[i].node != NULL))
1429 ++i;
1430 if (i >= MAX_HWIFS) {
1431 printk(KERN_ERR "ide-pmac: MacIO interface attach with no slot\n");
1432 printk(KERN_ERR " %s\n", mdev->ofdev.node->full_name);
1433 return -ENODEV;
1434 }
1435
1436 pmif = &pmac_ide[i];
1437 hwif = &ide_hwifs[i];
1438
1439 if (mdev->ofdev.node->n_addrs == 0) {
1440 printk(KERN_WARNING "ide%d: no address for %s\n",
1441 i, mdev->ofdev.node->full_name);
1442 return -ENXIO;
1443 }
1444
1445 /* Request memory resource for IO ports */
1446 if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) {
1447 printk(KERN_ERR "ide%d: can't request mmio resource !\n", i);
1448 return -EBUSY;
1449 }
1450
1451 /* XXX This is bogus. Should be fixed in the registry by checking
1452 * the kind of host interrupt controller, a bit like gatwick
1453 * fixes in irq.c. That works well enough for the single case
1454 * where that happens though...
1455 */
1456 if (macio_irq_count(mdev) == 0) {
1457 printk(KERN_WARNING "ide%d: no intrs for device %s, using 13\n",
1458 i, mdev->ofdev.node->full_name);
1459 irq = 13;
1460 } else
1461 irq = macio_irq(mdev, 0);
1462
1463 base = ioremap(macio_resource_start(mdev, 0), 0x400);
1464 regbase = (unsigned long) base;
1465
1466 hwif->pci_dev = mdev->bus->pdev;
1467 hwif->gendev.parent = &mdev->ofdev.dev;
1468
1469 pmif->mdev = mdev;
1470 pmif->node = mdev->ofdev.node;
1471 pmif->regbase = regbase;
1472 pmif->irq = irq;
1473 pmif->kauai_fcr = NULL;
1474#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1475 if (macio_resource_count(mdev) >= 2) {
1476 if (macio_request_resource(mdev, 1, "ide-pmac (dma)"))
1477 printk(KERN_WARNING "ide%d: can't request DMA resource !\n", i);
1478 else
1479 pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000);
1480 } else
1481 pmif->dma_regs = NULL;
1482#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1483 dev_set_drvdata(&mdev->ofdev.dev, hwif);
1484
1485 rc = pmac_ide_setup_device(pmif, hwif);
1486 if (rc != 0) {
1487 /* The inteface is released to the common IDE layer */
1488 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1489 iounmap(base);
1490 if (pmif->dma_regs)
1491 iounmap(pmif->dma_regs);
1492 memset(pmif, 0, sizeof(*pmif));
1493 macio_release_resource(mdev, 0);
1494 if (pmif->dma_regs)
1495 macio_release_resource(mdev, 1);
1496 }
1497
1498 return rc;
1499}
1500
1501static int
1502pmac_ide_macio_suspend(struct macio_dev *mdev, u32 state)
1503{
1504 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1505 int rc = 0;
1506
1507 if (state != mdev->ofdev.dev.power.power_state && state >= 2) {
1508 rc = pmac_ide_do_suspend(hwif);
1509 if (rc == 0)
1510 mdev->ofdev.dev.power.power_state = state;
1511 }
1512
1513 return rc;
1514}
1515
1516static int
1517pmac_ide_macio_resume(struct macio_dev *mdev)
1518{
1519 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1520 int rc = 0;
1521
1522 if (mdev->ofdev.dev.power.power_state != 0) {
1523 rc = pmac_ide_do_resume(hwif);
1524 if (rc == 0)
1525 mdev->ofdev.dev.power.power_state = 0;
1526 }
1527
1528 return rc;
1529}
1530
1531/*
1532 * Attach to a PCI probed interface
1533 */
1534static int __devinit
1535pmac_ide_pci_attach(struct pci_dev *pdev, const struct pci_device_id *id)
1536{
1537 ide_hwif_t *hwif;
1538 struct device_node *np;
1539 pmac_ide_hwif_t *pmif;
1540 void __iomem *base;
1541 unsigned long rbase, rlen;
1542 int i, rc;
1543
1544 np = pci_device_to_OF_node(pdev);
1545 if (np == NULL) {
1546 printk(KERN_ERR "ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
1547 return -ENODEV;
1548 }
1549 i = 0;
1550 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1551 || pmac_ide[i].node != NULL))
1552 ++i;
1553 if (i >= MAX_HWIFS) {
1554 printk(KERN_ERR "ide-pmac: PCI interface attach with no slot\n");
1555 printk(KERN_ERR " %s\n", np->full_name);
1556 return -ENODEV;
1557 }
1558
1559 pmif = &pmac_ide[i];
1560 hwif = &ide_hwifs[i];
1561
1562 if (pci_enable_device(pdev)) {
1563 printk(KERN_WARNING "ide%i: Can't enable PCI device for %s\n",
1564 i, np->full_name);
1565 return -ENXIO;
1566 }
1567 pci_set_master(pdev);
1568
1569 if (pci_request_regions(pdev, "Kauai ATA")) {
1570 printk(KERN_ERR "ide%d: Cannot obtain PCI resources for %s\n",
1571 i, np->full_name);
1572 return -ENXIO;
1573 }
1574
1575 hwif->pci_dev = pdev;
1576 hwif->gendev.parent = &pdev->dev;
1577 pmif->mdev = NULL;
1578 pmif->node = np;
1579
1580 rbase = pci_resource_start(pdev, 0);
1581 rlen = pci_resource_len(pdev, 0);
1582
1583 base = ioremap(rbase, rlen);
1584 pmif->regbase = (unsigned long) base + 0x2000;
1585#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1586 pmif->dma_regs = base + 0x1000;
1587#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1588 pmif->kauai_fcr = base;
1589 pmif->irq = pdev->irq;
1590
1591 pci_set_drvdata(pdev, hwif);
1592
1593 rc = pmac_ide_setup_device(pmif, hwif);
1594 if (rc != 0) {
1595 /* The inteface is released to the common IDE layer */
1596 pci_set_drvdata(pdev, NULL);
1597 iounmap(base);
1598 memset(pmif, 0, sizeof(*pmif));
1599 pci_release_regions(pdev);
1600 }
1601
1602 return rc;
1603}
1604
1605static int
1606pmac_ide_pci_suspend(struct pci_dev *pdev, u32 state)
1607{
1608 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1609 int rc = 0;
1610
1611 if (state != pdev->dev.power.power_state && state >= 2) {
1612 rc = pmac_ide_do_suspend(hwif);
1613 if (rc == 0)
1614 pdev->dev.power.power_state = state;
1615 }
1616
1617 return rc;
1618}
1619
1620static int
1621pmac_ide_pci_resume(struct pci_dev *pdev)
1622{
1623 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1624 int rc = 0;
1625
1626 if (pdev->dev.power.power_state != 0) {
1627 rc = pmac_ide_do_resume(hwif);
1628 if (rc == 0)
1629 pdev->dev.power.power_state = 0;
1630 }
1631
1632 return rc;
1633}
1634
1635static struct of_match pmac_ide_macio_match[] =
1636{
1637 {
1638 .name = "IDE",
1639 .type = OF_ANY_MATCH,
1640 .compatible = OF_ANY_MATCH
1641 },
1642 {
1643 .name = "ATA",
1644 .type = OF_ANY_MATCH,
1645 .compatible = OF_ANY_MATCH
1646 },
1647 {
1648 .name = OF_ANY_MATCH,
1649 .type = "ide",
1650 .compatible = OF_ANY_MATCH
1651 },
1652 {
1653 .name = OF_ANY_MATCH,
1654 .type = "ata",
1655 .compatible = OF_ANY_MATCH
1656 },
1657 {},
1658};
1659
1660static struct macio_driver pmac_ide_macio_driver =
1661{
1662 .name = "ide-pmac",
1663 .match_table = pmac_ide_macio_match,
1664 .probe = pmac_ide_macio_attach,
1665 .suspend = pmac_ide_macio_suspend,
1666 .resume = pmac_ide_macio_resume,
1667};
1668
1669static struct pci_device_id pmac_ide_pci_match[] = {
1670 { PCI_VENDOR_ID_APPLE, PCI_DEVIEC_ID_APPLE_UNI_N_ATA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1671 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1672 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1673 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_ATA,
1674 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1675};
1676
1677static struct pci_driver pmac_ide_pci_driver = {
1678 .name = "ide-pmac",
1679 .id_table = pmac_ide_pci_match,
1680 .probe = pmac_ide_pci_attach,
1681 .suspend = pmac_ide_pci_suspend,
1682 .resume = pmac_ide_pci_resume,
1683};
1684MODULE_DEVICE_TABLE(pci, pmac_ide_pci_match);
1685
1686void __init
1687pmac_ide_probe(void)
1688{
1689 if (_machine != _MACH_Pmac)
1690 return;
1691
1692#ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
1693 pci_register_driver(&pmac_ide_pci_driver);
1694 macio_register_driver(&pmac_ide_macio_driver);
1695#else
1696 macio_register_driver(&pmac_ide_macio_driver);
1697 pci_register_driver(&pmac_ide_pci_driver);
1698#endif
1699}
1700
1701#ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1702
1703/*
1704 * pmac_ide_build_dmatable builds the DBDMA command list
1705 * for a transfer and sets the DBDMA channel to point to it.
1706 */
1707static int __pmac
1708pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq)
1709{
1710 struct dbdma_cmd *table;
1711 int i, count = 0;
1712 ide_hwif_t *hwif = HWIF(drive);
1713 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1714 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1715 struct scatterlist *sg;
1716 int wr = (rq_data_dir(rq) == WRITE);
1717
1718 /* DMA table is already aligned */
1719 table = (struct dbdma_cmd *) pmif->dma_table_cpu;
1720
1721 /* Make sure DMA controller is stopped (necessary ?) */
1722 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control);
1723 while (readl(&dma->status) & RUN)
1724 udelay(1);
1725
1726 hwif->sg_nents = i = ide_build_sglist(drive, rq);
1727
1728 if (!i)
1729 return 0;
1730
1731 /* Build DBDMA commands list */
1732 sg = hwif->sg_table;
1733 while (i && sg_dma_len(sg)) {
1734 u32 cur_addr;
1735 u32 cur_len;
1736
1737 cur_addr = sg_dma_address(sg);
1738 cur_len = sg_dma_len(sg);
1739
1740 if (pmif->broken_dma && cur_addr & (L1_CACHE_BYTES - 1)) {
1741 if (pmif->broken_dma_warn == 0) {
1742 printk(KERN_WARNING "%s: DMA on non aligned address,"
1743 "switching to PIO on Ohare chipset\n", drive->name);
1744 pmif->broken_dma_warn = 1;
1745 }
1746 goto use_pio_instead;
1747 }
1748 while (cur_len) {
1749 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
1750
1751 if (count++ >= MAX_DCMDS) {
1752 printk(KERN_WARNING "%s: DMA table too small\n",
1753 drive->name);
1754 goto use_pio_instead;
1755 }
1756 st_le16(&table->command, wr? OUTPUT_MORE: INPUT_MORE);
1757 st_le16(&table->req_count, tc);
1758 st_le32(&table->phy_addr, cur_addr);
1759 table->cmd_dep = 0;
1760 table->xfer_status = 0;
1761 table->res_count = 0;
1762 cur_addr += tc;
1763 cur_len -= tc;
1764 ++table;
1765 }
1766 sg++;
1767 i--;
1768 }
1769
1770 /* convert the last command to an input/output last command */
1771 if (count) {
1772 st_le16(&table[-1].command, wr? OUTPUT_LAST: INPUT_LAST);
1773 /* add the stop command to the end of the list */
1774 memset(table, 0, sizeof(struct dbdma_cmd));
1775 st_le16(&table->command, DBDMA_STOP);
1776 mb();
1777 writel(hwif->dmatable_dma, &dma->cmdptr);
1778 return 1;
1779 }
1780
1781 printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name);
1782 use_pio_instead:
1783 pci_unmap_sg(hwif->pci_dev,
1784 hwif->sg_table,
1785 hwif->sg_nents,
1786 hwif->sg_dma_direction);
1787 return 0; /* revert to PIO for this request */
1788}
1789
1790/* Teardown mappings after DMA has completed. */
1791static void __pmac
1792pmac_ide_destroy_dmatable (ide_drive_t *drive)
1793{
1794 ide_hwif_t *hwif = drive->hwif;
1795 struct pci_dev *dev = HWIF(drive)->pci_dev;
1796 struct scatterlist *sg = hwif->sg_table;
1797 int nents = hwif->sg_nents;
1798
1799 if (nents) {
1800 pci_unmap_sg(dev, sg, nents, hwif->sg_dma_direction);
1801 hwif->sg_nents = 0;
1802 }
1803}
1804
1805/*
1806 * Pick up best MDMA timing for the drive and apply it
1807 */
1808static int __pmac
1809pmac_ide_mdma_enable(ide_drive_t *drive, u16 mode)
1810{
1811 ide_hwif_t *hwif = HWIF(drive);
1812 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1813 int drive_cycle_time;
1814 struct hd_driveid *id = drive->id;
1815 u32 *timings, *timings2;
1816 u32 timing_local[2];
1817 int ret;
1818
1819 /* which drive is it ? */
1820 timings = &pmif->timings[drive->select.b.unit & 0x01];
1821 timings2 = &pmif->timings[(drive->select.b.unit & 0x01) + 2];
1822
1823 /* Check if drive provide explicit cycle time */
1824 if ((id->field_valid & 2) && (id->eide_dma_time))
1825 drive_cycle_time = id->eide_dma_time;
1826 else
1827 drive_cycle_time = 0;
1828
1829 /* Copy timings to local image */
1830 timing_local[0] = *timings;
1831 timing_local[1] = *timings2;
1832
1833 /* Calculate controller timings */
1834 ret = set_timings_mdma( drive, pmif->kind,
1835 &timing_local[0],
1836 &timing_local[1],
1837 mode,
1838 drive_cycle_time);
1839 if (ret)
1840 return 0;
1841
1842 /* Set feature on drive */
1843 printk(KERN_INFO "%s: Enabling MultiWord DMA %d\n", drive->name, mode & 0xf);
1844 ret = pmac_ide_do_setfeature(drive, mode);
1845 if (ret) {
1846 printk(KERN_WARNING "%s: Failed !\n", drive->name);
1847 return 0;
1848 }
1849
1850 /* Apply timings to controller */
1851 *timings = timing_local[0];
1852 *timings2 = timing_local[1];
1853
1854 /* Set speed info in drive */
1855 drive->current_speed = mode;
1856 if (!drive->init_speed)
1857 drive->init_speed = mode;
1858
1859 return 1;
1860}
1861
1862/*
1863 * Pick up best UDMA timing for the drive and apply it
1864 */
1865static int __pmac
1866pmac_ide_udma_enable(ide_drive_t *drive, u16 mode)
1867{
1868 ide_hwif_t *hwif = HWIF(drive);
1869 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1870 u32 *timings, *timings2;
1871 u32 timing_local[2];
1872 int ret;
1873
1874 /* which drive is it ? */
1875 timings = &pmif->timings[drive->select.b.unit & 0x01];
1876 timings2 = &pmif->timings[(drive->select.b.unit & 0x01) + 2];
1877
1878 /* Copy timings to local image */
1879 timing_local[0] = *timings;
1880 timing_local[1] = *timings2;
1881
1882 /* Calculate timings for interface */
1883 if (pmif->kind == controller_un_ata6
1884 || pmif->kind == controller_k2_ata6)
1885 ret = set_timings_udma_ata6( &timing_local[0],
1886 &timing_local[1],
1887 mode);
1888 else if (pmif->kind == controller_sh_ata6)
1889 ret = set_timings_udma_shasta( &timing_local[0],
1890 &timing_local[1],
1891 mode);
1892 else
1893 ret = set_timings_udma_ata4(&timing_local[0], mode);
1894 if (ret)
1895 return 0;
1896
1897 /* Set feature on drive */
1898 printk(KERN_INFO "%s: Enabling Ultra DMA %d\n", drive->name, mode & 0x0f);
1899 ret = pmac_ide_do_setfeature(drive, mode);
1900 if (ret) {
1901 printk(KERN_WARNING "%s: Failed !\n", drive->name);
1902 return 0;
1903 }
1904
1905 /* Apply timings to controller */
1906 *timings = timing_local[0];
1907 *timings2 = timing_local[1];
1908
1909 /* Set speed info in drive */
1910 drive->current_speed = mode;
1911 if (!drive->init_speed)
1912 drive->init_speed = mode;
1913
1914 return 1;
1915}
1916
1917/*
1918 * Check what is the best DMA timing setting for the drive and
1919 * call appropriate functions to apply it.
1920 */
1921static int __pmac
1922pmac_ide_dma_check(ide_drive_t *drive)
1923{
1924 struct hd_driveid *id = drive->id;
1925 ide_hwif_t *hwif = HWIF(drive);
1926 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1927 int enable = 1;
1928 int map;
1929 drive->using_dma = 0;
1930
1931 if (drive->media == ide_floppy)
1932 enable = 0;
1933 if (((id->capability & 1) == 0) && !__ide_dma_good_drive(drive))
1934 enable = 0;
1935 if (__ide_dma_bad_drive(drive))
1936 enable = 0;
1937
1938 if (enable) {
1939 short mode;
1940
1941 map = XFER_MWDMA;
1942 if (pmif->kind == controller_kl_ata4
1943 || pmif->kind == controller_un_ata6
1944 || pmif->kind == controller_k2_ata6
1945 || pmif->kind == controller_sh_ata6) {
1946 map |= XFER_UDMA;
1947 if (pmif->cable_80) {
1948 map |= XFER_UDMA_66;
1949 if (pmif->kind == controller_un_ata6 ||
1950 pmif->kind == controller_k2_ata6 ||
1951 pmif->kind == controller_sh_ata6)
1952 map |= XFER_UDMA_100;
1953 if (pmif->kind == controller_sh_ata6)
1954 map |= XFER_UDMA_133;
1955 }
1956 }
1957 mode = ide_find_best_mode(drive, map);
1958 if (mode & XFER_UDMA)
1959 drive->using_dma = pmac_ide_udma_enable(drive, mode);
1960 else if (mode & XFER_MWDMA)
1961 drive->using_dma = pmac_ide_mdma_enable(drive, mode);
1962 hwif->OUTB(0, IDE_CONTROL_REG);
1963 /* Apply settings to controller */
1964 pmac_ide_do_update_timings(drive);
1965 }
1966 return 0;
1967}
1968
1969/*
1970 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1971 * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
1972 */
1973static int __pmac
1974pmac_ide_dma_setup(ide_drive_t *drive)
1975{
1976 ide_hwif_t *hwif = HWIF(drive);
1977 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1978 struct request *rq = HWGROUP(drive)->rq;
1979 u8 unit = (drive->select.b.unit & 0x01);
1980 u8 ata4;
1981
1982 if (pmif == NULL)
1983 return 1;
1984 ata4 = (pmif->kind == controller_kl_ata4);
1985
1986 if (!pmac_ide_build_dmatable(drive, rq)) {
1987 ide_map_sg(drive, rq);
1988 return 1;
1989 }
1990
1991 /* Apple adds 60ns to wrDataSetup on reads */
1992 if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) {
1993 writel(pmif->timings[unit] + (!rq_data_dir(rq) ? 0x00800000UL : 0),
1994 PMAC_IDE_REG(IDE_TIMING_CONFIG));
1995 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
1996 }
1997
1998 drive->waiting_for_dma = 1;
1999
2000 return 0;
2001}
2002
2003static void __pmac
2004pmac_ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
2005{
2006 /* issue cmd to drive */
2007 ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, NULL);
2008}
2009
2010/*
2011 * Kick the DMA controller into life after the DMA command has been issued
2012 * to the drive.
2013 */
2014static void __pmac
2015pmac_ide_dma_start(ide_drive_t *drive)
2016{
2017 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
2018 volatile struct dbdma_regs __iomem *dma;
2019
2020 dma = pmif->dma_regs;
2021
2022 writel((RUN << 16) | RUN, &dma->control);
2023 /* Make sure it gets to the controller right now */
2024 (void)readl(&dma->control);
2025}
2026
2027/*
2028 * After a DMA transfer, make sure the controller is stopped
2029 */
2030static int __pmac
2031pmac_ide_dma_end (ide_drive_t *drive)
2032{
2033 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
2034 volatile struct dbdma_regs __iomem *dma;
2035 u32 dstat;
2036
2037 if (pmif == NULL)
2038 return 0;
2039 dma = pmif->dma_regs;
2040
2041 drive->waiting_for_dma = 0;
2042 dstat = readl(&dma->status);
2043 writel(((RUN|WAKE|DEAD) << 16), &dma->control);
2044 pmac_ide_destroy_dmatable(drive);
2045 /* verify good dma status. we don't check for ACTIVE beeing 0. We should...
2046 * in theory, but with ATAPI decices doing buffer underruns, that would
2047 * cause us to disable DMA, which isn't what we want
2048 */
2049 return (dstat & (RUN|DEAD)) != RUN;
2050}
2051
2052/*
2053 * Check out that the interrupt we got was for us. We can't always know this
2054 * for sure with those Apple interfaces (well, we could on the recent ones but
2055 * that's not implemented yet), on the other hand, we don't have shared interrupts
2056 * so it's not really a problem
2057 */
2058static int __pmac
2059pmac_ide_dma_test_irq (ide_drive_t *drive)
2060{
2061 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
2062 volatile struct dbdma_regs __iomem *dma;
2063 unsigned long status, timeout;
2064
2065 if (pmif == NULL)
2066 return 0;
2067 dma = pmif->dma_regs;
2068
2069 /* We have to things to deal with here:
2070 *
2071 * - The dbdma won't stop if the command was started
2072 * but completed with an error without transferring all
2073 * datas. This happens when bad blocks are met during
2074 * a multi-block transfer.
2075 *
2076 * - The dbdma fifo hasn't yet finished flushing to
2077 * to system memory when the disk interrupt occurs.
2078 *
2079 */
2080
2081 /* If ACTIVE is cleared, the STOP command have passed and
2082 * transfer is complete.
2083 */
2084 status = readl(&dma->status);
2085 if (!(status & ACTIVE))
2086 return 1;
2087 if (!drive->waiting_for_dma)
2088 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
2089 called while not waiting\n", HWIF(drive)->index);
2090
2091 /* If dbdma didn't execute the STOP command yet, the
2092 * active bit is still set. We consider that we aren't
2093 * sharing interrupts (which is hopefully the case with
2094 * those controllers) and so we just try to flush the
2095 * channel for pending data in the fifo
2096 */
2097 udelay(1);
2098 writel((FLUSH << 16) | FLUSH, &dma->control);
2099 timeout = 0;
2100 for (;;) {
2101 udelay(1);
2102 status = readl(&dma->status);
2103 if ((status & FLUSH) == 0)
2104 break;
2105 if (++timeout > 100) {
2106 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
2107 timeout flushing channel\n", HWIF(drive)->index);
2108 break;
2109 }
2110 }
2111 return 1;
2112}
2113
2114static int __pmac
2115pmac_ide_dma_host_off (ide_drive_t *drive)
2116{
2117 return 0;
2118}
2119
2120static int __pmac
2121pmac_ide_dma_host_on (ide_drive_t *drive)
2122{
2123 return 0;
2124}
2125
2126static int __pmac
2127pmac_ide_dma_lostirq (ide_drive_t *drive)
2128{
2129 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
2130 volatile struct dbdma_regs __iomem *dma;
2131 unsigned long status;
2132
2133 if (pmif == NULL)
2134 return 0;
2135 dma = pmif->dma_regs;
2136
2137 status = readl(&dma->status);
2138 printk(KERN_ERR "ide-pmac lost interrupt, dma status: %lx\n", status);
2139 return 0;
2140}
2141
2142/*
2143 * Allocate the data structures needed for using DMA with an interface
2144 * and fill the proper list of functions pointers
2145 */
2146static void __init
2147pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif)
2148{
2149 /* We won't need pci_dev if we switch to generic consistent
2150 * DMA routines ...
2151 */
2152 if (hwif->pci_dev == NULL)
2153 return;
2154 /*
2155 * Allocate space for the DBDMA commands.
2156 * The +2 is +1 for the stop command and +1 to allow for
2157 * aligning the start address to a multiple of 16 bytes.
2158 */
2159 pmif->dma_table_cpu = (struct dbdma_cmd*)pci_alloc_consistent(
2160 hwif->pci_dev,
2161 (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
2162 &hwif->dmatable_dma);
2163 if (pmif->dma_table_cpu == NULL) {
2164 printk(KERN_ERR "%s: unable to allocate DMA command list\n",
2165 hwif->name);
2166 return;
2167 }
2168
2169 hwif->ide_dma_off_quietly = &__ide_dma_off_quietly;
2170 hwif->ide_dma_on = &__ide_dma_on;
2171 hwif->ide_dma_check = &pmac_ide_dma_check;
2172 hwif->dma_setup = &pmac_ide_dma_setup;
2173 hwif->dma_exec_cmd = &pmac_ide_dma_exec_cmd;
2174 hwif->dma_start = &pmac_ide_dma_start;
2175 hwif->ide_dma_end = &pmac_ide_dma_end;
2176 hwif->ide_dma_test_irq = &pmac_ide_dma_test_irq;
2177 hwif->ide_dma_host_off = &pmac_ide_dma_host_off;
2178 hwif->ide_dma_host_on = &pmac_ide_dma_host_on;
2179 hwif->ide_dma_timeout = &__ide_dma_timeout;
2180 hwif->ide_dma_lostirq = &pmac_ide_dma_lostirq;
2181
2182 hwif->atapi_dma = 1;
2183 switch(pmif->kind) {
2184 case controller_sh_ata6:
2185 hwif->ultra_mask = pmif->cable_80 ? 0x7f : 0x07;
2186 hwif->mwdma_mask = 0x07;
2187 hwif->swdma_mask = 0x00;
2188 break;
2189 case controller_un_ata6:
2190 case controller_k2_ata6:
2191 hwif->ultra_mask = pmif->cable_80 ? 0x3f : 0x07;
2192 hwif->mwdma_mask = 0x07;
2193 hwif->swdma_mask = 0x00;
2194 break;
2195 case controller_kl_ata4:
2196 hwif->ultra_mask = pmif->cable_80 ? 0x1f : 0x07;
2197 hwif->mwdma_mask = 0x07;
2198 hwif->swdma_mask = 0x00;
2199 break;
2200 default:
2201 hwif->ultra_mask = 0x00;
2202 hwif->mwdma_mask = 0x07;
2203 hwif->swdma_mask = 0x00;
2204 break;
2205 }
2206}
2207
2208#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 11:47:40 -0500