diff options
author | Sergei Shtylyov <sshtylyov@ru.mvista.com> | 2007-02-07 12:18:05 -0500 |
---|---|---|
committer | Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> | 2007-02-07 12:18:05 -0500 |
commit | abc4ad4c6b3c6a51a0aa633e3d3fbc80b0ecabfe (patch) | |
tree | 45adfdd195a639672bde7d61dad4c3bd8a42ec3e /drivers/ide/pci | |
parent | b4586715d7944dfbcb2b6b76a0098413cf3222e4 (diff) |
hpt366: cache channel's MCR address
Begin the real driver redesign. For the starters:
- cache the offset of the IDE channel's MISC. control registers which are used
throughout the driver in hwif->select_data;
- only touch the relevant MCR when detecting the cable type on HPT374's
function 1;
- make HPT36x's speedproc handler look the same way as HPT37x ones; fix the
PIO timing register mask for HPT37x.
- rename all the HPT3xx register related variables consistently; clean up the
whitespace.
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Diffstat (limited to 'drivers/ide/pci')
-rw-r--r-- | drivers/ide/pci/hpt366.c | 371 |
1 files changed, 181 insertions, 190 deletions
diff --git a/drivers/ide/pci/hpt366.c b/drivers/ide/pci/hpt366.c index 577aef94d7bf..fd15329d953f 100644 --- a/drivers/ide/pci/hpt366.c +++ b/drivers/ide/pci/hpt366.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * linux/drivers/ide/pci/hpt366.c Version 0.45 May 27, 2006 | 2 | * linux/drivers/ide/pci/hpt366.c Version 0.50 May 28, 2006 |
3 | * | 3 | * |
4 | * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> | 4 | * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> |
5 | * Portions Copyright (C) 2001 Sun Microsystems, Inc. | 5 | * Portions Copyright (C) 2001 Sun Microsystems, Inc. |
@@ -80,6 +80,11 @@ | |||
80 | * - claim the extra 240 bytes of I/O space for all chips | 80 | * - claim the extra 240 bytes of I/O space for all chips |
81 | * - optimize the rate masking/filtering and the drive list lookup code | 81 | * - optimize the rate masking/filtering and the drive list lookup code |
82 | * - use pci_get_slot() to get to the function 1 of HPT36x/374 | 82 | * - use pci_get_slot() to get to the function 1 of HPT36x/374 |
83 | * - cache the channel's MCRs' offset; only touch the relevant MCR when detecting | ||
84 | * the cable type on HPT374's function 1 | ||
85 | * - rename all the register related variables consistently | ||
86 | * - make HPT36x's speedproc handler look the same way as HPT37x ones; fix the | ||
87 | * PIO timing register mask for HPT37x | ||
83 | * <source@mvista.com> | 88 | * <source@mvista.com> |
84 | * | 89 | * |
85 | */ | 90 | */ |
@@ -497,109 +502,106 @@ static u32 pci_bus_clock_list(u8 speed, u32 *chipset_table) | |||
497 | 502 | ||
498 | static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed) | 503 | static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed) |
499 | { | 504 | { |
500 | ide_hwif_t *hwif = drive->hwif; | 505 | ide_hwif_t *hwif = HWIF(drive); |
501 | struct pci_dev *dev = hwif->pci_dev; | 506 | struct pci_dev *dev = hwif->pci_dev; |
502 | struct hpt_info *info = ide_get_hwifdata(hwif); | 507 | struct hpt_info *info = ide_get_hwifdata (hwif); |
503 | u8 speed = hpt3xx_ratefilter(drive, xferspeed); | 508 | u8 speed = hpt3xx_ratefilter(drive, xferspeed); |
504 | u8 regtime = (drive->select.b.unit & 0x01) ? 0x44 : 0x40; | 509 | u8 itr_addr = drive->dn ? 0x44 : 0x40; |
505 | u8 regfast = (hwif->channel) ? 0x55 : 0x51; | 510 | u8 mcr_addr = hwif->select_data + 1; |
506 | u8 drive_fast = 0; | 511 | u8 mcr = 0; |
507 | u32 reg1 = 0, reg2 = 0; | 512 | u32 new_itr, old_itr = 0; |
513 | u32 itr_mask = (speed < XFER_MW_DMA_0) ? 0x30070000 : 0xc0000000; | ||
508 | 514 | ||
509 | /* | 515 | /* |
510 | * Disable the "fast interrupt" prediction. | 516 | * Disable the "fast interrupt" prediction. |
511 | */ | 517 | */ |
512 | pci_read_config_byte(dev, regfast, &drive_fast); | 518 | pci_read_config_byte(dev, mcr_addr, &mcr); |
513 | if (drive_fast & 0x80) | 519 | if (mcr & 0x80) |
514 | pci_write_config_byte(dev, regfast, drive_fast & ~0x80); | 520 | pci_write_config_byte(dev, mcr_addr, mcr & ~0x80); |
515 | 521 | ||
516 | reg2 = pci_bus_clock_list(speed, info->speed); | 522 | new_itr = pci_bus_clock_list(speed, info->speed); |
517 | 523 | ||
518 | /* | 524 | /* |
519 | * Disable on-chip PIO FIFO/buffer | 525 | * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well) |
520 | * (to avoid problems handling I/O errors later) | 526 | * to avoid problems handling I/O errors later |
521 | */ | 527 | */ |
522 | pci_read_config_dword(dev, regtime, ®1); | 528 | pci_read_config_dword(dev, itr_addr, &old_itr); |
523 | if (speed >= XFER_MW_DMA_0) { | 529 | new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask); |
524 | reg2 = (reg2 & ~0xc0000000) | (reg1 & 0xc0000000); | 530 | new_itr &= ~0xc0000000; |
525 | } else { | ||
526 | reg2 = (reg2 & ~0x30070000) | (reg1 & 0x30070000); | ||
527 | } | ||
528 | reg2 &= ~0x80000000; | ||
529 | 531 | ||
530 | pci_write_config_dword(dev, regtime, reg2); | 532 | pci_write_config_dword(dev, itr_addr, new_itr); |
531 | 533 | ||
532 | return ide_config_drive_speed(drive, speed); | 534 | return ide_config_drive_speed(drive, speed); |
533 | } | 535 | } |
534 | 536 | ||
535 | static int hpt370_tune_chipset(ide_drive_t *drive, u8 xferspeed) | 537 | static int hpt370_tune_chipset(ide_drive_t *drive, u8 xferspeed) |
536 | { | 538 | { |
537 | ide_hwif_t *hwif = drive->hwif; | 539 | ide_hwif_t *hwif = HWIF(drive); |
538 | struct pci_dev *dev = hwif->pci_dev; | 540 | struct pci_dev *dev = hwif->pci_dev; |
539 | struct hpt_info *info = ide_get_hwifdata(hwif); | 541 | struct hpt_info *info = ide_get_hwifdata (hwif); |
540 | u8 speed = hpt3xx_ratefilter(drive, xferspeed); | 542 | u8 speed = hpt3xx_ratefilter(drive, xferspeed); |
541 | u8 regfast = (drive->hwif->channel) ? 0x55 : 0x51; | 543 | u8 mcr_addr = hwif->select_data + 1; |
542 | u8 drive_pci = 0x40 + (drive->dn * 4); | 544 | u8 itr_addr = 0x40 + (drive->dn * 4); |
543 | u8 new_fast = 0, drive_fast = 0; | 545 | u8 new_mcr = 0, old_mcr = 0; |
544 | u32 list_conf = 0, drive_conf = 0; | 546 | u32 new_itr, old_itr = 0; |
545 | u32 conf_mask = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000; | 547 | u32 itr_mask = (speed < XFER_MW_DMA_0) ? 0x303c0000 : 0xc0000000; |
546 | 548 | ||
547 | /* | 549 | /* |
548 | * Disable the "fast interrupt" prediction. | 550 | * Disable the "fast interrupt" prediction. |
549 | * don't holdoff on interrupts. (== 0x01 despite what the docs say) | 551 | * don't holdoff on interrupts. (== 0x01 despite what the docs say) |
550 | */ | 552 | */ |
551 | pci_read_config_byte(dev, regfast, &drive_fast); | 553 | pci_read_config_byte(dev, mcr_addr, &old_mcr); |
552 | new_fast = drive_fast; | 554 | new_mcr = old_mcr; |
553 | if (new_fast & 0x02) | 555 | if (new_mcr & 0x02) |
554 | new_fast &= ~0x02; | 556 | new_mcr &= ~0x02; |
555 | 557 | ||
556 | #ifdef HPT_DELAY_INTERRUPT | 558 | #ifdef HPT_DELAY_INTERRUPT |
557 | if (new_fast & 0x01) | 559 | if (new_mcr & 0x01) |
558 | new_fast &= ~0x01; | 560 | new_mcr &= ~0x01; |
559 | #else | 561 | #else |
560 | if ((new_fast & 0x01) == 0) | 562 | if ((new_mcr & 0x01) == 0) |
561 | new_fast |= 0x01; | 563 | new_mcr |= 0x01; |
562 | #endif | 564 | #endif |
563 | if (new_fast != drive_fast) | 565 | if (new_mcr != old_mcr) |
564 | pci_write_config_byte(dev, regfast, new_fast); | 566 | pci_write_config_byte(dev, mcr_addr, new_mcr); |
565 | 567 | ||
566 | list_conf = pci_bus_clock_list(speed, info->speed); | 568 | new_itr = pci_bus_clock_list(speed, info->speed); |
567 | 569 | ||
568 | pci_read_config_dword(dev, drive_pci, &drive_conf); | 570 | pci_read_config_dword(dev, itr_addr, &old_itr); |
569 | list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask); | 571 | new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask); |
570 | 572 | ||
571 | if (speed < XFER_MW_DMA_0) | 573 | if (speed < XFER_MW_DMA_0) |
572 | list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */ | 574 | new_itr &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */ |
573 | pci_write_config_dword(dev, drive_pci, list_conf); | 575 | pci_write_config_dword(dev, itr_addr, new_itr); |
574 | 576 | ||
575 | return ide_config_drive_speed(drive, speed); | 577 | return ide_config_drive_speed(drive, speed); |
576 | } | 578 | } |
577 | 579 | ||
578 | static int hpt372_tune_chipset(ide_drive_t *drive, u8 xferspeed) | 580 | static int hpt372_tune_chipset(ide_drive_t *drive, u8 xferspeed) |
579 | { | 581 | { |
580 | ide_hwif_t *hwif = drive->hwif; | 582 | ide_hwif_t *hwif = HWIF(drive); |
581 | struct pci_dev *dev = hwif->pci_dev; | 583 | struct pci_dev *dev = hwif->pci_dev; |
582 | struct hpt_info *info = ide_get_hwifdata(hwif); | 584 | struct hpt_info *info = ide_get_hwifdata (hwif); |
583 | u8 speed = hpt3xx_ratefilter(drive, xferspeed); | 585 | u8 speed = hpt3xx_ratefilter(drive, xferspeed); |
584 | u8 regfast = (drive->hwif->channel) ? 0x55 : 0x51; | 586 | u8 mcr_addr = hwif->select_data + 1; |
585 | u8 drive_fast = 0, drive_pci = 0x40 + (drive->dn * 4); | 587 | u8 itr_addr = 0x40 + (drive->dn * 4); |
586 | u32 list_conf = 0, drive_conf = 0; | 588 | u8 mcr = 0; |
587 | u32 conf_mask = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000; | 589 | u32 new_itr, old_itr = 0; |
590 | u32 itr_mask = (speed < XFER_MW_DMA_0) ? 0x303c0000 : 0xc0000000; | ||
588 | 591 | ||
589 | /* | 592 | /* |
590 | * Disable the "fast interrupt" prediction. | 593 | * Disable the "fast interrupt" prediction. |
591 | * don't holdoff on interrupts. (== 0x01 despite what the docs say) | 594 | * don't holdoff on interrupts. (== 0x01 despite what the docs say) |
592 | */ | 595 | */ |
593 | pci_read_config_byte(dev, regfast, &drive_fast); | 596 | pci_read_config_byte (dev, mcr_addr, &mcr); |
594 | drive_fast &= ~0x07; | 597 | pci_write_config_byte(dev, mcr_addr, (mcr & ~0x07)); |
595 | pci_write_config_byte(dev, regfast, drive_fast); | ||
596 | 598 | ||
597 | list_conf = pci_bus_clock_list(speed, info->speed); | 599 | new_itr = pci_bus_clock_list(speed, info->speed); |
598 | pci_read_config_dword(dev, drive_pci, &drive_conf); | 600 | pci_read_config_dword(dev, itr_addr, &old_itr); |
599 | list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask); | 601 | new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask); |
600 | if (speed < XFER_MW_DMA_0) | 602 | if (speed < XFER_MW_DMA_0) |
601 | list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */ | 603 | new_itr &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */ |
602 | pci_write_config_dword(dev, drive_pci, list_conf); | 604 | pci_write_config_dword(dev, itr_addr, new_itr); |
603 | 605 | ||
604 | return ide_config_drive_speed(drive, speed); | 606 | return ide_config_drive_speed(drive, speed); |
605 | } | 607 | } |
@@ -666,39 +668,41 @@ static int hpt3xx_quirkproc(ide_drive_t *drive) | |||
666 | 668 | ||
667 | static void hpt3xx_intrproc (ide_drive_t *drive) | 669 | static void hpt3xx_intrproc (ide_drive_t *drive) |
668 | { | 670 | { |
669 | ide_hwif_t *hwif = drive->hwif; | 671 | ide_hwif_t *hwif = HWIF(drive); |
670 | 672 | ||
671 | if (drive->quirk_list) | 673 | if (drive->quirk_list) |
672 | return; | 674 | return; |
673 | /* drives in the quirk_list may not like intr setups/cleanups */ | 675 | /* drives in the quirk_list may not like intr setups/cleanups */ |
674 | hwif->OUTB(drive->ctl|2, IDE_CONTROL_REG); | 676 | hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG); |
675 | } | 677 | } |
676 | 678 | ||
677 | static void hpt3xx_maskproc (ide_drive_t *drive, int mask) | 679 | static void hpt3xx_maskproc (ide_drive_t *drive, int mask) |
678 | { | 680 | { |
679 | ide_hwif_t *hwif = drive->hwif; | 681 | ide_hwif_t *hwif = HWIF(drive); |
680 | struct hpt_info *info = ide_get_hwifdata(hwif); | 682 | struct pci_dev *dev = hwif->pci_dev; |
681 | struct pci_dev *dev = hwif->pci_dev; | 683 | struct hpt_info *info = ide_get_hwifdata(hwif); |
682 | 684 | ||
683 | if (drive->quirk_list) { | 685 | if (drive->quirk_list) { |
684 | if (info->revision >= 3) { | 686 | if (info->revision >= 3) { |
685 | u8 reg5a = 0; | 687 | u8 scr1 = 0; |
686 | pci_read_config_byte(dev, 0x5a, ®5a); | 688 | |
687 | if (((reg5a & 0x10) >> 4) != mask) | 689 | pci_read_config_byte(dev, 0x5a, &scr1); |
688 | pci_write_config_byte(dev, 0x5a, mask ? (reg5a | 0x10) : (reg5a & ~0x10)); | 690 | if (((scr1 & 0x10) >> 4) != mask) { |
691 | if (mask) | ||
692 | scr1 |= 0x10; | ||
693 | else | ||
694 | scr1 &= ~0x10; | ||
695 | pci_write_config_byte(dev, 0x5a, scr1); | ||
696 | } | ||
689 | } else { | 697 | } else { |
690 | if (mask) { | 698 | if (mask) |
691 | disable_irq(hwif->irq); | 699 | disable_irq(hwif->irq); |
692 | } else { | 700 | else |
693 | enable_irq(hwif->irq); | 701 | enable_irq (hwif->irq); |
694 | } | ||
695 | } | 702 | } |
696 | } else { | 703 | } else |
697 | if (IDE_CONTROL_REG) | 704 | hwif->OUTB(mask ? (drive->ctl | 2) : (drive->ctl & ~2), |
698 | hwif->OUTB(mask ? (drive->ctl | 2) : | 705 | IDE_CONTROL_REG); |
699 | (drive->ctl & ~2), | ||
700 | IDE_CONTROL_REG); | ||
701 | } | ||
702 | } | 706 | } |
703 | 707 | ||
704 | static int hpt366_config_drive_xfer_rate (ide_drive_t *drive) | 708 | static int hpt366_config_drive_xfer_rate (ide_drive_t *drive) |
@@ -727,28 +731,29 @@ fast_ata_pio: | |||
727 | } | 731 | } |
728 | 732 | ||
729 | /* | 733 | /* |
730 | * This is specific to the HPT366 UDMA bios chipset | 734 | * This is specific to the HPT366 UDMA chipset |
731 | * by HighPoint|Triones Technologies, Inc. | 735 | * by HighPoint|Triones Technologies, Inc. |
732 | */ | 736 | */ |
733 | static int hpt366_ide_dma_lostirq (ide_drive_t *drive) | 737 | static int hpt366_ide_dma_lostirq(ide_drive_t *drive) |
734 | { | 738 | { |
735 | struct pci_dev *dev = HWIF(drive)->pci_dev; | 739 | struct pci_dev *dev = HWIF(drive)->pci_dev; |
736 | u8 reg50h = 0, reg52h = 0, reg5ah = 0; | 740 | u8 mcr1 = 0, mcr3 = 0, scr1 = 0; |
737 | 741 | ||
738 | pci_read_config_byte(dev, 0x50, ®50h); | 742 | pci_read_config_byte(dev, 0x50, &mcr1); |
739 | pci_read_config_byte(dev, 0x52, ®52h); | 743 | pci_read_config_byte(dev, 0x52, &mcr3); |
740 | pci_read_config_byte(dev, 0x5a, ®5ah); | 744 | pci_read_config_byte(dev, 0x5a, &scr1); |
741 | printk("%s: (%s) reg50h=0x%02x, reg52h=0x%02x, reg5ah=0x%02x\n", | 745 | printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n", |
742 | drive->name, __FUNCTION__, reg50h, reg52h, reg5ah); | 746 | drive->name, __FUNCTION__, mcr1, mcr3, scr1); |
743 | if (reg5ah & 0x10) | 747 | if (scr1 & 0x10) |
744 | pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10); | 748 | pci_write_config_byte(dev, 0x5a, scr1 & ~0x10); |
745 | return __ide_dma_lostirq(drive); | 749 | return __ide_dma_lostirq(drive); |
746 | } | 750 | } |
747 | 751 | ||
748 | static void hpt370_clear_engine (ide_drive_t *drive) | 752 | static void hpt370_clear_engine (ide_drive_t *drive) |
749 | { | 753 | { |
750 | u8 regstate = HWIF(drive)->channel ? 0x54 : 0x50; | 754 | ide_hwif_t *hwif = HWIF(drive); |
751 | pci_write_config_byte(HWIF(drive)->pci_dev, regstate, 0x37); | 755 | |
756 | pci_write_config_byte(hwif->pci_dev, hwif->select_data, 0x37); | ||
752 | udelay(10); | 757 | udelay(10); |
753 | } | 758 | } |
754 | 759 | ||
@@ -780,10 +785,10 @@ static int hpt370_ide_dma_end (ide_drive_t *drive) | |||
780 | static void hpt370_lostirq_timeout (ide_drive_t *drive) | 785 | static void hpt370_lostirq_timeout (ide_drive_t *drive) |
781 | { | 786 | { |
782 | ide_hwif_t *hwif = HWIF(drive); | 787 | ide_hwif_t *hwif = HWIF(drive); |
783 | u8 bfifo = 0, reginfo = hwif->channel ? 0x56 : 0x52; | 788 | u8 bfifo = 0; |
784 | u8 dma_stat = 0, dma_cmd = 0; | 789 | u8 dma_stat = 0, dma_cmd = 0; |
785 | 790 | ||
786 | pci_read_config_byte(HWIF(drive)->pci_dev, reginfo, &bfifo); | 791 | pci_read_config_byte(HWIF(drive)->pci_dev, hwif->select_data + 2, &bfifo); |
787 | printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo); | 792 | printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo); |
788 | hpt370_clear_engine(drive); | 793 | hpt370_clear_engine(drive); |
789 | /* get dma command mode */ | 794 | /* get dma command mode */ |
@@ -814,10 +819,9 @@ static int hpt374_ide_dma_test_irq(ide_drive_t *drive) | |||
814 | { | 819 | { |
815 | ide_hwif_t *hwif = HWIF(drive); | 820 | ide_hwif_t *hwif = HWIF(drive); |
816 | u16 bfifo = 0; | 821 | u16 bfifo = 0; |
817 | u8 reginfo = hwif->channel ? 0x56 : 0x52; | 822 | u8 dma_stat; |
818 | u8 dma_stat; | ||
819 | 823 | ||
820 | pci_read_config_word(hwif->pci_dev, reginfo, &bfifo); | 824 | pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo); |
821 | if (bfifo & 0x1FF) { | 825 | if (bfifo & 0x1FF) { |
822 | // printk("%s: %d bytes in FIFO\n", drive->name, bfifo); | 826 | // printk("%s: %d bytes in FIFO\n", drive->name, bfifo); |
823 | return 0; | 827 | return 0; |
@@ -825,7 +829,7 @@ static int hpt374_ide_dma_test_irq(ide_drive_t *drive) | |||
825 | 829 | ||
826 | dma_stat = hwif->INB(hwif->dma_status); | 830 | dma_stat = hwif->INB(hwif->dma_status); |
827 | /* return 1 if INTR asserted */ | 831 | /* return 1 if INTR asserted */ |
828 | if ((dma_stat & 4) == 4) | 832 | if (dma_stat & 4) |
829 | return 1; | 833 | return 1; |
830 | 834 | ||
831 | if (!drive->waiting_for_dma) | 835 | if (!drive->waiting_for_dma) |
@@ -834,17 +838,17 @@ static int hpt374_ide_dma_test_irq(ide_drive_t *drive) | |||
834 | return 0; | 838 | return 0; |
835 | } | 839 | } |
836 | 840 | ||
837 | static int hpt374_ide_dma_end (ide_drive_t *drive) | 841 | static int hpt374_ide_dma_end(ide_drive_t *drive) |
838 | { | 842 | { |
839 | struct pci_dev *dev = HWIF(drive)->pci_dev; | ||
840 | ide_hwif_t *hwif = HWIF(drive); | 843 | ide_hwif_t *hwif = HWIF(drive); |
841 | u8 msc_stat = 0, mscreg = hwif->channel ? 0x54 : 0x50; | 844 | struct pci_dev *dev = hwif->pci_dev; |
842 | u8 bwsr_stat = 0, bwsr_mask = hwif->channel ? 0x02 : 0x01; | 845 | u8 mcr = 0, mcr_addr = hwif->select_data; |
843 | 846 | u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01; | |
844 | pci_read_config_byte(dev, 0x6a, &bwsr_stat); | 847 | |
845 | pci_read_config_byte(dev, mscreg, &msc_stat); | 848 | pci_read_config_byte(dev, 0x6a, &bwsr); |
846 | if ((bwsr_stat & bwsr_mask) == bwsr_mask) | 849 | pci_read_config_byte(dev, mcr_addr, &mcr); |
847 | pci_write_config_byte(dev, mscreg, msc_stat|0x30); | 850 | if (bwsr & mask) |
851 | pci_write_config_byte(dev, mcr_addr, mcr | 0x30); | ||
848 | return __ide_dma_end(drive); | 852 | return __ide_dma_end(drive); |
849 | } | 853 | } |
850 | 854 | ||
@@ -910,6 +914,7 @@ static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq) | |||
910 | 914 | ||
911 | /* | 915 | /* |
912 | * Set/get power state for a drive. | 916 | * Set/get power state for a drive. |
917 | * NOTE: affects both drives on each channel. | ||
913 | * | 918 | * |
914 | * When we turn the power back on, we need to re-initialize things. | 919 | * When we turn the power back on, we need to re-initialize things. |
915 | */ | 920 | */ |
@@ -917,26 +922,18 @@ static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq) | |||
917 | 922 | ||
918 | static int hpt3xx_busproc(ide_drive_t *drive, int state) | 923 | static int hpt3xx_busproc(ide_drive_t *drive, int state) |
919 | { | 924 | { |
920 | ide_hwif_t *hwif = drive->hwif; | 925 | ide_hwif_t *hwif = HWIF(drive); |
921 | struct pci_dev *dev = hwif->pci_dev; | 926 | struct pci_dev *dev = hwif->pci_dev; |
922 | u8 tristate, resetmask, bus_reg = 0; | 927 | u8 mcr_addr = hwif->select_data + 2; |
923 | u16 tri_reg = 0; | 928 | u8 resetmask = hwif->channel ? 0x80 : 0x40; |
929 | u8 bsr2 = 0; | ||
930 | u16 mcr = 0; | ||
924 | 931 | ||
925 | hwif->bus_state = state; | 932 | hwif->bus_state = state; |
926 | 933 | ||
927 | if (hwif->channel) { | ||
928 | /* secondary channel */ | ||
929 | tristate = 0x56; | ||
930 | resetmask = 0x80; | ||
931 | } else { | ||
932 | /* primary channel */ | ||
933 | tristate = 0x52; | ||
934 | resetmask = 0x40; | ||
935 | } | ||
936 | |||
937 | /* Grab the status. */ | 934 | /* Grab the status. */ |
938 | pci_read_config_word(dev, tristate, &tri_reg); | 935 | pci_read_config_word(dev, mcr_addr, &mcr); |
939 | pci_read_config_byte(dev, 0x59, &bus_reg); | 936 | pci_read_config_byte(dev, 0x59, &bsr2); |
940 | 937 | ||
941 | /* | 938 | /* |
942 | * Set the state. We don't set it if we don't need to do so. | 939 | * Set the state. We don't set it if we don't need to do so. |
@@ -944,22 +941,22 @@ static int hpt3xx_busproc(ide_drive_t *drive, int state) | |||
944 | */ | 941 | */ |
945 | switch (state) { | 942 | switch (state) { |
946 | case BUSSTATE_ON: | 943 | case BUSSTATE_ON: |
947 | if (!(bus_reg & resetmask)) | 944 | if (!(bsr2 & resetmask)) |
948 | return 0; | 945 | return 0; |
949 | hwif->drives[0].failures = hwif->drives[1].failures = 0; | 946 | hwif->drives[0].failures = hwif->drives[1].failures = 0; |
950 | 947 | ||
951 | pci_write_config_byte(dev, 0x59, bus_reg & ~resetmask); | 948 | pci_write_config_byte(dev, 0x59, bsr2 & ~resetmask); |
952 | pci_write_config_word(dev, tristate, tri_reg & ~TRISTATE_BIT); | 949 | pci_write_config_word(dev, mcr_addr, mcr & ~TRISTATE_BIT); |
953 | return 0; | 950 | return 0; |
954 | case BUSSTATE_OFF: | 951 | case BUSSTATE_OFF: |
955 | if ((bus_reg & resetmask) && !(tri_reg & TRISTATE_BIT)) | 952 | if ((bsr2 & resetmask) && !(mcr & TRISTATE_BIT)) |
956 | return 0; | 953 | return 0; |
957 | tri_reg &= ~TRISTATE_BIT; | 954 | mcr &= ~TRISTATE_BIT; |
958 | break; | 955 | break; |
959 | case BUSSTATE_TRISTATE: | 956 | case BUSSTATE_TRISTATE: |
960 | if ((bus_reg & resetmask) && (tri_reg & TRISTATE_BIT)) | 957 | if ((bsr2 & resetmask) && (mcr & TRISTATE_BIT)) |
961 | return 0; | 958 | return 0; |
962 | tri_reg |= TRISTATE_BIT; | 959 | mcr |= TRISTATE_BIT; |
963 | break; | 960 | break; |
964 | default: | 961 | default: |
965 | return -EINVAL; | 962 | return -EINVAL; |
@@ -968,20 +965,20 @@ static int hpt3xx_busproc(ide_drive_t *drive, int state) | |||
968 | hwif->drives[0].failures = hwif->drives[0].max_failures + 1; | 965 | hwif->drives[0].failures = hwif->drives[0].max_failures + 1; |
969 | hwif->drives[1].failures = hwif->drives[1].max_failures + 1; | 966 | hwif->drives[1].failures = hwif->drives[1].max_failures + 1; |
970 | 967 | ||
971 | pci_write_config_word(dev, tristate, tri_reg); | 968 | pci_write_config_word(dev, mcr_addr, mcr); |
972 | pci_write_config_byte(dev, 0x59, bus_reg | resetmask); | 969 | pci_write_config_byte(dev, 0x59, bsr2 | resetmask); |
973 | return 0; | 970 | return 0; |
974 | } | 971 | } |
975 | 972 | ||
976 | static void __devinit hpt366_clocking(ide_hwif_t *hwif) | 973 | static void __devinit hpt366_clocking(ide_hwif_t *hwif) |
977 | { | 974 | { |
978 | u32 reg1 = 0; | 975 | u32 itr1 = 0; |
979 | struct hpt_info *info = ide_get_hwifdata(hwif); | 976 | struct hpt_info *info = ide_get_hwifdata(hwif); |
980 | 977 | ||
981 | pci_read_config_dword(hwif->pci_dev, 0x40, ®1); | 978 | pci_read_config_dword(hwif->pci_dev, 0x40, &itr1); |
982 | 979 | ||
983 | /* detect bus speed by looking at control reg timing: */ | 980 | /* detect bus speed by looking at control reg timing: */ |
984 | switch((reg1 >> 8) & 7) { | 981 | switch((itr1 >> 8) & 7) { |
985 | case 5: | 982 | case 5: |
986 | info->speed = forty_base_hpt36x; | 983 | info->speed = forty_base_hpt36x; |
987 | break; | 984 | break; |
@@ -1003,7 +1000,7 @@ static void __devinit hpt37x_clocking(ide_hwif_t *hwif) | |||
1003 | int adjust, i; | 1000 | int adjust, i; |
1004 | u16 freq = 0; | 1001 | u16 freq = 0; |
1005 | u32 pll, temp = 0; | 1002 | u32 pll, temp = 0; |
1006 | u8 reg5bh = 0, mcr1 = 0; | 1003 | u8 scr2 = 0, mcr1 = 0; |
1007 | 1004 | ||
1008 | /* | 1005 | /* |
1009 | * default to pci clock. make sure MA15/16 are set to output | 1006 | * default to pci clock. make sure MA15/16 are set to output |
@@ -1116,13 +1113,13 @@ static void __devinit hpt37x_clocking(ide_hwif_t *hwif) | |||
1116 | 1113 | ||
1117 | /* wait for clock stabilization */ | 1114 | /* wait for clock stabilization */ |
1118 | for (i = 0; i < 0x50000; i++) { | 1115 | for (i = 0; i < 0x50000; i++) { |
1119 | pci_read_config_byte(dev, 0x5b, ®5bh); | 1116 | pci_read_config_byte(dev, 0x5b, &scr2); |
1120 | if (reg5bh & 0x80) { | 1117 | if (scr2 & 0x80) { |
1121 | /* spin looking for the clock to destabilize */ | 1118 | /* spin looking for the clock to destabilize */ |
1122 | for (i = 0; i < 0x1000; ++i) { | 1119 | for (i = 0; i < 0x1000; ++i) { |
1123 | pci_read_config_byte(dev, 0x5b, | 1120 | pci_read_config_byte(dev, 0x5b, |
1124 | ®5bh); | 1121 | &scr2); |
1125 | if ((reg5bh & 0x80) == 0) | 1122 | if ((scr2 & 0x80) == 0) |
1126 | goto pll_recal; | 1123 | goto pll_recal; |
1127 | } | 1124 | } |
1128 | pci_read_config_dword(dev, 0x5c, &pll); | 1125 | pci_read_config_dword(dev, 0x5c, &pll); |
@@ -1159,26 +1156,24 @@ init_hpt37X_done: | |||
1159 | 1156 | ||
1160 | static int __devinit init_hpt37x(struct pci_dev *dev) | 1157 | static int __devinit init_hpt37x(struct pci_dev *dev) |
1161 | { | 1158 | { |
1162 | u8 reg5ah; | 1159 | u8 scr1; |
1163 | 1160 | ||
1164 | pci_read_config_byte(dev, 0x5a, ®5ah); | 1161 | pci_read_config_byte (dev, 0x5a, &scr1); |
1165 | /* interrupt force enable */ | 1162 | /* interrupt force enable */ |
1166 | pci_write_config_byte(dev, 0x5a, (reg5ah & ~0x10)); | 1163 | pci_write_config_byte(dev, 0x5a, (scr1 & ~0x10)); |
1167 | return 0; | 1164 | return 0; |
1168 | } | 1165 | } |
1169 | 1166 | ||
1170 | static int __devinit init_hpt366(struct pci_dev *dev) | 1167 | static int __devinit init_hpt366(struct pci_dev *dev) |
1171 | { | 1168 | { |
1172 | u32 reg1 = 0; | 1169 | u8 mcr = 0; |
1173 | u8 drive_fast = 0; | ||
1174 | 1170 | ||
1175 | /* | 1171 | /* |
1176 | * Disable the "fast interrupt" prediction. | 1172 | * Disable the "fast interrupt" prediction. |
1177 | */ | 1173 | */ |
1178 | pci_read_config_byte(dev, 0x51, &drive_fast); | 1174 | pci_read_config_byte(dev, 0x51, &mcr); |
1179 | if (drive_fast & 0x80) | 1175 | if (mcr & 0x80) |
1180 | pci_write_config_byte(dev, 0x51, drive_fast & ~0x80); | 1176 | pci_write_config_byte(dev, 0x51, mcr & ~0x80); |
1181 | pci_read_config_dword(dev, 0x40, ®1); | ||
1182 | 1177 | ||
1183 | return 0; | 1178 | return 0; |
1184 | } | 1179 | } |
@@ -1213,17 +1208,21 @@ static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const cha | |||
1213 | 1208 | ||
1214 | static void __devinit init_hwif_hpt366(ide_hwif_t *hwif) | 1209 | static void __devinit init_hwif_hpt366(ide_hwif_t *hwif) |
1215 | { | 1210 | { |
1216 | struct pci_dev *dev = hwif->pci_dev; | 1211 | struct pci_dev *dev = hwif->pci_dev; |
1217 | struct hpt_info *info = ide_get_hwifdata(hwif); | 1212 | struct hpt_info *info = ide_get_hwifdata(hwif); |
1218 | u8 ata66 = 0, regmask = (hwif->channel) ? 0x01 : 0x02; | ||
1219 | int serialize = HPT_SERIALIZE_IO; | 1213 | int serialize = HPT_SERIALIZE_IO; |
1220 | 1214 | u8 scr1 = 0, ata66 = (hwif->channel) ? 0x01 : 0x02; | |
1215 | |||
1216 | /* Cache the channel's MISC. control registers' offset */ | ||
1217 | hwif->select_data = hwif->channel ? 0x54 : 0x50; | ||
1218 | |||
1221 | hwif->tuneproc = &hpt3xx_tune_drive; | 1219 | hwif->tuneproc = &hpt3xx_tune_drive; |
1222 | hwif->speedproc = &hpt3xx_tune_chipset; | 1220 | hwif->speedproc = &hpt3xx_tune_chipset; |
1223 | hwif->quirkproc = &hpt3xx_quirkproc; | 1221 | hwif->quirkproc = &hpt3xx_quirkproc; |
1224 | hwif->intrproc = &hpt3xx_intrproc; | 1222 | hwif->intrproc = &hpt3xx_intrproc; |
1225 | hwif->maskproc = &hpt3xx_maskproc; | 1223 | hwif->maskproc = &hpt3xx_maskproc; |
1226 | 1224 | hwif->busproc = &hpt3xx_busproc; | |
1225 | |||
1227 | /* | 1226 | /* |
1228 | * HPT3xxN chips have some complications: | 1227 | * HPT3xxN chips have some complications: |
1229 | * | 1228 | * |
@@ -1241,7 +1240,7 @@ static void __devinit init_hwif_hpt366(ide_hwif_t *hwif) | |||
1241 | 1240 | ||
1242 | /* | 1241 | /* |
1243 | * The HPT37x uses the CBLID pins as outputs for MA15/MA16 | 1242 | * The HPT37x uses the CBLID pins as outputs for MA15/MA16 |
1244 | * address lines to access an external eeprom. To read valid | 1243 | * address lines to access an external EEPROM. To read valid |
1245 | * cable detect state the pins must be enabled as inputs. | 1244 | * cable detect state the pins must be enabled as inputs. |
1246 | */ | 1245 | */ |
1247 | if (info->revision >= 8 && (PCI_FUNC(dev->devfn) & 1)) { | 1246 | if (info->revision >= 8 && (PCI_FUNC(dev->devfn) & 1)) { |
@@ -1250,35 +1249,28 @@ static void __devinit init_hwif_hpt366(ide_hwif_t *hwif) | |||
1250 | * - set bit 15 of reg 0x52 to enable TCBLID as input | 1249 | * - set bit 15 of reg 0x52 to enable TCBLID as input |
1251 | * - set bit 15 of reg 0x56 to enable FCBLID as input | 1250 | * - set bit 15 of reg 0x56 to enable FCBLID as input |
1252 | */ | 1251 | */ |
1253 | u16 mcr3, mcr6; | 1252 | u8 mcr_addr = hwif->select_data + 2; |
1254 | pci_read_config_word(dev, 0x52, &mcr3); | 1253 | u16 mcr; |
1255 | pci_read_config_word(dev, 0x56, &mcr6); | 1254 | |
1256 | pci_write_config_word(dev, 0x52, mcr3 | 0x8000); | 1255 | pci_read_config_word (dev, mcr_addr, &mcr); |
1257 | pci_write_config_word(dev, 0x56, mcr6 | 0x8000); | 1256 | pci_write_config_word(dev, mcr_addr, (mcr | 0x8000)); |
1258 | /* now read cable id register */ | 1257 | /* now read cable id register */ |
1259 | pci_read_config_byte(dev, 0x5a, &ata66); | 1258 | pci_read_config_byte (dev, 0x5a, &scr1); |
1260 | pci_write_config_word(dev, 0x52, mcr3); | 1259 | pci_write_config_word(dev, mcr_addr, mcr); |
1261 | pci_write_config_word(dev, 0x56, mcr6); | ||
1262 | } else if (info->revision >= 3) { | 1260 | } else if (info->revision >= 3) { |
1263 | /* | 1261 | /* |
1264 | * HPT370/372 and 374 pcifn 0 | 1262 | * HPT370/372 and 374 pcifn 0 |
1265 | * - clear bit 0 of 0x5b to enable P/SCBLID as inputs | 1263 | * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs |
1266 | */ | 1264 | */ |
1267 | u8 scr2; | 1265 | u8 scr2 = 0; |
1268 | pci_read_config_byte(dev, 0x5b, &scr2); | ||
1269 | pci_write_config_byte(dev, 0x5b, scr2 & ~1); | ||
1270 | /* now read cable id register */ | ||
1271 | pci_read_config_byte(dev, 0x5a, &ata66); | ||
1272 | pci_write_config_byte(dev, 0x5b, scr2); | ||
1273 | } else { | ||
1274 | pci_read_config_byte(dev, 0x5a, &ata66); | ||
1275 | } | ||
1276 | 1266 | ||
1277 | #ifdef DEBUG | 1267 | pci_read_config_byte (dev, 0x5b, &scr2); |
1278 | printk("HPT366: reg5ah=0x%02x ATA-%s Cable Port%d\n", | 1268 | pci_write_config_byte(dev, 0x5b, (scr2 & ~1)); |
1279 | ata66, (ata66 & regmask) ? "33" : "66", | 1269 | /* now read cable id register */ |
1280 | PCI_FUNC(hwif->pci_dev->devfn)); | 1270 | pci_read_config_byte (dev, 0x5a, &scr1); |
1281 | #endif /* DEBUG */ | 1271 | pci_write_config_byte(dev, 0x5b, scr2); |
1272 | } else | ||
1273 | pci_read_config_byte (dev, 0x5a, &scr1); | ||
1282 | 1274 | ||
1283 | /* Serialize access to this device */ | 1275 | /* Serialize access to this device */ |
1284 | if (serialize && hwif->mate) | 1276 | if (serialize && hwif->mate) |
@@ -1300,7 +1292,7 @@ static void __devinit init_hwif_hpt366(ide_hwif_t *hwif) | |||
1300 | hwif->mwdma_mask = 0x07; | 1292 | hwif->mwdma_mask = 0x07; |
1301 | 1293 | ||
1302 | if (!(hwif->udma_four)) | 1294 | if (!(hwif->udma_four)) |
1303 | hwif->udma_four = ((ata66 & regmask) ? 0 : 1); | 1295 | hwif->udma_four = ((scr1 & ata66) ? 0 : 1); |
1304 | hwif->ide_dma_check = &hpt366_config_drive_xfer_rate; | 1296 | hwif->ide_dma_check = &hpt366_config_drive_xfer_rate; |
1305 | 1297 | ||
1306 | if (info->revision >= 8) { | 1298 | if (info->revision >= 8) { |
@@ -1327,11 +1319,10 @@ static void __devinit init_hwif_hpt366(ide_hwif_t *hwif) | |||
1327 | 1319 | ||
1328 | static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase) | 1320 | static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase) |
1329 | { | 1321 | { |
1330 | struct hpt_info *info = ide_get_hwifdata(hwif); | 1322 | struct pci_dev *dev = hwif->pci_dev; |
1331 | u8 masterdma = 0, slavedma = 0; | 1323 | struct hpt_info *info = ide_get_hwifdata(hwif); |
1332 | u8 dma_new = 0, dma_old = 0; | 1324 | u8 masterdma = 0, slavedma = 0; |
1333 | u8 primary = hwif->channel ? 0x4b : 0x43; | 1325 | u8 dma_new = 0, dma_old = 0; |
1334 | u8 secondary = hwif->channel ? 0x4f : 0x47; | ||
1335 | unsigned long flags; | 1326 | unsigned long flags; |
1336 | 1327 | ||
1337 | if (!dmabase) | 1328 | if (!dmabase) |
@@ -1348,13 +1339,13 @@ static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase) | |||
1348 | local_irq_save(flags); | 1339 | local_irq_save(flags); |
1349 | 1340 | ||
1350 | dma_new = dma_old; | 1341 | dma_new = dma_old; |
1351 | pci_read_config_byte(hwif->pci_dev, primary, &masterdma); | 1342 | pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma); |
1352 | pci_read_config_byte(hwif->pci_dev, secondary, &slavedma); | 1343 | pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma); |
1353 | 1344 | ||
1354 | if (masterdma & 0x30) dma_new |= 0x20; | 1345 | if (masterdma & 0x30) dma_new |= 0x20; |
1355 | if (slavedma & 0x30) dma_new |= 0x40; | 1346 | if ( slavedma & 0x30) dma_new |= 0x40; |
1356 | if (dma_new != dma_old) | 1347 | if (dma_new != dma_old) |
1357 | hwif->OUTB(dma_new, dmabase+2); | 1348 | hwif->OUTB(dma_new, dmabase + 2); |
1358 | 1349 | ||
1359 | local_irq_restore(flags); | 1350 | local_irq_restore(flags); |
1360 | 1351 | ||