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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/ide/pci
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/ide/pci')
-rw-r--r--drivers/ide/pci/Makefile34
-rw-r--r--drivers/ide/pci/aec62xx.c485
-rw-r--r--drivers/ide/pci/alim15x3.c913
-rw-r--r--drivers/ide/pci/amd74xx.c543
-rw-r--r--drivers/ide/pci/atiixp.c370
-rw-r--r--drivers/ide/pci/cmd640.c879
-rw-r--r--drivers/ide/pci/cmd64x.c821
-rw-r--r--drivers/ide/pci/cs5520.c274
-rw-r--r--drivers/ide/pci/cs5530.c384
-rw-r--r--drivers/ide/pci/cy82c693.c531
-rw-r--r--drivers/ide/pci/generic.c232
-rw-r--r--drivers/ide/pci/hpt34x.c278
-rw-r--r--drivers/ide/pci/hpt366.c1745
-rw-r--r--drivers/ide/pci/it8172.c308
-rw-r--r--drivers/ide/pci/ns87415.c315
-rw-r--r--drivers/ide/pci/opti621.c394
-rw-r--r--drivers/ide/pci/pdc202xx_new.c508
-rw-r--r--drivers/ide/pci/pdc202xx_old.c892
-rw-r--r--drivers/ide/pci/piix.c670
-rw-r--r--drivers/ide/pci/rz1000.c91
-rw-r--r--drivers/ide/pci/sc1200.c518
-rw-r--r--drivers/ide/pci/serverworks.c675
-rw-r--r--drivers/ide/pci/sgiioc4.c728
-rw-r--r--drivers/ide/pci/siimage.c1133
-rw-r--r--drivers/ide/pci/sis5513.c984
-rw-r--r--drivers/ide/pci/sl82c105.c516
-rw-r--r--drivers/ide/pci/slc90e66.c273
-rw-r--r--drivers/ide/pci/triflex.c188
-rw-r--r--drivers/ide/pci/trm290.c369
-rw-r--r--drivers/ide/pci/via82cxxx.c656
30 files changed, 16707 insertions, 0 deletions
diff --git a/drivers/ide/pci/Makefile b/drivers/ide/pci/Makefile
new file mode 100644
index 000000000000..55e6e553e497
--- /dev/null
+++ b/drivers/ide/pci/Makefile
@@ -0,0 +1,34 @@
1
2obj-$(CONFIG_BLK_DEV_AEC62XX) += aec62xx.o
3obj-$(CONFIG_BLK_DEV_ALI15X3) += alim15x3.o
4obj-$(CONFIG_BLK_DEV_AMD74XX) += amd74xx.o
5obj-$(CONFIG_BLK_DEV_ATIIXP) += atiixp.o
6obj-$(CONFIG_BLK_DEV_CMD64X) += cmd64x.o
7obj-$(CONFIG_BLK_DEV_CS5520) += cs5520.o
8obj-$(CONFIG_BLK_DEV_CS5530) += cs5530.o
9obj-$(CONFIG_BLK_DEV_SC1200) += sc1200.o
10obj-$(CONFIG_BLK_DEV_CY82C693) += cy82c693.o
11obj-$(CONFIG_BLK_DEV_HPT34X) += hpt34x.o
12obj-$(CONFIG_BLK_DEV_HPT366) += hpt366.o
13#obj-$(CONFIG_BLK_DEV_HPT37X) += hpt37x.o
14obj-$(CONFIG_BLK_DEV_IT8172) += it8172.o
15obj-$(CONFIG_BLK_DEV_NS87415) += ns87415.o
16obj-$(CONFIG_BLK_DEV_OPTI621) += opti621.o
17obj-$(CONFIG_BLK_DEV_PDC202XX_OLD) += pdc202xx_old.o
18obj-$(CONFIG_BLK_DEV_PDC202XX_NEW) += pdc202xx_new.o
19obj-$(CONFIG_BLK_DEV_PIIX) += piix.o
20obj-$(CONFIG_BLK_DEV_RZ1000) += rz1000.o
21obj-$(CONFIG_BLK_DEV_SVWKS) += serverworks.o
22obj-$(CONFIG_BLK_DEV_SGIIOC4) += sgiioc4.o
23obj-$(CONFIG_BLK_DEV_SIIMAGE) += siimage.o
24obj-$(CONFIG_BLK_DEV_SIS5513) += sis5513.o
25obj-$(CONFIG_BLK_DEV_SL82C105) += sl82c105.o
26obj-$(CONFIG_BLK_DEV_SLC90E66) += slc90e66.o
27obj-$(CONFIG_BLK_DEV_TRIFLEX) += triflex.o
28obj-$(CONFIG_BLK_DEV_TRM290) += trm290.o
29obj-$(CONFIG_BLK_DEV_VIA82CXXX) += via82cxxx.o
30
31# Must appear at the end of the block
32obj-$(CONFIG_BLK_DEV_GENERIC) += generic.o
33
34EXTRA_CFLAGS := -Idrivers/ide
diff --git a/drivers/ide/pci/aec62xx.c b/drivers/ide/pci/aec62xx.c
new file mode 100644
index 000000000000..52cadc005d72
--- /dev/null
+++ b/drivers/ide/pci/aec62xx.c
@@ -0,0 +1,485 @@
1/*
2 * linux/drivers/ide/pci/aec62xx.c Version 0.11 March 27, 2002
3 *
4 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
5 *
6 */
7
8#include <linux/module.h>
9#include <linux/config.h>
10#include <linux/types.h>
11#include <linux/pci.h>
12#include <linux/delay.h>
13#include <linux/hdreg.h>
14#include <linux/ide.h>
15#include <linux/init.h>
16
17#include <asm/io.h>
18
19struct chipset_bus_clock_list_entry {
20 u8 xfer_speed;
21 u8 chipset_settings;
22 u8 ultra_settings;
23};
24
25static struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
26 { XFER_UDMA_6, 0x31, 0x07 },
27 { XFER_UDMA_5, 0x31, 0x06 },
28 { XFER_UDMA_4, 0x31, 0x05 },
29 { XFER_UDMA_3, 0x31, 0x04 },
30 { XFER_UDMA_2, 0x31, 0x03 },
31 { XFER_UDMA_1, 0x31, 0x02 },
32 { XFER_UDMA_0, 0x31, 0x01 },
33
34 { XFER_MW_DMA_2, 0x31, 0x00 },
35 { XFER_MW_DMA_1, 0x31, 0x00 },
36 { XFER_MW_DMA_0, 0x0a, 0x00 },
37 { XFER_PIO_4, 0x31, 0x00 },
38 { XFER_PIO_3, 0x33, 0x00 },
39 { XFER_PIO_2, 0x08, 0x00 },
40 { XFER_PIO_1, 0x0a, 0x00 },
41 { XFER_PIO_0, 0x00, 0x00 },
42 { 0, 0x00, 0x00 }
43};
44
45static struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
46 { XFER_UDMA_6, 0x41, 0x06 },
47 { XFER_UDMA_5, 0x41, 0x05 },
48 { XFER_UDMA_4, 0x41, 0x04 },
49 { XFER_UDMA_3, 0x41, 0x03 },
50 { XFER_UDMA_2, 0x41, 0x02 },
51 { XFER_UDMA_1, 0x41, 0x01 },
52 { XFER_UDMA_0, 0x41, 0x01 },
53
54 { XFER_MW_DMA_2, 0x41, 0x00 },
55 { XFER_MW_DMA_1, 0x42, 0x00 },
56 { XFER_MW_DMA_0, 0x7a, 0x00 },
57 { XFER_PIO_4, 0x41, 0x00 },
58 { XFER_PIO_3, 0x43, 0x00 },
59 { XFER_PIO_2, 0x78, 0x00 },
60 { XFER_PIO_1, 0x7a, 0x00 },
61 { XFER_PIO_0, 0x70, 0x00 },
62 { 0, 0x00, 0x00 }
63};
64
65#define BUSCLOCK(D) \
66 ((struct chipset_bus_clock_list_entry *) pci_get_drvdata((D)))
67
68#if 0
69 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
70 (void) pci_read_config_byte(dev, 0x54, &art);
71 p += sprintf(p, "DMA Mode: %s(%s)",
72 (c0&0x20)?((art&0x03)?"UDMA":" DMA"):" PIO",
73 (art&0x02)?"2":(art&0x01)?"1":"0");
74 p += sprintf(p, " %s(%s)",
75 (c0&0x40)?((art&0x0c)?"UDMA":" DMA"):" PIO",
76 (art&0x08)?"2":(art&0x04)?"1":"0");
77 p += sprintf(p, " %s(%s)",
78 (c1&0x20)?((art&0x30)?"UDMA":" DMA"):" PIO",
79 (art&0x20)?"2":(art&0x10)?"1":"0");
80 p += sprintf(p, " %s(%s)\n",
81 (c1&0x40)?((art&0xc0)?"UDMA":" DMA"):" PIO",
82 (art&0x80)?"2":(art&0x40)?"1":"0");
83 } else {
84#endif
85
86/*
87 * TO DO: active tuning and correction of cards without a bios.
88 */
89static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
90{
91 for ( ; chipset_table->xfer_speed ; chipset_table++)
92 if (chipset_table->xfer_speed == speed) {
93 return chipset_table->chipset_settings;
94 }
95 return chipset_table->chipset_settings;
96}
97
98static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
99{
100 for ( ; chipset_table->xfer_speed ; chipset_table++)
101 if (chipset_table->xfer_speed == speed) {
102 return chipset_table->ultra_settings;
103 }
104 return chipset_table->ultra_settings;
105}
106
107static u8 aec62xx_ratemask (ide_drive_t *drive)
108{
109 ide_hwif_t *hwif = HWIF(drive);
110 u8 mode;
111
112 switch(hwif->pci_dev->device) {
113 case PCI_DEVICE_ID_ARTOP_ATP865:
114 case PCI_DEVICE_ID_ARTOP_ATP865R:
115#if 0
116 mode = (hwif->INB(hwif->dma_master) & 0x10) ? 4 : 3;
117#else
118 mode = (hwif->INB(((hwif->channel) ?
119 hwif->mate->dma_status :
120 hwif->dma_status)) & 0x10) ? 4 : 3;
121#endif
122 break;
123 case PCI_DEVICE_ID_ARTOP_ATP860:
124 case PCI_DEVICE_ID_ARTOP_ATP860R:
125 mode = 2;
126 break;
127 case PCI_DEVICE_ID_ARTOP_ATP850UF:
128 default:
129 return 1;
130 }
131
132 if (!eighty_ninty_three(drive))
133 mode = min(mode, (u8)1);
134 return mode;
135}
136
137static int aec6210_tune_chipset (ide_drive_t *drive, u8 xferspeed)
138{
139 ide_hwif_t *hwif = HWIF(drive);
140 struct pci_dev *dev = hwif->pci_dev;
141 u16 d_conf = 0;
142 u8 speed = ide_rate_filter(aec62xx_ratemask(drive), xferspeed);
143 u8 ultra = 0, ultra_conf = 0;
144 u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
145 unsigned long flags;
146
147 local_irq_save(flags);
148 /* 0x40|(2*drive->dn): Active, 0x41|(2*drive->dn): Recovery */
149 pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf);
150 tmp0 = pci_bus_clock_list(speed, BUSCLOCK(dev));
151 d_conf = ((tmp0 & 0xf0) << 4) | (tmp0 & 0xf);
152 pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf);
153
154 tmp1 = 0x00;
155 tmp2 = 0x00;
156 pci_read_config_byte(dev, 0x54, &ultra);
157 tmp1 = ((0x00 << (2*drive->dn)) | (ultra & ~(3 << (2*drive->dn))));
158 ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
159 tmp2 = ((ultra_conf << (2*drive->dn)) | (tmp1 & ~(3 << (2*drive->dn))));
160 pci_write_config_byte(dev, 0x54, tmp2);
161 local_irq_restore(flags);
162 return(ide_config_drive_speed(drive, speed));
163}
164
165static int aec6260_tune_chipset (ide_drive_t *drive, u8 xferspeed)
166{
167 ide_hwif_t *hwif = HWIF(drive);
168 struct pci_dev *dev = hwif->pci_dev;
169 u8 speed = ide_rate_filter(aec62xx_ratemask(drive), xferspeed);
170 u8 unit = (drive->select.b.unit & 0x01);
171 u8 tmp1 = 0, tmp2 = 0;
172 u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
173 unsigned long flags;
174
175 local_irq_save(flags);
176 /* high 4-bits: Active, low 4-bits: Recovery */
177 pci_read_config_byte(dev, 0x40|drive->dn, &drive_conf);
178 drive_conf = pci_bus_clock_list(speed, BUSCLOCK(dev));
179 pci_write_config_byte(dev, 0x40|drive->dn, drive_conf);
180
181 pci_read_config_byte(dev, (0x44|hwif->channel), &ultra);
182 tmp1 = ((0x00 << (4*unit)) | (ultra & ~(7 << (4*unit))));
183 ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev));
184 tmp2 = ((ultra_conf << (4*unit)) | (tmp1 & ~(7 << (4*unit))));
185 pci_write_config_byte(dev, (0x44|hwif->channel), tmp2);
186 local_irq_restore(flags);
187 return(ide_config_drive_speed(drive, speed));
188}
189
190static int aec62xx_tune_chipset (ide_drive_t *drive, u8 speed)
191{
192 switch (HWIF(drive)->pci_dev->device) {
193 case PCI_DEVICE_ID_ARTOP_ATP865:
194 case PCI_DEVICE_ID_ARTOP_ATP865R:
195 case PCI_DEVICE_ID_ARTOP_ATP860:
196 case PCI_DEVICE_ID_ARTOP_ATP860R:
197 return ((int) aec6260_tune_chipset(drive, speed));
198 case PCI_DEVICE_ID_ARTOP_ATP850UF:
199 return ((int) aec6210_tune_chipset(drive, speed));
200 default:
201 return -1;
202 }
203}
204
205static int config_chipset_for_dma (ide_drive_t *drive)
206{
207 u8 speed = ide_dma_speed(drive, aec62xx_ratemask(drive));
208
209 if (!(speed))
210 return 0;
211
212 (void) aec62xx_tune_chipset(drive, speed);
213 return ide_dma_enable(drive);
214}
215
216static void aec62xx_tune_drive (ide_drive_t *drive, u8 pio)
217{
218 u8 speed = 0;
219 u8 new_pio = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL);
220
221 switch(pio) {
222 case 5: speed = new_pio; break;
223 case 4: speed = XFER_PIO_4; break;
224 case 3: speed = XFER_PIO_3; break;
225 case 2: speed = XFER_PIO_2; break;
226 case 1: speed = XFER_PIO_1; break;
227 default: speed = XFER_PIO_0; break;
228 }
229 (void) aec62xx_tune_chipset(drive, speed);
230}
231
232static int aec62xx_config_drive_xfer_rate (ide_drive_t *drive)
233{
234 ide_hwif_t *hwif = HWIF(drive);
235 struct hd_driveid *id = drive->id;
236
237 if ((id->capability & 1) && drive->autodma) {
238
239 if (ide_use_dma(drive)) {
240 if (config_chipset_for_dma(drive))
241 return hwif->ide_dma_on(drive);
242 }
243
244 goto fast_ata_pio;
245
246 } else if ((id->capability & 8) || (id->field_valid & 2)) {
247fast_ata_pio:
248 aec62xx_tune_drive(drive, 5);
249 return hwif->ide_dma_off_quietly(drive);
250 }
251 /* IORDY not supported */
252 return 0;
253}
254
255static int aec62xx_irq_timeout (ide_drive_t *drive)
256{
257 ide_hwif_t *hwif = HWIF(drive);
258 struct pci_dev *dev = hwif->pci_dev;
259
260 switch(dev->device) {
261 case PCI_DEVICE_ID_ARTOP_ATP860:
262 case PCI_DEVICE_ID_ARTOP_ATP860R:
263 case PCI_DEVICE_ID_ARTOP_ATP865:
264 case PCI_DEVICE_ID_ARTOP_ATP865R:
265 printk(" AEC62XX time out ");
266#if 0
267 {
268 int i = 0;
269 u8 reg49h = 0;
270 pci_read_config_byte(HWIF(drive)->pci_dev, 0x49, &reg49h);
271 for (i=0;i<256;i++)
272 pci_write_config_byte(HWIF(drive)->pci_dev, 0x49, reg49h|0x10);
273 pci_write_config_byte(HWIF(drive)->pci_dev, 0x49, reg49h & ~0x10);
274 }
275 return 0;
276#endif
277 default:
278 break;
279 }
280#if 0
281 {
282 ide_hwif_t *hwif = HWIF(drive);
283 struct pci_dev *dev = hwif->pci_dev;
284 u8 tmp1 = 0, tmp2 = 0, mode6 = 0;
285
286 pci_read_config_byte(dev, 0x44, &tmp1);
287 pci_read_config_byte(dev, 0x45, &tmp2);
288 printk(" AEC6280 r44=%x r45=%x ",tmp1,tmp2);
289 mode6 = HWIF(drive)->INB(((hwif->channel) ?
290 hwif->mate->dma_status :
291 hwif->dma_status));
292 printk(" AEC6280 133=%x ", (mode6 & 0x10));
293 }
294#endif
295 return 0;
296}
297
298static unsigned int __devinit init_chipset_aec62xx(struct pci_dev *dev, const char *name)
299{
300 int bus_speed = system_bus_clock();
301
302 if (dev->resource[PCI_ROM_RESOURCE].start) {
303 pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
304 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name, dev->resource[PCI_ROM_RESOURCE].start);
305 }
306
307 if (bus_speed <= 33)
308 pci_set_drvdata(dev, (void *) aec6xxx_33_base);
309 else
310 pci_set_drvdata(dev, (void *) aec6xxx_34_base);
311
312 return dev->irq;
313}
314
315static void __devinit init_hwif_aec62xx(ide_hwif_t *hwif)
316{
317 hwif->autodma = 0;
318 hwif->tuneproc = &aec62xx_tune_drive;
319 hwif->speedproc = &aec62xx_tune_chipset;
320
321 if (hwif->pci_dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
322 hwif->serialized = hwif->channel;
323 hwif->no_dsc = 1;
324 }
325
326 if (hwif->mate)
327 hwif->mate->serialized = hwif->serialized;
328
329 if (!hwif->dma_base) {
330 hwif->drives[0].autotune = 1;
331 hwif->drives[1].autotune = 1;
332 return;
333 }
334
335 hwif->ultra_mask = 0x7f;
336 hwif->mwdma_mask = 0x07;
337 hwif->swdma_mask = 0x07;
338
339 hwif->ide_dma_check = &aec62xx_config_drive_xfer_rate;
340 hwif->ide_dma_lostirq = &aec62xx_irq_timeout;
341 hwif->ide_dma_timeout = &aec62xx_irq_timeout;
342 if (!noautodma)
343 hwif->autodma = 1;
344 hwif->drives[0].autodma = hwif->autodma;
345 hwif->drives[1].autodma = hwif->autodma;
346}
347
348static void __devinit init_dma_aec62xx(ide_hwif_t *hwif, unsigned long dmabase)
349{
350 struct pci_dev *dev = hwif->pci_dev;
351
352 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) {
353 u8 reg54h = 0;
354 unsigned long flags;
355
356 spin_lock_irqsave(&ide_lock, flags);
357 pci_read_config_byte(dev, 0x54, &reg54h);
358 pci_write_config_byte(dev, 0x54, reg54h & ~(hwif->channel ? 0xF0 : 0x0F));
359 spin_unlock_irqrestore(&ide_lock, flags);
360 } else {
361 u8 ata66 = 0;
362 pci_read_config_byte(hwif->pci_dev, 0x49, &ata66);
363 if (!(hwif->udma_four))
364 hwif->udma_four = (ata66&(hwif->channel?0x02:0x01))?0:1;
365 }
366
367 ide_setup_dma(hwif, dmabase, 8);
368}
369
370static int __devinit init_setup_aec62xx(struct pci_dev *dev, ide_pci_device_t *d)
371{
372 return ide_setup_pci_device(dev, d);
373}
374
375static int __devinit init_setup_aec6x80(struct pci_dev *dev, ide_pci_device_t *d)
376{
377 unsigned long bar4reg = pci_resource_start(dev, 4);
378
379 if (inb(bar4reg+2) & 0x10) {
380 strcpy(d->name, "AEC6880");
381 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)
382 strcpy(d->name, "AEC6880R");
383 } else {
384 strcpy(d->name, "AEC6280");
385 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)
386 strcpy(d->name, "AEC6280R");
387 }
388
389 return ide_setup_pci_device(dev, d);
390}
391
392static ide_pci_device_t aec62xx_chipsets[] __devinitdata = {
393 { /* 0 */
394 .name = "AEC6210",
395 .init_setup = init_setup_aec62xx,
396 .init_chipset = init_chipset_aec62xx,
397 .init_hwif = init_hwif_aec62xx,
398 .init_dma = init_dma_aec62xx,
399 .channels = 2,
400 .autodma = AUTODMA,
401 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
402 .bootable = OFF_BOARD,
403 },{ /* 1 */
404 .name = "AEC6260",
405 .init_setup = init_setup_aec62xx,
406 .init_chipset = init_chipset_aec62xx,
407 .init_hwif = init_hwif_aec62xx,
408 .init_dma = init_dma_aec62xx,
409 .channels = 2,
410 .autodma = NOAUTODMA,
411 .bootable = OFF_BOARD,
412 },{ /* 2 */
413 .name = "AEC6260R",
414 .init_setup = init_setup_aec62xx,
415 .init_chipset = init_chipset_aec62xx,
416 .init_hwif = init_hwif_aec62xx,
417 .init_dma = init_dma_aec62xx,
418 .channels = 2,
419 .autodma = AUTODMA,
420 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
421 .bootable = NEVER_BOARD,
422 },{ /* 3 */
423 .name = "AEC6X80",
424 .init_setup = init_setup_aec6x80,
425 .init_chipset = init_chipset_aec62xx,
426 .init_hwif = init_hwif_aec62xx,
427 .init_dma = init_dma_aec62xx,
428 .channels = 2,
429 .autodma = AUTODMA,
430 .bootable = OFF_BOARD,
431 },{ /* 4 */
432 .name = "AEC6X80R",
433 .init_setup = init_setup_aec6x80,
434 .init_chipset = init_chipset_aec62xx,
435 .init_hwif = init_hwif_aec62xx,
436 .init_dma = init_dma_aec62xx,
437 .channels = 2,
438 .autodma = AUTODMA,
439 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
440 .bootable = OFF_BOARD,
441 }
442};
443
444/**
445 * aec62xx_init_one - called when a AEC is found
446 * @dev: the aec62xx device
447 * @id: the matching pci id
448 *
449 * Called when the PCI registration layer (or the IDE initialization)
450 * finds a device matching our IDE device tables.
451 */
452
453static int __devinit aec62xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
454{
455 ide_pci_device_t *d = &aec62xx_chipsets[id->driver_data];
456
457 return d->init_setup(dev, d);
458}
459
460static struct pci_device_id aec62xx_pci_tbl[] = {
461 { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
462 { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
463 { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
464 { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
465 { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
466 { 0, },
467};
468MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl);
469
470static struct pci_driver driver = {
471 .name = "AEC62xx_IDE",
472 .id_table = aec62xx_pci_tbl,
473 .probe = aec62xx_init_one,
474};
475
476static int aec62xx_ide_init(void)
477{
478 return ide_pci_register_driver(&driver);
479}
480
481module_init(aec62xx_ide_init);
482
483MODULE_AUTHOR("Andre Hedrick");
484MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE");
485MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/alim15x3.c b/drivers/ide/pci/alim15x3.c
new file mode 100644
index 000000000000..67efb38a9f6c
--- /dev/null
+++ b/drivers/ide/pci/alim15x3.c
@@ -0,0 +1,913 @@
1/*
2 * linux/drivers/ide/pci/alim15x3.c Version 0.17 2003/01/02
3 *
4 * Copyright (C) 1998-2000 Michel Aubry, Maintainer
5 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer
6 * Copyright (C) 1999-2000 CJ, cjtsai@ali.com.tw, Maintainer
7 *
8 * Copyright (C) 1998-2000 Andre Hedrick (andre@linux-ide.org)
9 * May be copied or modified under the terms of the GNU General Public License
10 * Copyright (C) 2002 Alan Cox <alan@redhat.com>
11 * ALi (now ULi M5228) support by Clear Zhang <Clear.Zhang@ali.com.tw>
12 *
13 * (U)DMA capable version of ali 1533/1543(C), 1535(D)
14 *
15 **********************************************************************
16 * 9/7/99 --Parts from the above author are included and need to be
17 * converted into standard interface, once I finish the thought.
18 *
19 * Recent changes
20 * Don't use LBA48 mode on ALi <= 0xC4
21 * Don't poke 0x79 with a non ALi northbridge
22 * Don't flip undefined bits on newer chipsets (fix Fujitsu laptop hang)
23 * Allow UDMA6 on revisions > 0xC4
24 *
25 * Documentation
26 * Chipset documentation available under NDA only
27 *
28 */
29
30#include <linux/config.h>
31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/kernel.h>
34#include <linux/pci.h>
35#include <linux/delay.h>
36#include <linux/hdreg.h>
37#include <linux/ide.h>
38#include <linux/init.h>
39
40#include <asm/io.h>
41
42#define DISPLAY_ALI_TIMINGS
43
44/*
45 * ALi devices are not plug in. Otherwise these static values would
46 * need to go. They ought to go away anyway
47 */
48
49static u8 m5229_revision;
50static u8 chip_is_1543c_e;
51static struct pci_dev *isa_dev;
52
53#if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS)
54#include <linux/stat.h>
55#include <linux/proc_fs.h>
56
57static u8 ali_proc = 0;
58
59static struct pci_dev *bmide_dev;
60
61static char *fifo[4] = {
62 "FIFO Off",
63 "FIFO On ",
64 "DMA mode",
65 "PIO mode" };
66
67static char *udmaT[8] = {
68 "1.5T",
69 " 2T",
70 "2.5T",
71 " 3T",
72 "3.5T",
73 " 4T",
74 " 6T",
75 " 8T"
76};
77
78static char *channel_status[8] = {
79 "OK ",
80 "busy ",
81 "DRQ ",
82 "DRQ busy ",
83 "error ",
84 "error busy ",
85 "error DRQ ",
86 "error DRQ busy"
87};
88
89/**
90 * ali_get_info - generate proc file for ALi IDE
91 * @buffer: buffer to fill
92 * @addr: address of user start in buffer
93 * @offset: offset into 'file'
94 * @count: buffer count
95 *
96 * Walks the Ali devices and outputs summary data on the tuning and
97 * anything else that will help with debugging
98 */
99
100static int ali_get_info (char *buffer, char **addr, off_t offset, int count)
101{
102 unsigned long bibma;
103 u8 reg53h, reg5xh, reg5yh, reg5xh1, reg5yh1, c0, c1, rev, tmp;
104 char *q, *p = buffer;
105
106 /* fetch rev. */
107 pci_read_config_byte(bmide_dev, 0x08, &rev);
108 if (rev >= 0xc1) /* M1543C or newer */
109 udmaT[7] = " ???";
110 else
111 fifo[3] = " ??? ";
112
113 /* first fetch bibma: */
114
115 bibma = pci_resource_start(bmide_dev, 4);
116
117 /*
118 * at that point bibma+0x2 et bibma+0xa are byte
119 * registers to investigate:
120 */
121 c0 = inb(bibma + 0x02);
122 c1 = inb(bibma + 0x0a);
123
124 p += sprintf(p,
125 "\n Ali M15x3 Chipset.\n");
126 p += sprintf(p,
127 " ------------------\n");
128 pci_read_config_byte(bmide_dev, 0x78, &reg53h);
129 p += sprintf(p, "PCI Clock: %d.\n", reg53h);
130
131 pci_read_config_byte(bmide_dev, 0x53, &reg53h);
132 p += sprintf(p,
133 "CD_ROM FIFO:%s, CD_ROM DMA:%s\n",
134 (reg53h & 0x02) ? "Yes" : "No ",
135 (reg53h & 0x01) ? "Yes" : "No " );
136 pci_read_config_byte(bmide_dev, 0x74, &reg53h);
137 p += sprintf(p,
138 "FIFO Status: contains %d Words, runs%s%s\n\n",
139 (reg53h & 0x3f),
140 (reg53h & 0x40) ? " OVERWR" : "",
141 (reg53h & 0x80) ? " OVERRD." : "." );
142
143 p += sprintf(p,
144 "-------------------primary channel"
145 "-------------------secondary channel"
146 "---------\n\n");
147
148 pci_read_config_byte(bmide_dev, 0x09, &reg53h);
149 p += sprintf(p,
150 "channel status: %s"
151 " %s\n",
152 (reg53h & 0x20) ? "On " : "Off",
153 (reg53h & 0x10) ? "On " : "Off" );
154
155 p += sprintf(p,
156 "both channels togth: %s"
157 " %s\n",
158 (c0&0x80) ? "No " : "Yes",
159 (c1&0x80) ? "No " : "Yes" );
160
161 pci_read_config_byte(bmide_dev, 0x76, &reg53h);
162 p += sprintf(p,
163 "Channel state: %s %s\n",
164 channel_status[reg53h & 0x07],
165 channel_status[(reg53h & 0x70) >> 4] );
166
167 pci_read_config_byte(bmide_dev, 0x58, &reg5xh);
168 pci_read_config_byte(bmide_dev, 0x5c, &reg5yh);
169 p += sprintf(p,
170 "Add. Setup Timing: %dT"
171 " %dT\n",
172 (reg5xh & 0x07) ? (reg5xh & 0x07) : 8,
173 (reg5yh & 0x07) ? (reg5yh & 0x07) : 8 );
174
175 pci_read_config_byte(bmide_dev, 0x59, &reg5xh);
176 pci_read_config_byte(bmide_dev, 0x5d, &reg5yh);
177 p += sprintf(p,
178 "Command Act. Count: %dT"
179 " %dT\n"
180 "Command Rec. Count: %dT"
181 " %dT\n\n",
182 (reg5xh & 0x70) ? ((reg5xh & 0x70) >> 4) : 8,
183 (reg5yh & 0x70) ? ((reg5yh & 0x70) >> 4) : 8,
184 (reg5xh & 0x0f) ? (reg5xh & 0x0f) : 16,
185 (reg5yh & 0x0f) ? (reg5yh & 0x0f) : 16 );
186
187 p += sprintf(p,
188 "----------------drive0-----------drive1"
189 "------------drive0-----------drive1------\n\n");
190 p += sprintf(p,
191 "DMA enabled: %s %s"
192 " %s %s\n",
193 (c0&0x20) ? "Yes" : "No ",
194 (c0&0x40) ? "Yes" : "No ",
195 (c1&0x20) ? "Yes" : "No ",
196 (c1&0x40) ? "Yes" : "No " );
197
198 pci_read_config_byte(bmide_dev, 0x54, &reg5xh);
199 pci_read_config_byte(bmide_dev, 0x55, &reg5yh);
200 q = "FIFO threshold: %2d Words %2d Words"
201 " %2d Words %2d Words\n";
202 if (rev < 0xc1) {
203 if ((rev == 0x20) &&
204 (pci_read_config_byte(bmide_dev, 0x4f, &tmp), (tmp &= 0x20))) {
205 p += sprintf(p, q, 8, 8, 8, 8);
206 } else {
207 p += sprintf(p, q,
208 (reg5xh & 0x03) + 12,
209 ((reg5xh & 0x30)>>4) + 12,
210 (reg5yh & 0x03) + 12,
211 ((reg5yh & 0x30)>>4) + 12 );
212 }
213 } else {
214 int t1 = (tmp = (reg5xh & 0x03)) ? (tmp << 3) : 4;
215 int t2 = (tmp = ((reg5xh & 0x30)>>4)) ? (tmp << 3) : 4;
216 int t3 = (tmp = (reg5yh & 0x03)) ? (tmp << 3) : 4;
217 int t4 = (tmp = ((reg5yh & 0x30)>>4)) ? (tmp << 3) : 4;
218 p += sprintf(p, q, t1, t2, t3, t4);
219 }
220
221#if 0
222 p += sprintf(p,
223 "FIFO threshold: %2d Words %2d Words"
224 " %2d Words %2d Words\n",
225 (reg5xh & 0x03) + 12,
226 ((reg5xh & 0x30)>>4) + 12,
227 (reg5yh & 0x03) + 12,
228 ((reg5yh & 0x30)>>4) + 12 );
229#endif
230
231 p += sprintf(p,
232 "FIFO mode: %s %s %s %s\n",
233 fifo[((reg5xh & 0x0c) >> 2)],
234 fifo[((reg5xh & 0xc0) >> 6)],
235 fifo[((reg5yh & 0x0c) >> 2)],
236 fifo[((reg5yh & 0xc0) >> 6)] );
237
238 pci_read_config_byte(bmide_dev, 0x5a, &reg5xh);
239 pci_read_config_byte(bmide_dev, 0x5b, &reg5xh1);
240 pci_read_config_byte(bmide_dev, 0x5e, &reg5yh);
241 pci_read_config_byte(bmide_dev, 0x5f, &reg5yh1);
242
243 p += sprintf(p,/*
244 "------------------drive0-----------drive1"
245 "------------drive0-----------drive1------\n")*/
246 "Dt RW act. Cnt %2dT %2dT"
247 " %2dT %2dT\n"
248 "Dt RW rec. Cnt %2dT %2dT"
249 " %2dT %2dT\n\n",
250 (reg5xh & 0x70) ? ((reg5xh & 0x70) >> 4) : 8,
251 (reg5xh1 & 0x70) ? ((reg5xh1 & 0x70) >> 4) : 8,
252 (reg5yh & 0x70) ? ((reg5yh & 0x70) >> 4) : 8,
253 (reg5yh1 & 0x70) ? ((reg5yh1 & 0x70) >> 4) : 8,
254 (reg5xh & 0x0f) ? (reg5xh & 0x0f) : 16,
255 (reg5xh1 & 0x0f) ? (reg5xh1 & 0x0f) : 16,
256 (reg5yh & 0x0f) ? (reg5yh & 0x0f) : 16,
257 (reg5yh1 & 0x0f) ? (reg5yh1 & 0x0f) : 16 );
258
259 p += sprintf(p,
260 "-----------------------------------UDMA Timings"
261 "--------------------------------\n\n");
262
263 pci_read_config_byte(bmide_dev, 0x56, &reg5xh);
264 pci_read_config_byte(bmide_dev, 0x57, &reg5yh);
265 p += sprintf(p,
266 "UDMA: %s %s"
267 " %s %s\n"
268 "UDMA timings: %s %s"
269 " %s %s\n\n",
270 (reg5xh & 0x08) ? "OK" : "No",
271 (reg5xh & 0x80) ? "OK" : "No",
272 (reg5yh & 0x08) ? "OK" : "No",
273 (reg5yh & 0x80) ? "OK" : "No",
274 udmaT[(reg5xh & 0x07)],
275 udmaT[(reg5xh & 0x70) >> 4],
276 udmaT[reg5yh & 0x07],
277 udmaT[(reg5yh & 0x70) >> 4] );
278
279 return p-buffer; /* => must be less than 4k! */
280}
281#endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS) */
282
283/**
284 * ali15x3_tune_drive - set up a drive
285 * @drive: drive to tune
286 * @pio: unused
287 *
288 * Select the best PIO timing for the drive in question. Then
289 * program the controller for this drive set up
290 */
291
292static void ali15x3_tune_drive (ide_drive_t *drive, u8 pio)
293{
294 ide_pio_data_t d;
295 ide_hwif_t *hwif = HWIF(drive);
296 struct pci_dev *dev = hwif->pci_dev;
297 int s_time, a_time, c_time;
298 u8 s_clc, a_clc, r_clc;
299 unsigned long flags;
300 int bus_speed = system_bus_clock();
301 int port = hwif->channel ? 0x5c : 0x58;
302 int portFIFO = hwif->channel ? 0x55 : 0x54;
303 u8 cd_dma_fifo = 0;
304 int unit = drive->select.b.unit & 1;
305
306 pio = ide_get_best_pio_mode(drive, pio, 5, &d);
307 s_time = ide_pio_timings[pio].setup_time;
308 a_time = ide_pio_timings[pio].active_time;
309 if ((s_clc = (s_time * bus_speed + 999) / 1000) >= 8)
310 s_clc = 0;
311 if ((a_clc = (a_time * bus_speed + 999) / 1000) >= 8)
312 a_clc = 0;
313 c_time = ide_pio_timings[pio].cycle_time;
314
315#if 0
316 if ((r_clc = ((c_time - s_time - a_time) * bus_speed + 999) / 1000) >= 16)
317 r_clc = 0;
318#endif
319
320 if (!(r_clc = (c_time * bus_speed + 999) / 1000 - a_clc - s_clc)) {
321 r_clc = 1;
322 } else {
323 if (r_clc >= 16)
324 r_clc = 0;
325 }
326 local_irq_save(flags);
327
328 /*
329 * PIO mode => ATA FIFO on, ATAPI FIFO off
330 */
331 pci_read_config_byte(dev, portFIFO, &cd_dma_fifo);
332 if (drive->media==ide_disk) {
333 if (unit) {
334 pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0x0F) | 0x50);
335 } else {
336 pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0xF0) | 0x05);
337 }
338 } else {
339 if (unit) {
340 pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0x0F);
341 } else {
342 pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0xF0);
343 }
344 }
345
346 pci_write_config_byte(dev, port, s_clc);
347 pci_write_config_byte(dev, port+drive->select.b.unit+2, (a_clc << 4) | r_clc);
348 local_irq_restore(flags);
349
350 /*
351 * setup active rec
352 * { 70, 165, 365 }, PIO Mode 0
353 * { 50, 125, 208 }, PIO Mode 1
354 * { 30, 100, 110 }, PIO Mode 2
355 * { 30, 80, 70 }, PIO Mode 3 with IORDY
356 * { 25, 70, 25 }, PIO Mode 4 with IORDY ns
357 * { 20, 50, 30 } PIO Mode 5 with IORDY (nonstandard)
358 */
359
360}
361
362/**
363 * ali15x3_can_ultra - check for ultra DMA support
364 * @drive: drive to do the check
365 *
366 * Check the drive and controller revisions. Return 0 if UDMA is
367 * not available, or 1 if UDMA can be used. The actual rules for
368 * the ALi are
369 * No UDMA on revisions <= 0x20
370 * Disk only for revisions < 0xC2
371 * Not WDC drives for revisions < 0xC2
372 *
373 * FIXME: WDC ifdef needs to die
374 */
375
376static u8 ali15x3_can_ultra (ide_drive_t *drive)
377{
378#ifndef CONFIG_WDC_ALI15X3
379 struct hd_driveid *id = drive->id;
380#endif /* CONFIG_WDC_ALI15X3 */
381
382 if (m5229_revision <= 0x20) {
383 return 0;
384 } else if ((m5229_revision < 0xC2) &&
385#ifndef CONFIG_WDC_ALI15X3
386 ((chip_is_1543c_e && strstr(id->model, "WDC ")) ||
387 (drive->media!=ide_disk))) {
388#else /* CONFIG_WDC_ALI15X3 */
389 (drive->media!=ide_disk)) {
390#endif /* CONFIG_WDC_ALI15X3 */
391 return 0;
392 } else {
393 return 1;
394 }
395}
396
397/**
398 * ali15x3_ratemask - generate DMA mode list
399 * @drive: drive to compute against
400 *
401 * Generate a list of the available DMA modes for the drive.
402 * FIXME: this function contains lots of bogus masking we can dump
403 *
404 * Return the highest available mode (UDMA33, UDMA66, UDMA100,..)
405 */
406
407static u8 ali15x3_ratemask (ide_drive_t *drive)
408{
409 u8 mode = 0, can_ultra = ali15x3_can_ultra(drive);
410
411 if (m5229_revision > 0xC4 && can_ultra) {
412 mode = 4;
413 } else if (m5229_revision == 0xC4 && can_ultra) {
414 mode = 3;
415 } else if (m5229_revision >= 0xC2 && can_ultra) {
416 mode = 2;
417 } else if (can_ultra) {
418 return 1;
419 } else {
420 return 0;
421 }
422
423 /*
424 * If the drive sees no suitable cable then UDMA 33
425 * is the highest permitted mode
426 */
427
428 if (!eighty_ninty_three(drive))
429 mode = min(mode, (u8)1);
430 return mode;
431}
432
433/**
434 * ali15x3_tune_chipset - set up chiset for new speed
435 * @drive: drive to configure for
436 * @xferspeed: desired speed
437 *
438 * Configure the hardware for the desired IDE transfer mode.
439 * We also do the needed drive configuration through helpers
440 */
441
442static int ali15x3_tune_chipset (ide_drive_t *drive, u8 xferspeed)
443{
444 ide_hwif_t *hwif = HWIF(drive);
445 struct pci_dev *dev = hwif->pci_dev;
446 u8 speed = ide_rate_filter(ali15x3_ratemask(drive), xferspeed);
447 u8 speed1 = speed;
448 u8 unit = (drive->select.b.unit & 0x01);
449 u8 tmpbyte = 0x00;
450 int m5229_udma = (hwif->channel) ? 0x57 : 0x56;
451
452 if (speed == XFER_UDMA_6)
453 speed1 = 0x47;
454
455 if (speed < XFER_UDMA_0) {
456 u8 ultra_enable = (unit) ? 0x7f : 0xf7;
457 /*
458 * clear "ultra enable" bit
459 */
460 pci_read_config_byte(dev, m5229_udma, &tmpbyte);
461 tmpbyte &= ultra_enable;
462 pci_write_config_byte(dev, m5229_udma, tmpbyte);
463
464 if (speed < XFER_SW_DMA_0)
465 ali15x3_tune_drive(drive, speed);
466 } else {
467 pci_read_config_byte(dev, m5229_udma, &tmpbyte);
468 tmpbyte &= (0x0f << ((1-unit) << 2));
469 /*
470 * enable ultra dma and set timing
471 */
472 tmpbyte |= ((0x08 | ((4-speed1)&0x07)) << (unit << 2));
473 pci_write_config_byte(dev, m5229_udma, tmpbyte);
474 if (speed >= XFER_UDMA_3) {
475 pci_read_config_byte(dev, 0x4b, &tmpbyte);
476 tmpbyte |= 1;
477 pci_write_config_byte(dev, 0x4b, tmpbyte);
478 }
479 }
480 return (ide_config_drive_speed(drive, speed));
481}
482
483
484/**
485 * config_chipset_for_dma - set up DMA mode
486 * @drive: drive to configure for
487 *
488 * Place a drive into DMA mode and tune the chipset for
489 * the selected speed.
490 *
491 * Returns true if DMA mode can be used
492 */
493
494static int config_chipset_for_dma (ide_drive_t *drive)
495{
496 u8 speed = ide_dma_speed(drive, ali15x3_ratemask(drive));
497
498 if (!(speed))
499 return 0;
500
501 (void) ali15x3_tune_chipset(drive, speed);
502 return ide_dma_enable(drive);
503}
504
505/**
506 * ali15x3_config_drive_for_dma - configure for DMA
507 * @drive: drive to configure
508 *
509 * Configure a drive for DMA operation. If DMA is not possible we
510 * drop the drive into PIO mode instead.
511 *
512 * FIXME: exactly what are we trying to return here
513 */
514
515static int ali15x3_config_drive_for_dma(ide_drive_t *drive)
516{
517 ide_hwif_t *hwif = HWIF(drive);
518 struct hd_driveid *id = drive->id;
519
520 if ((m5229_revision<=0x20) && (drive->media!=ide_disk))
521 return hwif->ide_dma_off_quietly(drive);
522
523 drive->init_speed = 0;
524
525 if ((id != NULL) && ((id->capability & 1) != 0) && drive->autodma) {
526 /* Consult the list of known "bad" drives */
527 if (__ide_dma_bad_drive(drive))
528 goto ata_pio;
529 if ((id->field_valid & 4) && (m5229_revision >= 0xC2)) {
530 if (id->dma_ultra & hwif->ultra_mask) {
531 /* Force if Capable UltraDMA */
532 int dma = config_chipset_for_dma(drive);
533 if ((id->field_valid & 2) && !dma)
534 goto try_dma_modes;
535 }
536 } else if (id->field_valid & 2) {
537try_dma_modes:
538 if ((id->dma_mword & hwif->mwdma_mask) ||
539 (id->dma_1word & hwif->swdma_mask)) {
540 /* Force if Capable regular DMA modes */
541 if (!config_chipset_for_dma(drive))
542 goto no_dma_set;
543 }
544 } else if (__ide_dma_good_drive(drive) &&
545 (id->eide_dma_time < 150)) {
546 /* Consult the list of known "good" drives */
547 if (!config_chipset_for_dma(drive))
548 goto no_dma_set;
549 } else {
550 goto ata_pio;
551 }
552 } else {
553ata_pio:
554 hwif->tuneproc(drive, 255);
555no_dma_set:
556 return hwif->ide_dma_off_quietly(drive);
557 }
558 return hwif->ide_dma_on(drive);
559}
560
561/**
562 * ali15x3_dma_setup - begin a DMA phase
563 * @drive: target device
564 *
565 * Returns 1 if the DMA cannot be performed, zero on success.
566 */
567
568static int ali15x3_dma_setup(ide_drive_t *drive)
569{
570 if (m5229_revision < 0xC2 && drive->media != ide_disk) {
571 if (rq_data_dir(drive->hwif->hwgroup->rq))
572 return 1; /* try PIO instead of DMA */
573 }
574 return ide_dma_setup(drive);
575}
576
577/**
578 * init_chipset_ali15x3 - Initialise an ALi IDE controller
579 * @dev: PCI device
580 * @name: Name of the controller
581 *
582 * This function initializes the ALI IDE controller and where
583 * appropriate also sets up the 1533 southbridge.
584 */
585
586static unsigned int __init init_chipset_ali15x3 (struct pci_dev *dev, const char *name)
587{
588 unsigned long flags;
589 u8 tmpbyte;
590 struct pci_dev *north = pci_find_slot(0, PCI_DEVFN(0,0));
591
592 pci_read_config_byte(dev, PCI_REVISION_ID, &m5229_revision);
593
594 isa_dev = pci_find_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL);
595
596#if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS)
597 if (!ali_proc) {
598 ali_proc = 1;
599 bmide_dev = dev;
600 ide_pci_create_host_proc("ali", ali_get_info);
601 }
602#endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_PROC_FS) */
603
604 local_irq_save(flags);
605
606 if (m5229_revision < 0xC2) {
607 /*
608 * revision 0x20 (1543-E, 1543-F)
609 * revision 0xC0, 0xC1 (1543C-C, 1543C-D, 1543C-E)
610 * clear CD-ROM DMA write bit, m5229, 0x4b, bit 7
611 */
612 pci_read_config_byte(dev, 0x4b, &tmpbyte);
613 /*
614 * clear bit 7
615 */
616 pci_write_config_byte(dev, 0x4b, tmpbyte & 0x7F);
617 local_irq_restore(flags);
618 return 0;
619 }
620
621 /*
622 * 1543C-B?, 1535, 1535D, 1553
623 * Note 1: not all "motherboard" support this detection
624 * Note 2: if no udma 66 device, the detection may "error".
625 * but in this case, we will not set the device to
626 * ultra 66, the detection result is not important
627 */
628
629 /*
630 * enable "Cable Detection", m5229, 0x4b, bit3
631 */
632 pci_read_config_byte(dev, 0x4b, &tmpbyte);
633 pci_write_config_byte(dev, 0x4b, tmpbyte | 0x08);
634
635 /*
636 * We should only tune the 1533 enable if we are using an ALi
637 * North bridge. We might have no north found on some zany
638 * box without a device at 0:0.0. The ALi bridge will be at
639 * 0:0.0 so if we didn't find one we know what is cooking.
640 */
641 if (north && north->vendor != PCI_VENDOR_ID_AL) {
642 local_irq_restore(flags);
643 return 0;
644 }
645
646 if (m5229_revision < 0xC5 && isa_dev)
647 {
648 /*
649 * set south-bridge's enable bit, m1533, 0x79
650 */
651
652 pci_read_config_byte(isa_dev, 0x79, &tmpbyte);
653 if (m5229_revision == 0xC2) {
654 /*
655 * 1543C-B0 (m1533, 0x79, bit 2)
656 */
657 pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x04);
658 } else if (m5229_revision >= 0xC3) {
659 /*
660 * 1553/1535 (m1533, 0x79, bit 1)
661 */
662 pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x02);
663 }
664 }
665 local_irq_restore(flags);
666 return 0;
667}
668
669/**
670 * ata66_ali15x3 - check for UDMA 66 support
671 * @hwif: IDE interface
672 *
673 * This checks if the controller and the cable are capable
674 * of UDMA66 transfers. It doesn't check the drives.
675 * But see note 2 below!
676 *
677 * FIXME: frobs bits that are not defined on newer ALi devicea
678 */
679
680static unsigned int __init ata66_ali15x3 (ide_hwif_t *hwif)
681{
682 struct pci_dev *dev = hwif->pci_dev;
683 unsigned int ata66 = 0;
684 u8 cable_80_pin[2] = { 0, 0 };
685
686 unsigned long flags;
687 u8 tmpbyte;
688
689 local_irq_save(flags);
690
691 if (m5229_revision >= 0xC2) {
692 /*
693 * Ultra66 cable detection (from Host View)
694 * m5229, 0x4a, bit0: primary, bit1: secondary 80 pin
695 */
696 pci_read_config_byte(dev, 0x4a, &tmpbyte);
697 /*
698 * 0x4a, bit0 is 0 => primary channel
699 * has 80-pin (from host view)
700 */
701 if (!(tmpbyte & 0x01)) cable_80_pin[0] = 1;
702 /*
703 * 0x4a, bit1 is 0 => secondary channel
704 * has 80-pin (from host view)
705 */
706 if (!(tmpbyte & 0x02)) cable_80_pin[1] = 1;
707 /*
708 * Allow ata66 if cable of current channel has 80 pins
709 */
710 ata66 = (hwif->channel)?cable_80_pin[1]:cable_80_pin[0];
711 } else {
712 /*
713 * check m1533, 0x5e, bit 1~4 == 1001 => & 00011110 = 00010010
714 */
715 pci_read_config_byte(isa_dev, 0x5e, &tmpbyte);
716 chip_is_1543c_e = ((tmpbyte & 0x1e) == 0x12) ? 1: 0;
717 }
718
719 /*
720 * CD_ROM DMA on (m5229, 0x53, bit0)
721 * Enable this bit even if we want to use PIO
722 * PIO FIFO off (m5229, 0x53, bit1)
723 * The hardware will use 0x54h and 0x55h to control PIO FIFO
724 * (Not on later devices it seems)
725 *
726 * 0x53 changes meaning on later revs - we must no touch
727 * bit 1 on them. Need to check if 0x20 is the right break
728 */
729
730 pci_read_config_byte(dev, 0x53, &tmpbyte);
731
732 if(m5229_revision <= 0x20)
733 tmpbyte = (tmpbyte & (~0x02)) | 0x01;
734 else
735 tmpbyte |= 0x01;
736
737 pci_write_config_byte(dev, 0x53, tmpbyte);
738
739 local_irq_restore(flags);
740
741 return(ata66);
742}
743
744/**
745 * init_hwif_common_ali15x3 - Set up ALI IDE hardware
746 * @hwif: IDE interface
747 *
748 * Initialize the IDE structure side of the ALi 15x3 driver.
749 */
750
751static void __init init_hwif_common_ali15x3 (ide_hwif_t *hwif)
752{
753 hwif->autodma = 0;
754 hwif->tuneproc = &ali15x3_tune_drive;
755 hwif->speedproc = &ali15x3_tune_chipset;
756
757 /* don't use LBA48 DMA on ALi devices before rev 0xC5 */
758 hwif->no_lba48_dma = (m5229_revision <= 0xC4) ? 1 : 0;
759
760 if (!hwif->dma_base) {
761 hwif->drives[0].autotune = 1;
762 hwif->drives[1].autotune = 1;
763 return;
764 }
765
766 hwif->atapi_dma = 1;
767
768 if (m5229_revision > 0x20)
769 hwif->ultra_mask = 0x7f;
770 hwif->mwdma_mask = 0x07;
771 hwif->swdma_mask = 0x07;
772
773 if (m5229_revision >= 0x20) {
774 /*
775 * M1543C or newer for DMAing
776 */
777 hwif->ide_dma_check = &ali15x3_config_drive_for_dma;
778 hwif->dma_setup = &ali15x3_dma_setup;
779 if (!noautodma)
780 hwif->autodma = 1;
781 if (!(hwif->udma_four))
782 hwif->udma_four = ata66_ali15x3(hwif);
783 }
784 hwif->drives[0].autodma = hwif->autodma;
785 hwif->drives[1].autodma = hwif->autodma;
786}
787
788/**
789 * init_hwif_ali15x3 - Initialize the ALI IDE x86 stuff
790 * @hwif: interface to configure
791 *
792 * Obtain the IRQ tables for an ALi based IDE solution on the PC
793 * class platforms. This part of the code isn't applicable to the
794 * Sparc systems
795 */
796
797static void __init init_hwif_ali15x3 (ide_hwif_t *hwif)
798{
799 u8 ideic, inmir;
800 s8 irq_routing_table[] = { -1, 9, 3, 10, 4, 5, 7, 6,
801 1, 11, 0, 12, 0, 14, 0, 15 };
802 int irq = -1;
803
804 if (hwif->pci_dev->device == PCI_DEVICE_ID_AL_M5229)
805 hwif->irq = hwif->channel ? 15 : 14;
806
807 if (isa_dev) {
808 /*
809 * read IDE interface control
810 */
811 pci_read_config_byte(isa_dev, 0x58, &ideic);
812
813 /* bit0, bit1 */
814 ideic = ideic & 0x03;
815
816 /* get IRQ for IDE Controller */
817 if ((hwif->channel && ideic == 0x03) ||
818 (!hwif->channel && !ideic)) {
819 /*
820 * get SIRQ1 routing table
821 */
822 pci_read_config_byte(isa_dev, 0x44, &inmir);
823 inmir = inmir & 0x0f;
824 irq = irq_routing_table[inmir];
825 } else if (hwif->channel && !(ideic & 0x01)) {
826 /*
827 * get SIRQ2 routing table
828 */
829 pci_read_config_byte(isa_dev, 0x75, &inmir);
830 inmir = inmir & 0x0f;
831 irq = irq_routing_table[inmir];
832 }
833 if(irq >= 0)
834 hwif->irq = irq;
835 }
836
837 init_hwif_common_ali15x3(hwif);
838}
839
840/**
841 * init_dma_ali15x3 - set up DMA on ALi15x3
842 * @hwif: IDE interface
843 * @dmabase: DMA interface base PCI address
844 *
845 * Set up the DMA functionality on the ALi 15x3. For the ALi
846 * controllers this is generic so we can let the generic code do
847 * the actual work.
848 */
849
850static void __init init_dma_ali15x3 (ide_hwif_t *hwif, unsigned long dmabase)
851{
852 if (m5229_revision < 0x20)
853 return;
854 if (!(hwif->channel))
855 hwif->OUTB(hwif->INB(dmabase+2) & 0x60, dmabase+2);
856 ide_setup_dma(hwif, dmabase, 8);
857}
858
859static ide_pci_device_t ali15x3_chipset __devinitdata = {
860 .name = "ALI15X3",
861 .init_chipset = init_chipset_ali15x3,
862 .init_hwif = init_hwif_ali15x3,
863 .init_dma = init_dma_ali15x3,
864 .channels = 2,
865 .autodma = AUTODMA,
866 .bootable = ON_BOARD,
867};
868
869/**
870 * alim15x3_init_one - set up an ALi15x3 IDE controller
871 * @dev: PCI device to set up
872 *
873 * Perform the actual set up for an ALi15x3 that has been found by the
874 * hot plug layer.
875 */
876
877static int __devinit alim15x3_init_one(struct pci_dev *dev, const struct pci_device_id *id)
878{
879 ide_pci_device_t *d = &ali15x3_chipset;
880
881 if(pci_find_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, NULL))
882 printk(KERN_ERR "Warning: ATI Radeon IGP Northbridge is not yet fully tested.\n");
883
884#if defined(CONFIG_SPARC64)
885 d->init_hwif = init_hwif_common_ali15x3;
886#endif /* CONFIG_SPARC64 */
887 return ide_setup_pci_device(dev, d);
888}
889
890
891static struct pci_device_id alim15x3_pci_tbl[] = {
892 { PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5229, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
893 { PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5228, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
894 { 0, },
895};
896MODULE_DEVICE_TABLE(pci, alim15x3_pci_tbl);
897
898static struct pci_driver driver = {
899 .name = "ALI15x3_IDE",
900 .id_table = alim15x3_pci_tbl,
901 .probe = alim15x3_init_one,
902};
903
904static int ali15x3_ide_init(void)
905{
906 return ide_pci_register_driver(&driver);
907}
908
909module_init(ali15x3_ide_init);
910
911MODULE_AUTHOR("Michael Aubry, Andrzej Krzysztofowicz, CJ, Andre Hedrick, Alan Cox");
912MODULE_DESCRIPTION("PCI driver module for ALi 15x3 IDE");
913MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/amd74xx.c b/drivers/ide/pci/amd74xx.c
new file mode 100644
index 000000000000..47225e324356
--- /dev/null
+++ b/drivers/ide/pci/amd74xx.c
@@ -0,0 +1,543 @@
1/*
2 * Version 2.13
3 *
4 * AMD 755/756/766/8111 and nVidia nForce/2/2s/3/3s/CK804/MCP04
5 * IDE driver for Linux.
6 *
7 * Copyright (c) 2000-2002 Vojtech Pavlik
8 *
9 * Based on the work of:
10 * Andre Hedrick
11 */
12
13/*
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License version 2 as published by
16 * the Free Software Foundation.
17 */
18
19#include <linux/config.h>
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/ioport.h>
23#include <linux/blkdev.h>
24#include <linux/pci.h>
25#include <linux/init.h>
26#include <linux/ide.h>
27#include <asm/io.h>
28
29#include "ide-timing.h"
30
31#define DISPLAY_AMD_TIMINGS
32
33#define AMD_IDE_ENABLE (0x00 + amd_config->base)
34#define AMD_IDE_CONFIG (0x01 + amd_config->base)
35#define AMD_CABLE_DETECT (0x02 + amd_config->base)
36#define AMD_DRIVE_TIMING (0x08 + amd_config->base)
37#define AMD_8BIT_TIMING (0x0e + amd_config->base)
38#define AMD_ADDRESS_SETUP (0x0c + amd_config->base)
39#define AMD_UDMA_TIMING (0x10 + amd_config->base)
40
41#define AMD_UDMA 0x07
42#define AMD_UDMA_33 0x01
43#define AMD_UDMA_66 0x02
44#define AMD_UDMA_100 0x03
45#define AMD_UDMA_133 0x04
46#define AMD_CHECK_SWDMA 0x08
47#define AMD_BAD_SWDMA 0x10
48#define AMD_BAD_FIFO 0x20
49#define AMD_CHECK_SERENADE 0x40
50
51/*
52 * AMD SouthBridge chips.
53 */
54
55static struct amd_ide_chip {
56 unsigned short id;
57 unsigned long base;
58 unsigned char flags;
59} amd_ide_chips[] = {
60 { PCI_DEVICE_ID_AMD_COBRA_7401, 0x40, AMD_UDMA_33 | AMD_BAD_SWDMA },
61 { PCI_DEVICE_ID_AMD_VIPER_7409, 0x40, AMD_UDMA_66 | AMD_CHECK_SWDMA },
62 { PCI_DEVICE_ID_AMD_VIPER_7411, 0x40, AMD_UDMA_100 | AMD_BAD_FIFO },
63 { PCI_DEVICE_ID_AMD_OPUS_7441, 0x40, AMD_UDMA_100 },
64 { PCI_DEVICE_ID_AMD_8111_IDE, 0x40, AMD_UDMA_133 | AMD_CHECK_SERENADE },
65 { PCI_DEVICE_ID_NVIDIA_NFORCE_IDE, 0x50, AMD_UDMA_100 },
66 { PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE, 0x50, AMD_UDMA_133 },
67 { PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE, 0x50, AMD_UDMA_133 },
68 { PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA, 0x50, AMD_UDMA_133 },
69 { PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE, 0x50, AMD_UDMA_133 },
70 { PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE, 0x50, AMD_UDMA_133 },
71 { PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA, 0x50, AMD_UDMA_133 },
72 { PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2, 0x50, AMD_UDMA_133 },
73 { PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE, 0x50, AMD_UDMA_133 },
74 { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE, 0x50, AMD_UDMA_133 },
75 { 0 }
76};
77
78static struct amd_ide_chip *amd_config;
79static ide_pci_device_t *amd_chipset;
80static unsigned int amd_80w;
81static unsigned int amd_clock;
82
83static char *amd_dma[] = { "MWDMA16", "UDMA33", "UDMA66", "UDMA100", "UDMA133" };
84static unsigned char amd_cyc2udma[] = { 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 };
85
86/*
87 * AMD /proc entry.
88 */
89
90#ifdef CONFIG_PROC_FS
91
92#include <linux/stat.h>
93#include <linux/proc_fs.h>
94
95static u8 amd74xx_proc;
96
97static unsigned char amd_udma2cyc[] = { 4, 6, 8, 10, 3, 2, 1, 15 };
98static unsigned long amd_base;
99static struct pci_dev *bmide_dev;
100extern int (*amd74xx_display_info)(char *, char **, off_t, int); /* ide-proc.c */
101
102#define amd_print(format, arg...) p += sprintf(p, format "\n" , ## arg)
103#define amd_print_drive(name, format, arg...)\
104 p += sprintf(p, name); for (i = 0; i < 4; i++) p += sprintf(p, format, ## arg); p += sprintf(p, "\n");
105
106static int amd74xx_get_info(char *buffer, char **addr, off_t offset, int count)
107{
108 int speed[4], cycle[4], setup[4], active[4], recover[4], den[4],
109 uen[4], udma[4], active8b[4], recover8b[4];
110 struct pci_dev *dev = bmide_dev;
111 unsigned int v, u, i;
112 unsigned short c, w;
113 unsigned char t;
114 int len;
115 char *p = buffer;
116
117 amd_print("----------AMD BusMastering IDE Configuration----------------");
118
119 amd_print("Driver Version: 2.13");
120 amd_print("South Bridge: %s", pci_name(bmide_dev));
121
122 pci_read_config_byte(dev, PCI_REVISION_ID, &t);
123 amd_print("Revision: IDE %#x", t);
124 amd_print("Highest DMA rate: %s", amd_dma[amd_config->flags & AMD_UDMA]);
125
126 amd_print("BM-DMA base: %#lx", amd_base);
127 amd_print("PCI clock: %d.%dMHz", amd_clock / 1000, amd_clock / 100 % 10);
128
129 amd_print("-----------------------Primary IDE-------Secondary IDE------");
130
131 pci_read_config_byte(dev, AMD_IDE_CONFIG, &t);
132 amd_print("Prefetch Buffer: %10s%20s", (t & 0x80) ? "yes" : "no", (t & 0x20) ? "yes" : "no");
133 amd_print("Post Write Buffer: %10s%20s", (t & 0x40) ? "yes" : "no", (t & 0x10) ? "yes" : "no");
134
135 pci_read_config_byte(dev, AMD_IDE_ENABLE, &t);
136 amd_print("Enabled: %10s%20s", (t & 0x02) ? "yes" : "no", (t & 0x01) ? "yes" : "no");
137
138 c = inb(amd_base + 0x02) | (inb(amd_base + 0x0a) << 8);
139 amd_print("Simplex only: %10s%20s", (c & 0x80) ? "yes" : "no", (c & 0x8000) ? "yes" : "no");
140
141 amd_print("Cable Type: %10s%20s", (amd_80w & 1) ? "80w" : "40w", (amd_80w & 2) ? "80w" : "40w");
142
143 if (!amd_clock)
144 return p - buffer;
145
146 amd_print("-------------------drive0----drive1----drive2----drive3-----");
147
148 pci_read_config_byte(dev, AMD_ADDRESS_SETUP, &t);
149 pci_read_config_dword(dev, AMD_DRIVE_TIMING, &v);
150 pci_read_config_word(dev, AMD_8BIT_TIMING, &w);
151 pci_read_config_dword(dev, AMD_UDMA_TIMING, &u);
152
153 for (i = 0; i < 4; i++) {
154 setup[i] = ((t >> ((3 - i) << 1)) & 0x3) + 1;
155 recover8b[i] = ((w >> ((1 - (i >> 1)) << 3)) & 0xf) + 1;
156 active8b[i] = ((w >> (((1 - (i >> 1)) << 3) + 4)) & 0xf) + 1;
157 active[i] = ((v >> (((3 - i) << 3) + 4)) & 0xf) + 1;
158 recover[i] = ((v >> ((3 - i) << 3)) & 0xf) + 1;
159
160 udma[i] = amd_udma2cyc[((u >> ((3 - i) << 3)) & 0x7)];
161 uen[i] = ((u >> ((3 - i) << 3)) & 0x40) ? 1 : 0;
162 den[i] = (c & ((i & 1) ? 0x40 : 0x20) << ((i & 2) << 2));
163
164 if (den[i] && uen[i] && udma[i] == 1) {
165 speed[i] = amd_clock * 3;
166 cycle[i] = 666666 / amd_clock;
167 continue;
168 }
169
170 if (den[i] && uen[i] && udma[i] == 15) {
171 speed[i] = amd_clock * 4;
172 cycle[i] = 500000 / amd_clock;
173 continue;
174 }
175
176 speed[i] = 4 * amd_clock / ((den[i] && uen[i]) ? udma[i] : (active[i] + recover[i]) * 2);
177 cycle[i] = 1000000 * ((den[i] && uen[i]) ? udma[i] : (active[i] + recover[i]) * 2) / amd_clock / 2;
178 }
179
180 amd_print_drive("Transfer Mode: ", "%10s", den[i] ? (uen[i] ? "UDMA" : "DMA") : "PIO");
181
182 amd_print_drive("Address Setup: ", "%8dns", 1000000 * setup[i] / amd_clock);
183 amd_print_drive("Cmd Active: ", "%8dns", 1000000 * active8b[i] / amd_clock);
184 amd_print_drive("Cmd Recovery: ", "%8dns", 1000000 * recover8b[i] / amd_clock);
185 amd_print_drive("Data Active: ", "%8dns", 1000000 * active[i] / amd_clock);
186 amd_print_drive("Data Recovery: ", "%8dns", 1000000 * recover[i] / amd_clock);
187 amd_print_drive("Cycle Time: ", "%8dns", cycle[i]);
188 amd_print_drive("Transfer Rate: ", "%4d.%dMB/s", speed[i] / 1000, speed[i] / 100 % 10);
189
190 /* hoping p - buffer is less than 4K... */
191 len = (p - buffer) - offset;
192 *addr = buffer + offset;
193
194 return len > count ? count : len;
195}
196
197#endif
198
199/*
200 * amd_set_speed() writes timing values to the chipset registers
201 */
202
203static void amd_set_speed(struct pci_dev *dev, unsigned char dn, struct ide_timing *timing)
204{
205 unsigned char t;
206
207 pci_read_config_byte(dev, AMD_ADDRESS_SETUP, &t);
208 t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
209 pci_write_config_byte(dev, AMD_ADDRESS_SETUP, t);
210
211 pci_write_config_byte(dev, AMD_8BIT_TIMING + (1 - (dn >> 1)),
212 ((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1));
213
214 pci_write_config_byte(dev, AMD_DRIVE_TIMING + (3 - dn),
215 ((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1));
216
217 switch (amd_config->flags & AMD_UDMA) {
218 case AMD_UDMA_33: t = timing->udma ? (0xc0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
219 case AMD_UDMA_66: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 2, 10)]) : 0x03; break;
220 case AMD_UDMA_100: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 1, 10)]) : 0x03; break;
221 case AMD_UDMA_133: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 1, 15)]) : 0x03; break;
222 default: return;
223 }
224
225 pci_write_config_byte(dev, AMD_UDMA_TIMING + (3 - dn), t);
226}
227
228/*
229 * amd_set_drive() computes timing values configures the drive and
230 * the chipset to a desired transfer mode. It also can be called
231 * by upper layers.
232 */
233
234static int amd_set_drive(ide_drive_t *drive, u8 speed)
235{
236 ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1);
237 struct ide_timing t, p;
238 int T, UT;
239
240 if (speed != XFER_PIO_SLOW && speed != drive->current_speed)
241 if (ide_config_drive_speed(drive, speed))
242 printk(KERN_WARNING "ide%d: Drive %d didn't accept speed setting. Oh, well.\n",
243 drive->dn >> 1, drive->dn & 1);
244
245 T = 1000000000 / amd_clock;
246 UT = T / min_t(int, max_t(int, amd_config->flags & AMD_UDMA, 1), 2);
247
248 ide_timing_compute(drive, speed, &t, T, UT);
249
250 if (peer->present) {
251 ide_timing_compute(peer, peer->current_speed, &p, T, UT);
252 ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
253 }
254
255 if (speed == XFER_UDMA_5 && amd_clock <= 33333) t.udma = 1;
256 if (speed == XFER_UDMA_6 && amd_clock <= 33333) t.udma = 15;
257
258 amd_set_speed(HWIF(drive)->pci_dev, drive->dn, &t);
259
260 if (!drive->init_speed)
261 drive->init_speed = speed;
262 drive->current_speed = speed;
263
264 return 0;
265}
266
267/*
268 * amd74xx_tune_drive() is a callback from upper layers for
269 * PIO-only tuning.
270 */
271
272static void amd74xx_tune_drive(ide_drive_t *drive, u8 pio)
273{
274 if (pio == 255) {
275 amd_set_drive(drive, ide_find_best_mode(drive, XFER_PIO | XFER_EPIO));
276 return;
277 }
278
279 amd_set_drive(drive, XFER_PIO_0 + min_t(byte, pio, 5));
280}
281
282/*
283 * amd74xx_dmaproc() is a callback from upper layers that can do
284 * a lot, but we use it for DMA/PIO tuning only, delegating everything
285 * else to the default ide_dmaproc().
286 */
287
288static int amd74xx_ide_dma_check(ide_drive_t *drive)
289{
290 int w80 = HWIF(drive)->udma_four;
291
292 u8 speed = ide_find_best_mode(drive,
293 XFER_PIO | XFER_EPIO | XFER_MWDMA | XFER_UDMA |
294 ((amd_config->flags & AMD_BAD_SWDMA) ? 0 : XFER_SWDMA) |
295 (w80 && (amd_config->flags & AMD_UDMA) >= AMD_UDMA_66 ? XFER_UDMA_66 : 0) |
296 (w80 && (amd_config->flags & AMD_UDMA) >= AMD_UDMA_100 ? XFER_UDMA_100 : 0) |
297 (w80 && (amd_config->flags & AMD_UDMA) >= AMD_UDMA_133 ? XFER_UDMA_133 : 0));
298
299 amd_set_drive(drive, speed);
300
301 if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
302 return HWIF(drive)->ide_dma_on(drive);
303 return HWIF(drive)->ide_dma_off_quietly(drive);
304}
305
306/*
307 * The initialization callback. Here we determine the IDE chip type
308 * and initialize its drive independent registers.
309 */
310
311static unsigned int __init init_chipset_amd74xx(struct pci_dev *dev, const char *name)
312{
313 unsigned char t;
314 unsigned int u;
315 int i;
316
317/*
318 * Check for bad SWDMA.
319 */
320
321 if (amd_config->flags & AMD_CHECK_SWDMA) {
322 pci_read_config_byte(dev, PCI_REVISION_ID, &t);
323 if (t <= 7)
324 amd_config->flags |= AMD_BAD_SWDMA;
325 }
326
327/*
328 * Check 80-wire cable presence.
329 */
330
331 switch (amd_config->flags & AMD_UDMA) {
332
333 case AMD_UDMA_133:
334 case AMD_UDMA_100:
335 pci_read_config_byte(dev, AMD_CABLE_DETECT, &t);
336 pci_read_config_dword(dev, AMD_UDMA_TIMING, &u);
337 amd_80w = ((t & 0x3) ? 1 : 0) | ((t & 0xc) ? 2 : 0);
338 for (i = 24; i >= 0; i -= 8)
339 if (((u >> i) & 4) && !(amd_80w & (1 << (1 - (i >> 4))))) {
340 printk(KERN_WARNING "%s: BIOS didn't set cable bits correctly. Enabling workaround.\n",
341 amd_chipset->name);
342 amd_80w |= (1 << (1 - (i >> 4)));
343 }
344 break;
345
346 case AMD_UDMA_66:
347 pci_read_config_dword(dev, AMD_UDMA_TIMING, &u);
348 for (i = 24; i >= 0; i -= 8)
349 if ((u >> i) & 4)
350 amd_80w |= (1 << (1 - (i >> 4)));
351 break;
352 }
353
354/*
355 * Take care of prefetch & postwrite.
356 */
357
358 pci_read_config_byte(dev, AMD_IDE_CONFIG, &t);
359 pci_write_config_byte(dev, AMD_IDE_CONFIG,
360 (amd_config->flags & AMD_BAD_FIFO) ? (t & 0x0f) : (t | 0xf0));
361
362/*
363 * Take care of incorrectly wired Serenade mainboards.
364 */
365
366 if ((amd_config->flags & AMD_CHECK_SERENADE) &&
367 dev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
368 dev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
369 amd_config->flags = AMD_UDMA_100;
370
371/*
372 * Determine the system bus clock.
373 */
374
375 amd_clock = system_bus_clock() * 1000;
376
377 switch (amd_clock) {
378 case 33000: amd_clock = 33333; break;
379 case 37000: amd_clock = 37500; break;
380 case 41000: amd_clock = 41666; break;
381 }
382
383 if (amd_clock < 20000 || amd_clock > 50000) {
384 printk(KERN_WARNING "%s: User given PCI clock speed impossible (%d), using 33 MHz instead.\n",
385 amd_chipset->name, amd_clock);
386 printk(KERN_WARNING "%s: Use ide0=ata66 if you want to assume 80-wire cable\n",
387 amd_chipset->name);
388 amd_clock = 33333;
389 }
390
391/*
392 * Print the boot message.
393 */
394
395 pci_read_config_byte(dev, PCI_REVISION_ID, &t);
396 printk(KERN_INFO "%s: %s (rev %02x) %s controller\n",
397 amd_chipset->name, pci_name(dev), t, amd_dma[amd_config->flags & AMD_UDMA]);
398
399/*
400 * Register /proc/ide/amd74xx entry
401 */
402
403#if defined(DISPLAY_AMD_TIMINGS) && defined(CONFIG_PROC_FS)
404 if (!amd74xx_proc) {
405 amd_base = pci_resource_start(dev, 4);
406 bmide_dev = dev;
407 ide_pci_create_host_proc("amd74xx", amd74xx_get_info);
408 amd74xx_proc = 1;
409 }
410#endif /* DISPLAY_AMD_TIMINGS && CONFIG_PROC_FS */
411
412 return dev->irq;
413}
414
415static void __init init_hwif_amd74xx(ide_hwif_t *hwif)
416{
417 int i;
418
419 if (hwif->irq == 0) /* 0 is bogus but will do for now */
420 hwif->irq = pci_get_legacy_ide_irq(hwif->pci_dev, hwif->channel);
421
422 hwif->autodma = 0;
423
424 hwif->tuneproc = &amd74xx_tune_drive;
425 hwif->speedproc = &amd_set_drive;
426
427 for (i = 0; i < 2; i++) {
428 hwif->drives[i].io_32bit = 1;
429 hwif->drives[i].unmask = 1;
430 hwif->drives[i].autotune = 1;
431 hwif->drives[i].dn = hwif->channel * 2 + i;
432 }
433
434 if (!hwif->dma_base)
435 return;
436
437 hwif->atapi_dma = 1;
438 hwif->ultra_mask = 0x7f;
439 hwif->mwdma_mask = 0x07;
440 hwif->swdma_mask = 0x07;
441
442 if (!hwif->udma_four)
443 hwif->udma_four = (amd_80w >> hwif->channel) & 1;
444 hwif->ide_dma_check = &amd74xx_ide_dma_check;
445 if (!noautodma)
446 hwif->autodma = 1;
447 hwif->drives[0].autodma = hwif->autodma;
448 hwif->drives[1].autodma = hwif->autodma;
449}
450
451#define DECLARE_AMD_DEV(name_str) \
452 { \
453 .name = name_str, \
454 .init_chipset = init_chipset_amd74xx, \
455 .init_hwif = init_hwif_amd74xx, \
456 .channels = 2, \
457 .autodma = AUTODMA, \
458 .enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, \
459 .bootable = ON_BOARD, \
460 }
461
462#define DECLARE_NV_DEV(name_str) \
463 { \
464 .name = name_str, \
465 .init_chipset = init_chipset_amd74xx, \
466 .init_hwif = init_hwif_amd74xx, \
467 .channels = 2, \
468 .autodma = AUTODMA, \
469 .enablebits = {{0x50,0x02,0x02}, {0x50,0x01,0x01}}, \
470 .bootable = ON_BOARD, \
471 }
472
473static ide_pci_device_t amd74xx_chipsets[] __devinitdata = {
474 /* 0 */ DECLARE_AMD_DEV("AMD7401"),
475 /* 1 */ DECLARE_AMD_DEV("AMD7409"),
476 /* 2 */ DECLARE_AMD_DEV("AMD7411"),
477 /* 3 */ DECLARE_AMD_DEV("AMD7441"),
478 /* 4 */ DECLARE_AMD_DEV("AMD8111"),
479
480 /* 5 */ DECLARE_NV_DEV("NFORCE"),
481 /* 6 */ DECLARE_NV_DEV("NFORCE2"),
482 /* 7 */ DECLARE_NV_DEV("NFORCE2-U400R"),
483 /* 8 */ DECLARE_NV_DEV("NFORCE2-U400R-SATA"),
484 /* 9 */ DECLARE_NV_DEV("NFORCE3-150"),
485 /* 10 */ DECLARE_NV_DEV("NFORCE3-250"),
486 /* 11 */ DECLARE_NV_DEV("NFORCE3-250-SATA"),
487 /* 12 */ DECLARE_NV_DEV("NFORCE3-250-SATA2"),
488 /* 13 */ DECLARE_NV_DEV("NFORCE-CK804"),
489 /* 14 */ DECLARE_NV_DEV("NFORCE-MCP04"),
490};
491
492static int __devinit amd74xx_probe(struct pci_dev *dev, const struct pci_device_id *id)
493{
494 amd_chipset = amd74xx_chipsets + id->driver_data;
495 amd_config = amd_ide_chips + id->driver_data;
496 if (dev->device != amd_config->id) {
497 printk(KERN_ERR "%s: assertion 0x%02x == 0x%02x failed !\n",
498 pci_name(dev), dev->device, amd_config->id);
499 return -ENODEV;
500 }
501 return ide_setup_pci_device(dev, amd_chipset);
502}
503
504static struct pci_device_id amd74xx_pci_tbl[] = {
505 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_COBRA_7401, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
506 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7409, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
507 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
508 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_OPUS_7441, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
509 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
510 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 },
511 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6 },
512 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7 },
513#ifdef CONFIG_BLK_DEV_IDE_SATA
514 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
515#endif
516 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9 },
517 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10 },
518#ifdef CONFIG_BLK_DEV_IDE_SATA
519 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11 },
520 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12 },
521#endif
522 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 13 },
523 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 14 },
524 { 0, },
525};
526MODULE_DEVICE_TABLE(pci, amd74xx_pci_tbl);
527
528static struct pci_driver driver = {
529 .name = "AMD_IDE",
530 .id_table = amd74xx_pci_tbl,
531 .probe = amd74xx_probe,
532};
533
534static int amd74xx_ide_init(void)
535{
536 return ide_pci_register_driver(&driver);
537}
538
539module_init(amd74xx_ide_init);
540
541MODULE_AUTHOR("Vojtech Pavlik");
542MODULE_DESCRIPTION("AMD PCI IDE driver");
543MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/atiixp.c b/drivers/ide/pci/atiixp.c
new file mode 100644
index 000000000000..df9ee9a78435
--- /dev/null
+++ b/drivers/ide/pci/atiixp.c
@@ -0,0 +1,370 @@
1/*
2 * linux/drivers/ide/pci/atiixp.c Version 0.01-bart2 Feb. 26, 2004
3 *
4 * Copyright (C) 2003 ATI Inc. <hyu@ati.com>
5 * Copyright (C) 2004 Bartlomiej Zolnierkiewicz
6 *
7 */
8
9#include <linux/config.h>
10#include <linux/types.h>
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/ioport.h>
14#include <linux/pci.h>
15#include <linux/hdreg.h>
16#include <linux/ide.h>
17#include <linux/delay.h>
18#include <linux/init.h>
19
20#include <asm/io.h>
21
22#define ATIIXP_IDE_PIO_TIMING 0x40
23#define ATIIXP_IDE_MDMA_TIMING 0x44
24#define ATIIXP_IDE_PIO_CONTROL 0x48
25#define ATIIXP_IDE_PIO_MODE 0x4a
26#define ATIIXP_IDE_UDMA_CONTROL 0x54
27#define ATIIXP_IDE_UDMA_MODE 0x56
28
29typedef struct {
30 u8 command_width;
31 u8 recover_width;
32} atiixp_ide_timing;
33
34static atiixp_ide_timing pio_timing[] = {
35 { 0x05, 0x0d },
36 { 0x04, 0x07 },
37 { 0x03, 0x04 },
38 { 0x02, 0x02 },
39 { 0x02, 0x00 },
40};
41
42static atiixp_ide_timing mdma_timing[] = {
43 { 0x07, 0x07 },
44 { 0x02, 0x01 },
45 { 0x02, 0x00 },
46};
47
48static int save_mdma_mode[4];
49
50/**
51 * atiixp_ratemask - compute rate mask for ATIIXP IDE
52 * @drive: IDE drive to compute for
53 *
54 * Returns the available modes for the ATIIXP IDE controller.
55 */
56
57static u8 atiixp_ratemask(ide_drive_t *drive)
58{
59 u8 mode = 3;
60
61 if (!eighty_ninty_three(drive))
62 mode = min(mode, (u8)1);
63 return mode;
64}
65
66/**
67 * atiixp_dma_2_pio - return the PIO mode matching DMA
68 * @xfer_rate: transfer speed
69 *
70 * Returns the nearest equivalent PIO timing for the PIO or DMA
71 * mode requested by the controller.
72 */
73
74static u8 atiixp_dma_2_pio(u8 xfer_rate) {
75 switch(xfer_rate) {
76 case XFER_UDMA_6:
77 case XFER_UDMA_5:
78 case XFER_UDMA_4:
79 case XFER_UDMA_3:
80 case XFER_UDMA_2:
81 case XFER_UDMA_1:
82 case XFER_UDMA_0:
83 case XFER_MW_DMA_2:
84 case XFER_PIO_4:
85 return 4;
86 case XFER_MW_DMA_1:
87 case XFER_PIO_3:
88 return 3;
89 case XFER_SW_DMA_2:
90 case XFER_PIO_2:
91 return 2;
92 case XFER_MW_DMA_0:
93 case XFER_SW_DMA_1:
94 case XFER_SW_DMA_0:
95 case XFER_PIO_1:
96 case XFER_PIO_0:
97 case XFER_PIO_SLOW:
98 default:
99 return 0;
100 }
101}
102
103static int atiixp_ide_dma_host_on(ide_drive_t *drive)
104{
105 struct pci_dev *dev = drive->hwif->pci_dev;
106 unsigned long flags;
107 u16 tmp16;
108
109 spin_lock_irqsave(&ide_lock, flags);
110
111 pci_read_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
112 if (save_mdma_mode[drive->dn])
113 tmp16 &= ~(1 << drive->dn);
114 else
115 tmp16 |= (1 << drive->dn);
116 pci_write_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, tmp16);
117
118 spin_unlock_irqrestore(&ide_lock, flags);
119
120 return __ide_dma_host_on(drive);
121}
122
123static int atiixp_ide_dma_host_off(ide_drive_t *drive)
124{
125 struct pci_dev *dev = drive->hwif->pci_dev;
126 unsigned long flags;
127 u16 tmp16;
128
129 spin_lock_irqsave(&ide_lock, flags);
130
131 pci_read_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
132 tmp16 &= ~(1 << drive->dn);
133 pci_write_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, tmp16);
134
135 spin_unlock_irqrestore(&ide_lock, flags);
136
137 return __ide_dma_host_off(drive);
138}
139
140/**
141 * atiixp_tune_drive - tune a drive attached to a ATIIXP
142 * @drive: drive to tune
143 * @pio: desired PIO mode
144 *
145 * Set the interface PIO mode.
146 */
147
148static void atiixp_tuneproc(ide_drive_t *drive, u8 pio)
149{
150 struct pci_dev *dev = drive->hwif->pci_dev;
151 unsigned long flags;
152 int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8;
153 u32 pio_timing_data;
154 u16 pio_mode_data;
155
156 spin_lock_irqsave(&ide_lock, flags);
157
158 pci_read_config_word(dev, ATIIXP_IDE_PIO_MODE, &pio_mode_data);
159 pio_mode_data &= ~(0x07 << (drive->dn * 4));
160 pio_mode_data |= (pio << (drive->dn * 4));
161 pci_write_config_word(dev, ATIIXP_IDE_PIO_MODE, pio_mode_data);
162
163 pci_read_config_dword(dev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data);
164 pio_timing_data &= ~(0xff << timing_shift);
165 pio_timing_data |= (pio_timing[pio].recover_width << timing_shift) |
166 (pio_timing[pio].command_width << (timing_shift + 4));
167 pci_write_config_dword(dev, ATIIXP_IDE_PIO_TIMING, pio_timing_data);
168
169 spin_unlock_irqrestore(&ide_lock, flags);
170}
171
172/**
173 * atiixp_tune_chipset - tune a ATIIXP interface
174 * @drive: IDE drive to tune
175 * @xferspeed: speed to configure
176 *
177 * Set a ATIIXP interface channel to the desired speeds. This involves
178 * requires the right timing data into the ATIIXP configuration space
179 * then setting the drive parameters appropriately
180 */
181
182static int atiixp_speedproc(ide_drive_t *drive, u8 xferspeed)
183{
184 struct pci_dev *dev = drive->hwif->pci_dev;
185 unsigned long flags;
186 int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8;
187 u32 tmp32;
188 u16 tmp16;
189 u8 speed, pio;
190
191 speed = ide_rate_filter(atiixp_ratemask(drive), xferspeed);
192
193 spin_lock_irqsave(&ide_lock, flags);
194
195 save_mdma_mode[drive->dn] = 0;
196 if (speed >= XFER_UDMA_0) {
197 pci_read_config_word(dev, ATIIXP_IDE_UDMA_MODE, &tmp16);
198 tmp16 &= ~(0x07 << (drive->dn * 4));
199 tmp16 |= ((speed & 0x07) << (drive->dn * 4));
200 pci_write_config_word(dev, ATIIXP_IDE_UDMA_MODE, tmp16);
201 } else {
202 if ((speed >= XFER_MW_DMA_0) && (speed <= XFER_MW_DMA_2)) {
203 save_mdma_mode[drive->dn] = speed;
204 pci_read_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, &tmp32);
205 tmp32 &= ~(0xff << timing_shift);
206 tmp32 |= (mdma_timing[speed & 0x03].recover_width << timing_shift) |
207 (mdma_timing[speed & 0x03].command_width << (timing_shift + 4));
208 pci_write_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, tmp32);
209 }
210 }
211
212 spin_unlock_irqrestore(&ide_lock, flags);
213
214 if (speed >= XFER_SW_DMA_0)
215 pio = atiixp_dma_2_pio(speed);
216 else
217 pio = speed - XFER_PIO_0;
218
219 atiixp_tuneproc(drive, pio);
220
221 return ide_config_drive_speed(drive, speed);
222}
223
224/**
225 * atiixp_config_drive_for_dma - configure drive for DMA
226 * @drive: IDE drive to configure
227 *
228 * Set up a ATIIXP interface channel for the best available speed.
229 * We prefer UDMA if it is available and then MWDMA. If DMA is
230 * not available we switch to PIO and return 0.
231 */
232
233static int atiixp_config_drive_for_dma(ide_drive_t *drive)
234{
235 u8 speed = ide_dma_speed(drive, atiixp_ratemask(drive));
236
237 /* If no DMA speed was available then disable DMA and use PIO. */
238 if (!speed) {
239 u8 tspeed = ide_get_best_pio_mode(drive, 255, 5, NULL);
240 speed = atiixp_dma_2_pio(XFER_PIO_0 + tspeed) + XFER_PIO_0;
241 }
242
243 (void) atiixp_speedproc(drive, speed);
244 return ide_dma_enable(drive);
245}
246
247/**
248 * atiixp_dma_check - set up an IDE device
249 * @drive: IDE drive to configure
250 *
251 * Set up the ATIIXP interface for the best available speed on this
252 * interface, preferring DMA to PIO.
253 */
254
255static int atiixp_dma_check(ide_drive_t *drive)
256{
257 ide_hwif_t *hwif = HWIF(drive);
258 struct hd_driveid *id = drive->id;
259 u8 tspeed, speed;
260
261 drive->init_speed = 0;
262
263 if ((id->capability & 1) && drive->autodma) {
264
265 if (ide_use_dma(drive)) {
266 if (atiixp_config_drive_for_dma(drive))
267 return hwif->ide_dma_on(drive);
268 }
269
270 goto fast_ata_pio;
271
272 } else if ((id->capability & 8) || (id->field_valid & 2)) {
273fast_ata_pio:
274 tspeed = ide_get_best_pio_mode(drive, 255, 5, NULL);
275 speed = atiixp_dma_2_pio(XFER_PIO_0 + tspeed) + XFER_PIO_0;
276 hwif->speedproc(drive, speed);
277 return hwif->ide_dma_off_quietly(drive);
278 }
279 /* IORDY not supported */
280 return 0;
281}
282
283/**
284 * init_hwif_atiixp - fill in the hwif for the ATIIXP
285 * @hwif: IDE interface
286 *
287 * Set up the ide_hwif_t for the ATIIXP interface according to the
288 * capabilities of the hardware.
289 */
290
291static void __devinit init_hwif_atiixp(ide_hwif_t *hwif)
292{
293 if (!hwif->irq)
294 hwif->irq = hwif->channel ? 15 : 14;
295
296 hwif->autodma = 0;
297 hwif->tuneproc = &atiixp_tuneproc;
298 hwif->speedproc = &atiixp_speedproc;
299 hwif->drives[0].autotune = 1;
300 hwif->drives[1].autotune = 1;
301
302 if (!hwif->dma_base)
303 return;
304
305 hwif->atapi_dma = 1;
306 hwif->ultra_mask = 0x3f;
307 hwif->mwdma_mask = 0x06;
308 hwif->swdma_mask = 0x04;
309
310 /* FIXME: proper cable detection needed */
311 hwif->udma_four = 1;
312 hwif->ide_dma_host_on = &atiixp_ide_dma_host_on;
313 hwif->ide_dma_host_off = &atiixp_ide_dma_host_off;
314 hwif->ide_dma_check = &atiixp_dma_check;
315 if (!noautodma)
316 hwif->autodma = 1;
317
318 hwif->drives[1].autodma = hwif->autodma;
319 hwif->drives[0].autodma = hwif->autodma;
320}
321
322static ide_pci_device_t atiixp_pci_info[] __devinitdata = {
323 { /* 0 */
324 .name = "ATIIXP",
325 .init_hwif = init_hwif_atiixp,
326 .channels = 2,
327 .autodma = AUTODMA,
328 .enablebits = {{0x48,0x01,0x00}, {0x48,0x08,0x00}},
329 .bootable = ON_BOARD,
330 }
331};
332
333/**
334 * atiixp_init_one - called when a ATIIXP is found
335 * @dev: the atiixp device
336 * @id: the matching pci id
337 *
338 * Called when the PCI registration layer (or the IDE initialization)
339 * finds a device matching our IDE device tables.
340 */
341
342static int __devinit atiixp_init_one(struct pci_dev *dev, const struct pci_device_id *id)
343{
344 return ide_setup_pci_device(dev, &atiixp_pci_info[id->driver_data]);
345}
346
347static struct pci_device_id atiixp_pci_tbl[] = {
348 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
349 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
350 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
351 { 0, },
352};
353MODULE_DEVICE_TABLE(pci, atiixp_pci_tbl);
354
355static struct pci_driver driver = {
356 .name = "ATIIXP_IDE",
357 .id_table = atiixp_pci_tbl,
358 .probe = atiixp_init_one,
359};
360
361static int atiixp_ide_init(void)
362{
363 return ide_pci_register_driver(&driver);
364}
365
366module_init(atiixp_ide_init);
367
368MODULE_AUTHOR("HUI YU");
369MODULE_DESCRIPTION("PCI driver module for ATI IXP IDE");
370MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/cmd640.c b/drivers/ide/pci/cmd640.c
new file mode 100644
index 000000000000..92a2b7caed58
--- /dev/null
+++ b/drivers/ide/pci/cmd640.c
@@ -0,0 +1,879 @@
1/*
2 * linux/drivers/ide/pci/cmd640.c Version 1.02 Sep 01, 1996
3 *
4 * Copyright (C) 1995-1996 Linus Torvalds & authors (see below)
5 */
6
7/*
8 * Original authors: abramov@cecmow.enet.dec.com (Igor Abramov)
9 * mlord@pobox.com (Mark Lord)
10 *
11 * See linux/MAINTAINERS for address of current maintainer.
12 *
13 * This file provides support for the advanced features and bugs
14 * of IDE interfaces using the CMD Technologies 0640 IDE interface chip.
15 *
16 * These chips are basically fucked by design, and getting this driver
17 * to work on every motherboard design that uses this screwed chip seems
18 * bloody well impossible. However, we're still trying.
19 *
20 * Version 0.97 worked for everybody.
21 *
22 * User feedback is essential. Many thanks to the beta test team:
23 *
24 * A.Hartgers@stud.tue.nl, JZDQC@CUNYVM.CUNY.edu, abramov@cecmow.enet.dec.com,
25 * bardj@utopia.ppp.sn.no, bart@gaga.tue.nl, bbol001@cs.auckland.ac.nz,
26 * chrisc@dbass.demon.co.uk, dalecki@namu26.Num.Math.Uni-Goettingen.de,
27 * derekn@vw.ece.cmu.edu, florian@btp2x3.phy.uni-bayreuth.de,
28 * flynn@dei.unipd.it, gadio@netvision.net.il, godzilla@futuris.net,
29 * j@pobox.com, jkemp1@mises.uni-paderborn.de, jtoppe@hiwaay.net,
30 * kerouac@ssnet.com, meskes@informatik.rwth-aachen.de, hzoli@cs.elte.hu,
31 * peter@udgaard.isgtec.com, phil@tazenda.demon.co.uk, roadcapw@cfw.com,
32 * s0033las@sun10.vsz.bme.hu, schaffer@tam.cornell.edu, sjd@slip.net,
33 * steve@ei.org, ulrpeg@bigcomm.gun.de, ism@tardis.ed.ac.uk, mack@cray.com
34 * liug@mama.indstate.edu, and others.
35 *
36 * Version 0.01 Initial version, hacked out of ide.c,
37 * and #include'd rather than compiled separately.
38 * This will get cleaned up in a subsequent release.
39 *
40 * Version 0.02 Fixes for vlb initialization code, enable prefetch
41 * for versions 'B' and 'C' of chip by default,
42 * some code cleanup.
43 *
44 * Version 0.03 Added reset of secondary interface,
45 * and black list for devices which are not compatible
46 * with prefetch mode. Separate function for setting
47 * prefetch is added, possibly it will be called some
48 * day from ioctl processing code.
49 *
50 * Version 0.04 Now configs/compiles separate from ide.c
51 *
52 * Version 0.05 Major rewrite of interface timing code.
53 * Added new function cmd640_set_mode to set PIO mode
54 * from ioctl call. New drives added to black list.
55 *
56 * Version 0.06 More code cleanup. Prefetch is enabled only for
57 * detected hard drives, not included in prefetch
58 * black list.
59 *
60 * Version 0.07 Changed to more conservative drive tuning policy.
61 * Unknown drives, which report PIO < 4 are set to
62 * (reported_PIO - 1) if it is supported, or to PIO0.
63 * List of known drives extended by info provided by
64 * CMD at their ftp site.
65 *
66 * Version 0.08 Added autotune/noautotune support.
67 *
68 * Version 0.09 Try to be smarter about 2nd port enabling.
69 * Version 0.10 Be nice and don't reset 2nd port.
70 * Version 0.11 Try to handle more weird situations.
71 *
72 * Version 0.12 Lots of bug fixes from Laszlo Peter
73 * irq unmasking disabled for reliability.
74 * try to be even smarter about the second port.
75 * tidy up source code formatting.
76 * Version 0.13 permit irq unmasking again.
77 * Version 0.90 massive code cleanup, some bugs fixed.
78 * defaults all drives to PIO mode0, prefetch off.
79 * autotune is OFF by default, with compile time flag.
80 * prefetch can be turned OFF/ON using "hdparm -p8/-p9"
81 * (requires hdparm-3.1 or newer)
82 * Version 0.91 first release to linux-kernel list.
83 * Version 0.92 move initial reg dump to separate callable function
84 * change "readahead" to "prefetch" to avoid confusion
85 * Version 0.95 respect original BIOS timings unless autotuning.
86 * tons of code cleanup and rearrangement.
87 * added CONFIG_BLK_DEV_CMD640_ENHANCED option
88 * prevent use of unmask when prefetch is on
89 * Version 0.96 prevent use of io_32bit when prefetch is off
90 * Version 0.97 fix VLB secondary interface for sjd@slip.net
91 * other minor tune-ups: 0.96 was very good.
92 * Version 0.98 ignore PCI version when disabled by BIOS
93 * Version 0.99 display setup/active/recovery clocks with PIO mode
94 * Version 1.00 Mmm.. cannot depend on PCMD_ENA in all systems
95 * Version 1.01 slow/fast devsel can be selected with "hdparm -p6/-p7"
96 * ("fast" is necessary for 32bit I/O in some systems)
97 * Version 1.02 fix bug that resulted in slow "setup times"
98 * (patch courtesy of Zoltan Hidvegi)
99 */
100
101#undef REALLY_SLOW_IO /* most systems can safely undef this */
102#define CMD640_PREFETCH_MASKS 1
103
104//#define CMD640_DUMP_REGS
105
106#include <linux/config.h>
107#include <linux/types.h>
108#include <linux/kernel.h>
109#include <linux/delay.h>
110#include <linux/timer.h>
111#include <linux/mm.h>
112#include <linux/ioport.h>
113#include <linux/blkdev.h>
114#include <linux/hdreg.h>
115#include <linux/ide.h>
116#include <linux/init.h>
117
118#include <asm/io.h>
119
120/*
121 * This flag is set in ide.c by the parameter: ide0=cmd640_vlb
122 */
123int cmd640_vlb = 0;
124
125/*
126 * CMD640 specific registers definition.
127 */
128
129#define VID 0x00
130#define DID 0x02
131#define PCMD 0x04
132#define PCMD_ENA 0x01
133#define PSTTS 0x06
134#define REVID 0x08
135#define PROGIF 0x09
136#define SUBCL 0x0a
137#define BASCL 0x0b
138#define BaseA0 0x10
139#define BaseA1 0x14
140#define BaseA2 0x18
141#define BaseA3 0x1c
142#define INTLINE 0x3c
143#define INPINE 0x3d
144
145#define CFR 0x50
146#define CFR_DEVREV 0x03
147#define CFR_IDE01INTR 0x04
148#define CFR_DEVID 0x18
149#define CFR_AT_VESA_078h 0x20
150#define CFR_DSA1 0x40
151#define CFR_DSA0 0x80
152
153#define CNTRL 0x51
154#define CNTRL_DIS_RA0 0x40
155#define CNTRL_DIS_RA1 0x80
156#define CNTRL_ENA_2ND 0x08
157
158#define CMDTIM 0x52
159#define ARTTIM0 0x53
160#define DRWTIM0 0x54
161#define ARTTIM1 0x55
162#define DRWTIM1 0x56
163#define ARTTIM23 0x57
164#define ARTTIM23_DIS_RA2 0x04
165#define ARTTIM23_DIS_RA3 0x08
166#define DRWTIM23 0x58
167#define BRST 0x59
168
169/*
170 * Registers and masks for easy access by drive index:
171 */
172static u8 prefetch_regs[4] = {CNTRL, CNTRL, ARTTIM23, ARTTIM23};
173static u8 prefetch_masks[4] = {CNTRL_DIS_RA0, CNTRL_DIS_RA1, ARTTIM23_DIS_RA2, ARTTIM23_DIS_RA3};
174
175#ifdef CONFIG_BLK_DEV_CMD640_ENHANCED
176
177static u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
178static u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM23, DRWTIM23};
179
180/*
181 * Current cmd640 timing values for each drive.
182 * The defaults for each are the slowest possible timings.
183 */
184static u8 setup_counts[4] = {4, 4, 4, 4}; /* Address setup count (in clocks) */
185static u8 active_counts[4] = {16, 16, 16, 16}; /* Active count (encoded) */
186static u8 recovery_counts[4] = {16, 16, 16, 16}; /* Recovery count (encoded) */
187
188#endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */
189
190/*
191 * These are initialized to point at the devices we control
192 */
193static ide_hwif_t *cmd_hwif0, *cmd_hwif1;
194static ide_drive_t *cmd_drives[4];
195
196/*
197 * Interface to access cmd640x registers
198 */
199static unsigned int cmd640_key;
200static void (*__put_cmd640_reg)(u16 reg, u8 val);
201static u8 (*__get_cmd640_reg)(u16 reg);
202
203/*
204 * This is read from the CFR reg, and is used in several places.
205 */
206static unsigned int cmd640_chip_version;
207
208/*
209 * The CMD640x chip does not support DWORD config write cycles, but some
210 * of the BIOSes use them to implement the config services.
211 * Therefore, we must use direct IO instead.
212 */
213
214/* PCI method 1 access */
215
216static void put_cmd640_reg_pci1 (u16 reg, u8 val)
217{
218 outl_p((reg & 0xfc) | cmd640_key, 0xcf8);
219 outb_p(val, (reg & 3) | 0xcfc);
220}
221
222static u8 get_cmd640_reg_pci1 (u16 reg)
223{
224 outl_p((reg & 0xfc) | cmd640_key, 0xcf8);
225 return inb_p((reg & 3) | 0xcfc);
226}
227
228/* PCI method 2 access (from CMD datasheet) */
229
230static void put_cmd640_reg_pci2 (u16 reg, u8 val)
231{
232 outb_p(0x10, 0xcf8);
233 outb_p(val, cmd640_key + reg);
234 outb_p(0, 0xcf8);
235}
236
237static u8 get_cmd640_reg_pci2 (u16 reg)
238{
239 u8 b;
240
241 outb_p(0x10, 0xcf8);
242 b = inb_p(cmd640_key + reg);
243 outb_p(0, 0xcf8);
244 return b;
245}
246
247/* VLB access */
248
249static void put_cmd640_reg_vlb (u16 reg, u8 val)
250{
251 outb_p(reg, cmd640_key);
252 outb_p(val, cmd640_key + 4);
253}
254
255static u8 get_cmd640_reg_vlb (u16 reg)
256{
257 outb_p(reg, cmd640_key);
258 return inb_p(cmd640_key + 4);
259}
260
261static u8 get_cmd640_reg(u16 reg)
262{
263 u8 b;
264 unsigned long flags;
265
266 spin_lock_irqsave(&ide_lock, flags);
267 b = __get_cmd640_reg(reg);
268 spin_unlock_irqrestore(&ide_lock, flags);
269 return b;
270}
271
272static void put_cmd640_reg(u16 reg, u8 val)
273{
274 unsigned long flags;
275
276 spin_lock_irqsave(&ide_lock, flags);
277 __put_cmd640_reg(reg,val);
278 spin_unlock_irqrestore(&ide_lock, flags);
279}
280
281static int __init match_pci_cmd640_device (void)
282{
283 const u8 ven_dev[4] = {0x95, 0x10, 0x40, 0x06};
284 unsigned int i;
285 for (i = 0; i < 4; i++) {
286 if (get_cmd640_reg(i) != ven_dev[i])
287 return 0;
288 }
289#ifdef STUPIDLY_TRUST_BROKEN_PCMD_ENA_BIT
290 if ((get_cmd640_reg(PCMD) & PCMD_ENA) == 0) {
291 printk("ide: cmd640 on PCI disabled by BIOS\n");
292 return 0;
293 }
294#endif /* STUPIDLY_TRUST_BROKEN_PCMD_ENA_BIT */
295 return 1; /* success */
296}
297
298/*
299 * Probe for CMD640x -- pci method 1
300 */
301static int __init probe_for_cmd640_pci1 (void)
302{
303 __get_cmd640_reg = get_cmd640_reg_pci1;
304 __put_cmd640_reg = put_cmd640_reg_pci1;
305 for (cmd640_key = 0x80000000;
306 cmd640_key <= 0x8000f800;
307 cmd640_key += 0x800) {
308 if (match_pci_cmd640_device())
309 return 1; /* success */
310 }
311 return 0;
312}
313
314/*
315 * Probe for CMD640x -- pci method 2
316 */
317static int __init probe_for_cmd640_pci2 (void)
318{
319 __get_cmd640_reg = get_cmd640_reg_pci2;
320 __put_cmd640_reg = put_cmd640_reg_pci2;
321 for (cmd640_key = 0xc000; cmd640_key <= 0xcf00; cmd640_key += 0x100) {
322 if (match_pci_cmd640_device())
323 return 1; /* success */
324 }
325 return 0;
326}
327
328/*
329 * Probe for CMD640x -- vlb
330 */
331static int __init probe_for_cmd640_vlb (void)
332{
333 u8 b;
334
335 __get_cmd640_reg = get_cmd640_reg_vlb;
336 __put_cmd640_reg = put_cmd640_reg_vlb;
337 cmd640_key = 0x178;
338 b = get_cmd640_reg(CFR);
339 if (b == 0xff || b == 0x00 || (b & CFR_AT_VESA_078h)) {
340 cmd640_key = 0x78;
341 b = get_cmd640_reg(CFR);
342 if (b == 0xff || b == 0x00 || !(b & CFR_AT_VESA_078h))
343 return 0;
344 }
345 return 1; /* success */
346}
347
348/*
349 * Returns 1 if an IDE interface/drive exists at 0x170,
350 * Returns 0 otherwise.
351 */
352static int __init secondary_port_responding (void)
353{
354 unsigned long flags;
355
356 spin_lock_irqsave(&ide_lock, flags);
357
358 outb_p(0x0a, 0x170 + IDE_SELECT_OFFSET); /* select drive0 */
359 udelay(100);
360 if ((inb_p(0x170 + IDE_SELECT_OFFSET) & 0x1f) != 0x0a) {
361 outb_p(0x1a, 0x170 + IDE_SELECT_OFFSET); /* select drive1 */
362 udelay(100);
363 if ((inb_p(0x170 + IDE_SELECT_OFFSET) & 0x1f) != 0x1a) {
364 spin_unlock_irqrestore(&ide_lock, flags);
365 return 0; /* nothing responded */
366 }
367 }
368 spin_unlock_irqrestore(&ide_lock, flags);
369 return 1; /* success */
370}
371
372#ifdef CMD640_DUMP_REGS
373/*
374 * Dump out all cmd640 registers. May be called from ide.c
375 */
376static void cmd640_dump_regs (void)
377{
378 unsigned int reg = cmd640_vlb ? 0x50 : 0x00;
379
380 /* Dump current state of chip registers */
381 printk("ide: cmd640 internal register dump:");
382 for (; reg <= 0x59; reg++) {
383 if (!(reg & 0x0f))
384 printk("\n%04x:", reg);
385 printk(" %02x", get_cmd640_reg(reg));
386 }
387 printk("\n");
388}
389#endif
390
391/*
392 * Check whether prefetch is on for a drive,
393 * and initialize the unmask flags for safe operation.
394 */
395static void __init check_prefetch (unsigned int index)
396{
397 ide_drive_t *drive = cmd_drives[index];
398 u8 b = get_cmd640_reg(prefetch_regs[index]);
399
400 if (b & prefetch_masks[index]) { /* is prefetch off? */
401 drive->no_unmask = 0;
402 drive->no_io_32bit = 1;
403 drive->io_32bit = 0;
404 } else {
405#if CMD640_PREFETCH_MASKS
406 drive->no_unmask = 1;
407 drive->unmask = 0;
408#endif
409 drive->no_io_32bit = 0;
410 }
411}
412
413/*
414 * Figure out which devices we control
415 */
416static void __init setup_device_ptrs (void)
417{
418 unsigned int i;
419
420 cmd_hwif0 = &ide_hwifs[0]; /* default, if not found below */
421 cmd_hwif1 = &ide_hwifs[1]; /* default, if not found below */
422 for (i = 0; i < MAX_HWIFS; i++) {
423 ide_hwif_t *hwif = &ide_hwifs[i];
424 if (hwif->chipset == ide_unknown || hwif->chipset == ide_forced) {
425 if (hwif->io_ports[IDE_DATA_OFFSET] == 0x1f0)
426 cmd_hwif0 = hwif;
427 else if (hwif->io_ports[IDE_DATA_OFFSET] == 0x170)
428 cmd_hwif1 = hwif;
429 }
430 }
431 cmd_drives[0] = &cmd_hwif0->drives[0];
432 cmd_drives[1] = &cmd_hwif0->drives[1];
433 cmd_drives[2] = &cmd_hwif1->drives[0];
434 cmd_drives[3] = &cmd_hwif1->drives[1];
435}
436
437#ifdef CONFIG_BLK_DEV_CMD640_ENHANCED
438
439/*
440 * Sets prefetch mode for a drive.
441 */
442static void set_prefetch_mode (unsigned int index, int mode)
443{
444 ide_drive_t *drive = cmd_drives[index];
445 int reg = prefetch_regs[index];
446 u8 b;
447 unsigned long flags;
448
449 spin_lock_irqsave(&ide_lock, flags);
450 b = __get_cmd640_reg(reg);
451 if (mode) { /* want prefetch on? */
452#if CMD640_PREFETCH_MASKS
453 drive->no_unmask = 1;
454 drive->unmask = 0;
455#endif
456 drive->no_io_32bit = 0;
457 b &= ~prefetch_masks[index]; /* enable prefetch */
458 } else {
459 drive->no_unmask = 0;
460 drive->no_io_32bit = 1;
461 drive->io_32bit = 0;
462 b |= prefetch_masks[index]; /* disable prefetch */
463 }
464 __put_cmd640_reg(reg, b);
465 spin_unlock_irqrestore(&ide_lock, flags);
466}
467
468/*
469 * Dump out current drive clocks settings
470 */
471static void display_clocks (unsigned int index)
472{
473 u8 active_count, recovery_count;
474
475 active_count = active_counts[index];
476 if (active_count == 1)
477 ++active_count;
478 recovery_count = recovery_counts[index];
479 if (active_count > 3 && recovery_count == 1)
480 ++recovery_count;
481 if (cmd640_chip_version > 1)
482 recovery_count += 1; /* cmd640b uses (count + 1)*/
483 printk(", clocks=%d/%d/%d\n", setup_counts[index], active_count, recovery_count);
484}
485
486/*
487 * Pack active and recovery counts into single byte representation
488 * used by controller
489 */
490inline static u8 pack_nibbles (u8 upper, u8 lower)
491{
492 return ((upper & 0x0f) << 4) | (lower & 0x0f);
493}
494
495/*
496 * This routine retrieves the initial drive timings from the chipset.
497 */
498static void __init retrieve_drive_counts (unsigned int index)
499{
500 u8 b;
501
502 /*
503 * Get the internal setup timing, and convert to clock count
504 */
505 b = get_cmd640_reg(arttim_regs[index]) & ~0x3f;
506 switch (b) {
507 case 0x00: b = 4; break;
508 case 0x80: b = 3; break;
509 case 0x40: b = 2; break;
510 default: b = 5; break;
511 }
512 setup_counts[index] = b;
513
514 /*
515 * Get the active/recovery counts
516 */
517 b = get_cmd640_reg(drwtim_regs[index]);
518 active_counts[index] = (b >> 4) ? (b >> 4) : 0x10;
519 recovery_counts[index] = (b & 0x0f) ? (b & 0x0f) : 0x10;
520}
521
522
523/*
524 * This routine writes the prepared setup/active/recovery counts
525 * for a drive into the cmd640 chipset registers to active them.
526 */
527static void program_drive_counts (unsigned int index)
528{
529 unsigned long flags;
530 u8 setup_count = setup_counts[index];
531 u8 active_count = active_counts[index];
532 u8 recovery_count = recovery_counts[index];
533
534 /*
535 * Set up address setup count and drive read/write timing registers.
536 * Primary interface has individual count/timing registers for
537 * each drive. Secondary interface has one common set of registers,
538 * so we merge the timings, using the slowest value for each timing.
539 */
540 if (index > 1) {
541 unsigned int mate;
542 if (cmd_drives[mate = index ^ 1]->present) {
543 if (setup_count < setup_counts[mate])
544 setup_count = setup_counts[mate];
545 if (active_count < active_counts[mate])
546 active_count = active_counts[mate];
547 if (recovery_count < recovery_counts[mate])
548 recovery_count = recovery_counts[mate];
549 }
550 }
551
552 /*
553 * Convert setup_count to internal chipset representation
554 */
555 switch (setup_count) {
556 case 4: setup_count = 0x00; break;
557 case 3: setup_count = 0x80; break;
558 case 1:
559 case 2: setup_count = 0x40; break;
560 default: setup_count = 0xc0; /* case 5 */
561 }
562
563 /*
564 * Now that everything is ready, program the new timings
565 */
566 spin_lock_irqsave(&ide_lock, flags);
567 /*
568 * Program the address_setup clocks into ARTTIM reg,
569 * and then the active/recovery counts into the DRWTIM reg
570 * (this converts counts of 16 into counts of zero -- okay).
571 */
572 setup_count |= __get_cmd640_reg(arttim_regs[index]) & 0x3f;
573 __put_cmd640_reg(arttim_regs[index], setup_count);
574 __put_cmd640_reg(drwtim_regs[index], pack_nibbles(active_count, recovery_count));
575 spin_unlock_irqrestore(&ide_lock, flags);
576}
577
578/*
579 * Set a specific pio_mode for a drive
580 */
581static void cmd640_set_mode (unsigned int index, u8 pio_mode, unsigned int cycle_time)
582{
583 int setup_time, active_time, recovery_time, clock_time;
584 u8 setup_count, active_count, recovery_count, recovery_count2, cycle_count;
585 int bus_speed = system_bus_clock();
586
587 if (pio_mode > 5)
588 pio_mode = 5;
589 setup_time = ide_pio_timings[pio_mode].setup_time;
590 active_time = ide_pio_timings[pio_mode].active_time;
591 recovery_time = cycle_time - (setup_time + active_time);
592 clock_time = 1000 / bus_speed;
593 cycle_count = (cycle_time + clock_time - 1) / clock_time;
594
595 setup_count = (setup_time + clock_time - 1) / clock_time;
596
597 active_count = (active_time + clock_time - 1) / clock_time;
598 if (active_count < 2)
599 active_count = 2; /* minimum allowed by cmd640 */
600
601 recovery_count = (recovery_time + clock_time - 1) / clock_time;
602 recovery_count2 = cycle_count - (setup_count + active_count);
603 if (recovery_count2 > recovery_count)
604 recovery_count = recovery_count2;
605 if (recovery_count < 2)
606 recovery_count = 2; /* minimum allowed by cmd640 */
607 if (recovery_count > 17) {
608 active_count += recovery_count - 17;
609 recovery_count = 17;
610 }
611 if (active_count > 16)
612 active_count = 16; /* maximum allowed by cmd640 */
613 if (cmd640_chip_version > 1)
614 recovery_count -= 1; /* cmd640b uses (count + 1)*/
615 if (recovery_count > 16)
616 recovery_count = 16; /* maximum allowed by cmd640 */
617
618 setup_counts[index] = setup_count;
619 active_counts[index] = active_count;
620 recovery_counts[index] = recovery_count;
621
622 /*
623 * In a perfect world, we might set the drive pio mode here
624 * (using WIN_SETFEATURE) before continuing.
625 *
626 * But we do not, because:
627 * 1) this is the wrong place to do it (proper is do_special() in ide.c)
628 * 2) in practice this is rarely, if ever, necessary
629 */
630 program_drive_counts (index);
631}
632
633/*
634 * Drive PIO mode selection:
635 */
636static void cmd640_tune_drive (ide_drive_t *drive, u8 mode_wanted)
637{
638 u8 b;
639 ide_pio_data_t d;
640 unsigned int index = 0;
641
642 while (drive != cmd_drives[index]) {
643 if (++index > 3) {
644 printk("%s: bad news in cmd640_tune_drive\n", drive->name);
645 return;
646 }
647 }
648 switch (mode_wanted) {
649 case 6: /* set fast-devsel off */
650 case 7: /* set fast-devsel on */
651 mode_wanted &= 1;
652 b = get_cmd640_reg(CNTRL) & ~0x27;
653 if (mode_wanted)
654 b |= 0x27;
655 put_cmd640_reg(CNTRL, b);
656 printk("%s: %sabled cmd640 fast host timing (devsel)\n", drive->name, mode_wanted ? "en" : "dis");
657 return;
658
659 case 8: /* set prefetch off */
660 case 9: /* set prefetch on */
661 mode_wanted &= 1;
662 set_prefetch_mode(index, mode_wanted);
663 printk("%s: %sabled cmd640 prefetch\n", drive->name, mode_wanted ? "en" : "dis");
664 return;
665 }
666
667 (void) ide_get_best_pio_mode (drive, mode_wanted, 5, &d);
668 cmd640_set_mode (index, d.pio_mode, d.cycle_time);
669
670 printk ("%s: selected cmd640 PIO mode%d (%dns)%s",
671 drive->name,
672 d.pio_mode,
673 d.cycle_time,
674 d.overridden ? " (overriding vendor mode)" : "");
675 display_clocks(index);
676 return;
677}
678
679#endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */
680
681static int pci_conf1(void)
682{
683 u32 tmp;
684 unsigned long flags;
685
686 spin_lock_irqsave(&ide_lock, flags);
687 outb(0x01, 0xCFB);
688 tmp = inl(0xCF8);
689 outl(0x80000000, 0xCF8);
690 if (inl(0xCF8) == 0x80000000) {
691 outl(tmp, 0xCF8);
692 spin_unlock_irqrestore(&ide_lock, flags);
693 return 1;
694 }
695 outl(tmp, 0xCF8);
696 spin_unlock_irqrestore(&ide_lock, flags);
697 return 0;
698}
699
700static int pci_conf2(void)
701{
702 unsigned long flags;
703
704 spin_lock_irqsave(&ide_lock, flags);
705 outb(0x00, 0xCFB);
706 outb(0x00, 0xCF8);
707 outb(0x00, 0xCFA);
708 if (inb(0xCF8) == 0x00 && inb(0xCF8) == 0x00) {
709 spin_unlock_irqrestore(&ide_lock, flags);
710 return 1;
711 }
712 spin_unlock_irqrestore(&ide_lock, flags);
713 return 0;
714}
715
716/*
717 * Probe for a cmd640 chipset, and initialize it if found. Called from ide.c
718 */
719int __init ide_probe_for_cmd640x (void)
720{
721#ifdef CONFIG_BLK_DEV_CMD640_ENHANCED
722 int second_port_toggled = 0;
723#endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */
724 int second_port_cmd640 = 0;
725 const char *bus_type, *port2;
726 unsigned int index;
727 u8 b, cfr;
728
729 if (cmd640_vlb && probe_for_cmd640_vlb()) {
730 bus_type = "VLB";
731 } else {
732 cmd640_vlb = 0;
733 /* Find out what kind of PCI probing is supported otherwise
734 Justin Gibbs will sulk.. */
735 if (pci_conf1() && probe_for_cmd640_pci1())
736 bus_type = "PCI (type1)";
737 else if (pci_conf2() && probe_for_cmd640_pci2())
738 bus_type = "PCI (type2)";
739 else
740 return 0;
741 }
742 /*
743 * Undocumented magic (there is no 0x5b reg in specs)
744 */
745 put_cmd640_reg(0x5b, 0xbd);
746 if (get_cmd640_reg(0x5b) != 0xbd) {
747 printk(KERN_ERR "ide: cmd640 init failed: wrong value in reg 0x5b\n");
748 return 0;
749 }
750 put_cmd640_reg(0x5b, 0);
751
752#ifdef CMD640_DUMP_REGS
753 cmd640_dump_regs();
754#endif
755
756 /*
757 * Documented magic begins here
758 */
759 cfr = get_cmd640_reg(CFR);
760 cmd640_chip_version = cfr & CFR_DEVREV;
761 if (cmd640_chip_version == 0) {
762 printk ("ide: bad cmd640 revision: %d\n", cmd640_chip_version);
763 return 0;
764 }
765
766 /*
767 * Initialize data for primary port
768 */
769 setup_device_ptrs ();
770 printk("%s: buggy cmd640%c interface on %s, config=0x%02x\n",
771 cmd_hwif0->name, 'a' + cmd640_chip_version - 1, bus_type, cfr);
772 cmd_hwif0->chipset = ide_cmd640;
773#ifdef CONFIG_BLK_DEV_CMD640_ENHANCED
774 cmd_hwif0->tuneproc = &cmd640_tune_drive;
775#endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */
776
777 /*
778 * Ensure compatibility by always using the slowest timings
779 * for access to the drive's command register block,
780 * and reset the prefetch burstsize to default (512 bytes).
781 *
782 * Maybe we need a way to NOT do these on *some* systems?
783 */
784 put_cmd640_reg(CMDTIM, 0);
785 put_cmd640_reg(BRST, 0x40);
786
787 /*
788 * Try to enable the secondary interface, if not already enabled
789 */
790 if (cmd_hwif1->noprobe) {
791 port2 = "not probed";
792 } else {
793 b = get_cmd640_reg(CNTRL);
794 if (secondary_port_responding()) {
795 if ((b & CNTRL_ENA_2ND)) {
796 second_port_cmd640 = 1;
797 port2 = "okay";
798 } else if (cmd640_vlb) {
799 second_port_cmd640 = 1;
800 port2 = "alive";
801 } else
802 port2 = "not cmd640";
803 } else {
804 put_cmd640_reg(CNTRL, b ^ CNTRL_ENA_2ND); /* toggle the bit */
805 if (secondary_port_responding()) {
806 second_port_cmd640 = 1;
807#ifdef CONFIG_BLK_DEV_CMD640_ENHANCED
808 second_port_toggled = 1;
809#endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */
810 port2 = "enabled";
811 } else {
812 put_cmd640_reg(CNTRL, b); /* restore original setting */
813 port2 = "not responding";
814 }
815 }
816 }
817
818 /*
819 * Initialize data for secondary cmd640 port, if enabled
820 */
821 if (second_port_cmd640) {
822 cmd_hwif0->serialized = 1;
823 cmd_hwif1->serialized = 1;
824 cmd_hwif1->chipset = ide_cmd640;
825 cmd_hwif0->mate = cmd_hwif1;
826 cmd_hwif1->mate = cmd_hwif0;
827 cmd_hwif1->channel = 1;
828#ifdef CONFIG_BLK_DEV_CMD640_ENHANCED
829 cmd_hwif1->tuneproc = &cmd640_tune_drive;
830#endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */
831 }
832 printk(KERN_INFO "%s: %sserialized, secondary interface %s\n", cmd_hwif1->name,
833 cmd_hwif0->serialized ? "" : "not ", port2);
834
835 /*
836 * Establish initial timings/prefetch for all drives.
837 * Do not unnecessarily disturb any prior BIOS setup of these.
838 */
839 for (index = 0; index < (2 + (second_port_cmd640 << 1)); index++) {
840 ide_drive_t *drive = cmd_drives[index];
841#ifdef CONFIG_BLK_DEV_CMD640_ENHANCED
842 if (drive->autotune || ((index > 1) && second_port_toggled)) {
843 /*
844 * Reset timing to the slowest speed and turn off prefetch.
845 * This way, the drive identify code has a better chance.
846 */
847 setup_counts [index] = 4; /* max possible */
848 active_counts [index] = 16; /* max possible */
849 recovery_counts [index] = 16; /* max possible */
850 program_drive_counts (index);
851 set_prefetch_mode (index, 0);
852 printk("cmd640: drive%d timings/prefetch cleared\n", index);
853 } else {
854 /*
855 * Record timings/prefetch without changing them.
856 * This preserves any prior BIOS setup.
857 */
858 retrieve_drive_counts (index);
859 check_prefetch (index);
860 printk("cmd640: drive%d timings/prefetch(%s) preserved",
861 index, drive->no_io_32bit ? "off" : "on");
862 display_clocks(index);
863 }
864#else
865 /*
866 * Set the drive unmask flags to match the prefetch setting
867 */
868 check_prefetch (index);
869 printk("cmd640: drive%d timings/prefetch(%s) preserved\n",
870 index, drive->no_io_32bit ? "off" : "on");
871#endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */
872 }
873
874#ifdef CMD640_DUMP_REGS
875 cmd640_dump_regs();
876#endif
877 return 1;
878}
879
diff --git a/drivers/ide/pci/cmd64x.c b/drivers/ide/pci/cmd64x.c
new file mode 100644
index 000000000000..3de9ab897e42
--- /dev/null
+++ b/drivers/ide/pci/cmd64x.c
@@ -0,0 +1,821 @@
1/* $Id: cmd64x.c,v 1.21 2000/01/30 23:23:16
2 *
3 * linux/drivers/ide/pci/cmd64x.c Version 1.30 Sept 10, 2002
4 *
5 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
6 * Note, this driver is not used at all on other systems because
7 * there the "BIOS" has done all of the following already.
8 * Due to massive hardware bugs, UltraDMA is only supported
9 * on the 646U2 and not on the 646U.
10 *
11 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
12 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
13 *
14 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
15 */
16
17#include <linux/config.h>
18#include <linux/module.h>
19#include <linux/types.h>
20#include <linux/pci.h>
21#include <linux/delay.h>
22#include <linux/hdreg.h>
23#include <linux/ide.h>
24#include <linux/init.h>
25
26#include <asm/io.h>
27
28#define DISPLAY_CMD64X_TIMINGS
29
30#define CMD_DEBUG 0
31
32#if CMD_DEBUG
33#define cmdprintk(x...) printk(x)
34#else
35#define cmdprintk(x...)
36#endif
37
38/*
39 * CMD64x specific registers definition.
40 */
41#define CFR 0x50
42#define CFR_INTR_CH0 0x02
43#define CNTRL 0x51
44#define CNTRL_DIS_RA0 0x40
45#define CNTRL_DIS_RA1 0x80
46#define CNTRL_ENA_2ND 0x08
47
48#define CMDTIM 0x52
49#define ARTTIM0 0x53
50#define DRWTIM0 0x54
51#define ARTTIM1 0x55
52#define DRWTIM1 0x56
53#define ARTTIM23 0x57
54#define ARTTIM23_DIS_RA2 0x04
55#define ARTTIM23_DIS_RA3 0x08
56#define ARTTIM23_INTR_CH1 0x10
57#define ARTTIM2 0x57
58#define ARTTIM3 0x57
59#define DRWTIM23 0x58
60#define DRWTIM2 0x58
61#define BRST 0x59
62#define DRWTIM3 0x5b
63
64#define BMIDECR0 0x70
65#define MRDMODE 0x71
66#define MRDMODE_INTR_CH0 0x04
67#define MRDMODE_INTR_CH1 0x08
68#define MRDMODE_BLK_CH0 0x10
69#define MRDMODE_BLK_CH1 0x20
70#define BMIDESR0 0x72
71#define UDIDETCR0 0x73
72#define DTPR0 0x74
73#define BMIDECR1 0x78
74#define BMIDECSR 0x79
75#define BMIDESR1 0x7A
76#define UDIDETCR1 0x7B
77#define DTPR1 0x7C
78
79#if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS)
80#include <linux/stat.h>
81#include <linux/proc_fs.h>
82
83static u8 cmd64x_proc = 0;
84
85#define CMD_MAX_DEVS 5
86
87static struct pci_dev *cmd_devs[CMD_MAX_DEVS];
88static int n_cmd_devs;
89
90static char * print_cmd64x_get_info (char *buf, struct pci_dev *dev, int index)
91{
92 char *p = buf;
93
94 u8 reg53 = 0, reg54 = 0, reg55 = 0, reg56 = 0; /* primary */
95 u8 reg57 = 0, reg58 = 0, reg5b; /* secondary */
96 u8 reg72 = 0, reg73 = 0; /* primary */
97 u8 reg7a = 0, reg7b = 0; /* secondary */
98 u8 reg50 = 0, reg71 = 0; /* extra */
99
100 p += sprintf(p, "\nController: %d\n", index);
101 p += sprintf(p, "CMD%x Chipset.\n", dev->device);
102 (void) pci_read_config_byte(dev, CFR, &reg50);
103 (void) pci_read_config_byte(dev, ARTTIM0, &reg53);
104 (void) pci_read_config_byte(dev, DRWTIM0, &reg54);
105 (void) pci_read_config_byte(dev, ARTTIM1, &reg55);
106 (void) pci_read_config_byte(dev, DRWTIM1, &reg56);
107 (void) pci_read_config_byte(dev, ARTTIM2, &reg57);
108 (void) pci_read_config_byte(dev, DRWTIM2, &reg58);
109 (void) pci_read_config_byte(dev, DRWTIM3, &reg5b);
110 (void) pci_read_config_byte(dev, MRDMODE, &reg71);
111 (void) pci_read_config_byte(dev, BMIDESR0, &reg72);
112 (void) pci_read_config_byte(dev, UDIDETCR0, &reg73);
113 (void) pci_read_config_byte(dev, BMIDESR1, &reg7a);
114 (void) pci_read_config_byte(dev, UDIDETCR1, &reg7b);
115
116 p += sprintf(p, "--------------- Primary Channel "
117 "---------------- Secondary Channel "
118 "-------------\n");
119 p += sprintf(p, " %sabled "
120 " %sabled\n",
121 (reg72&0x80)?"dis":" en",
122 (reg7a&0x80)?"dis":" en");
123 p += sprintf(p, "--------------- drive0 "
124 "--------- drive1 -------- drive0 "
125 "---------- drive1 ------\n");
126 p += sprintf(p, "DMA enabled: %s %s"
127 " %s %s\n",
128 (reg72&0x20)?"yes":"no ", (reg72&0x40)?"yes":"no ",
129 (reg7a&0x20)?"yes":"no ", (reg7a&0x40)?"yes":"no ");
130
131 p += sprintf(p, "DMA Mode: %s(%s) %s(%s)",
132 (reg72&0x20)?((reg73&0x01)?"UDMA":" DMA"):" PIO",
133 (reg72&0x20)?(
134 ((reg73&0x30)==0x30)?(((reg73&0x35)==0x35)?"3":"0"):
135 ((reg73&0x20)==0x20)?(((reg73&0x25)==0x25)?"3":"1"):
136 ((reg73&0x10)==0x10)?(((reg73&0x15)==0x15)?"4":"2"):
137 ((reg73&0x00)==0x00)?(((reg73&0x05)==0x05)?"5":"2"):
138 "X"):"?",
139 (reg72&0x40)?((reg73&0x02)?"UDMA":" DMA"):" PIO",
140 (reg72&0x40)?(
141 ((reg73&0xC0)==0xC0)?(((reg73&0xC5)==0xC5)?"3":"0"):
142 ((reg73&0x80)==0x80)?(((reg73&0x85)==0x85)?"3":"1"):
143 ((reg73&0x40)==0x40)?(((reg73&0x4A)==0x4A)?"4":"2"):
144 ((reg73&0x00)==0x00)?(((reg73&0x0A)==0x0A)?"5":"2"):
145 "X"):"?");
146 p += sprintf(p, " %s(%s) %s(%s)\n",
147 (reg7a&0x20)?((reg7b&0x01)?"UDMA":" DMA"):" PIO",
148 (reg7a&0x20)?(
149 ((reg7b&0x30)==0x30)?(((reg7b&0x35)==0x35)?"3":"0"):
150 ((reg7b&0x20)==0x20)?(((reg7b&0x25)==0x25)?"3":"1"):
151 ((reg7b&0x10)==0x10)?(((reg7b&0x15)==0x15)?"4":"2"):
152 ((reg7b&0x00)==0x00)?(((reg7b&0x05)==0x05)?"5":"2"):
153 "X"):"?",
154 (reg7a&0x40)?((reg7b&0x02)?"UDMA":" DMA"):" PIO",
155 (reg7a&0x40)?(
156 ((reg7b&0xC0)==0xC0)?(((reg7b&0xC5)==0xC5)?"3":"0"):
157 ((reg7b&0x80)==0x80)?(((reg7b&0x85)==0x85)?"3":"1"):
158 ((reg7b&0x40)==0x40)?(((reg7b&0x4A)==0x4A)?"4":"2"):
159 ((reg7b&0x00)==0x00)?(((reg7b&0x0A)==0x0A)?"5":"2"):
160 "X"):"?" );
161 p += sprintf(p, "PIO Mode: %s %s"
162 " %s %s\n",
163 "?", "?", "?", "?");
164 p += sprintf(p, " %s %s\n",
165 (reg50 & CFR_INTR_CH0) ? "interrupting" : "polling ",
166 (reg57 & ARTTIM23_INTR_CH1) ? "interrupting" : "polling");
167 p += sprintf(p, " %s %s\n",
168 (reg71 & MRDMODE_INTR_CH0) ? "pending" : "clear ",
169 (reg71 & MRDMODE_INTR_CH1) ? "pending" : "clear");
170 p += sprintf(p, " %s %s\n",
171 (reg71 & MRDMODE_BLK_CH0) ? "blocked" : "enabled",
172 (reg71 & MRDMODE_BLK_CH1) ? "blocked" : "enabled");
173
174 return (char *)p;
175}
176
177static int cmd64x_get_info (char *buffer, char **addr, off_t offset, int count)
178{
179 char *p = buffer;
180 int i;
181
182 p += sprintf(p, "\n");
183 for (i = 0; i < n_cmd_devs; i++) {
184 struct pci_dev *dev = cmd_devs[i];
185 p = print_cmd64x_get_info(p, dev, i);
186 }
187 return p-buffer; /* => must be less than 4k! */
188}
189
190#endif /* defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS) */
191
192/*
193 * Registers and masks for easy access by drive index:
194 */
195#if 0
196static u8 prefetch_regs[4] = {CNTRL, CNTRL, ARTTIM23, ARTTIM23};
197static u8 prefetch_masks[4] = {CNTRL_DIS_RA0, CNTRL_DIS_RA1, ARTTIM23_DIS_RA2, ARTTIM23_DIS_RA3};
198#endif
199
200/*
201 * This routine writes the prepared setup/active/recovery counts
202 * for a drive into the cmd646 chipset registers to active them.
203 */
204static void program_drive_counts (ide_drive_t *drive, int setup_count, int active_count, int recovery_count)
205{
206 unsigned long flags;
207 struct pci_dev *dev = HWIF(drive)->pci_dev;
208 ide_drive_t *drives = HWIF(drive)->drives;
209 u8 temp_b;
210 static const u8 setup_counts[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
211 static const u8 recovery_counts[] =
212 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
213 static const u8 arttim_regs[2][2] = {
214 { ARTTIM0, ARTTIM1 },
215 { ARTTIM23, ARTTIM23 }
216 };
217 static const u8 drwtim_regs[2][2] = {
218 { DRWTIM0, DRWTIM1 },
219 { DRWTIM2, DRWTIM3 }
220 };
221 int channel = (int) HWIF(drive)->channel;
222 int slave = (drives != drive); /* Is this really the best way to determine this?? */
223
224 cmdprintk("program_drive_count parameters = s(%d),a(%d),r(%d),p(%d)\n",
225 setup_count, active_count, recovery_count, drive->present);
226 /*
227 * Set up address setup count registers.
228 * Primary interface has individual count/timing registers for
229 * each drive. Secondary interface has one common set of registers,
230 * for address setup so we merge these timings, using the slowest
231 * value.
232 */
233 if (channel) {
234 drive->drive_data = setup_count;
235 setup_count = max(drives[0].drive_data,
236 drives[1].drive_data);
237 cmdprintk("Secondary interface, setup_count = %d\n",
238 setup_count);
239 }
240
241 /*
242 * Convert values to internal chipset representation
243 */
244 setup_count = (setup_count > 5) ? 0xc0 : (int) setup_counts[setup_count];
245 active_count &= 0xf; /* Remember, max value is 16 */
246 recovery_count = (int) recovery_counts[recovery_count];
247
248 cmdprintk("Final values = %d,%d,%d\n",
249 setup_count, active_count, recovery_count);
250
251 /*
252 * Now that everything is ready, program the new timings
253 */
254 local_irq_save(flags);
255 /*
256 * Program the address_setup clocks into ARTTIM reg,
257 * and then the active/recovery counts into the DRWTIM reg
258 */
259 (void) pci_read_config_byte(dev, arttim_regs[channel][slave], &temp_b);
260 (void) pci_write_config_byte(dev, arttim_regs[channel][slave],
261 ((u8) setup_count) | (temp_b & 0x3f));
262 (void) pci_write_config_byte(dev, drwtim_regs[channel][slave],
263 (u8) ((active_count << 4) | recovery_count));
264 cmdprintk ("Write %x to %x\n",
265 ((u8) setup_count) | (temp_b & 0x3f),
266 arttim_regs[channel][slave]);
267 cmdprintk ("Write %x to %x\n",
268 (u8) ((active_count << 4) | recovery_count),
269 drwtim_regs[channel][slave]);
270 local_irq_restore(flags);
271}
272
273/*
274 * Attempts to set the interface PIO mode.
275 * The preferred method of selecting PIO modes (e.g. mode 4) is
276 * "echo 'piomode:4' > /proc/ide/hdx/settings". Special cases are
277 * 8: prefetch off, 9: prefetch on, 255: auto-select best mode.
278 * Called with 255 at boot time.
279 */
280
281static void cmd64x_tuneproc (ide_drive_t *drive, u8 mode_wanted)
282{
283 int setup_time, active_time, recovery_time;
284 int clock_time, pio_mode, cycle_time;
285 u8 recovery_count2, cycle_count;
286 int setup_count, active_count, recovery_count;
287 int bus_speed = system_bus_clock();
288 /*byte b;*/
289 ide_pio_data_t d;
290
291 switch (mode_wanted) {
292 case 8: /* set prefetch off */
293 case 9: /* set prefetch on */
294 mode_wanted &= 1;
295 /*set_prefetch_mode(index, mode_wanted);*/
296 cmdprintk("%s: %sabled cmd640 prefetch\n",
297 drive->name, mode_wanted ? "en" : "dis");
298 return;
299 }
300
301 mode_wanted = ide_get_best_pio_mode (drive, mode_wanted, 5, &d);
302 pio_mode = d.pio_mode;
303 cycle_time = d.cycle_time;
304
305 /*
306 * I copied all this complicated stuff from cmd640.c and made a few
307 * minor changes. For now I am just going to pray that it is correct.
308 */
309 if (pio_mode > 5)
310 pio_mode = 5;
311 setup_time = ide_pio_timings[pio_mode].setup_time;
312 active_time = ide_pio_timings[pio_mode].active_time;
313 recovery_time = cycle_time - (setup_time + active_time);
314 clock_time = 1000 / bus_speed;
315 cycle_count = (cycle_time + clock_time - 1) / clock_time;
316
317 setup_count = (setup_time + clock_time - 1) / clock_time;
318
319 active_count = (active_time + clock_time - 1) / clock_time;
320
321 recovery_count = (recovery_time + clock_time - 1) / clock_time;
322 recovery_count2 = cycle_count - (setup_count + active_count);
323 if (recovery_count2 > recovery_count)
324 recovery_count = recovery_count2;
325 if (recovery_count > 16) {
326 active_count += recovery_count - 16;
327 recovery_count = 16;
328 }
329 if (active_count > 16)
330 active_count = 16; /* maximum allowed by cmd646 */
331
332 /*
333 * In a perfect world, we might set the drive pio mode here
334 * (using WIN_SETFEATURE) before continuing.
335 *
336 * But we do not, because:
337 * 1) this is the wrong place to do it
338 * (proper is do_special() in ide.c)
339 * 2) in practice this is rarely, if ever, necessary
340 */
341 program_drive_counts (drive, setup_count, active_count, recovery_count);
342
343 cmdprintk("%s: selected cmd646 PIO mode%d : %d (%dns)%s, "
344 "clocks=%d/%d/%d\n",
345 drive->name, pio_mode, mode_wanted, cycle_time,
346 d.overridden ? " (overriding vendor mode)" : "",
347 setup_count, active_count, recovery_count);
348}
349
350static u8 cmd64x_ratemask (ide_drive_t *drive)
351{
352 struct pci_dev *dev = HWIF(drive)->pci_dev;
353 u8 mode = 0;
354
355 switch(dev->device) {
356 case PCI_DEVICE_ID_CMD_649:
357 mode = 3;
358 break;
359 case PCI_DEVICE_ID_CMD_648:
360 mode = 2;
361 break;
362 case PCI_DEVICE_ID_CMD_643:
363 return 0;
364
365 case PCI_DEVICE_ID_CMD_646:
366 {
367 unsigned int class_rev = 0;
368 pci_read_config_dword(dev,
369 PCI_CLASS_REVISION, &class_rev);
370 class_rev &= 0xff;
371 /*
372 * UltraDMA only supported on PCI646U and PCI646U2, which
373 * correspond to revisions 0x03, 0x05 and 0x07 respectively.
374 * Actually, although the CMD tech support people won't
375 * tell me the details, the 0x03 revision cannot support
376 * UDMA correctly without hardware modifications, and even
377 * then it only works with Quantum disks due to some
378 * hold time assumptions in the 646U part which are fixed
379 * in the 646U2.
380 *
381 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
382 */
383 switch(class_rev) {
384 case 0x07:
385 case 0x05:
386 return 1;
387 case 0x03:
388 case 0x01:
389 default:
390 return 0;
391 }
392 }
393 }
394 if (!eighty_ninty_three(drive))
395 mode = min(mode, (u8)1);
396 return mode;
397}
398
399static void config_cmd64x_chipset_for_pio (ide_drive_t *drive, u8 set_speed)
400{
401 u8 speed = 0x00;
402 u8 set_pio = ide_get_best_pio_mode(drive, 4, 5, NULL);
403
404 cmd64x_tuneproc(drive, set_pio);
405 speed = XFER_PIO_0 + set_pio;
406 if (set_speed)
407 (void) ide_config_drive_speed(drive, speed);
408}
409
410static void config_chipset_for_pio (ide_drive_t *drive, u8 set_speed)
411{
412 config_cmd64x_chipset_for_pio(drive, set_speed);
413}
414
415static int cmd64x_tune_chipset (ide_drive_t *drive, u8 xferspeed)
416{
417 ide_hwif_t *hwif = HWIF(drive);
418 struct pci_dev *dev = hwif->pci_dev;
419
420 u8 unit = (drive->select.b.unit & 0x01);
421 u8 regU = 0, pciU = (hwif->channel) ? UDIDETCR1 : UDIDETCR0;
422 u8 regD = 0, pciD = (hwif->channel) ? BMIDESR1 : BMIDESR0;
423
424 u8 speed = ide_rate_filter(cmd64x_ratemask(drive), xferspeed);
425
426 if (speed > XFER_PIO_4) {
427 (void) pci_read_config_byte(dev, pciD, &regD);
428 (void) pci_read_config_byte(dev, pciU, &regU);
429 regD &= ~(unit ? 0x40 : 0x20);
430 regU &= ~(unit ? 0xCA : 0x35);
431 (void) pci_write_config_byte(dev, pciD, regD);
432 (void) pci_write_config_byte(dev, pciU, regU);
433 (void) pci_read_config_byte(dev, pciD, &regD);
434 (void) pci_read_config_byte(dev, pciU, &regU);
435 }
436
437 switch(speed) {
438 case XFER_UDMA_5: regU |= (unit ? 0x0A : 0x05); break;
439 case XFER_UDMA_4: regU |= (unit ? 0x4A : 0x15); break;
440 case XFER_UDMA_3: regU |= (unit ? 0x8A : 0x25); break;
441 case XFER_UDMA_2: regU |= (unit ? 0x42 : 0x11); break;
442 case XFER_UDMA_1: regU |= (unit ? 0x82 : 0x21); break;
443 case XFER_UDMA_0: regU |= (unit ? 0xC2 : 0x31); break;
444 case XFER_MW_DMA_2: regD |= (unit ? 0x40 : 0x10); break;
445 case XFER_MW_DMA_1: regD |= (unit ? 0x80 : 0x20); break;
446 case XFER_MW_DMA_0: regD |= (unit ? 0xC0 : 0x30); break;
447 case XFER_SW_DMA_2: regD |= (unit ? 0x40 : 0x10); break;
448 case XFER_SW_DMA_1: regD |= (unit ? 0x80 : 0x20); break;
449 case XFER_SW_DMA_0: regD |= (unit ? 0xC0 : 0x30); break;
450 case XFER_PIO_4: cmd64x_tuneproc(drive, 4); break;
451 case XFER_PIO_3: cmd64x_tuneproc(drive, 3); break;
452 case XFER_PIO_2: cmd64x_tuneproc(drive, 2); break;
453 case XFER_PIO_1: cmd64x_tuneproc(drive, 1); break;
454 case XFER_PIO_0: cmd64x_tuneproc(drive, 0); break;
455
456 default:
457 return 1;
458 }
459
460 if (speed > XFER_PIO_4) {
461 (void) pci_write_config_byte(dev, pciU, regU);
462 regD |= (unit ? 0x40 : 0x20);
463 (void) pci_write_config_byte(dev, pciD, regD);
464 }
465
466 return (ide_config_drive_speed(drive, speed));
467}
468
469static int config_chipset_for_dma (ide_drive_t *drive)
470{
471 u8 speed = ide_dma_speed(drive, cmd64x_ratemask(drive));
472
473 config_chipset_for_pio(drive, !speed);
474
475 if (!speed)
476 return 0;
477
478 if(ide_set_xfer_rate(drive, speed))
479 return 0;
480
481 if (!drive->init_speed)
482 drive->init_speed = speed;
483
484 return ide_dma_enable(drive);
485}
486
487static int cmd64x_config_drive_for_dma (ide_drive_t *drive)
488{
489 ide_hwif_t *hwif = HWIF(drive);
490 struct hd_driveid *id = drive->id;
491
492 if ((id != NULL) && ((id->capability & 1) != 0) && drive->autodma) {
493
494 if (ide_use_dma(drive)) {
495 if (config_chipset_for_dma(drive))
496 return hwif->ide_dma_on(drive);
497 }
498
499 goto fast_ata_pio;
500
501 } else if ((id->capability & 8) || (id->field_valid & 2)) {
502fast_ata_pio:
503 config_chipset_for_pio(drive, 1);
504 return hwif->ide_dma_off_quietly(drive);
505 }
506 /* IORDY not supported */
507 return 0;
508}
509
510static int cmd64x_alt_dma_status (struct pci_dev *dev)
511{
512 switch(dev->device) {
513 case PCI_DEVICE_ID_CMD_648:
514 case PCI_DEVICE_ID_CMD_649:
515 return 1;
516 default:
517 break;
518 }
519 return 0;
520}
521
522static int cmd64x_ide_dma_end (ide_drive_t *drive)
523{
524 u8 dma_stat = 0, dma_cmd = 0;
525 ide_hwif_t *hwif = HWIF(drive);
526 struct pci_dev *dev = hwif->pci_dev;
527
528 drive->waiting_for_dma = 0;
529 /* read DMA command state */
530 dma_cmd = hwif->INB(hwif->dma_command);
531 /* stop DMA */
532 hwif->OUTB((dma_cmd & ~1), hwif->dma_command);
533 /* get DMA status */
534 dma_stat = hwif->INB(hwif->dma_status);
535 /* clear the INTR & ERROR bits */
536 hwif->OUTB(dma_stat|6, hwif->dma_status);
537 if (cmd64x_alt_dma_status(dev)) {
538 u8 dma_intr = 0;
539 u8 dma_mask = (hwif->channel) ? ARTTIM23_INTR_CH1 :
540 CFR_INTR_CH0;
541 u8 dma_reg = (hwif->channel) ? ARTTIM2 : CFR;
542 (void) pci_read_config_byte(dev, dma_reg, &dma_intr);
543 /* clear the INTR bit */
544 (void) pci_write_config_byte(dev, dma_reg, dma_intr|dma_mask);
545 }
546 /* purge DMA mappings */
547 ide_destroy_dmatable(drive);
548 /* verify good DMA status */
549 return (dma_stat & 7) != 4;
550}
551
552static int cmd64x_ide_dma_test_irq (ide_drive_t *drive)
553{
554 ide_hwif_t *hwif = HWIF(drive);
555 struct pci_dev *dev = hwif->pci_dev;
556 u8 dma_alt_stat = 0, mask = (hwif->channel) ? MRDMODE_INTR_CH1 :
557 MRDMODE_INTR_CH0;
558 u8 dma_stat = hwif->INB(hwif->dma_status);
559
560 (void) pci_read_config_byte(dev, MRDMODE, &dma_alt_stat);
561#ifdef DEBUG
562 printk("%s: dma_stat: 0x%02x dma_alt_stat: "
563 "0x%02x mask: 0x%02x\n", drive->name,
564 dma_stat, dma_alt_stat, mask);
565#endif
566 if (!(dma_alt_stat & mask))
567 return 0;
568
569 /* return 1 if INTR asserted */
570 if ((dma_stat & 4) == 4)
571 return 1;
572
573 return 0;
574}
575
576/*
577 * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
578 * event order for DMA transfers.
579 */
580
581static int cmd646_1_ide_dma_end (ide_drive_t *drive)
582{
583 ide_hwif_t *hwif = HWIF(drive);
584 u8 dma_stat = 0, dma_cmd = 0;
585
586 drive->waiting_for_dma = 0;
587 /* get DMA status */
588 dma_stat = hwif->INB(hwif->dma_status);
589 /* read DMA command state */
590 dma_cmd = hwif->INB(hwif->dma_command);
591 /* stop DMA */
592 hwif->OUTB((dma_cmd & ~1), hwif->dma_command);
593 /* clear the INTR & ERROR bits */
594 hwif->OUTB(dma_stat|6, hwif->dma_status);
595 /* and free any DMA resources */
596 ide_destroy_dmatable(drive);
597 /* verify good DMA status */
598 return (dma_stat & 7) != 4;
599}
600
601static unsigned int __devinit init_chipset_cmd64x(struct pci_dev *dev, const char *name)
602{
603 u32 class_rev = 0;
604 u8 mrdmode = 0;
605
606 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
607 class_rev &= 0xff;
608
609#ifdef __i386__
610 if (dev->resource[PCI_ROM_RESOURCE].start) {
611 pci_write_config_byte(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
612 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name, dev->resource[PCI_ROM_RESOURCE].start);
613 }
614#endif
615
616 switch(dev->device) {
617 case PCI_DEVICE_ID_CMD_643:
618 break;
619 case PCI_DEVICE_ID_CMD_646:
620 printk(KERN_INFO "%s: chipset revision 0x%02X, ", name, class_rev);
621 switch(class_rev) {
622 case 0x07:
623 case 0x05:
624 printk("UltraDMA Capable");
625 break;
626 case 0x03:
627 printk("MultiWord DMA Force Limited");
628 break;
629 case 0x01:
630 default:
631 printk("MultiWord DMA Limited, IRQ workaround enabled");
632 break;
633 }
634 printk("\n");
635 break;
636 case PCI_DEVICE_ID_CMD_648:
637 case PCI_DEVICE_ID_CMD_649:
638 break;
639 default:
640 break;
641 }
642
643 /* Set a good latency timer and cache line size value. */
644 (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
645 /* FIXME: pci_set_master() to ensure a good latency timer value */
646
647 /* Setup interrupts. */
648 (void) pci_read_config_byte(dev, MRDMODE, &mrdmode);
649 mrdmode &= ~(0x30);
650 (void) pci_write_config_byte(dev, MRDMODE, mrdmode);
651
652 /* Use MEMORY READ LINE for reads.
653 * NOTE: Although not mentioned in the PCI0646U specs,
654 * these bits are write only and won't be read
655 * back as set or not. The PCI0646U2 specs clarify
656 * this point.
657 */
658 (void) pci_write_config_byte(dev, MRDMODE, mrdmode | 0x02);
659
660 /* Set reasonable active/recovery/address-setup values. */
661 (void) pci_write_config_byte(dev, ARTTIM0, 0x40);
662 (void) pci_write_config_byte(dev, DRWTIM0, 0x3f);
663 (void) pci_write_config_byte(dev, ARTTIM1, 0x40);
664 (void) pci_write_config_byte(dev, DRWTIM1, 0x3f);
665#ifdef __i386__
666 (void) pci_write_config_byte(dev, ARTTIM23, 0x1c);
667#else
668 (void) pci_write_config_byte(dev, ARTTIM23, 0x5c);
669#endif
670 (void) pci_write_config_byte(dev, DRWTIM23, 0x3f);
671 (void) pci_write_config_byte(dev, DRWTIM3, 0x3f);
672#ifdef CONFIG_PPC
673 (void) pci_write_config_byte(dev, UDIDETCR0, 0xf0);
674#endif /* CONFIG_PPC */
675
676#if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS)
677
678 cmd_devs[n_cmd_devs++] = dev;
679
680 if (!cmd64x_proc) {
681 cmd64x_proc = 1;
682 ide_pci_create_host_proc("cmd64x", cmd64x_get_info);
683 }
684#endif /* DISPLAY_CMD64X_TIMINGS && CONFIG_PROC_FS */
685
686 return 0;
687}
688
689static unsigned int __devinit ata66_cmd64x(ide_hwif_t *hwif)
690{
691 u8 ata66 = 0, mask = (hwif->channel) ? 0x02 : 0x01;
692
693 switch(hwif->pci_dev->device) {
694 case PCI_DEVICE_ID_CMD_643:
695 case PCI_DEVICE_ID_CMD_646:
696 return ata66;
697 default:
698 break;
699 }
700 pci_read_config_byte(hwif->pci_dev, BMIDECSR, &ata66);
701 return (ata66 & mask) ? 1 : 0;
702}
703
704static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif)
705{
706 struct pci_dev *dev = hwif->pci_dev;
707 unsigned int class_rev;
708
709 hwif->autodma = 0;
710 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
711 class_rev &= 0xff;
712
713 hwif->tuneproc = &cmd64x_tuneproc;
714 hwif->speedproc = &cmd64x_tune_chipset;
715
716 if (!hwif->dma_base) {
717 hwif->drives[0].autotune = 1;
718 hwif->drives[1].autotune = 1;
719 return;
720 }
721
722 hwif->atapi_dma = 1;
723
724 hwif->ultra_mask = 0x3f;
725 hwif->mwdma_mask = 0x07;
726 hwif->swdma_mask = 0x07;
727
728 if (dev->device == PCI_DEVICE_ID_CMD_643)
729 hwif->ultra_mask = 0x80;
730 if (dev->device == PCI_DEVICE_ID_CMD_646)
731 hwif->ultra_mask = (class_rev > 0x04) ? 0x07 : 0x80;
732 if (dev->device == PCI_DEVICE_ID_CMD_648)
733 hwif->ultra_mask = 0x1f;
734
735 hwif->ide_dma_check = &cmd64x_config_drive_for_dma;
736 if (!(hwif->udma_four))
737 hwif->udma_four = ata66_cmd64x(hwif);
738
739 if (dev->device == PCI_DEVICE_ID_CMD_646) {
740 hwif->chipset = ide_cmd646;
741 if (class_rev == 0x01) {
742 hwif->ide_dma_end = &cmd646_1_ide_dma_end;
743 } else {
744 hwif->ide_dma_end = &cmd64x_ide_dma_end;
745 hwif->ide_dma_test_irq = &cmd64x_ide_dma_test_irq;
746 }
747 } else {
748 hwif->ide_dma_end = &cmd64x_ide_dma_end;
749 hwif->ide_dma_test_irq = &cmd64x_ide_dma_test_irq;
750 }
751
752
753 if (!noautodma)
754 hwif->autodma = 1;
755 hwif->drives[0].autodma = hwif->autodma;
756 hwif->drives[1].autodma = hwif->autodma;
757}
758
759static ide_pci_device_t cmd64x_chipsets[] __devinitdata = {
760 { /* 0 */
761 .name = "CMD643",
762 .init_chipset = init_chipset_cmd64x,
763 .init_hwif = init_hwif_cmd64x,
764 .channels = 2,
765 .autodma = AUTODMA,
766 .bootable = ON_BOARD,
767 },{ /* 1 */
768 .name = "CMD646",
769 .init_chipset = init_chipset_cmd64x,
770 .init_hwif = init_hwif_cmd64x,
771 .channels = 2,
772 .autodma = AUTODMA,
773 .enablebits = {{0x00,0x00,0x00}, {0x51,0x80,0x80}},
774 .bootable = ON_BOARD,
775 },{ /* 2 */
776 .name = "CMD648",
777 .init_chipset = init_chipset_cmd64x,
778 .init_hwif = init_hwif_cmd64x,
779 .channels = 2,
780 .autodma = AUTODMA,
781 .bootable = ON_BOARD,
782 },{ /* 3 */
783 .name = "CMD649",
784 .init_chipset = init_chipset_cmd64x,
785 .init_hwif = init_hwif_cmd64x,
786 .channels = 2,
787 .autodma = AUTODMA,
788 .bootable = ON_BOARD,
789 }
790};
791
792static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
793{
794 return ide_setup_pci_device(dev, &cmd64x_chipsets[id->driver_data]);
795}
796
797static struct pci_device_id cmd64x_pci_tbl[] = {
798 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_643, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
799 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
800 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_648, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
801 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
802 { 0, },
803};
804MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);
805
806static struct pci_driver driver = {
807 .name = "CMD64x_IDE",
808 .id_table = cmd64x_pci_tbl,
809 .probe = cmd64x_init_one,
810};
811
812static int cmd64x_ide_init(void)
813{
814 return ide_pci_register_driver(&driver);
815}
816
817module_init(cmd64x_ide_init);
818
819MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick");
820MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
821MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/cs5520.c b/drivers/ide/pci/cs5520.c
new file mode 100644
index 000000000000..7dc24682d197
--- /dev/null
+++ b/drivers/ide/pci/cs5520.c
@@ -0,0 +1,274 @@
1/*
2 * IDE tuning and bus mastering support for the CS5510/CS5520
3 * chipsets
4 *
5 * The CS5510/CS5520 are slightly unusual devices. Unlike the
6 * typical IDE controllers they do bus mastering with the drive in
7 * PIO mode and smarter silicon.
8 *
9 * The practical upshot of this is that we must always tune the
10 * drive for the right PIO mode. We must also ignore all the blacklists
11 * and the drive bus mastering DMA information.
12 *
13 * *** This driver is strictly experimental ***
14 *
15 * (c) Copyright Red Hat Inc 2002
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the
19 * Free Software Foundation; either version 2, or (at your option) any
20 * later version.
21 *
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
25 * General Public License for more details.
26 *
27 * For the avoidance of doubt the "preferred form" of this code is one which
28 * is in an open non patent encumbered format. Where cryptographic key signing
29 * forms part of the process of creating an executable the information
30 * including keys needed to generate an equivalently functional executable
31 * are deemed to be part of the source code.
32 *
33 */
34
35#include <linux/config.h>
36#include <linux/module.h>
37#include <linux/types.h>
38#include <linux/kernel.h>
39#include <linux/delay.h>
40#include <linux/timer.h>
41#include <linux/mm.h>
42#include <linux/ioport.h>
43#include <linux/blkdev.h>
44#include <linux/hdreg.h>
45
46#include <linux/interrupt.h>
47#include <linux/init.h>
48#include <linux/pci.h>
49#include <linux/ide.h>
50#include <linux/dma-mapping.h>
51
52#include <asm/io.h>
53#include <asm/irq.h>
54
55struct pio_clocks
56{
57 int address;
58 int assert;
59 int recovery;
60};
61
62static struct pio_clocks cs5520_pio_clocks[]={
63 {3, 6, 11},
64 {2, 5, 6},
65 {1, 4, 3},
66 {1, 3, 2},
67 {1, 2, 1}
68};
69
70static int cs5520_tune_chipset(ide_drive_t *drive, u8 xferspeed)
71{
72 ide_hwif_t *hwif = HWIF(drive);
73 struct pci_dev *pdev = hwif->pci_dev;
74 u8 speed = min((u8)XFER_PIO_4, xferspeed);
75 int pio = speed;
76 u8 reg;
77 int controller = drive->dn > 1 ? 1 : 0;
78 int error;
79
80 switch(speed)
81 {
82 case XFER_PIO_4:
83 case XFER_PIO_3:
84 case XFER_PIO_2:
85 case XFER_PIO_1:
86 case XFER_PIO_0:
87 pio -= XFER_PIO_0;
88 break;
89 default:
90 pio = 0;
91 printk(KERN_ERR "cs55x0: bad ide timing.\n");
92 }
93
94 printk("PIO clocking = %d\n", pio);
95
96 /* FIXME: if DMA = 1 do we need to set the DMA bit here ? */
97
98 /* 8bit CAT/CRT - 8bit command timing for channel */
99 pci_write_config_byte(pdev, 0x62 + controller,
100 (cs5520_pio_clocks[pio].recovery << 4) |
101 (cs5520_pio_clocks[pio].assert));
102
103 /* 0x64 - 16bit Primary, 0x68 - 16bit Secondary */
104
105 /* FIXME: should these use address ? */
106 /* Data read timing */
107 pci_write_config_byte(pdev, 0x64 + 4*controller + (drive->dn&1),
108 (cs5520_pio_clocks[pio].recovery << 4) |
109 (cs5520_pio_clocks[pio].assert));
110 /* Write command timing */
111 pci_write_config_byte(pdev, 0x66 + 4*controller + (drive->dn&1),
112 (cs5520_pio_clocks[pio].recovery << 4) |
113 (cs5520_pio_clocks[pio].assert));
114
115 /* Set the DMA enable/disable flag */
116 reg = inb(hwif->dma_base + 0x02 + 8*controller);
117 reg |= 1<<((drive->dn&1)+5);
118 outb(reg, hwif->dma_base + 0x02 + 8*controller);
119
120 error = ide_config_drive_speed(drive, speed);
121 /* ATAPI is harder so leave it for now */
122 if(!error && drive->media == ide_disk)
123 error = hwif->ide_dma_on(drive);
124
125 return error;
126}
127
128static void cs5520_tune_drive(ide_drive_t *drive, u8 pio)
129{
130 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
131 cs5520_tune_chipset(drive, (XFER_PIO_0 + pio));
132}
133
134static int cs5520_config_drive_xfer_rate(ide_drive_t *drive)
135{
136 ide_hwif_t *hwif = HWIF(drive);
137
138 /* Tune the drive for PIO modes up to PIO 4 */
139 cs5520_tune_drive(drive, 4);
140 /* Then tell the core to use DMA operations */
141 return hwif->ide_dma_on(drive);
142}
143
144/*
145 * We provide a callback for our nonstandard DMA location
146 */
147
148static void __devinit cs5520_init_setup_dma(struct pci_dev *dev, ide_pci_device_t *d, ide_hwif_t *hwif)
149{
150 unsigned long bmide = pci_resource_start(dev, 2); /* Not the usual 4 */
151 if(hwif->mate && hwif->mate->dma_base) /* Second channel at primary + 8 */
152 bmide += 8;
153 ide_setup_dma(hwif, bmide, 8);
154}
155
156/*
157 * We wrap the DMA activate to set the vdma flag. This is needed
158 * so that the IDE DMA layer issues PIO not DMA commands over the
159 * DMA channel
160 */
161
162static int cs5520_dma_on(ide_drive_t *drive)
163{
164 drive->vdma = 1;
165 return 0;
166}
167
168static void __devinit init_hwif_cs5520(ide_hwif_t *hwif)
169{
170 hwif->tuneproc = &cs5520_tune_drive;
171 hwif->speedproc = &cs5520_tune_chipset;
172 hwif->ide_dma_check = &cs5520_config_drive_xfer_rate;
173 hwif->ide_dma_on = &cs5520_dma_on;
174
175 if(!noautodma)
176 hwif->autodma = 1;
177
178 if(!hwif->dma_base)
179 {
180 hwif->drives[0].autotune = 1;
181 hwif->drives[1].autotune = 1;
182 return;
183 }
184
185 hwif->atapi_dma = 0;
186 hwif->ultra_mask = 0;
187 hwif->swdma_mask = 0;
188 hwif->mwdma_mask = 0;
189
190 hwif->drives[0].autodma = hwif->autodma;
191 hwif->drives[1].autodma = hwif->autodma;
192}
193
194#define DECLARE_CS_DEV(name_str) \
195 { \
196 .name = name_str, \
197 .init_setup_dma = cs5520_init_setup_dma, \
198 .init_hwif = init_hwif_cs5520, \
199 .channels = 2, \
200 .autodma = AUTODMA, \
201 .bootable = ON_BOARD, \
202 .flags = IDEPCI_FLAG_ISA_PORTS, \
203 }
204
205static ide_pci_device_t cyrix_chipsets[] __devinitdata = {
206 /* 0 */ DECLARE_CS_DEV("Cyrix 5510"),
207 /* 1 */ DECLARE_CS_DEV("Cyrix 5520")
208};
209
210/*
211 * The 5510/5520 are a bit weird. They don't quite set up the way
212 * the PCI helper layer expects so we must do much of the set up
213 * work longhand.
214 */
215
216static int __devinit cs5520_init_one(struct pci_dev *dev, const struct pci_device_id *id)
217{
218 ata_index_t index;
219 ide_pci_device_t *d = &cyrix_chipsets[id->driver_data];
220
221 ide_setup_pci_noise(dev, d);
222
223 /* We must not grab the entire device, it has 'ISA' space in its
224 BARS too and we will freak out other bits of the kernel */
225 if(pci_enable_device_bars(dev, 1<<2))
226 {
227 printk(KERN_WARNING "%s: Unable to enable 55x0.\n", d->name);
228 return 1;
229 }
230 pci_set_master(dev);
231 if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) {
232 printk(KERN_WARNING "cs5520: No suitable DMA available.\n");
233 return -ENODEV;
234 }
235
236 index.all = 0xf0f0;
237
238 /*
239 * Now the chipset is configured we can let the core
240 * do all the device setup for us
241 */
242
243 ide_pci_setup_ports(dev, d, 14, &index);
244
245 if((index.b.low & 0xf0) != 0xf0)
246 probe_hwif_init(&ide_hwifs[index.b.low]);
247 if((index.b.high & 0xf0) != 0xf0)
248 probe_hwif_init(&ide_hwifs[index.b.high]);
249 return 0;
250}
251
252static struct pci_device_id cs5520_pci_tbl[] = {
253 { PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5510, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
254 { PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
255 { 0, },
256};
257MODULE_DEVICE_TABLE(pci, cs5520_pci_tbl);
258
259static struct pci_driver driver = {
260 .name = "Cyrix_IDE",
261 .id_table = cs5520_pci_tbl,
262 .probe = cs5520_init_one,
263};
264
265static int cs5520_ide_init(void)
266{
267 return ide_pci_register_driver(&driver);
268}
269
270module_init(cs5520_ide_init);
271
272MODULE_AUTHOR("Alan Cox");
273MODULE_DESCRIPTION("PCI driver module for Cyrix 5510/5520 IDE");
274MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/cs5530.c b/drivers/ide/pci/cs5530.c
new file mode 100644
index 000000000000..0381961db263
--- /dev/null
+++ b/drivers/ide/pci/cs5530.c
@@ -0,0 +1,384 @@
1/*
2 * linux/drivers/ide/pci/cs5530.c Version 0.7 Sept 10, 2002
3 *
4 * Copyright (C) 2000 Andre Hedrick <andre@linux-ide.org>
5 * Ditto of GNU General Public License.
6 *
7 * Copyright (C) 2000 Mark Lord <mlord@pobox.com>
8 * May be copied or modified under the terms of the GNU General Public License
9 *
10 * Development of this chipset driver was funded
11 * by the nice folks at National Semiconductor.
12 *
13 * Documentation:
14 * CS5530 documentation available from National Semiconductor.
15 */
16
17#include <linux/config.h>
18#include <linux/module.h>
19#include <linux/types.h>
20#include <linux/kernel.h>
21#include <linux/delay.h>
22#include <linux/timer.h>
23#include <linux/mm.h>
24#include <linux/ioport.h>
25#include <linux/blkdev.h>
26#include <linux/hdreg.h>
27#include <linux/interrupt.h>
28#include <linux/pci.h>
29#include <linux/init.h>
30#include <linux/ide.h>
31#include <asm/io.h>
32#include <asm/irq.h>
33
34/**
35 * cs5530_xfer_set_mode - set a new transfer mode at the drive
36 * @drive: drive to tune
37 * @mode: new mode
38 *
39 * Logging wrapper to the IDE driver speed configuration. This can
40 * probably go away now.
41 */
42
43static int cs5530_set_xfer_mode (ide_drive_t *drive, u8 mode)
44{
45 printk(KERN_DEBUG "%s: cs5530_set_xfer_mode(%s)\n",
46 drive->name, ide_xfer_verbose(mode));
47 return (ide_config_drive_speed(drive, mode));
48}
49
50/*
51 * Here are the standard PIO mode 0-4 timings for each "format".
52 * Format-0 uses fast data reg timings, with slower command reg timings.
53 * Format-1 uses fast timings for all registers, but won't work with all drives.
54 */
55static unsigned int cs5530_pio_timings[2][5] = {
56 {0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
57 {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
58};
59
60/*
61 * After chip reset, the PIO timings are set to 0x0000e132, which is not valid.
62 */
63#define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132)
64#define CS5530_BASEREG(hwif) (((hwif)->dma_base & ~0xf) + ((hwif)->channel ? 0x30 : 0x20))
65
66/**
67 * cs5530_tuneproc - select/set PIO modes
68 *
69 * cs5530_tuneproc() handles selection/setting of PIO modes
70 * for both the chipset and drive.
71 *
72 * The ide_init_cs5530() routine guarantees that all drives
73 * will have valid default PIO timings set up before we get here.
74 */
75
76static void cs5530_tuneproc (ide_drive_t *drive, u8 pio) /* pio=255 means "autotune" */
77{
78 ide_hwif_t *hwif = HWIF(drive);
79 unsigned int format;
80 unsigned long basereg = CS5530_BASEREG(hwif);
81 static u8 modes[5] = { XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3, XFER_PIO_4};
82
83 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
84 if (!cs5530_set_xfer_mode(drive, modes[pio])) {
85 format = (hwif->INL(basereg+4) >> 31) & 1;
86 hwif->OUTL(cs5530_pio_timings[format][pio],
87 basereg+(drive->select.b.unit<<3));
88 }
89}
90
91/**
92 * cs5530_config_dma - select/set DMA and UDMA modes
93 * @drive: drive to tune
94 *
95 * cs5530_config_dma() handles selection/setting of DMA/UDMA modes
96 * for both the chipset and drive. The CS5530 has limitations about
97 * mixing DMA/UDMA on the same cable.
98 */
99
100static int cs5530_config_dma (ide_drive_t *drive)
101{
102 int udma_ok = 1, mode = 0;
103 ide_hwif_t *hwif = HWIF(drive);
104 int unit = drive->select.b.unit;
105 ide_drive_t *mate = &hwif->drives[unit^1];
106 struct hd_driveid *id = drive->id;
107 unsigned int reg, timings;
108 unsigned long basereg;
109
110 /*
111 * Default to DMA-off in case we run into trouble here.
112 */
113 hwif->ide_dma_off_quietly(drive);
114 /* turn off DMA while we fiddle */
115 hwif->ide_dma_host_off(drive);
116 /* clear DMA_capable bit */
117
118 /*
119 * The CS5530 specifies that two drives sharing a cable cannot
120 * mix UDMA/MDMA. It has to be one or the other, for the pair,
121 * though different timings can still be chosen for each drive.
122 * We could set the appropriate timing bits on the fly,
123 * but that might be a bit confusing. So, for now we statically
124 * handle this requirement by looking at our mate drive to see
125 * what it is capable of, before choosing a mode for our own drive.
126 *
127 * Note: This relies on the fact we never fail from UDMA to MWDMA_2
128 * but instead drop to PIO
129 */
130 if (mate->present) {
131 struct hd_driveid *mateid = mate->id;
132 if (mateid && (mateid->capability & 1) &&
133 !__ide_dma_bad_drive(mate)) {
134 if ((mateid->field_valid & 4) &&
135 (mateid->dma_ultra & 7))
136 udma_ok = 1;
137 else if ((mateid->field_valid & 2) &&
138 (mateid->dma_mword & 7))
139 udma_ok = 0;
140 else
141 udma_ok = 1;
142 }
143 }
144
145 /*
146 * Now see what the current drive is capable of,
147 * selecting UDMA only if the mate said it was ok.
148 */
149 if (id && (id->capability & 1) && drive->autodma &&
150 !__ide_dma_bad_drive(drive)) {
151 if (udma_ok && (id->field_valid & 4) && (id->dma_ultra & 7)) {
152 if (id->dma_ultra & 4)
153 mode = XFER_UDMA_2;
154 else if (id->dma_ultra & 2)
155 mode = XFER_UDMA_1;
156 else if (id->dma_ultra & 1)
157 mode = XFER_UDMA_0;
158 }
159 if (!mode && (id->field_valid & 2) && (id->dma_mword & 7)) {
160 if (id->dma_mword & 4)
161 mode = XFER_MW_DMA_2;
162 else if (id->dma_mword & 2)
163 mode = XFER_MW_DMA_1;
164 else if (id->dma_mword & 1)
165 mode = XFER_MW_DMA_0;
166 }
167 }
168
169 /*
170 * Tell the drive to switch to the new mode; abort on failure.
171 */
172 if (!mode || cs5530_set_xfer_mode(drive, mode))
173 return 1; /* failure */
174
175 /*
176 * Now tune the chipset to match the drive:
177 */
178 switch (mode) {
179 case XFER_UDMA_0: timings = 0x00921250; break;
180 case XFER_UDMA_1: timings = 0x00911140; break;
181 case XFER_UDMA_2: timings = 0x00911030; break;
182 case XFER_MW_DMA_0: timings = 0x00077771; break;
183 case XFER_MW_DMA_1: timings = 0x00012121; break;
184 case XFER_MW_DMA_2: timings = 0x00002020; break;
185 default:
186 printk(KERN_ERR "%s: cs5530_config_dma: huh? mode=%02x\n",
187 drive->name, mode);
188 return 1; /* failure */
189 }
190 basereg = CS5530_BASEREG(hwif);
191 reg = hwif->INL(basereg+4); /* get drive0 config register */
192 timings |= reg & 0x80000000; /* preserve PIO format bit */
193 if (unit == 0) { /* are we configuring drive0? */
194 hwif->OUTL(timings, basereg+4); /* write drive0 config register */
195 } else {
196 if (timings & 0x00100000)
197 reg |= 0x00100000; /* enable UDMA timings for both drives */
198 else
199 reg &= ~0x00100000; /* disable UDMA timings for both drives */
200 hwif->OUTL(reg, basereg+4); /* write drive0 config register */
201 hwif->OUTL(timings, basereg+12); /* write drive1 config register */
202 }
203 (void) hwif->ide_dma_host_on(drive);
204 /* set DMA_capable bit */
205
206 /*
207 * Finally, turn DMA on in software, and exit.
208 */
209 return hwif->ide_dma_on(drive); /* success */
210}
211
212/**
213 * init_chipset_5530 - set up 5530 bridge
214 * @dev: PCI device
215 * @name: device name
216 *
217 * Initialize the cs5530 bridge for reliable IDE DMA operation.
218 */
219
220static unsigned int __init init_chipset_cs5530 (struct pci_dev *dev, const char *name)
221{
222 struct pci_dev *master_0 = NULL, *cs5530_0 = NULL;
223 unsigned long flags;
224
225 dev = NULL;
226 while ((dev = pci_find_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
227 switch (dev->device) {
228 case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
229 master_0 = dev;
230 break;
231 case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
232 cs5530_0 = dev;
233 break;
234 }
235 }
236 if (!master_0) {
237 printk(KERN_ERR "%s: unable to locate PCI MASTER function\n", name);
238 return 0;
239 }
240 if (!cs5530_0) {
241 printk(KERN_ERR "%s: unable to locate CS5530 LEGACY function\n", name);
242 return 0;
243 }
244
245 spin_lock_irqsave(&ide_lock, flags);
246 /* all CPUs (there should only be one CPU with this chipset) */
247
248 /*
249 * Enable BusMaster and MemoryWriteAndInvalidate for the cs5530:
250 * --> OR 0x14 into 16-bit PCI COMMAND reg of function 0 of the cs5530
251 */
252
253 pci_set_master(cs5530_0);
254 pci_set_mwi(cs5530_0);
255
256 /*
257 * Set PCI CacheLineSize to 16-bytes:
258 * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
259 */
260
261 pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);
262
263 /*
264 * Disable trapping of UDMA register accesses (Win98 hack):
265 * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
266 */
267
268 pci_write_config_word(cs5530_0, 0xd0, 0x5006);
269
270 /*
271 * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
272 * The other settings are what is necessary to get the register
273 * into a sane state for IDE DMA operation.
274 */
275
276 pci_write_config_byte(master_0, 0x40, 0x1e);
277
278 /*
279 * Set max PCI burst size (16-bytes seems to work best):
280 * 16bytes: set bit-1 at 0x41 (reg value of 0x16)
281 * all others: clear bit-1 at 0x41, and do:
282 * 128bytes: OR 0x00 at 0x41
283 * 256bytes: OR 0x04 at 0x41
284 * 512bytes: OR 0x08 at 0x41
285 * 1024bytes: OR 0x0c at 0x41
286 */
287
288 pci_write_config_byte(master_0, 0x41, 0x14);
289
290 /*
291 * These settings are necessary to get the chip
292 * into a sane state for IDE DMA operation.
293 */
294
295 pci_write_config_byte(master_0, 0x42, 0x00);
296 pci_write_config_byte(master_0, 0x43, 0xc1);
297
298 spin_unlock_irqrestore(&ide_lock, flags);
299
300 return 0;
301}
302
303/**
304 * init_hwif_cs5530 - initialise an IDE channel
305 * @hwif: IDE to initialize
306 *
307 * This gets invoked by the IDE driver once for each channel. It
308 * performs channel-specific pre-initialization before drive probing.
309 */
310
311static void __init init_hwif_cs5530 (ide_hwif_t *hwif)
312{
313 unsigned long basereg;
314 u32 d0_timings;
315 hwif->autodma = 0;
316
317 if (hwif->mate)
318 hwif->serialized = hwif->mate->serialized = 1;
319
320 hwif->tuneproc = &cs5530_tuneproc;
321 basereg = CS5530_BASEREG(hwif);
322 d0_timings = hwif->INL(basereg+0);
323 if (CS5530_BAD_PIO(d0_timings)) {
324 /* PIO timings not initialized? */
325 hwif->OUTL(cs5530_pio_timings[(d0_timings>>31)&1][0], basereg+0);
326 if (!hwif->drives[0].autotune)
327 hwif->drives[0].autotune = 1;
328 /* needs autotuning later */
329 }
330 if (CS5530_BAD_PIO(hwif->INL(basereg+8))) {
331 /* PIO timings not initialized? */
332 hwif->OUTL(cs5530_pio_timings[(d0_timings>>31)&1][0], basereg+8);
333 if (!hwif->drives[1].autotune)
334 hwif->drives[1].autotune = 1;
335 /* needs autotuning later */
336 }
337
338 hwif->atapi_dma = 1;
339 hwif->ultra_mask = 0x07;
340 hwif->mwdma_mask = 0x07;
341
342 hwif->ide_dma_check = &cs5530_config_dma;
343 if (!noautodma)
344 hwif->autodma = 1;
345 hwif->drives[0].autodma = hwif->autodma;
346 hwif->drives[1].autodma = hwif->autodma;
347}
348
349static ide_pci_device_t cs5530_chipset __devinitdata = {
350 .name = "CS5530",
351 .init_chipset = init_chipset_cs5530,
352 .init_hwif = init_hwif_cs5530,
353 .channels = 2,
354 .autodma = AUTODMA,
355 .bootable = ON_BOARD,
356};
357
358static int __devinit cs5530_init_one(struct pci_dev *dev, const struct pci_device_id *id)
359{
360 return ide_setup_pci_device(dev, &cs5530_chipset);
361}
362
363static struct pci_device_id cs5530_pci_tbl[] = {
364 { PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
365 { 0, },
366};
367MODULE_DEVICE_TABLE(pci, cs5530_pci_tbl);
368
369static struct pci_driver driver = {
370 .name = "CS5530 IDE",
371 .id_table = cs5530_pci_tbl,
372 .probe = cs5530_init_one,
373};
374
375static int cs5530_ide_init(void)
376{
377 return ide_pci_register_driver(&driver);
378}
379
380module_init(cs5530_ide_init);
381
382MODULE_AUTHOR("Mark Lord");
383MODULE_DESCRIPTION("PCI driver module for Cyrix/NS 5530 IDE");
384MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/cy82c693.c b/drivers/ide/pci/cy82c693.c
new file mode 100644
index 000000000000..80d67e99ccb5
--- /dev/null
+++ b/drivers/ide/pci/cy82c693.c
@@ -0,0 +1,531 @@
1/*
2 * linux/drivers/ide/pci/cy82c693.c Version 0.40 Sep. 10, 2002
3 *
4 * Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer
5 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator
6 *
7 * CYPRESS CY82C693 chipset IDE controller
8 *
9 * The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards.
10 * Writing the driver was quite simple, since most of the job is
11 * done by the generic pci-ide support.
12 * The hard part was finding the CY82C693's datasheet on Cypress's
13 * web page :-(. But Altavista solved this problem :-).
14 *
15 *
16 * Notes:
17 * - I recently got a 16.8G IBM DTTA, so I was able to test it with
18 * a large and fast disk - the results look great, so I'd say the
19 * driver is working fine :-)
20 * hdparm -t reports 8.17 MB/sec at about 6% CPU usage for the DTTA
21 * - this is my first linux driver, so there's probably a lot of room
22 * for optimizations and bug fixing, so feel free to do it.
23 * - use idebus=xx parameter to set PCI bus speed - needed to calc
24 * timings for PIO modes (default will be 40)
25 * - if using PIO mode it's a good idea to set the PIO mode and
26 * 32-bit I/O support (if possible), e.g. hdparm -p2 -c1 /dev/hda
27 * - I had some problems with my IBM DHEA with PIO modes < 2
28 * (lost interrupts) ?????
29 * - first tests with DMA look okay, they seem to work, but there is a
30 * problem with sound - the BusMaster IDE TimeOut should fixed this
31 *
32 * Ancient History:
33 * AMH@1999-08-24: v0.34 init_cy82c693_chip moved to pci_init_cy82c693
34 * ASK@1999-01-23: v0.33 made a few minor code clean ups
35 * removed DMA clock speed setting by default
36 * added boot message
37 * ASK@1998-11-01: v0.32 added support to set BusMaster IDE TimeOut
38 * added support to set DMA Controller Clock Speed
39 * ASK@1998-10-31: v0.31 fixed problem with setting to high DMA modes
40 * on some drives.
41 * ASK@1998-10-29: v0.3 added support to set DMA modes
42 * ASK@1998-10-28: v0.2 added support to set PIO modes
43 * ASK@1998-10-27: v0.1 first version - chipset detection
44 *
45 */
46
47#include <linux/config.h>
48#include <linux/module.h>
49#include <linux/types.h>
50#include <linux/pci.h>
51#include <linux/delay.h>
52#include <linux/ide.h>
53#include <linux/init.h>
54
55#include <asm/io.h>
56
57/* the current version */
58#define CY82_VERSION "CY82C693U driver v0.34 99-13-12 Andreas S. Krebs (akrebs@altavista.net)"
59
60/*
61 * The following are used to debug the driver.
62 */
63#define CY82C693_DEBUG_LOGS 0
64#define CY82C693_DEBUG_INFO 0
65
66/* define CY82C693_SETDMA_CLOCK to set DMA Controller Clock Speed to ATCLK */
67#undef CY82C693_SETDMA_CLOCK
68
69/*
70 * NOTE: the value for busmaster timeout is tricky and I got it by
71 * trial and error! By using a to low value will cause DMA timeouts
72 * and drop IDE performance, and by using a to high value will cause
73 * audio playback to scatter.
74 * If you know a better value or how to calc it, please let me know.
75 */
76
77/* twice the value written in cy82c693ub datasheet */
78#define BUSMASTER_TIMEOUT 0x50
79/*
80 * the value above was tested on my machine and it seems to work okay
81 */
82
83/* here are the offset definitions for the registers */
84#define CY82_IDE_CMDREG 0x04
85#define CY82_IDE_ADDRSETUP 0x48
86#define CY82_IDE_MASTER_IOR 0x4C
87#define CY82_IDE_MASTER_IOW 0x4D
88#define CY82_IDE_SLAVE_IOR 0x4E
89#define CY82_IDE_SLAVE_IOW 0x4F
90#define CY82_IDE_MASTER_8BIT 0x50
91#define CY82_IDE_SLAVE_8BIT 0x51
92
93#define CY82_INDEX_PORT 0x22
94#define CY82_DATA_PORT 0x23
95
96#define CY82_INDEX_CTRLREG1 0x01
97#define CY82_INDEX_CHANNEL0 0x30
98#define CY82_INDEX_CHANNEL1 0x31
99#define CY82_INDEX_TIMEOUT 0x32
100
101/* the max PIO mode - from datasheet */
102#define CY82C693_MAX_PIO 4
103
104/* the min and max PCI bus speed in MHz - from datasheet */
105#define CY82C963_MIN_BUS_SPEED 25
106#define CY82C963_MAX_BUS_SPEED 33
107
108/* the struct for the PIO mode timings */
109typedef struct pio_clocks_s {
110 u8 address_time; /* Address setup (clocks) */
111 u8 time_16r; /* clocks for 16bit IOR (0xF0=Active/data, 0x0F=Recovery) */
112 u8 time_16w; /* clocks for 16bit IOW (0xF0=Active/data, 0x0F=Recovery) */
113 u8 time_8; /* clocks for 8bit (0xF0=Active/data, 0x0F=Recovery) */
114} pio_clocks_t;
115
116/*
117 * calc clocks using bus_speed
118 * returns (rounded up) time in bus clocks for time in ns
119 */
120static int calc_clk (int time, int bus_speed)
121{
122 int clocks;
123
124 clocks = (time*bus_speed+999)/1000 -1;
125
126 if (clocks < 0)
127 clocks = 0;
128
129 if (clocks > 0x0F)
130 clocks = 0x0F;
131
132 return clocks;
133}
134
135/*
136 * compute the values for the clock registers for PIO
137 * mode and pci_clk [MHz] speed
138 *
139 * NOTE: for mode 0,1 and 2 drives 8-bit IDE command control registers are used
140 * for mode 3 and 4 drives 8 and 16-bit timings are the same
141 *
142 */
143static void compute_clocks (u8 pio, pio_clocks_t *p_pclk)
144{
145 int clk1, clk2;
146 int bus_speed = system_bus_clock(); /* get speed of PCI bus */
147
148 /* we don't check against CY82C693's min and max speed,
149 * so you can play with the idebus=xx parameter
150 */
151
152 if (pio > CY82C693_MAX_PIO)
153 pio = CY82C693_MAX_PIO;
154
155 /* let's calc the address setup time clocks */
156 p_pclk->address_time = (u8)calc_clk(ide_pio_timings[pio].setup_time, bus_speed);
157
158 /* let's calc the active and recovery time clocks */
159 clk1 = calc_clk(ide_pio_timings[pio].active_time, bus_speed);
160
161 /* calc recovery timing */
162 clk2 = ide_pio_timings[pio].cycle_time -
163 ide_pio_timings[pio].active_time -
164 ide_pio_timings[pio].setup_time;
165
166 clk2 = calc_clk(clk2, bus_speed);
167
168 clk1 = (clk1<<4)|clk2; /* combine active and recovery clocks */
169
170 /* note: we use the same values for 16bit IOR and IOW
171 * those are all the same, since I don't have other
172 * timings than those from ide-lib.c
173 */
174
175 p_pclk->time_16r = (u8)clk1;
176 p_pclk->time_16w = (u8)clk1;
177
178 /* what are good values for 8bit ?? */
179 p_pclk->time_8 = (u8)clk1;
180}
181
182/*
183 * set DMA mode a specific channel for CY82C693
184 */
185
186static void cy82c693_dma_enable (ide_drive_t *drive, int mode, int single)
187{
188 u8 index = 0, data = 0;
189
190 if (mode>2) /* make sure we set a valid mode */
191 mode = 2;
192
193 if (mode > drive->id->tDMA) /* to be absolutly sure we have a valid mode */
194 mode = drive->id->tDMA;
195
196 index = (HWIF(drive)->channel==0) ? CY82_INDEX_CHANNEL0 : CY82_INDEX_CHANNEL1;
197
198#if CY82C693_DEBUG_LOGS
199 /* for debug let's show the previous values */
200
201 HWIF(drive)->OUTB(index, CY82_INDEX_PORT);
202 data = HWIF(drive)->INB(CY82_DATA_PORT);
203
204 printk (KERN_INFO "%s (ch=%d, dev=%d): DMA mode is %d (single=%d)\n",
205 drive->name, HWIF(drive)->channel, drive->select.b.unit,
206 (data&0x3), ((data>>2)&1));
207#endif /* CY82C693_DEBUG_LOGS */
208
209 data = (u8)mode|(u8)(single<<2);
210
211 HWIF(drive)->OUTB(index, CY82_INDEX_PORT);
212 HWIF(drive)->OUTB(data, CY82_DATA_PORT);
213
214#if CY82C693_DEBUG_INFO
215 printk(KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n",
216 drive->name, HWIF(drive)->channel, drive->select.b.unit,
217 mode, single);
218#endif /* CY82C693_DEBUG_INFO */
219
220 /*
221 * note: below we set the value for Bus Master IDE TimeOut Register
222 * I'm not absolutly sure what this does, but it solved my problem
223 * with IDE DMA and sound, so I now can play sound and work with
224 * my IDE driver at the same time :-)
225 *
226 * If you know the correct (best) value for this register please
227 * let me know - ASK
228 */
229
230 data = BUSMASTER_TIMEOUT;
231 HWIF(drive)->OUTB(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
232 HWIF(drive)->OUTB(data, CY82_DATA_PORT);
233
234#if CY82C693_DEBUG_INFO
235 printk (KERN_INFO "%s: Set IDE Bus Master TimeOut Register to 0x%X\n",
236 drive->name, data);
237#endif /* CY82C693_DEBUG_INFO */
238}
239
240/*
241 * used to set DMA mode for CY82C693 (single and multi modes)
242 */
243static int cy82c693_ide_dma_on (ide_drive_t *drive)
244{
245 struct hd_driveid *id = drive->id;
246
247#if CY82C693_DEBUG_INFO
248 printk (KERN_INFO "dma_on: %s\n", drive->name);
249#endif /* CY82C693_DEBUG_INFO */
250
251 if (id != NULL) {
252 /* Enable DMA on any drive that has DMA
253 * (multi or single) enabled
254 */
255 if (id->field_valid & 2) { /* regular DMA */
256 int mmode, smode;
257
258 mmode = id->dma_mword & (id->dma_mword >> 8);
259 smode = id->dma_1word & (id->dma_1word >> 8);
260
261 if (mmode != 0) {
262 /* enable multi */
263 cy82c693_dma_enable(drive, (mmode >> 1), 0);
264 } else if (smode != 0) {
265 /* enable single */
266 cy82c693_dma_enable(drive, (smode >> 1), 1);
267 }
268 }
269 }
270 return __ide_dma_on(drive);
271}
272
273/*
274 * tune ide drive - set PIO mode
275 */
276static void cy82c693_tune_drive (ide_drive_t *drive, u8 pio)
277{
278 ide_hwif_t *hwif = HWIF(drive);
279 struct pci_dev *dev = hwif->pci_dev;
280 pio_clocks_t pclk;
281 unsigned int addrCtrl;
282
283 /* select primary or secondary channel */
284 if (hwif->index > 0) { /* drive is on the secondary channel */
285 dev = pci_find_slot(dev->bus->number, dev->devfn+1);
286 if (!dev) {
287 printk(KERN_ERR "%s: tune_drive: "
288 "Cannot find secondary interface!\n",
289 drive->name);
290 return;
291 }
292 }
293
294#if CY82C693_DEBUG_LOGS
295 /* for debug let's show the register values */
296
297 if (drive->select.b.unit == 0) {
298 /*
299 * get master drive registers
300 * address setup control register
301 * is 32 bit !!!
302 */
303 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
304 addrCtrl &= 0x0F;
305
306 /* now let's get the remaining registers */
307 pci_read_config_byte(dev, CY82_IDE_MASTER_IOR, &pclk.time_16r);
308 pci_read_config_byte(dev, CY82_IDE_MASTER_IOW, &pclk.time_16w);
309 pci_read_config_byte(dev, CY82_IDE_MASTER_8BIT, &pclk.time_8);
310 } else {
311 /*
312 * set slave drive registers
313 * address setup control register
314 * is 32 bit !!!
315 */
316 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
317
318 addrCtrl &= 0xF0;
319 addrCtrl >>= 4;
320
321 /* now let's get the remaining registers */
322 pci_read_config_byte(dev, CY82_IDE_SLAVE_IOR, &pclk.time_16r);
323 pci_read_config_byte(dev, CY82_IDE_SLAVE_IOW, &pclk.time_16w);
324 pci_read_config_byte(dev, CY82_IDE_SLAVE_8BIT, &pclk.time_8);
325 }
326
327 printk(KERN_INFO "%s (ch=%d, dev=%d): PIO timing is "
328 "(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
329 drive->name, hwif->channel, drive->select.b.unit,
330 addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
331#endif /* CY82C693_DEBUG_LOGS */
332
333 /* first let's calc the pio modes */
334 pio = ide_get_best_pio_mode(drive, pio, CY82C693_MAX_PIO, NULL);
335
336#if CY82C693_DEBUG_INFO
337 printk (KERN_INFO "%s: Selected PIO mode %d\n", drive->name, pio);
338#endif /* CY82C693_DEBUG_INFO */
339
340 /* let's calc the values for this PIO mode */
341 compute_clocks(pio, &pclk);
342
343 /* now let's write the clocks registers */
344 if (drive->select.b.unit == 0) {
345 /*
346 * set master drive
347 * address setup control register
348 * is 32 bit !!!
349 */
350 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
351
352 addrCtrl &= (~0xF);
353 addrCtrl |= (unsigned int)pclk.address_time;
354 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
355
356 /* now let's set the remaining registers */
357 pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, pclk.time_16r);
358 pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, pclk.time_16w);
359 pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, pclk.time_8);
360
361 addrCtrl &= 0xF;
362 } else {
363 /*
364 * set slave drive
365 * address setup control register
366 * is 32 bit !!!
367 */
368 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
369
370 addrCtrl &= (~0xF0);
371 addrCtrl |= ((unsigned int)pclk.address_time<<4);
372 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
373
374 /* now let's set the remaining registers */
375 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, pclk.time_16r);
376 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, pclk.time_16w);
377 pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, pclk.time_8);
378
379 addrCtrl >>= 4;
380 addrCtrl &= 0xF;
381 }
382
383#if CY82C693_DEBUG_INFO
384 printk(KERN_INFO "%s (ch=%d, dev=%d): set PIO timing to "
385 "(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
386 drive->name, hwif->channel, drive->select.b.unit,
387 addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
388#endif /* CY82C693_DEBUG_INFO */
389}
390
391/*
392 * this function is called during init and is used to setup the cy82c693 chip
393 */
394static unsigned int __init init_chipset_cy82c693(struct pci_dev *dev, const char *name)
395{
396 if (PCI_FUNC(dev->devfn) != 1)
397 return 0;
398
399#ifdef CY82C693_SETDMA_CLOCK
400 u8 data = 0;
401#endif /* CY82C693_SETDMA_CLOCK */
402
403 /* write info about this verion of the driver */
404 printk(KERN_INFO CY82_VERSION "\n");
405
406#ifdef CY82C693_SETDMA_CLOCK
407 /* okay let's set the DMA clock speed */
408
409 outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
410 data = inb(CY82_DATA_PORT);
411
412#if CY82C693_DEBUG_INFO
413 printk(KERN_INFO "%s: Peripheral Configuration Register: 0x%X\n",
414 name, data);
415#endif /* CY82C693_DEBUG_INFO */
416
417 /*
418 * for some reason sometimes the DMA controller
419 * speed is set to ATCLK/2 ???? - we fix this here
420 *
421 * note: i don't know what causes this strange behaviour,
422 * but even changing the dma speed doesn't solve it :-(
423 * the ide performance is still only half the normal speed
424 *
425 * if anybody knows what goes wrong with my machine, please
426 * let me know - ASK
427 */
428
429 data |= 0x03;
430
431 outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
432 outb(data, CY82_DATA_PORT);
433
434#if CY82C693_DEBUG_INFO
435 printk (KERN_INFO "%s: New Peripheral Configuration Register: 0x%X\n",
436 name, data);
437#endif /* CY82C693_DEBUG_INFO */
438
439#endif /* CY82C693_SETDMA_CLOCK */
440 return 0;
441}
442
443/*
444 * the init function - called for each ide channel once
445 */
446static void __init init_hwif_cy82c693(ide_hwif_t *hwif)
447{
448 hwif->autodma = 0;
449
450 hwif->chipset = ide_cy82c693;
451 hwif->tuneproc = &cy82c693_tune_drive;
452
453 if (!hwif->dma_base) {
454 hwif->drives[0].autotune = 1;
455 hwif->drives[1].autotune = 1;
456 return;
457 }
458
459 hwif->atapi_dma = 1;
460 hwif->mwdma_mask = 0x04;
461 hwif->swdma_mask = 0x04;
462
463 hwif->ide_dma_on = &cy82c693_ide_dma_on;
464 if (!noautodma)
465 hwif->autodma = 1;
466 hwif->drives[0].autodma = hwif->autodma;
467 hwif->drives[1].autodma = hwif->autodma;
468}
469
470static __initdata ide_hwif_t *primary;
471
472void __init init_iops_cy82c693(ide_hwif_t *hwif)
473{
474 if (PCI_FUNC(hwif->pci_dev->devfn) == 1)
475 primary = hwif;
476 else {
477 hwif->mate = primary;
478 hwif->channel = 1;
479 }
480}
481
482static ide_pci_device_t cy82c693_chipsets[] __devinitdata = {
483 { /* 0 */
484 .name = "CY82C693",
485 .init_chipset = init_chipset_cy82c693,
486 .init_iops = init_iops_cy82c693,
487 .init_hwif = init_hwif_cy82c693,
488 .channels = 1,
489 .autodma = AUTODMA,
490 .bootable = ON_BOARD,
491 }
492};
493
494static int __devinit cy82c693_init_one(struct pci_dev *dev, const struct pci_device_id *id)
495{
496 ide_pci_device_t *d = &cy82c693_chipsets[id->driver_data];
497 struct pci_dev *dev2;
498 int ret = -ENODEV;
499
500 /* CY82C693 is more than only a IDE controller.
501 Function 1 is primary IDE channel, function 2 - secondary. */
502 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE &&
503 PCI_FUNC(dev->devfn) == 1) {
504 dev2 = pci_find_slot(dev->bus->number, dev->devfn + 1);
505 ret = ide_setup_pci_devices(dev, dev2, d);
506 }
507 return ret;
508}
509
510static struct pci_device_id cy82c693_pci_tbl[] = {
511 { PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
512 { 0, },
513};
514MODULE_DEVICE_TABLE(pci, cy82c693_pci_tbl);
515
516static struct pci_driver driver = {
517 .name = "Cypress_IDE",
518 .id_table = cy82c693_pci_tbl,
519 .probe = cy82c693_init_one,
520};
521
522static int cy82c693_ide_init(void)
523{
524 return ide_pci_register_driver(&driver);
525}
526
527module_init(cy82c693_ide_init);
528
529MODULE_AUTHOR("Andreas Krebs, Andre Hedrick");
530MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE");
531MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/generic.c b/drivers/ide/pci/generic.c
new file mode 100644
index 000000000000..4565cc311ff3
--- /dev/null
+++ b/drivers/ide/pci/generic.c
@@ -0,0 +1,232 @@
1/*
2 * linux/drivers/ide/pci/generic.c Version 0.11 December 30, 2002
3 *
4 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
5 * Portions (C) Copyright 2002 Red Hat Inc <alan@redhat.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2, or (at your option) any
10 * later version.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * For the avoidance of doubt the "preferred form" of this code is one which
18 * is in an open non patent encumbered format. Where cryptographic key signing
19 * forms part of the process of creating an executable the information
20 * including keys needed to generate an equivalently functional executable
21 * are deemed to be part of the source code.
22 */
23
24#undef REALLY_SLOW_IO /* most systems can safely undef this */
25
26#include <linux/config.h> /* for CONFIG_BLK_DEV_IDEPCI */
27#include <linux/types.h>
28#include <linux/module.h>
29#include <linux/kernel.h>
30#include <linux/delay.h>
31#include <linux/timer.h>
32#include <linux/mm.h>
33#include <linux/ioport.h>
34#include <linux/blkdev.h>
35#include <linux/hdreg.h>
36#include <linux/pci.h>
37#include <linux/ide.h>
38#include <linux/init.h>
39
40#include <asm/io.h>
41
42static void __devinit init_hwif_generic (ide_hwif_t *hwif)
43{
44 switch(hwif->pci_dev->device) {
45 case PCI_DEVICE_ID_UMC_UM8673F:
46 case PCI_DEVICE_ID_UMC_UM8886A:
47 case PCI_DEVICE_ID_UMC_UM8886BF:
48 hwif->irq = hwif->channel ? 15 : 14;
49 break;
50 default:
51 break;
52 }
53
54 if (!(hwif->dma_base))
55 return;
56
57 hwif->atapi_dma = 1;
58 hwif->ultra_mask = 0x7f;
59 hwif->mwdma_mask = 0x07;
60 hwif->swdma_mask = 0x07;
61
62 if (!noautodma)
63 hwif->autodma = 1;
64 hwif->drives[0].autodma = hwif->autodma;
65 hwif->drives[1].autodma = hwif->autodma;
66}
67
68#if 0
69 /* Logic to add back later on */
70
71 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
72 ide_pci_device_t *unknown = unknown_chipset;
73 init_setup_unknown(dev, unknown);
74 return 1;
75 }
76 return 0;
77#endif
78
79static ide_pci_device_t generic_chipsets[] __devinitdata = {
80 { /* 0 */
81 .name = "NS87410",
82 .init_hwif = init_hwif_generic,
83 .channels = 2,
84 .autodma = AUTODMA,
85 .enablebits = {{0x43,0x08,0x08}, {0x47,0x08,0x08}},
86 .bootable = ON_BOARD,
87 },{ /* 1 */
88 .name = "SAMURAI",
89 .init_hwif = init_hwif_generic,
90 .channels = 2,
91 .autodma = AUTODMA,
92 .bootable = ON_BOARD,
93 },{ /* 2 */
94 .name = "HT6565",
95 .init_hwif = init_hwif_generic,
96 .channels = 2,
97 .autodma = AUTODMA,
98 .bootable = ON_BOARD,
99 },{ /* 3 */
100 .name = "UM8673F",
101 .init_hwif = init_hwif_generic,
102 .channels = 2,
103 .autodma = NODMA,
104 .bootable = ON_BOARD,
105 },{ /* 4 */
106 .name = "UM8886A",
107 .init_hwif = init_hwif_generic,
108 .channels = 2,
109 .autodma = NODMA,
110 .bootable = ON_BOARD,
111 },{ /* 5 */
112 .name = "UM8886BF",
113 .init_hwif = init_hwif_generic,
114 .channels = 2,
115 .autodma = NODMA,
116 .bootable = ON_BOARD,
117 },{ /* 6 */
118 .name = "HINT_IDE",
119 .init_hwif = init_hwif_generic,
120 .channels = 2,
121 .autodma = AUTODMA,
122 .bootable = ON_BOARD,
123 },{ /* 7 */
124 .name = "VIA_IDE",
125 .init_hwif = init_hwif_generic,
126 .channels = 2,
127 .autodma = NOAUTODMA,
128 .bootable = ON_BOARD,
129 },{ /* 8 */
130 .name = "OPTI621V",
131 .init_hwif = init_hwif_generic,
132 .channels = 2,
133 .autodma = NOAUTODMA,
134 .bootable = ON_BOARD,
135 },{ /* 9 */
136 .name = "VIA8237SATA",
137 .init_hwif = init_hwif_generic,
138 .channels = 2,
139 .autodma = AUTODMA,
140 .bootable = OFF_BOARD,
141 },{ /* 10 */
142 .name = "Piccolo0102",
143 .init_hwif = init_hwif_generic,
144 .channels = 2,
145 .autodma = NOAUTODMA,
146 .bootable = ON_BOARD,
147 },{ /* 11 */
148 .name = "Piccolo0103",
149 .init_hwif = init_hwif_generic,
150 .channels = 2,
151 .autodma = NOAUTODMA,
152 .bootable = ON_BOARD,
153 },{ /* 12 */
154 .name = "Piccolo0105",
155 .init_hwif = init_hwif_generic,
156 .channels = 2,
157 .autodma = NOAUTODMA,
158 .bootable = ON_BOARD,
159 }
160};
161
162/**
163 * generic_init_one - called when a PIIX is found
164 * @dev: the generic device
165 * @id: the matching pci id
166 *
167 * Called when the PCI registration layer (or the IDE initialization)
168 * finds a device matching our IDE device tables.
169 */
170
171static int __devinit generic_init_one(struct pci_dev *dev, const struct pci_device_id *id)
172{
173 ide_pci_device_t *d = &generic_chipsets[id->driver_data];
174 u16 command;
175 int ret = -ENODEV;
176
177 if (dev->vendor == PCI_VENDOR_ID_UMC &&
178 dev->device == PCI_DEVICE_ID_UMC_UM8886A &&
179 (!(PCI_FUNC(dev->devfn) & 1)))
180 goto out; /* UM8886A/BF pair */
181
182 if (dev->vendor == PCI_VENDOR_ID_OPTI &&
183 dev->device == PCI_DEVICE_ID_OPTI_82C558 &&
184 (!(PCI_FUNC(dev->devfn) & 1)))
185 goto out;
186
187 pci_read_config_word(dev, PCI_COMMAND, &command);
188 if (!(command & PCI_COMMAND_IO)) {
189 printk(KERN_INFO "Skipping disabled %s IDE controller.\n", d->name);
190 goto out;
191 }
192 ret = ide_setup_pci_device(dev, d);
193out:
194 return ret;
195}
196
197static struct pci_device_id generic_pci_tbl[] = {
198 { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
199 { PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_SAMURAI_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
200 { PCI_VENDOR_ID_HOLTEK, PCI_DEVICE_ID_HOLTEK_6565, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
201 { PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8673F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
202 { PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
203 { PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
204 { PCI_VENDOR_ID_HINT, PCI_DEVICE_ID_HINT_VXPROII_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6},
205 { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C561, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7},
206 { PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C558, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8},
207#ifdef CONFIG_BLK_DEV_IDE_SATA
208 { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237_SATA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9},
209#endif
210 { PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10},
211 { PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11},
212 { PCI_VENDOR_ID_TOSHIBA,PCI_DEVICE_ID_TOSHIBA_PICCOLO_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12},
213 { 0, },
214};
215MODULE_DEVICE_TABLE(pci, generic_pci_tbl);
216
217static struct pci_driver driver = {
218 .name = "PCI_IDE",
219 .id_table = generic_pci_tbl,
220 .probe = generic_init_one,
221};
222
223static int generic_ide_init(void)
224{
225 return ide_pci_register_driver(&driver);
226}
227
228module_init(generic_ide_init);
229
230MODULE_AUTHOR("Andre Hedrick");
231MODULE_DESCRIPTION("PCI driver module for generic PCI IDE");
232MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/hpt34x.c b/drivers/ide/pci/hpt34x.c
new file mode 100644
index 000000000000..bbde46279984
--- /dev/null
+++ b/drivers/ide/pci/hpt34x.c
@@ -0,0 +1,278 @@
1/*
2 * linux/drivers/ide/pci/hpt34x.c Version 0.40 Sept 10, 2002
3 *
4 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
5 * May be copied or modified under the terms of the GNU General Public License
6 *
7 *
8 * 00:12.0 Unknown mass storage controller:
9 * Triones Technologies, Inc.
10 * Unknown device 0003 (rev 01)
11 *
12 * hde: UDMA 2 (0x0000 0x0002) (0x0000 0x0010)
13 * hdf: UDMA 2 (0x0002 0x0012) (0x0010 0x0030)
14 * hde: DMA 2 (0x0000 0x0002) (0x0000 0x0010)
15 * hdf: DMA 2 (0x0002 0x0012) (0x0010 0x0030)
16 * hdg: DMA 1 (0x0012 0x0052) (0x0030 0x0070)
17 * hdh: DMA 1 (0x0052 0x0252) (0x0070 0x00f0)
18 *
19 * ide-pci.c reference
20 *
21 * Since there are two cards that report almost identically,
22 * the only discernable difference is the values reported in pcicmd.
23 * Booting-BIOS card or HPT363 :: pcicmd == 0x07
24 * Non-bootable card or HPT343 :: pcicmd == 0x05
25 */
26
27#include <linux/config.h>
28#include <linux/module.h>
29#include <linux/types.h>
30#include <linux/kernel.h>
31#include <linux/delay.h>
32#include <linux/timer.h>
33#include <linux/mm.h>
34#include <linux/ioport.h>
35#include <linux/blkdev.h>
36#include <linux/hdreg.h>
37#include <linux/interrupt.h>
38#include <linux/pci.h>
39#include <linux/init.h>
40#include <linux/ide.h>
41
42#include <asm/io.h>
43#include <asm/irq.h>
44
45#define HPT343_DEBUG_DRIVE_INFO 0
46
47static u8 hpt34x_ratemask (ide_drive_t *drive)
48{
49 return 1;
50}
51
52static void hpt34x_clear_chipset (ide_drive_t *drive)
53{
54 struct pci_dev *dev = HWIF(drive)->pci_dev;
55 u32 reg1 = 0, tmp1 = 0, reg2 = 0, tmp2 = 0;
56
57 pci_read_config_dword(dev, 0x44, &reg1);
58 pci_read_config_dword(dev, 0x48, &reg2);
59 tmp1 = ((0x00 << (3*drive->dn)) | (reg1 & ~(7 << (3*drive->dn))));
60 tmp2 = (reg2 & ~(0x11 << drive->dn));
61 pci_write_config_dword(dev, 0x44, tmp1);
62 pci_write_config_dword(dev, 0x48, tmp2);
63}
64
65static int hpt34x_tune_chipset (ide_drive_t *drive, u8 xferspeed)
66{
67 struct pci_dev *dev = HWIF(drive)->pci_dev;
68 u8 speed = ide_rate_filter(hpt34x_ratemask(drive), xferspeed);
69 u32 reg1= 0, tmp1 = 0, reg2 = 0, tmp2 = 0;
70 u8 hi_speed, lo_speed;
71
72 hi_speed = speed >> 4;
73 lo_speed = speed & 0x0f;
74
75 if (hi_speed & 7) {
76 hi_speed = (hi_speed & 4) ? 0x01 : 0x10;
77 } else {
78 lo_speed <<= 5;
79 lo_speed >>= 5;
80 }
81
82 pci_read_config_dword(dev, 0x44, &reg1);
83 pci_read_config_dword(dev, 0x48, &reg2);
84 tmp1 = ((lo_speed << (3*drive->dn)) | (reg1 & ~(7 << (3*drive->dn))));
85 tmp2 = ((hi_speed << drive->dn) | reg2);
86 pci_write_config_dword(dev, 0x44, tmp1);
87 pci_write_config_dword(dev, 0x48, tmp2);
88
89#if HPT343_DEBUG_DRIVE_INFO
90 printk("%s: %s drive%d (0x%04x 0x%04x) (0x%04x 0x%04x)" \
91 " (0x%02x 0x%02x)\n",
92 drive->name, ide_xfer_verbose(speed),
93 drive->dn, reg1, tmp1, reg2, tmp2,
94 hi_speed, lo_speed);
95#endif /* HPT343_DEBUG_DRIVE_INFO */
96
97 return(ide_config_drive_speed(drive, speed));
98}
99
100static void hpt34x_tune_drive (ide_drive_t *drive, u8 pio)
101{
102 pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
103 hpt34x_clear_chipset(drive);
104 (void) hpt34x_tune_chipset(drive, (XFER_PIO_0 + pio));
105}
106
107/*
108 * This allows the configuration of ide_pci chipset registers
109 * for cards that learn about the drive's UDMA, DMA, PIO capabilities
110 * after the drive is reported by the OS. Initially for designed for
111 * HPT343 UDMA chipset by HighPoint|Triones Technologies, Inc.
112 */
113
114static int config_chipset_for_dma (ide_drive_t *drive)
115{
116 u8 speed = ide_dma_speed(drive, hpt34x_ratemask(drive));
117
118 if (!(speed))
119 return 0;
120
121 hpt34x_clear_chipset(drive);
122 (void) hpt34x_tune_chipset(drive, speed);
123 return ide_dma_enable(drive);
124}
125
126static int hpt34x_config_drive_xfer_rate (ide_drive_t *drive)
127{
128 ide_hwif_t *hwif = HWIF(drive);
129 struct hd_driveid *id = drive->id;
130
131 drive->init_speed = 0;
132
133 if (id && (id->capability & 1) && drive->autodma) {
134
135 if (ide_use_dma(drive)) {
136 if (config_chipset_for_dma(drive))
137#ifndef CONFIG_HPT34X_AUTODMA
138 return hwif->ide_dma_off_quietly(drive);
139#else
140 return hwif->ide_dma_on(drive);
141#endif
142 }
143
144 goto fast_ata_pio;
145
146 } else if ((id->capability & 8) || (id->field_valid & 2)) {
147fast_ata_pio:
148 hpt34x_tune_drive(drive, 255);
149 return hwif->ide_dma_off_quietly(drive);
150 }
151 /* IORDY not supported */
152 return 0;
153}
154
155/*
156 * If the BIOS does not set the IO base addaress to XX00, 343 will fail.
157 */
158#define HPT34X_PCI_INIT_REG 0x80
159
160static unsigned int __devinit init_chipset_hpt34x(struct pci_dev *dev, const char *name)
161{
162 int i = 0;
163 unsigned long hpt34xIoBase = pci_resource_start(dev, 4);
164 unsigned long hpt_addr[4] = { 0x20, 0x34, 0x28, 0x3c };
165 unsigned long hpt_addr_len[4] = { 7, 3, 7, 3 };
166 u16 cmd;
167 unsigned long flags;
168
169 local_irq_save(flags);
170
171 pci_write_config_byte(dev, HPT34X_PCI_INIT_REG, 0x00);
172 pci_read_config_word(dev, PCI_COMMAND, &cmd);
173
174 if (cmd & PCI_COMMAND_MEMORY) {
175 if (pci_resource_start(dev, PCI_ROM_RESOURCE)) {
176 pci_write_config_byte(dev, PCI_ROM_ADDRESS,
177 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
178 printk(KERN_INFO "HPT345: ROM enabled at 0x%08lx\n",
179 dev->resource[PCI_ROM_RESOURCE].start);
180 }
181 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
182 } else {
183 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
184 }
185
186 /*
187 * Since 20-23 can be assigned and are R/W, we correct them.
188 */
189 pci_write_config_word(dev, PCI_COMMAND, cmd & ~PCI_COMMAND_IO);
190 for(i=0; i<4; i++) {
191 dev->resource[i].start = (hpt34xIoBase + hpt_addr[i]);
192 dev->resource[i].end = dev->resource[i].start + hpt_addr_len[i];
193 dev->resource[i].flags = IORESOURCE_IO;
194 pci_write_config_dword(dev,
195 (PCI_BASE_ADDRESS_0 + (i * 4)),
196 dev->resource[i].start);
197 }
198 pci_write_config_word(dev, PCI_COMMAND, cmd);
199
200 local_irq_restore(flags);
201
202 return dev->irq;
203}
204
205static void __devinit init_hwif_hpt34x(ide_hwif_t *hwif)
206{
207 u16 pcicmd = 0;
208
209 hwif->autodma = 0;
210
211 hwif->tuneproc = &hpt34x_tune_drive;
212 hwif->speedproc = &hpt34x_tune_chipset;
213 hwif->no_dsc = 1;
214 hwif->drives[0].autotune = 1;
215 hwif->drives[1].autotune = 1;
216
217 pci_read_config_word(hwif->pci_dev, PCI_COMMAND, &pcicmd);
218
219 if (!hwif->dma_base)
220 return;
221
222 hwif->ultra_mask = 0x07;
223 hwif->mwdma_mask = 0x07;
224 hwif->swdma_mask = 0x07;
225
226 hwif->ide_dma_check = &hpt34x_config_drive_xfer_rate;
227 if (!noautodma)
228 hwif->autodma = (pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0;
229 hwif->drives[0].autodma = hwif->autodma;
230 hwif->drives[1].autodma = hwif->autodma;
231}
232
233static ide_pci_device_t hpt34x_chipset __devinitdata = {
234 .name = "HPT34X",
235 .init_chipset = init_chipset_hpt34x,
236 .init_hwif = init_hwif_hpt34x,
237 .channels = 2,
238 .autodma = NOAUTODMA,
239 .bootable = NEVER_BOARD,
240 .extra = 16
241};
242
243static int __devinit hpt34x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
244{
245 ide_pci_device_t *d = &hpt34x_chipset;
246 static char *chipset_names[] = {"HPT343", "HPT345"};
247 u16 pcicmd = 0;
248
249 pci_read_config_word(dev, PCI_COMMAND, &pcicmd);
250
251 d->name = chipset_names[(pcicmd & PCI_COMMAND_MEMORY) ? 1 : 0];
252 d->bootable = (pcicmd & PCI_COMMAND_MEMORY) ? OFF_BOARD : NEVER_BOARD;
253
254 return ide_setup_pci_device(dev, d);
255}
256
257static struct pci_device_id hpt34x_pci_tbl[] = {
258 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT343, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
259 { 0, },
260};
261MODULE_DEVICE_TABLE(pci, hpt34x_pci_tbl);
262
263static struct pci_driver driver = {
264 .name = "HPT34x_IDE",
265 .id_table = hpt34x_pci_tbl,
266 .probe = hpt34x_init_one,
267};
268
269static int hpt34x_ide_init(void)
270{
271 return ide_pci_register_driver(&driver);
272}
273
274module_init(hpt34x_ide_init);
275
276MODULE_AUTHOR("Andre Hedrick");
277MODULE_DESCRIPTION("PCI driver module for Highpoint 34x IDE");
278MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/hpt366.c b/drivers/ide/pci/hpt366.c
new file mode 100644
index 000000000000..c8ee0b8c0292
--- /dev/null
+++ b/drivers/ide/pci/hpt366.c
@@ -0,0 +1,1745 @@
1/*
2 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
3 *
4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
5 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
6 * Portions Copyright (C) 2003 Red Hat Inc
7 *
8 * Thanks to HighPoint Technologies for their assistance, and hardware.
9 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
10 * donation of an ABit BP6 mainboard, processor, and memory acellerated
11 * development and support.
12 *
13 * Note that final HPT370 support was done by force extraction of GPL.
14 *
15 * - add function for getting/setting power status of drive
16 * - the HPT370's state machine can get confused. reset it before each dma
17 * xfer to prevent that from happening.
18 * - reset state engine whenever we get an error.
19 * - check for busmaster state at end of dma.
20 * - use new highpoint timings.
21 * - detect bus speed using highpoint register.
22 * - use pll if we don't have a clock table. added a 66MHz table that's
23 * just 2x the 33MHz table.
24 * - removed turnaround. NOTE: we never want to switch between pll and
25 * pci clocks as the chip can glitch in those cases. the highpoint
26 * approved workaround slows everything down too much to be useful. in
27 * addition, we would have to serialize access to each chip.
28 * Adrian Sun <a.sun@sun.com>
29 *
30 * add drive timings for 66MHz PCI bus,
31 * fix ATA Cable signal detection, fix incorrect /proc info
32 * add /proc display for per-drive PIO/DMA/UDMA mode and
33 * per-channel ATA-33/66 Cable detect.
34 * Duncan Laurie <void@sun.com>
35 *
36 * fixup /proc output for multiple controllers
37 * Tim Hockin <thockin@sun.com>
38 *
39 * On hpt366:
40 * Reset the hpt366 on error, reset on dma
41 * Fix disabling Fast Interrupt hpt366.
42 * Mike Waychison <crlf@sun.com>
43 *
44 * Added support for 372N clocking and clock switching. The 372N needs
45 * different clocks on read/write. This requires overloading rw_disk and
46 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
47 * keeping me sane.
48 * Alan Cox <alan@redhat.com>
49 *
50 */
51
52
53#include <linux/config.h>
54#include <linux/types.h>
55#include <linux/module.h>
56#include <linux/kernel.h>
57#include <linux/delay.h>
58#include <linux/timer.h>
59#include <linux/mm.h>
60#include <linux/ioport.h>
61#include <linux/blkdev.h>
62#include <linux/hdreg.h>
63
64#include <linux/interrupt.h>
65#include <linux/pci.h>
66#include <linux/init.h>
67#include <linux/ide.h>
68
69#include <asm/uaccess.h>
70#include <asm/io.h>
71#include <asm/irq.h>
72
73/* various tuning parameters */
74#define HPT_RESET_STATE_ENGINE
75#undef HPT_DELAY_INTERRUPT
76#undef HPT_SERIALIZE_IO
77
78static const char *quirk_drives[] = {
79 "QUANTUM FIREBALLlct08 08",
80 "QUANTUM FIREBALLP KA6.4",
81 "QUANTUM FIREBALLP LM20.4",
82 "QUANTUM FIREBALLP LM20.5",
83 NULL
84};
85
86static const char *bad_ata100_5[] = {
87 "IBM-DTLA-307075",
88 "IBM-DTLA-307060",
89 "IBM-DTLA-307045",
90 "IBM-DTLA-307030",
91 "IBM-DTLA-307020",
92 "IBM-DTLA-307015",
93 "IBM-DTLA-305040",
94 "IBM-DTLA-305030",
95 "IBM-DTLA-305020",
96 "IC35L010AVER07-0",
97 "IC35L020AVER07-0",
98 "IC35L030AVER07-0",
99 "IC35L040AVER07-0",
100 "IC35L060AVER07-0",
101 "WDC AC310200R",
102 NULL
103};
104
105static const char *bad_ata66_4[] = {
106 "IBM-DTLA-307075",
107 "IBM-DTLA-307060",
108 "IBM-DTLA-307045",
109 "IBM-DTLA-307030",
110 "IBM-DTLA-307020",
111 "IBM-DTLA-307015",
112 "IBM-DTLA-305040",
113 "IBM-DTLA-305030",
114 "IBM-DTLA-305020",
115 "IC35L010AVER07-0",
116 "IC35L020AVER07-0",
117 "IC35L030AVER07-0",
118 "IC35L040AVER07-0",
119 "IC35L060AVER07-0",
120 "WDC AC310200R",
121 NULL
122};
123
124static const char *bad_ata66_3[] = {
125 "WDC AC310200R",
126 NULL
127};
128
129static const char *bad_ata33[] = {
130 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
131 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
132 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
133 "Maxtor 90510D4",
134 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
135 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
136 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
137 NULL
138};
139
140struct chipset_bus_clock_list_entry {
141 u8 xfer_speed;
142 unsigned int chipset_settings;
143};
144
145/* key for bus clock timings
146 * bit
147 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
148 * DMA. cycles = value + 1
149 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
150 * DMA. cycles = value + 1
151 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
152 * register access.
153 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
154 * register access.
155 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
156 * during task file register access.
157 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
158 * xfer.
159 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
160 * register access.
161 * 28 UDMA enable
162 * 29 DMA enable
163 * 30 PIO_MST enable. if set, the chip is in bus master mode during
164 * PIO.
165 * 31 FIFO enable.
166 */
167static struct chipset_bus_clock_list_entry forty_base_hpt366[] = {
168 { XFER_UDMA_4, 0x900fd943 },
169 { XFER_UDMA_3, 0x900ad943 },
170 { XFER_UDMA_2, 0x900bd943 },
171 { XFER_UDMA_1, 0x9008d943 },
172 { XFER_UDMA_0, 0x9008d943 },
173
174 { XFER_MW_DMA_2, 0xa008d943 },
175 { XFER_MW_DMA_1, 0xa010d955 },
176 { XFER_MW_DMA_0, 0xa010d9fc },
177
178 { XFER_PIO_4, 0xc008d963 },
179 { XFER_PIO_3, 0xc010d974 },
180 { XFER_PIO_2, 0xc010d997 },
181 { XFER_PIO_1, 0xc010d9c7 },
182 { XFER_PIO_0, 0xc018d9d9 },
183 { 0, 0x0120d9d9 }
184};
185
186static struct chipset_bus_clock_list_entry thirty_three_base_hpt366[] = {
187 { XFER_UDMA_4, 0x90c9a731 },
188 { XFER_UDMA_3, 0x90cfa731 },
189 { XFER_UDMA_2, 0x90caa731 },
190 { XFER_UDMA_1, 0x90cba731 },
191 { XFER_UDMA_0, 0x90c8a731 },
192
193 { XFER_MW_DMA_2, 0xa0c8a731 },
194 { XFER_MW_DMA_1, 0xa0c8a732 }, /* 0xa0c8a733 */
195 { XFER_MW_DMA_0, 0xa0c8a797 },
196
197 { XFER_PIO_4, 0xc0c8a731 },
198 { XFER_PIO_3, 0xc0c8a742 },
199 { XFER_PIO_2, 0xc0d0a753 },
200 { XFER_PIO_1, 0xc0d0a7a3 }, /* 0xc0d0a793 */
201 { XFER_PIO_0, 0xc0d0a7aa }, /* 0xc0d0a7a7 */
202 { 0, 0x0120a7a7 }
203};
204
205static struct chipset_bus_clock_list_entry twenty_five_base_hpt366[] = {
206 { XFER_UDMA_4, 0x90c98521 },
207 { XFER_UDMA_3, 0x90cf8521 },
208 { XFER_UDMA_2, 0x90cf8521 },
209 { XFER_UDMA_1, 0x90cb8521 },
210 { XFER_UDMA_0, 0x90cb8521 },
211
212 { XFER_MW_DMA_2, 0xa0ca8521 },
213 { XFER_MW_DMA_1, 0xa0ca8532 },
214 { XFER_MW_DMA_0, 0xa0ca8575 },
215
216 { XFER_PIO_4, 0xc0ca8521 },
217 { XFER_PIO_3, 0xc0ca8532 },
218 { XFER_PIO_2, 0xc0ca8542 },
219 { XFER_PIO_1, 0xc0d08572 },
220 { XFER_PIO_0, 0xc0d08585 },
221 { 0, 0x01208585 }
222};
223
224/* from highpoint documentation. these are old values */
225static struct chipset_bus_clock_list_entry thirty_three_base_hpt370[] = {
226/* { XFER_UDMA_5, 0x1A85F442, 0x16454e31 }, */
227 { XFER_UDMA_5, 0x16454e31 },
228 { XFER_UDMA_4, 0x16454e31 },
229 { XFER_UDMA_3, 0x166d4e31 },
230 { XFER_UDMA_2, 0x16494e31 },
231 { XFER_UDMA_1, 0x164d4e31 },
232 { XFER_UDMA_0, 0x16514e31 },
233
234 { XFER_MW_DMA_2, 0x26514e21 },
235 { XFER_MW_DMA_1, 0x26514e33 },
236 { XFER_MW_DMA_0, 0x26514e97 },
237
238 { XFER_PIO_4, 0x06514e21 },
239 { XFER_PIO_3, 0x06514e22 },
240 { XFER_PIO_2, 0x06514e33 },
241 { XFER_PIO_1, 0x06914e43 },
242 { XFER_PIO_0, 0x06914e57 },
243 { 0, 0x06514e57 }
244};
245
246static struct chipset_bus_clock_list_entry sixty_six_base_hpt370[] = {
247 { XFER_UDMA_5, 0x14846231 },
248 { XFER_UDMA_4, 0x14886231 },
249 { XFER_UDMA_3, 0x148c6231 },
250 { XFER_UDMA_2, 0x148c6231 },
251 { XFER_UDMA_1, 0x14906231 },
252 { XFER_UDMA_0, 0x14986231 },
253
254 { XFER_MW_DMA_2, 0x26514e21 },
255 { XFER_MW_DMA_1, 0x26514e33 },
256 { XFER_MW_DMA_0, 0x26514e97 },
257
258 { XFER_PIO_4, 0x06514e21 },
259 { XFER_PIO_3, 0x06514e22 },
260 { XFER_PIO_2, 0x06514e33 },
261 { XFER_PIO_1, 0x06914e43 },
262 { XFER_PIO_0, 0x06914e57 },
263 { 0, 0x06514e57 }
264};
265
266/* these are the current (4 sep 2001) timings from highpoint */
267static struct chipset_bus_clock_list_entry thirty_three_base_hpt370a[] = {
268 { XFER_UDMA_5, 0x12446231 },
269 { XFER_UDMA_4, 0x12446231 },
270 { XFER_UDMA_3, 0x126c6231 },
271 { XFER_UDMA_2, 0x12486231 },
272 { XFER_UDMA_1, 0x124c6233 },
273 { XFER_UDMA_0, 0x12506297 },
274
275 { XFER_MW_DMA_2, 0x22406c31 },
276 { XFER_MW_DMA_1, 0x22406c33 },
277 { XFER_MW_DMA_0, 0x22406c97 },
278
279 { XFER_PIO_4, 0x06414e31 },
280 { XFER_PIO_3, 0x06414e42 },
281 { XFER_PIO_2, 0x06414e53 },
282 { XFER_PIO_1, 0x06814e93 },
283 { XFER_PIO_0, 0x06814ea7 },
284 { 0, 0x06814ea7 }
285};
286
287/* 2x 33MHz timings */
288static struct chipset_bus_clock_list_entry sixty_six_base_hpt370a[] = {
289 { XFER_UDMA_5, 0x1488e673 },
290 { XFER_UDMA_4, 0x1488e673 },
291 { XFER_UDMA_3, 0x1498e673 },
292 { XFER_UDMA_2, 0x1490e673 },
293 { XFER_UDMA_1, 0x1498e677 },
294 { XFER_UDMA_0, 0x14a0e73f },
295
296 { XFER_MW_DMA_2, 0x2480fa73 },
297 { XFER_MW_DMA_1, 0x2480fa77 },
298 { XFER_MW_DMA_0, 0x2480fb3f },
299
300 { XFER_PIO_4, 0x0c82be73 },
301 { XFER_PIO_3, 0x0c82be95 },
302 { XFER_PIO_2, 0x0c82beb7 },
303 { XFER_PIO_1, 0x0d02bf37 },
304 { XFER_PIO_0, 0x0d02bf5f },
305 { 0, 0x0d02bf5f }
306};
307
308static struct chipset_bus_clock_list_entry fifty_base_hpt370a[] = {
309 { XFER_UDMA_5, 0x12848242 },
310 { XFER_UDMA_4, 0x12ac8242 },
311 { XFER_UDMA_3, 0x128c8242 },
312 { XFER_UDMA_2, 0x120c8242 },
313 { XFER_UDMA_1, 0x12148254 },
314 { XFER_UDMA_0, 0x121882ea },
315
316 { XFER_MW_DMA_2, 0x22808242 },
317 { XFER_MW_DMA_1, 0x22808254 },
318 { XFER_MW_DMA_0, 0x228082ea },
319
320 { XFER_PIO_4, 0x0a81f442 },
321 { XFER_PIO_3, 0x0a81f443 },
322 { XFER_PIO_2, 0x0a81f454 },
323 { XFER_PIO_1, 0x0ac1f465 },
324 { XFER_PIO_0, 0x0ac1f48a },
325 { 0, 0x0ac1f48a }
326};
327
328static struct chipset_bus_clock_list_entry thirty_three_base_hpt372[] = {
329 { XFER_UDMA_6, 0x1c81dc62 },
330 { XFER_UDMA_5, 0x1c6ddc62 },
331 { XFER_UDMA_4, 0x1c8ddc62 },
332 { XFER_UDMA_3, 0x1c8edc62 }, /* checkme */
333 { XFER_UDMA_2, 0x1c91dc62 },
334 { XFER_UDMA_1, 0x1c9adc62 }, /* checkme */
335 { XFER_UDMA_0, 0x1c82dc62 }, /* checkme */
336
337 { XFER_MW_DMA_2, 0x2c829262 },
338 { XFER_MW_DMA_1, 0x2c829266 }, /* checkme */
339 { XFER_MW_DMA_0, 0x2c82922e }, /* checkme */
340
341 { XFER_PIO_4, 0x0c829c62 },
342 { XFER_PIO_3, 0x0c829c84 },
343 { XFER_PIO_2, 0x0c829ca6 },
344 { XFER_PIO_1, 0x0d029d26 },
345 { XFER_PIO_0, 0x0d029d5e },
346 { 0, 0x0d029d5e }
347};
348
349static struct chipset_bus_clock_list_entry fifty_base_hpt372[] = {
350 { XFER_UDMA_5, 0x12848242 },
351 { XFER_UDMA_4, 0x12ac8242 },
352 { XFER_UDMA_3, 0x128c8242 },
353 { XFER_UDMA_2, 0x120c8242 },
354 { XFER_UDMA_1, 0x12148254 },
355 { XFER_UDMA_0, 0x121882ea },
356
357 { XFER_MW_DMA_2, 0x22808242 },
358 { XFER_MW_DMA_1, 0x22808254 },
359 { XFER_MW_DMA_0, 0x228082ea },
360
361 { XFER_PIO_4, 0x0a81f442 },
362 { XFER_PIO_3, 0x0a81f443 },
363 { XFER_PIO_2, 0x0a81f454 },
364 { XFER_PIO_1, 0x0ac1f465 },
365 { XFER_PIO_0, 0x0ac1f48a },
366 { 0, 0x0a81f443 }
367};
368
369static struct chipset_bus_clock_list_entry sixty_six_base_hpt372[] = {
370 { XFER_UDMA_6, 0x1c869c62 },
371 { XFER_UDMA_5, 0x1cae9c62 },
372 { XFER_UDMA_4, 0x1c8a9c62 },
373 { XFER_UDMA_3, 0x1c8e9c62 },
374 { XFER_UDMA_2, 0x1c929c62 },
375 { XFER_UDMA_1, 0x1c9a9c62 },
376 { XFER_UDMA_0, 0x1c829c62 },
377
378 { XFER_MW_DMA_2, 0x2c829c62 },
379 { XFER_MW_DMA_1, 0x2c829c66 },
380 { XFER_MW_DMA_0, 0x2c829d2e },
381
382 { XFER_PIO_4, 0x0c829c62 },
383 { XFER_PIO_3, 0x0c829c84 },
384 { XFER_PIO_2, 0x0c829ca6 },
385 { XFER_PIO_1, 0x0d029d26 },
386 { XFER_PIO_0, 0x0d029d5e },
387 { 0, 0x0d029d26 }
388};
389
390static struct chipset_bus_clock_list_entry thirty_three_base_hpt374[] = {
391 { XFER_UDMA_6, 0x12808242 },
392 { XFER_UDMA_5, 0x12848242 },
393 { XFER_UDMA_4, 0x12ac8242 },
394 { XFER_UDMA_3, 0x128c8242 },
395 { XFER_UDMA_2, 0x120c8242 },
396 { XFER_UDMA_1, 0x12148254 },
397 { XFER_UDMA_0, 0x121882ea },
398
399 { XFER_MW_DMA_2, 0x22808242 },
400 { XFER_MW_DMA_1, 0x22808254 },
401 { XFER_MW_DMA_0, 0x228082ea },
402
403 { XFER_PIO_4, 0x0a81f442 },
404 { XFER_PIO_3, 0x0a81f443 },
405 { XFER_PIO_2, 0x0a81f454 },
406 { XFER_PIO_1, 0x0ac1f465 },
407 { XFER_PIO_0, 0x0ac1f48a },
408 { 0, 0x06814e93 }
409};
410
411/* FIXME: 50MHz timings for HPT374 */
412
413#if 0
414static struct chipset_bus_clock_list_entry sixty_six_base_hpt374[] = {
415 { XFER_UDMA_6, 0x12406231 }, /* checkme */
416 { XFER_UDMA_5, 0x12446231 }, /* 0x14846231 */
417 { XFER_UDMA_4, 0x16814ea7 }, /* 0x14886231 */
418 { XFER_UDMA_3, 0x16814ea7 }, /* 0x148c6231 */
419 { XFER_UDMA_2, 0x16814ea7 }, /* 0x148c6231 */
420 { XFER_UDMA_1, 0x16814ea7 }, /* 0x14906231 */
421 { XFER_UDMA_0, 0x16814ea7 }, /* 0x14986231 */
422 { XFER_MW_DMA_2, 0x16814ea7 }, /* 0x26514e21 */
423 { XFER_MW_DMA_1, 0x16814ea7 }, /* 0x26514e97 */
424 { XFER_MW_DMA_0, 0x16814ea7 }, /* 0x26514e97 */
425 { XFER_PIO_4, 0x06814ea7 }, /* 0x06514e21 */
426 { XFER_PIO_3, 0x06814ea7 }, /* 0x06514e22 */
427 { XFER_PIO_2, 0x06814ea7 }, /* 0x06514e33 */
428 { XFER_PIO_1, 0x06814ea7 }, /* 0x06914e43 */
429 { XFER_PIO_0, 0x06814ea7 }, /* 0x06914e57 */
430 { 0, 0x06814ea7 }
431};
432#endif
433
434#define HPT366_DEBUG_DRIVE_INFO 0
435#define HPT374_ALLOW_ATA133_6 0
436#define HPT371_ALLOW_ATA133_6 0
437#define HPT302_ALLOW_ATA133_6 0
438#define HPT372_ALLOW_ATA133_6 1
439#define HPT370_ALLOW_ATA100_5 1
440#define HPT366_ALLOW_ATA66_4 1
441#define HPT366_ALLOW_ATA66_3 1
442#define HPT366_MAX_DEVS 8
443
444#define F_LOW_PCI_33 0x23
445#define F_LOW_PCI_40 0x29
446#define F_LOW_PCI_50 0x2d
447#define F_LOW_PCI_66 0x42
448
449/* FIXME: compare with driver's code before removing */
450#if 0
451 if (hpt_minimum_revision(dev, 3)) {
452 u8 cbl;
453 cbl = inb(iobase + 0x7b);
454 outb(cbl | 1, iobase + 0x7b);
455 outb(cbl & ~1, iobase + 0x7b);
456 cbl = inb(iobase + 0x7a);
457 p += sprintf(p, "Cable: ATA-%d"
458 " ATA-%d\n",
459 (cbl & 0x02) ? 33 : 66,
460 (cbl & 0x01) ? 33 : 66);
461 p += sprintf(p, "\n");
462 }
463 {
464 u8 c2, c3;
465 /* older revs don't have these registers mapped
466 * into io space */
467 pci_read_config_byte(dev, 0x43, &c0);
468 pci_read_config_byte(dev, 0x47, &c1);
469 pci_read_config_byte(dev, 0x4b, &c2);
470 pci_read_config_byte(dev, 0x4f, &c3);
471
472 p += sprintf(p, "Mode: %s %s"
473 " %s %s\n",
474 (c0 & 0x10) ? "UDMA" : (c0 & 0x20) ? "DMA " :
475 (c0 & 0x80) ? "PIO " : "off ",
476 (c1 & 0x10) ? "UDMA" : (c1 & 0x20) ? "DMA " :
477 (c1 & 0x80) ? "PIO " : "off ",
478 (c2 & 0x10) ? "UDMA" : (c2 & 0x20) ? "DMA " :
479 (c2 & 0x80) ? "PIO " : "off ",
480 (c3 & 0x10) ? "UDMA" : (c3 & 0x20) ? "DMA " :
481 (c3 & 0x80) ? "PIO " : "off ");
482 }
483 }
484#endif
485
486static u32 hpt_revision (struct pci_dev *dev)
487{
488 u32 class_rev;
489 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
490 class_rev &= 0xff;
491
492 switch(dev->device) {
493 /* Remap new 372N onto 372 */
494 case PCI_DEVICE_ID_TTI_HPT372N:
495 class_rev = PCI_DEVICE_ID_TTI_HPT372; break;
496 case PCI_DEVICE_ID_TTI_HPT374:
497 class_rev = PCI_DEVICE_ID_TTI_HPT374; break;
498 case PCI_DEVICE_ID_TTI_HPT371:
499 class_rev = PCI_DEVICE_ID_TTI_HPT371; break;
500 case PCI_DEVICE_ID_TTI_HPT302:
501 class_rev = PCI_DEVICE_ID_TTI_HPT302; break;
502 case PCI_DEVICE_ID_TTI_HPT372:
503 class_rev = PCI_DEVICE_ID_TTI_HPT372; break;
504 default:
505 break;
506 }
507 return class_rev;
508}
509
510static u32 hpt_minimum_revision (struct pci_dev *dev, int revision)
511{
512 unsigned int class_rev = hpt_revision(dev);
513 revision--;
514 return ((int) (class_rev > revision) ? 1 : 0);
515}
516
517static int check_in_drive_lists(ide_drive_t *drive, const char **list);
518
519static u8 hpt3xx_ratemask (ide_drive_t *drive)
520{
521 struct pci_dev *dev = HWIF(drive)->pci_dev;
522 u8 mode = 0;
523
524 if (hpt_minimum_revision(dev, 8)) { /* HPT374 */
525 mode = (HPT374_ALLOW_ATA133_6) ? 4 : 3;
526 } else if (hpt_minimum_revision(dev, 7)) { /* HPT371 */
527 mode = (HPT371_ALLOW_ATA133_6) ? 4 : 3;
528 } else if (hpt_minimum_revision(dev, 6)) { /* HPT302 */
529 mode = (HPT302_ALLOW_ATA133_6) ? 4 : 3;
530 } else if (hpt_minimum_revision(dev, 5)) { /* HPT372 */
531 mode = (HPT372_ALLOW_ATA133_6) ? 4 : 3;
532 } else if (hpt_minimum_revision(dev, 4)) { /* HPT370A */
533 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
534 } else if (hpt_minimum_revision(dev, 3)) { /* HPT370 */
535 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
536 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : mode;
537 } else { /* HPT366 and HPT368 */
538 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : 2;
539 }
540 if (!eighty_ninty_three(drive) && (mode))
541 mode = min(mode, (u8)1);
542 return mode;
543}
544
545/*
546 * Note for the future; the SATA hpt37x we must set
547 * either PIO or UDMA modes 0,4,5
548 */
549
550static u8 hpt3xx_ratefilter (ide_drive_t *drive, u8 speed)
551{
552 struct pci_dev *dev = HWIF(drive)->pci_dev;
553 u8 mode = hpt3xx_ratemask(drive);
554
555 if (drive->media != ide_disk)
556 return min(speed, (u8)XFER_PIO_4);
557
558 switch(mode) {
559 case 0x04:
560 speed = min(speed, (u8)XFER_UDMA_6);
561 break;
562 case 0x03:
563 speed = min(speed, (u8)XFER_UDMA_5);
564 if (hpt_minimum_revision(dev, 5))
565 break;
566 if (check_in_drive_lists(drive, bad_ata100_5))
567 speed = min(speed, (u8)XFER_UDMA_4);
568 break;
569 case 0x02:
570 speed = min(speed, (u8)XFER_UDMA_4);
571 /*
572 * CHECK ME, Does this need to be set to 5 ??
573 */
574 if (hpt_minimum_revision(dev, 3))
575 break;
576 if ((check_in_drive_lists(drive, bad_ata66_4)) ||
577 (!(HPT366_ALLOW_ATA66_4)))
578 speed = min(speed, (u8)XFER_UDMA_3);
579 if ((check_in_drive_lists(drive, bad_ata66_3)) ||
580 (!(HPT366_ALLOW_ATA66_3)))
581 speed = min(speed, (u8)XFER_UDMA_2);
582 break;
583 case 0x01:
584 speed = min(speed, (u8)XFER_UDMA_2);
585 /*
586 * CHECK ME, Does this need to be set to 5 ??
587 */
588 if (hpt_minimum_revision(dev, 3))
589 break;
590 if (check_in_drive_lists(drive, bad_ata33))
591 speed = min(speed, (u8)XFER_MW_DMA_2);
592 break;
593 case 0x00:
594 default:
595 speed = min(speed, (u8)XFER_MW_DMA_2);
596 break;
597 }
598 return speed;
599}
600
601static int check_in_drive_lists (ide_drive_t *drive, const char **list)
602{
603 struct hd_driveid *id = drive->id;
604
605 if (quirk_drives == list) {
606 while (*list)
607 if (strstr(id->model, *list++))
608 return 1;
609 } else {
610 while (*list)
611 if (!strcmp(*list++,id->model))
612 return 1;
613 }
614 return 0;
615}
616
617static unsigned int pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
618{
619 for ( ; chipset_table->xfer_speed ; chipset_table++)
620 if (chipset_table->xfer_speed == speed)
621 return chipset_table->chipset_settings;
622 return chipset_table->chipset_settings;
623}
624
625static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
626{
627 struct pci_dev *dev = HWIF(drive)->pci_dev;
628 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
629// u8 speed = ide_rate_filter(hpt3xx_ratemask(drive), xferspeed);
630 u8 regtime = (drive->select.b.unit & 0x01) ? 0x44 : 0x40;
631 u8 regfast = (HWIF(drive)->channel) ? 0x55 : 0x51;
632 u8 drive_fast = 0;
633 u32 reg1 = 0, reg2 = 0;
634
635 /*
636 * Disable the "fast interrupt" prediction.
637 */
638 pci_read_config_byte(dev, regfast, &drive_fast);
639#if 0
640 if (drive_fast & 0x02)
641 pci_write_config_byte(dev, regfast, drive_fast & ~0x20);
642#else
643 if (drive_fast & 0x80)
644 pci_write_config_byte(dev, regfast, drive_fast & ~0x80);
645#endif
646
647 reg2 = pci_bus_clock_list(speed,
648 (struct chipset_bus_clock_list_entry *) pci_get_drvdata(dev));
649 /*
650 * Disable on-chip PIO FIFO/buffer
651 * (to avoid problems handling I/O errors later)
652 */
653 pci_read_config_dword(dev, regtime, &reg1);
654 if (speed >= XFER_MW_DMA_0) {
655 reg2 = (reg2 & ~0xc0000000) | (reg1 & 0xc0000000);
656 } else {
657 reg2 = (reg2 & ~0x30070000) | (reg1 & 0x30070000);
658 }
659 reg2 &= ~0x80000000;
660
661 pci_write_config_dword(dev, regtime, reg2);
662
663 return ide_config_drive_speed(drive, speed);
664}
665
666static int hpt370_tune_chipset(ide_drive_t *drive, u8 xferspeed)
667{
668 struct pci_dev *dev = HWIF(drive)->pci_dev;
669 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
670// u8 speed = ide_rate_filter(hpt3xx_ratemask(drive), xferspeed);
671 u8 regfast = (HWIF(drive)->channel) ? 0x55 : 0x51;
672 u8 drive_pci = 0x40 + (drive->dn * 4);
673 u8 new_fast = 0, drive_fast = 0;
674 u32 list_conf = 0, drive_conf = 0;
675 u32 conf_mask = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
676
677 /*
678 * Disable the "fast interrupt" prediction.
679 * don't holdoff on interrupts. (== 0x01 despite what the docs say)
680 */
681 pci_read_config_byte(dev, regfast, &drive_fast);
682 new_fast = drive_fast;
683 if (new_fast & 0x02)
684 new_fast &= ~0x02;
685
686#ifdef HPT_DELAY_INTERRUPT
687 if (new_fast & 0x01)
688 new_fast &= ~0x01;
689#else
690 if ((new_fast & 0x01) == 0)
691 new_fast |= 0x01;
692#endif
693 if (new_fast != drive_fast)
694 pci_write_config_byte(dev, regfast, new_fast);
695
696 list_conf = pci_bus_clock_list(speed,
697 (struct chipset_bus_clock_list_entry *)
698 pci_get_drvdata(dev));
699
700 pci_read_config_dword(dev, drive_pci, &drive_conf);
701 list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
702
703 if (speed < XFER_MW_DMA_0) {
704 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
705 }
706
707 pci_write_config_dword(dev, drive_pci, list_conf);
708
709 return ide_config_drive_speed(drive, speed);
710}
711
712static int hpt372_tune_chipset(ide_drive_t *drive, u8 xferspeed)
713{
714 struct pci_dev *dev = HWIF(drive)->pci_dev;
715 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
716// u8 speed = ide_rate_filter(hpt3xx_ratemask(drive), xferspeed);
717 u8 regfast = (HWIF(drive)->channel) ? 0x55 : 0x51;
718 u8 drive_fast = 0, drive_pci = 0x40 + (drive->dn * 4);
719 u32 list_conf = 0, drive_conf = 0;
720 u32 conf_mask = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
721
722 /*
723 * Disable the "fast interrupt" prediction.
724 * don't holdoff on interrupts. (== 0x01 despite what the docs say)
725 */
726 pci_read_config_byte(dev, regfast, &drive_fast);
727 drive_fast &= ~0x07;
728 pci_write_config_byte(dev, regfast, drive_fast);
729
730 list_conf = pci_bus_clock_list(speed,
731 (struct chipset_bus_clock_list_entry *)
732 pci_get_drvdata(dev));
733 pci_read_config_dword(dev, drive_pci, &drive_conf);
734 list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
735 if (speed < XFER_MW_DMA_0)
736 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
737 pci_write_config_dword(dev, drive_pci, list_conf);
738
739 return ide_config_drive_speed(drive, speed);
740}
741
742static int hpt3xx_tune_chipset (ide_drive_t *drive, u8 speed)
743{
744 struct pci_dev *dev = HWIF(drive)->pci_dev;
745
746 if (hpt_minimum_revision(dev, 8))
747 return hpt372_tune_chipset(drive, speed); /* not a typo */
748#if 0
749 else if (hpt_minimum_revision(dev, 7))
750 hpt371_tune_chipset(drive, speed);
751 else if (hpt_minimum_revision(dev, 6))
752 hpt302_tune_chipset(drive, speed);
753#endif
754 else if (hpt_minimum_revision(dev, 5))
755 return hpt372_tune_chipset(drive, speed);
756 else if (hpt_minimum_revision(dev, 3))
757 return hpt370_tune_chipset(drive, speed);
758 else /* hpt368: hpt_minimum_revision(dev, 2) */
759 return hpt36x_tune_chipset(drive, speed);
760}
761
762static void hpt3xx_tune_drive (ide_drive_t *drive, u8 pio)
763{
764 pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
765 (void) hpt3xx_tune_chipset(drive, (XFER_PIO_0 + pio));
766}
767
768/*
769 * This allows the configuration of ide_pci chipset registers
770 * for cards that learn about the drive's UDMA, DMA, PIO capabilities
771 * after the drive is reported by the OS. Initially for designed for
772 * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
773 *
774 * check_in_drive_lists(drive, bad_ata66_4)
775 * check_in_drive_lists(drive, bad_ata66_3)
776 * check_in_drive_lists(drive, bad_ata33)
777 *
778 */
779static int config_chipset_for_dma (ide_drive_t *drive)
780{
781 u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive));
782
783 if (!(speed))
784 return 0;
785
786 (void) hpt3xx_tune_chipset(drive, speed);
787 return ide_dma_enable(drive);
788}
789
790static int hpt3xx_quirkproc (ide_drive_t *drive)
791{
792 return ((int) check_in_drive_lists(drive, quirk_drives));
793}
794
795static void hpt3xx_intrproc (ide_drive_t *drive)
796{
797 ide_hwif_t *hwif = HWIF(drive);
798
799 if (drive->quirk_list)
800 return;
801 /* drives in the quirk_list may not like intr setups/cleanups */
802 hwif->OUTB(drive->ctl|2, IDE_CONTROL_REG);
803}
804
805static void hpt3xx_maskproc (ide_drive_t *drive, int mask)
806{
807 struct pci_dev *dev = HWIF(drive)->pci_dev;
808
809 if (drive->quirk_list) {
810 if (hpt_minimum_revision(dev,3)) {
811 u8 reg5a = 0;
812 pci_read_config_byte(dev, 0x5a, &reg5a);
813 if (((reg5a & 0x10) >> 4) != mask)
814 pci_write_config_byte(dev, 0x5a, mask ? (reg5a | 0x10) : (reg5a & ~0x10));
815 } else {
816 if (mask) {
817 disable_irq(HWIF(drive)->irq);
818 } else {
819 enable_irq(HWIF(drive)->irq);
820 }
821 }
822 } else {
823 if (IDE_CONTROL_REG)
824 HWIF(drive)->OUTB(mask ? (drive->ctl | 2) :
825 (drive->ctl & ~2),
826 IDE_CONTROL_REG);
827 }
828}
829
830static int hpt366_config_drive_xfer_rate (ide_drive_t *drive)
831{
832 ide_hwif_t *hwif = HWIF(drive);
833 struct hd_driveid *id = drive->id;
834
835 drive->init_speed = 0;
836
837 if (id && (id->capability & 1) && drive->autodma) {
838
839 if (ide_use_dma(drive)) {
840 if (config_chipset_for_dma(drive))
841 return hwif->ide_dma_on(drive);
842 }
843
844 goto fast_ata_pio;
845
846 } else if ((id->capability & 8) || (id->field_valid & 2)) {
847fast_ata_pio:
848 hpt3xx_tune_drive(drive, 5);
849 return hwif->ide_dma_off_quietly(drive);
850 }
851 /* IORDY not supported */
852 return 0;
853}
854
855/*
856 * This is specific to the HPT366 UDMA bios chipset
857 * by HighPoint|Triones Technologies, Inc.
858 */
859static int hpt366_ide_dma_lostirq (ide_drive_t *drive)
860{
861 struct pci_dev *dev = HWIF(drive)->pci_dev;
862 u8 reg50h = 0, reg52h = 0, reg5ah = 0;
863
864 pci_read_config_byte(dev, 0x50, &reg50h);
865 pci_read_config_byte(dev, 0x52, &reg52h);
866 pci_read_config_byte(dev, 0x5a, &reg5ah);
867 printk("%s: (%s) reg50h=0x%02x, reg52h=0x%02x, reg5ah=0x%02x\n",
868 drive->name, __FUNCTION__, reg50h, reg52h, reg5ah);
869 if (reg5ah & 0x10)
870 pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
871#if 0
872 /* how about we flush and reset, mmmkay? */
873 pci_write_config_byte(dev, 0x51, 0x1F);
874 /* fall through to a reset */
875 case dma_start:
876 case ide_dma_end:
877 /* reset the chips state over and over.. */
878 pci_write_config_byte(dev, 0x51, 0x13);
879#endif
880 return __ide_dma_lostirq(drive);
881}
882
883static void hpt370_clear_engine (ide_drive_t *drive)
884{
885 u8 regstate = HWIF(drive)->channel ? 0x54 : 0x50;
886 pci_write_config_byte(HWIF(drive)->pci_dev, regstate, 0x37);
887 udelay(10);
888}
889
890static void hpt370_ide_dma_start(ide_drive_t *drive)
891{
892#ifdef HPT_RESET_STATE_ENGINE
893 hpt370_clear_engine(drive);
894#endif
895 ide_dma_start(drive);
896}
897
898static int hpt370_ide_dma_end (ide_drive_t *drive)
899{
900 ide_hwif_t *hwif = HWIF(drive);
901 u8 dma_stat = hwif->INB(hwif->dma_status);
902
903 if (dma_stat & 0x01) {
904 /* wait a little */
905 udelay(20);
906 dma_stat = hwif->INB(hwif->dma_status);
907 }
908 if ((dma_stat & 0x01) != 0)
909 /* fallthrough */
910 (void) HWIF(drive)->ide_dma_timeout(drive);
911
912 return __ide_dma_end(drive);
913}
914
915static void hpt370_lostirq_timeout (ide_drive_t *drive)
916{
917 ide_hwif_t *hwif = HWIF(drive);
918 u8 bfifo = 0, reginfo = hwif->channel ? 0x56 : 0x52;
919 u8 dma_stat = 0, dma_cmd = 0;
920
921 pci_read_config_byte(HWIF(drive)->pci_dev, reginfo, &bfifo);
922 printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
923 hpt370_clear_engine(drive);
924 /* get dma command mode */
925 dma_cmd = hwif->INB(hwif->dma_command);
926 /* stop dma */
927 hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
928 dma_stat = hwif->INB(hwif->dma_status);
929 /* clear errors */
930 hwif->OUTB(dma_stat | 0x6, hwif->dma_status);
931}
932
933static int hpt370_ide_dma_timeout (ide_drive_t *drive)
934{
935 hpt370_lostirq_timeout(drive);
936 hpt370_clear_engine(drive);
937 return __ide_dma_timeout(drive);
938}
939
940static int hpt370_ide_dma_lostirq (ide_drive_t *drive)
941{
942 hpt370_lostirq_timeout(drive);
943 hpt370_clear_engine(drive);
944 return __ide_dma_lostirq(drive);
945}
946
947/* returns 1 if DMA IRQ issued, 0 otherwise */
948static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
949{
950 ide_hwif_t *hwif = HWIF(drive);
951 u16 bfifo = 0;
952 u8 reginfo = hwif->channel ? 0x56 : 0x52;
953 u8 dma_stat;
954
955 pci_read_config_word(hwif->pci_dev, reginfo, &bfifo);
956 if (bfifo & 0x1FF) {
957// printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
958 return 0;
959 }
960
961 dma_stat = hwif->INB(hwif->dma_status);
962 /* return 1 if INTR asserted */
963 if ((dma_stat & 4) == 4)
964 return 1;
965
966 if (!drive->waiting_for_dma)
967 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
968 drive->name, __FUNCTION__);
969 return 0;
970}
971
972static int hpt374_ide_dma_end (ide_drive_t *drive)
973{
974 struct pci_dev *dev = HWIF(drive)->pci_dev;
975 ide_hwif_t *hwif = HWIF(drive);
976 u8 msc_stat = 0, mscreg = hwif->channel ? 0x54 : 0x50;
977 u8 bwsr_stat = 0, bwsr_mask = hwif->channel ? 0x02 : 0x01;
978
979 pci_read_config_byte(dev, 0x6a, &bwsr_stat);
980 pci_read_config_byte(dev, mscreg, &msc_stat);
981 if ((bwsr_stat & bwsr_mask) == bwsr_mask)
982 pci_write_config_byte(dev, mscreg, msc_stat|0x30);
983 return __ide_dma_end(drive);
984}
985
986/**
987 * hpt372n_set_clock - perform clock switching dance
988 * @drive: Drive to switch
989 * @mode: Switching mode (0x21 for write, 0x23 otherwise)
990 *
991 * Switch the DPLL clock on the HPT372N devices. This is a
992 * right mess.
993 */
994
995static void hpt372n_set_clock(ide_drive_t *drive, int mode)
996{
997 ide_hwif_t *hwif = HWIF(drive);
998
999 /* FIXME: should we check for DMA active and BUG() */
1000 /* Tristate the bus */
1001 outb(0x80, hwif->dma_base+0x73);
1002 outb(0x80, hwif->dma_base+0x77);
1003
1004 /* Switch clock and reset channels */
1005 outb(mode, hwif->dma_base+0x7B);
1006 outb(0xC0, hwif->dma_base+0x79);
1007
1008 /* Reset state machines */
1009 outb(0x37, hwif->dma_base+0x70);
1010 outb(0x37, hwif->dma_base+0x74);
1011
1012 /* Complete reset */
1013 outb(0x00, hwif->dma_base+0x79);
1014
1015 /* Reconnect channels to bus */
1016 outb(0x00, hwif->dma_base+0x73);
1017 outb(0x00, hwif->dma_base+0x77);
1018}
1019
1020/**
1021 * hpt372n_rw_disk - prepare for I/O
1022 * @drive: drive for command
1023 * @rq: block request structure
1024 *
1025 * This is called when a disk I/O is issued to the 372N.
1026 * We need it because of the clock switching.
1027 */
1028
1029static void hpt372n_rw_disk(ide_drive_t *drive, struct request *rq)
1030{
1031 ide_hwif_t *hwif = drive->hwif;
1032 int wantclock;
1033
1034 wantclock = rq_data_dir(rq) ? 0x23 : 0x21;
1035
1036 if (hwif->config_data != wantclock) {
1037 hpt372n_set_clock(drive, wantclock);
1038 hwif->config_data = wantclock;
1039 }
1040}
1041
1042/*
1043 * Since SUN Cobalt is attempting to do this operation, I should disclose
1044 * this has been a long time ago Thu Jul 27 16:40:57 2000 was the patch date
1045 * HOTSWAP ATA Infrastructure.
1046 */
1047
1048static void hpt3xx_reset (ide_drive_t *drive)
1049{
1050#if 0
1051 unsigned long high_16 = pci_resource_start(HWIF(drive)->pci_dev, 4);
1052 u8 reset = (HWIF(drive)->channel) ? 0x80 : 0x40;
1053 u8 reg59h = 0;
1054
1055 pci_read_config_byte(HWIF(drive)->pci_dev, 0x59, &reg59h);
1056 pci_write_config_byte(HWIF(drive)->pci_dev, 0x59, reg59h|reset);
1057 pci_write_config_byte(HWIF(drive)->pci_dev, 0x59, reg59h);
1058#endif
1059}
1060
1061static int hpt3xx_tristate (ide_drive_t * drive, int state)
1062{
1063 ide_hwif_t *hwif = HWIF(drive);
1064 struct pci_dev *dev = hwif->pci_dev;
1065 u8 reg59h = 0, reset = (hwif->channel) ? 0x80 : 0x40;
1066 u8 regXXh = 0, state_reg= (hwif->channel) ? 0x57 : 0x53;
1067
1068// hwif->bus_state = state;
1069
1070 pci_read_config_byte(dev, 0x59, &reg59h);
1071 pci_read_config_byte(dev, state_reg, &regXXh);
1072
1073 if (state) {
1074 (void) ide_do_reset(drive);
1075 pci_write_config_byte(dev, state_reg, regXXh|0x80);
1076 pci_write_config_byte(dev, 0x59, reg59h|reset);
1077 } else {
1078 pci_write_config_byte(dev, 0x59, reg59h & ~(reset));
1079 pci_write_config_byte(dev, state_reg, regXXh & ~(0x80));
1080 (void) ide_do_reset(drive);
1081 }
1082 return 0;
1083}
1084
1085/*
1086 * set/get power state for a drive.
1087 * turning the power off does the following things:
1088 * 1) soft-reset the drive
1089 * 2) tri-states the ide bus
1090 *
1091 * when we turn things back on, we need to re-initialize things.
1092 */
1093#define TRISTATE_BIT 0x8000
1094static int hpt370_busproc(ide_drive_t * drive, int state)
1095{
1096 ide_hwif_t *hwif = HWIF(drive);
1097 struct pci_dev *dev = hwif->pci_dev;
1098 u8 tristate = 0, resetmask = 0, bus_reg = 0;
1099 u16 tri_reg;
1100
1101 hwif->bus_state = state;
1102
1103 if (hwif->channel) {
1104 /* secondary channel */
1105 tristate = 0x56;
1106 resetmask = 0x80;
1107 } else {
1108 /* primary channel */
1109 tristate = 0x52;
1110 resetmask = 0x40;
1111 }
1112
1113 /* grab status */
1114 pci_read_config_word(dev, tristate, &tri_reg);
1115 pci_read_config_byte(dev, 0x59, &bus_reg);
1116
1117 /* set the state. we don't set it if we don't need to do so.
1118 * make sure that the drive knows that it has failed if it's off */
1119 switch (state) {
1120 case BUSSTATE_ON:
1121 hwif->drives[0].failures = 0;
1122 hwif->drives[1].failures = 0;
1123 if ((bus_reg & resetmask) == 0)
1124 return 0;
1125 tri_reg &= ~TRISTATE_BIT;
1126 bus_reg &= ~resetmask;
1127 break;
1128 case BUSSTATE_OFF:
1129 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
1130 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
1131 if ((tri_reg & TRISTATE_BIT) == 0 && (bus_reg & resetmask))
1132 return 0;
1133 tri_reg &= ~TRISTATE_BIT;
1134 bus_reg |= resetmask;
1135 break;
1136 case BUSSTATE_TRISTATE:
1137 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
1138 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
1139 if ((tri_reg & TRISTATE_BIT) && (bus_reg & resetmask))
1140 return 0;
1141 tri_reg |= TRISTATE_BIT;
1142 bus_reg |= resetmask;
1143 break;
1144 }
1145 pci_write_config_byte(dev, 0x59, bus_reg);
1146 pci_write_config_word(dev, tristate, tri_reg);
1147
1148 return 0;
1149}
1150
1151static int __devinit init_hpt37x(struct pci_dev *dev)
1152{
1153 int adjust, i;
1154 u16 freq;
1155 u32 pll;
1156 u8 reg5bh;
1157 u8 reg5ah = 0;
1158 unsigned long dmabase = pci_resource_start(dev, 4);
1159 u8 did, rid;
1160 int is_372n = 0;
1161
1162 pci_read_config_byte(dev, 0x5a, &reg5ah);
1163 /* interrupt force enable */
1164 pci_write_config_byte(dev, 0x5a, (reg5ah & ~0x10));
1165
1166 if(dmabase)
1167 {
1168 did = inb(dmabase + 0x22);
1169 rid = inb(dmabase + 0x28);
1170
1171 if((did == 4 && rid == 6) || (did == 5 && rid > 1))
1172 is_372n = 1;
1173 }
1174
1175 /*
1176 * default to pci clock. make sure MA15/16 are set to output
1177 * to prevent drives having problems with 40-pin cables.
1178 */
1179 pci_write_config_byte(dev, 0x5b, 0x23);
1180
1181 /*
1182 * set up the PLL. we need to adjust it so that it's stable.
1183 * freq = Tpll * 192 / Tpci
1184 *
1185 * Todo. For non x86 should probably check the dword is
1186 * set to 0xABCDExxx indicating the BIOS saved f_CNT
1187 */
1188 pci_read_config_word(dev, 0x78, &freq);
1189 freq &= 0x1FF;
1190
1191 /*
1192 * The 372N uses different PCI clock information and has
1193 * some other complications
1194 * On PCI33 timing we must clock switch
1195 * On PCI66 timing we must NOT use the PCI clock
1196 *
1197 * Currently we always set up the PLL for the 372N
1198 */
1199
1200 pci_set_drvdata(dev, NULL);
1201
1202 if(is_372n)
1203 {
1204 printk(KERN_INFO "hpt: HPT372N detected, using 372N timing.\n");
1205 if(freq < 0x55)
1206 pll = F_LOW_PCI_33;
1207 else if(freq < 0x70)
1208 pll = F_LOW_PCI_40;
1209 else if(freq < 0x7F)
1210 pll = F_LOW_PCI_50;
1211 else
1212 pll = F_LOW_PCI_66;
1213
1214 printk(KERN_INFO "FREQ: %d PLL: %d\n", freq, pll);
1215
1216 /* We always use the pll not the PCI clock on 372N */
1217 }
1218 else
1219 {
1220 if(freq < 0x9C)
1221 pll = F_LOW_PCI_33;
1222 else if(freq < 0xb0)
1223 pll = F_LOW_PCI_40;
1224 else if(freq <0xc8)
1225 pll = F_LOW_PCI_50;
1226 else
1227 pll = F_LOW_PCI_66;
1228
1229 if (pll == F_LOW_PCI_33) {
1230 if (hpt_minimum_revision(dev,8))
1231 pci_set_drvdata(dev, (void *) thirty_three_base_hpt374);
1232 else if (hpt_minimum_revision(dev,5))
1233 pci_set_drvdata(dev, (void *) thirty_three_base_hpt372);
1234 else if (hpt_minimum_revision(dev,4))
1235 pci_set_drvdata(dev, (void *) thirty_three_base_hpt370a);
1236 else
1237 pci_set_drvdata(dev, (void *) thirty_three_base_hpt370);
1238 printk("HPT37X: using 33MHz PCI clock\n");
1239 } else if (pll == F_LOW_PCI_40) {
1240 /* Unsupported */
1241 } else if (pll == F_LOW_PCI_50) {
1242 if (hpt_minimum_revision(dev,8))
1243 pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
1244 else if (hpt_minimum_revision(dev,5))
1245 pci_set_drvdata(dev, (void *) fifty_base_hpt372);
1246 else if (hpt_minimum_revision(dev,4))
1247 pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
1248 else
1249 pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
1250 printk("HPT37X: using 50MHz PCI clock\n");
1251 } else {
1252 if (hpt_minimum_revision(dev,8))
1253 {
1254 printk(KERN_ERR "HPT37x: 66MHz timings are not supported.\n");
1255 }
1256 else if (hpt_minimum_revision(dev,5))
1257 pci_set_drvdata(dev, (void *) sixty_six_base_hpt372);
1258 else if (hpt_minimum_revision(dev,4))
1259 pci_set_drvdata(dev, (void *) sixty_six_base_hpt370a);
1260 else
1261 pci_set_drvdata(dev, (void *) sixty_six_base_hpt370);
1262 printk("HPT37X: using 66MHz PCI clock\n");
1263 }
1264 }
1265
1266 /*
1267 * only try the pll if we don't have a table for the clock
1268 * speed that we're running at. NOTE: the internal PLL will
1269 * result in slow reads when using a 33MHz PCI clock. we also
1270 * don't like to use the PLL because it will cause glitches
1271 * on PRST/SRST when the HPT state engine gets reset.
1272 */
1273 if (pci_get_drvdata(dev))
1274 goto init_hpt37X_done;
1275
1276 /*
1277 * adjust PLL based upon PCI clock, enable it, and wait for
1278 * stabilization.
1279 */
1280 adjust = 0;
1281 freq = (pll < F_LOW_PCI_50) ? 2 : 4;
1282 while (adjust++ < 6) {
1283 pci_write_config_dword(dev, 0x5c, (freq + pll) << 16 |
1284 pll | 0x100);
1285
1286 /* wait for clock stabilization */
1287 for (i = 0; i < 0x50000; i++) {
1288 pci_read_config_byte(dev, 0x5b, &reg5bh);
1289 if (reg5bh & 0x80) {
1290 /* spin looking for the clock to destabilize */
1291 for (i = 0; i < 0x1000; ++i) {
1292 pci_read_config_byte(dev, 0x5b,
1293 &reg5bh);
1294 if ((reg5bh & 0x80) == 0)
1295 goto pll_recal;
1296 }
1297 pci_read_config_dword(dev, 0x5c, &pll);
1298 pci_write_config_dword(dev, 0x5c,
1299 pll & ~0x100);
1300 pci_write_config_byte(dev, 0x5b, 0x21);
1301 if (hpt_minimum_revision(dev,8))
1302 pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
1303 else if (hpt_minimum_revision(dev,5))
1304 pci_set_drvdata(dev, (void *) fifty_base_hpt372);
1305 else if (hpt_minimum_revision(dev,4))
1306 pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
1307 else
1308 pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
1309 printk("HPT37X: using 50MHz internal PLL\n");
1310 goto init_hpt37X_done;
1311 }
1312 }
1313pll_recal:
1314 if (adjust & 1)
1315 pll -= (adjust >> 1);
1316 else
1317 pll += (adjust >> 1);
1318 }
1319
1320init_hpt37X_done:
1321 /* reset state engine */
1322 pci_write_config_byte(dev, 0x50, 0x37);
1323 pci_write_config_byte(dev, 0x54, 0x37);
1324 udelay(100);
1325 return 0;
1326}
1327
1328static int __devinit init_hpt366(struct pci_dev *dev)
1329{
1330 u32 reg1 = 0;
1331 u8 drive_fast = 0;
1332
1333 /*
1334 * Disable the "fast interrupt" prediction.
1335 */
1336 pci_read_config_byte(dev, 0x51, &drive_fast);
1337 if (drive_fast & 0x80)
1338 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
1339 pci_read_config_dword(dev, 0x40, &reg1);
1340
1341 /* detect bus speed by looking at control reg timing: */
1342 switch((reg1 >> 8) & 7) {
1343 case 5:
1344 pci_set_drvdata(dev, (void *) forty_base_hpt366);
1345 break;
1346 case 9:
1347 pci_set_drvdata(dev, (void *) twenty_five_base_hpt366);
1348 break;
1349 case 7:
1350 default:
1351 pci_set_drvdata(dev, (void *) thirty_three_base_hpt366);
1352 break;
1353 }
1354
1355 if (!pci_get_drvdata(dev))
1356 {
1357 printk(KERN_ERR "hpt366: unknown bus timing.\n");
1358 pci_set_drvdata(dev, NULL);
1359 }
1360 return 0;
1361}
1362
1363static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
1364{
1365 int ret = 0;
1366 u8 test = 0;
1367
1368 if (dev->resource[PCI_ROM_RESOURCE].start)
1369 pci_write_config_byte(dev, PCI_ROM_ADDRESS,
1370 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
1371
1372 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &test);
1373 if (test != (L1_CACHE_BYTES / 4))
1374 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
1375 (L1_CACHE_BYTES / 4));
1376
1377 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &test);
1378 if (test != 0x78)
1379 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1380
1381 pci_read_config_byte(dev, PCI_MIN_GNT, &test);
1382 if (test != 0x08)
1383 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1384
1385 pci_read_config_byte(dev, PCI_MAX_LAT, &test);
1386 if (test != 0x08)
1387 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1388
1389 if (hpt_minimum_revision(dev, 3)) {
1390 ret = init_hpt37x(dev);
1391 } else {
1392 ret =init_hpt366(dev);
1393 }
1394 if (ret)
1395 return ret;
1396
1397 return dev->irq;
1398}
1399
1400static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1401{
1402 struct pci_dev *dev = hwif->pci_dev;
1403 u8 ata66 = 0, regmask = (hwif->channel) ? 0x01 : 0x02;
1404 u8 did, rid;
1405 unsigned long dmabase = hwif->dma_base;
1406 int is_372n = 0;
1407
1408 if(dmabase)
1409 {
1410 did = inb(dmabase + 0x22);
1411 rid = inb(dmabase + 0x28);
1412
1413 if((did == 4 && rid == 6) || (did == 5 && rid > 1))
1414 is_372n = 1;
1415 }
1416
1417 hwif->tuneproc = &hpt3xx_tune_drive;
1418 hwif->speedproc = &hpt3xx_tune_chipset;
1419 hwif->quirkproc = &hpt3xx_quirkproc;
1420 hwif->intrproc = &hpt3xx_intrproc;
1421 hwif->maskproc = &hpt3xx_maskproc;
1422
1423 if(is_372n)
1424 hwif->rw_disk = &hpt372n_rw_disk;
1425
1426 /*
1427 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1428 * address lines to access an external eeprom. To read valid
1429 * cable detect state the pins must be enabled as inputs.
1430 */
1431 if (hpt_minimum_revision(dev, 8) && PCI_FUNC(dev->devfn) & 1) {
1432 /*
1433 * HPT374 PCI function 1
1434 * - set bit 15 of reg 0x52 to enable TCBLID as input
1435 * - set bit 15 of reg 0x56 to enable FCBLID as input
1436 */
1437 u16 mcr3, mcr6;
1438 pci_read_config_word(dev, 0x52, &mcr3);
1439 pci_read_config_word(dev, 0x56, &mcr6);
1440 pci_write_config_word(dev, 0x52, mcr3 | 0x8000);
1441 pci_write_config_word(dev, 0x56, mcr6 | 0x8000);
1442 /* now read cable id register */
1443 pci_read_config_byte(dev, 0x5a, &ata66);
1444 pci_write_config_word(dev, 0x52, mcr3);
1445 pci_write_config_word(dev, 0x56, mcr6);
1446 } else if (hpt_minimum_revision(dev, 3)) {
1447 /*
1448 * HPT370/372 and 374 pcifn 0
1449 * - clear bit 0 of 0x5b to enable P/SCBLID as inputs
1450 */
1451 u8 scr2;
1452 pci_read_config_byte(dev, 0x5b, &scr2);
1453 pci_write_config_byte(dev, 0x5b, scr2 & ~1);
1454 /* now read cable id register */
1455 pci_read_config_byte(dev, 0x5a, &ata66);
1456 pci_write_config_byte(dev, 0x5b, scr2);
1457 } else {
1458 pci_read_config_byte(dev, 0x5a, &ata66);
1459 }
1460
1461#ifdef DEBUG
1462 printk("HPT366: reg5ah=0x%02x ATA-%s Cable Port%d\n",
1463 ata66, (ata66 & regmask) ? "33" : "66",
1464 PCI_FUNC(hwif->pci_dev->devfn));
1465#endif /* DEBUG */
1466
1467#ifdef HPT_SERIALIZE_IO
1468 /* serialize access to this device */
1469 if (hwif->mate)
1470 hwif->serialized = hwif->mate->serialized = 1;
1471#endif
1472
1473 if (hpt_minimum_revision(dev,3)) {
1474 u8 reg5ah = 0;
1475 pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
1476 /*
1477 * set up ioctl for power status.
1478 * note: power affects both
1479 * drives on each channel
1480 */
1481 hwif->resetproc = &hpt3xx_reset;
1482 hwif->busproc = &hpt370_busproc;
1483// hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
1484 } else if (hpt_minimum_revision(dev,2)) {
1485 hwif->resetproc = &hpt3xx_reset;
1486 hwif->busproc = &hpt3xx_tristate;
1487 } else {
1488 hwif->resetproc = &hpt3xx_reset;
1489 hwif->busproc = &hpt3xx_tristate;
1490 }
1491
1492 if (!hwif->dma_base) {
1493 hwif->drives[0].autotune = 1;
1494 hwif->drives[1].autotune = 1;
1495 return;
1496 }
1497
1498 hwif->ultra_mask = 0x7f;
1499 hwif->mwdma_mask = 0x07;
1500
1501 if (!(hwif->udma_four))
1502 hwif->udma_four = ((ata66 & regmask) ? 0 : 1);
1503 hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
1504
1505 if (hpt_minimum_revision(dev,8)) {
1506 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1507 hwif->ide_dma_end = &hpt374_ide_dma_end;
1508 } else if (hpt_minimum_revision(dev,5)) {
1509 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1510 hwif->ide_dma_end = &hpt374_ide_dma_end;
1511 } else if (hpt_minimum_revision(dev,3)) {
1512 hwif->dma_start = &hpt370_ide_dma_start;
1513 hwif->ide_dma_end = &hpt370_ide_dma_end;
1514 hwif->ide_dma_timeout = &hpt370_ide_dma_timeout;
1515 hwif->ide_dma_lostirq = &hpt370_ide_dma_lostirq;
1516 } else if (hpt_minimum_revision(dev,2))
1517 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1518 else
1519 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1520
1521 if (!noautodma)
1522 hwif->autodma = 1;
1523 hwif->drives[0].autodma = hwif->autodma;
1524 hwif->drives[1].autodma = hwif->autodma;
1525}
1526
1527static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1528{
1529 u8 masterdma = 0, slavedma = 0;
1530 u8 dma_new = 0, dma_old = 0;
1531 u8 primary = hwif->channel ? 0x4b : 0x43;
1532 u8 secondary = hwif->channel ? 0x4f : 0x47;
1533 unsigned long flags;
1534
1535 if (!dmabase)
1536 return;
1537
1538 if(pci_get_drvdata(hwif->pci_dev) == NULL)
1539 {
1540 printk(KERN_WARNING "hpt: no known IDE timings, disabling DMA.\n");
1541 return;
1542 }
1543
1544 dma_old = hwif->INB(dmabase+2);
1545
1546 local_irq_save(flags);
1547
1548 dma_new = dma_old;
1549 pci_read_config_byte(hwif->pci_dev, primary, &masterdma);
1550 pci_read_config_byte(hwif->pci_dev, secondary, &slavedma);
1551
1552 if (masterdma & 0x30) dma_new |= 0x20;
1553 if (slavedma & 0x30) dma_new |= 0x40;
1554 if (dma_new != dma_old)
1555 hwif->OUTB(dma_new, dmabase+2);
1556
1557 local_irq_restore(flags);
1558
1559 ide_setup_dma(hwif, dmabase, 8);
1560}
1561
1562static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1563{
1564 struct pci_dev *findev = NULL;
1565
1566 if (PCI_FUNC(dev->devfn) & 1)
1567 return -ENODEV;
1568
1569 while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1570 if ((findev->vendor == dev->vendor) &&
1571 (findev->device == dev->device) &&
1572 ((findev->devfn - dev->devfn) == 1) &&
1573 (PCI_FUNC(findev->devfn) & 1)) {
1574 if (findev->irq != dev->irq) {
1575 /* FIXME: we need a core pci_set_interrupt() */
1576 findev->irq = dev->irq;
1577 printk(KERN_WARNING "%s: pci-config space interrupt "
1578 "fixed.\n", d->name);
1579 }
1580 return ide_setup_pci_devices(dev, findev, d);
1581 }
1582 }
1583 return ide_setup_pci_device(dev, d);
1584}
1585
1586static int __devinit init_setup_hpt37x(struct pci_dev *dev, ide_pci_device_t *d)
1587{
1588 return ide_setup_pci_device(dev, d);
1589}
1590
1591static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1592{
1593 struct pci_dev *findev = NULL;
1594 u8 pin1 = 0, pin2 = 0;
1595 unsigned int class_rev;
1596 char *chipset_names[] = {"HPT366", "HPT366", "HPT368",
1597 "HPT370", "HPT370A", "HPT372",
1598 "HPT372N" };
1599
1600 if (PCI_FUNC(dev->devfn) & 1)
1601 return -ENODEV;
1602
1603 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
1604 class_rev &= 0xff;
1605
1606 if(dev->device == PCI_DEVICE_ID_TTI_HPT372N)
1607 class_rev = 6;
1608
1609 if(class_rev <= 6)
1610 d->name = chipset_names[class_rev];
1611
1612 switch(class_rev) {
1613 case 6:
1614 case 5:
1615 case 4:
1616 case 3:
1617 goto init_single;
1618 default:
1619 break;
1620 }
1621
1622 d->channels = 1;
1623
1624 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1625 while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1626 if ((findev->vendor == dev->vendor) &&
1627 (findev->device == dev->device) &&
1628 ((findev->devfn - dev->devfn) == 1) &&
1629 (PCI_FUNC(findev->devfn) & 1)) {
1630 pci_read_config_byte(findev, PCI_INTERRUPT_PIN, &pin2);
1631 if ((pin1 != pin2) && (dev->irq == findev->irq)) {
1632 d->bootable = ON_BOARD;
1633 printk("%s: onboard version of chipset, "
1634 "pin1=%d pin2=%d\n", d->name,
1635 pin1, pin2);
1636 }
1637 return ide_setup_pci_devices(dev, findev, d);
1638 }
1639 }
1640init_single:
1641 return ide_setup_pci_device(dev, d);
1642}
1643
1644static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1645 { /* 0 */
1646 .name = "HPT366",
1647 .init_setup = init_setup_hpt366,
1648 .init_chipset = init_chipset_hpt366,
1649 .init_hwif = init_hwif_hpt366,
1650 .init_dma = init_dma_hpt366,
1651 .channels = 2,
1652 .autodma = AUTODMA,
1653 .bootable = OFF_BOARD,
1654 .extra = 240
1655 },{ /* 1 */
1656 .name = "HPT372A",
1657 .init_setup = init_setup_hpt37x,
1658 .init_chipset = init_chipset_hpt366,
1659 .init_hwif = init_hwif_hpt366,
1660 .init_dma = init_dma_hpt366,
1661 .channels = 2,
1662 .autodma = AUTODMA,
1663 .bootable = OFF_BOARD,
1664 },{ /* 2 */
1665 .name = "HPT302",
1666 .init_setup = init_setup_hpt37x,
1667 .init_chipset = init_chipset_hpt366,
1668 .init_hwif = init_hwif_hpt366,
1669 .init_dma = init_dma_hpt366,
1670 .channels = 2,
1671 .autodma = AUTODMA,
1672 .bootable = OFF_BOARD,
1673 },{ /* 3 */
1674 .name = "HPT371",
1675 .init_setup = init_setup_hpt37x,
1676 .init_chipset = init_chipset_hpt366,
1677 .init_hwif = init_hwif_hpt366,
1678 .init_dma = init_dma_hpt366,
1679 .channels = 2,
1680 .autodma = AUTODMA,
1681 .bootable = OFF_BOARD,
1682 },{ /* 4 */
1683 .name = "HPT374",
1684 .init_setup = init_setup_hpt374,
1685 .init_chipset = init_chipset_hpt366,
1686 .init_hwif = init_hwif_hpt366,
1687 .init_dma = init_dma_hpt366,
1688 .channels = 2, /* 4 */
1689 .autodma = AUTODMA,
1690 .bootable = OFF_BOARD,
1691 },{ /* 5 */
1692 .name = "HPT372N",
1693 .init_setup = init_setup_hpt37x,
1694 .init_chipset = init_chipset_hpt366,
1695 .init_hwif = init_hwif_hpt366,
1696 .init_dma = init_dma_hpt366,
1697 .channels = 2, /* 4 */
1698 .autodma = AUTODMA,
1699 .bootable = OFF_BOARD,
1700 }
1701};
1702
1703/**
1704 * hpt366_init_one - called when an HPT366 is found
1705 * @dev: the hpt366 device
1706 * @id: the matching pci id
1707 *
1708 * Called when the PCI registration layer (or the IDE initialization)
1709 * finds a device matching our IDE device tables.
1710 */
1711
1712static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1713{
1714 ide_pci_device_t *d = &hpt366_chipsets[id->driver_data];
1715
1716 return d->init_setup(dev, d);
1717}
1718
1719static struct pci_device_id hpt366_pci_tbl[] = {
1720 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1721 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1722 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1723 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
1724 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1725 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
1726 { 0, },
1727};
1728MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1729
1730static struct pci_driver driver = {
1731 .name = "HPT366_IDE",
1732 .id_table = hpt366_pci_tbl,
1733 .probe = hpt366_init_one,
1734};
1735
1736static int hpt366_ide_init(void)
1737{
1738 return ide_pci_register_driver(&driver);
1739}
1740
1741module_init(hpt366_ide_init);
1742
1743MODULE_AUTHOR("Andre Hedrick");
1744MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1745MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/it8172.c b/drivers/ide/pci/it8172.c
new file mode 100644
index 000000000000..631927cf17d4
--- /dev/null
+++ b/drivers/ide/pci/it8172.c
@@ -0,0 +1,308 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * IT8172 IDE controller support
5 *
6 * Copyright 2000 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * stevel@mvista.com or source@mvista.com
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <linux/config.h>
32#include <linux/module.h>
33#include <linux/types.h>
34#include <linux/kernel.h>
35#include <linux/ioport.h>
36#include <linux/pci.h>
37#include <linux/hdreg.h>
38#include <linux/ide.h>
39#include <linux/delay.h>
40#include <linux/init.h>
41
42#include <asm/io.h>
43#include <asm/it8172/it8172_int.h>
44
45/*
46 * Prototypes
47 */
48static u8 it8172_ratemask (ide_drive_t *drive)
49{
50 return 1;
51}
52
53static void it8172_tune_drive (ide_drive_t *drive, u8 pio)
54{
55 ide_hwif_t *hwif = HWIF(drive);
56 struct pci_dev *dev = hwif->pci_dev;
57 int is_slave = (&hwif->drives[1] == drive);
58 unsigned long flags;
59 u16 drive_enables;
60 u32 drive_timing;
61
62 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
63 spin_lock_irqsave(&ide_lock, flags);
64 pci_read_config_word(dev, 0x40, &drive_enables);
65 pci_read_config_dword(dev, 0x44, &drive_timing);
66
67 /*
68 * FIX! The DIOR/DIOW pulse width and recovery times in port 0x44
69 * are being left at the default values of 8 PCI clocks (242 nsec
70 * for a 33 MHz clock). These can be safely shortened at higher
71 * PIO modes. The DIOR/DIOW pulse width and recovery times only
72 * apply to PIO modes, not to the DMA modes.
73 */
74
75 /*
76 * Enable port 0x44. The IT8172G spec is confused; it calls
77 * this register the "Slave IDE Timing Register", but in fact,
78 * it controls timing for both master and slave drives.
79 */
80 drive_enables |= 0x4000;
81
82 if (is_slave) {
83 drive_enables &= 0xc006;
84 if (pio > 1)
85 /* enable prefetch and IORDY sample-point */
86 drive_enables |= 0x0060;
87 } else {
88 drive_enables &= 0xc060;
89 if (pio > 1)
90 /* enable prefetch and IORDY sample-point */
91 drive_enables |= 0x0006;
92 }
93
94 pci_write_config_word(dev, 0x40, drive_enables);
95 spin_unlock_irqrestore(&ide_lock, flags);
96}
97
98static u8 it8172_dma_2_pio (u8 xfer_rate)
99{
100 switch(xfer_rate) {
101 case XFER_UDMA_5:
102 case XFER_UDMA_4:
103 case XFER_UDMA_3:
104 case XFER_UDMA_2:
105 case XFER_UDMA_1:
106 case XFER_UDMA_0:
107 case XFER_MW_DMA_2:
108 case XFER_PIO_4:
109 return 4;
110 case XFER_MW_DMA_1:
111 case XFER_PIO_3:
112 return 3;
113 case XFER_SW_DMA_2:
114 case XFER_PIO_2:
115 return 2;
116 case XFER_MW_DMA_0:
117 case XFER_SW_DMA_1:
118 case XFER_SW_DMA_0:
119 case XFER_PIO_1:
120 case XFER_PIO_0:
121 case XFER_PIO_SLOW:
122 default:
123 return 0;
124 }
125}
126
127static int it8172_tune_chipset (ide_drive_t *drive, u8 xferspeed)
128{
129 ide_hwif_t *hwif = HWIF(drive);
130 struct pci_dev *dev = hwif->pci_dev;
131 u8 speed = ide_rate_filter(it8172_ratemask(drive), xferspeed);
132 int a_speed = 3 << (drive->dn * 4);
133 int u_flag = 1 << drive->dn;
134 int u_speed = 0;
135 u8 reg48, reg4a;
136
137 pci_read_config_byte(dev, 0x48, &reg48);
138 pci_read_config_byte(dev, 0x4a, &reg4a);
139
140 /*
141 * Setting the DMA cycle time to 2 or 3 PCI clocks (60 and 91 nsec
142 * at 33 MHz PCI clock) seems to cause BadCRC errors during DMA
143 * transfers on some drives, even though both numbers meet the minimum
144 * ATAPI-4 spec of 73 and 54 nsec for UDMA 1 and 2 respectively.
145 * So the faster times are just commented out here. The good news is
146 * that the slower cycle time has very little affect on transfer
147 * performance.
148 */
149
150 switch(speed) {
151 case XFER_UDMA_4:
152 case XFER_UDMA_2: //u_speed = 2 << (drive->dn * 4); break;
153 case XFER_UDMA_5:
154 case XFER_UDMA_3:
155 case XFER_UDMA_1: //u_speed = 1 << (drive->dn * 4); break;
156 case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;
157 case XFER_MW_DMA_2:
158 case XFER_MW_DMA_1:
159 case XFER_MW_DMA_0:
160 case XFER_SW_DMA_2: break;
161 case XFER_PIO_4:
162 case XFER_PIO_3:
163 case XFER_PIO_2:
164 case XFER_PIO_0: break;
165 default: return -1;
166 }
167
168 if (speed >= XFER_UDMA_0) {
169 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
170 reg4a &= ~a_speed;
171 pci_write_config_byte(dev, 0x4a, reg4a | u_speed);
172 } else {
173 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
174 pci_write_config_byte(dev, 0x4a, reg4a & ~a_speed);
175 }
176
177 it8172_tune_drive(drive, it8172_dma_2_pio(speed));
178 return (ide_config_drive_speed(drive, speed));
179}
180
181static int it8172_config_chipset_for_dma (ide_drive_t *drive)
182{
183 u8 speed = ide_dma_speed(drive, it8172_ratemask(drive));
184
185 if (!(speed)) {
186 u8 tspeed = ide_get_best_pio_mode(drive, 255, 4, NULL);
187 speed = it8172_dma_2_pio(XFER_PIO_0 + tspeed);
188 }
189
190 (void) it8172_tune_chipset(drive, speed);
191 return ide_dma_enable(drive);
192}
193
194static int it8172_config_drive_xfer_rate (ide_drive_t *drive)
195{
196 ide_hwif_t *hwif = HWIF(drive);
197 struct hd_driveid *id = drive->id;
198
199 drive->init_speed = 0;
200
201 if (id && (id->capability & 1) && drive->autodma) {
202
203 if (ide_use_dma(drive)) {
204 if (it8172_config_chipset_for_dma(drive))
205 return hwif->ide_dma_on(drive);
206 }
207
208 goto fast_ata_pio;
209
210 } else if ((id->capability & 8) || (id->field_valid & 2)) {
211fast_ata_pio:
212 it8172_tune_drive(drive, 5);
213 return hwif->ide_dma_off_quietly(drive);
214 }
215 /* IORDY not supported */
216 return 0;
217}
218
219static unsigned int __init init_chipset_it8172 (struct pci_dev *dev, const char *name)
220{
221 unsigned char progif;
222
223 /*
224 * Place both IDE interfaces into PCI "native" mode
225 */
226 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
227 pci_write_config_byte(dev, PCI_CLASS_PROG, progif | 0x05);
228
229 return IT8172_IDE_IRQ;
230}
231
232
233static void __init init_hwif_it8172 (ide_hwif_t *hwif)
234{
235 struct pci_dev* dev = hwif->pci_dev;
236 unsigned long cmdBase, ctrlBase;
237
238 hwif->autodma = 0;
239 hwif->tuneproc = &it8172_tune_drive;
240 hwif->speedproc = &it8172_tune_chipset;
241
242 cmdBase = dev->resource[0].start;
243 ctrlBase = dev->resource[1].start;
244
245 ide_init_hwif_ports(&hwif->hw, cmdBase, ctrlBase | 2, NULL);
246 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
247 hwif->noprobe = 0;
248
249 if (!hwif->dma_base) {
250 hwif->drives[0].autotune = 1;
251 hwif->drives[1].autotune = 1;
252 return;
253 }
254
255 hwif->atapi_dma = 1;
256 hwif->ultra_mask = 0x07;
257 hwif->mwdma_mask = 0x06;
258 hwif->swdma_mask = 0x04;
259
260 hwif->ide_dma_check = &it8172_config_drive_xfer_rate;
261 if (!noautodma)
262 hwif->autodma = 1;
263 hwif->drives[0].autodma = hwif->autodma;
264 hwif->drives[1].autodma = hwif->autodma;
265}
266
267static ide_pci_device_t it8172_chipsets[] __devinitdata = {
268 { /* 0 */
269 .name = "IT8172G",
270 .init_chipset = init_chipset_it8172,
271 .init_hwif = init_hwif_it8172,
272 .channels = 2,
273 .autodma = AUTODMA,
274 .enablebits = {{0x00,0x00,0x00}, {0x40,0x00,0x01}},
275 .bootable = ON_BOARD,
276 }
277};
278
279static int __devinit it8172_init_one(struct pci_dev *dev, const struct pci_device_id *id)
280{
281 if ((!(PCI_FUNC(dev->devfn) & 1) ||
282 (!((dev->class >> 8) == PCI_CLASS_STORAGE_IDE))))
283 return -ENODEV; /* IT8172 is more than an IDE controller */
284 return ide_setup_pci_device(dev, &it8172_chipsets[id->driver_data]);
285}
286
287static struct pci_device_id it8172_pci_tbl[] = {
288 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_IT8172G, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
289 { 0, },
290};
291MODULE_DEVICE_TABLE(pci, it8172_pci_tbl);
292
293static struct pci_driver driver = {
294 .name = "IT8172_IDE",
295 .id_table = it8172_pci_tbl,
296 .probe = it8172_init_one,
297};
298
299static int it8172_ide_init(void)
300{
301 return ide_pci_register_driver(&driver);
302}
303
304module_init(it8172_ide_init);
305
306MODULE_AUTHOR("SteveL@mvista.com");
307MODULE_DESCRIPTION("PCI driver module for ITE 8172 IDE");
308MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/ns87415.c b/drivers/ide/pci/ns87415.c
new file mode 100644
index 000000000000..205a32fbc2f0
--- /dev/null
+++ b/drivers/ide/pci/ns87415.c
@@ -0,0 +1,315 @@
1/*
2 * linux/drivers/ide/pci/ns87415.c Version 2.00 Sep. 10, 2002
3 *
4 * Copyright (C) 1997-1998 Mark Lord <mlord@pobox.com>
5 * Copyright (C) 1998 Eddie C. Dost <ecd@skynet.be>
6 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
7 * Copyright (C) 2004 Grant Grundler <grundler at parisc-linux.org>
8 *
9 * Inspired by an earlier effort from David S. Miller <davem@redhat.com>
10 */
11
12#include <linux/config.h>
13#include <linux/module.h>
14#include <linux/types.h>
15#include <linux/kernel.h>
16#include <linux/timer.h>
17#include <linux/mm.h>
18#include <linux/ioport.h>
19#include <linux/interrupt.h>
20#include <linux/blkdev.h>
21#include <linux/hdreg.h>
22#include <linux/pci.h>
23#include <linux/delay.h>
24#include <linux/ide.h>
25#include <linux/init.h>
26
27#include <asm/io.h>
28
29#ifdef CONFIG_SUPERIO
30/* SUPERIO 87560 is a PoS chip that NatSem denies exists.
31 * Unfortunately, it's built-in on all Astro-based PA-RISC workstations
32 * which use the integrated NS87514 cell for CD-ROM support.
33 * i.e we have to support for CD-ROM installs.
34 * See drivers/parisc/superio.c for more gory details.
35 */
36#include <asm/superio.h>
37
38static unsigned long superio_ide_status[2];
39static unsigned long superio_ide_select[2];
40static unsigned long superio_ide_dma_status[2];
41
42#define SUPERIO_IDE_MAX_RETRIES 25
43
44/* Because of a defect in Super I/O, all reads of the PCI DMA status
45 * registers, IDE status register and the IDE select register need to be
46 * retried
47 */
48static u8 superio_ide_inb (unsigned long port)
49{
50 if (port == superio_ide_status[0] ||
51 port == superio_ide_status[1] ||
52 port == superio_ide_select[0] ||
53 port == superio_ide_select[1] ||
54 port == superio_ide_dma_status[0] ||
55 port == superio_ide_dma_status[1]) {
56 u8 tmp;
57 int retries = SUPERIO_IDE_MAX_RETRIES;
58
59 /* printk(" [ reading port 0x%x with retry ] ", port); */
60
61 do {
62 tmp = inb(port);
63 if (tmp == 0)
64 udelay(50);
65 } while (tmp == 0 && retries-- > 0);
66
67 return tmp;
68 }
69
70 return inb(port);
71}
72
73static void __devinit superio_ide_init_iops (struct hwif_s *hwif)
74{
75 u32 base, dmabase;
76 u8 tmp;
77 struct pci_dev *pdev = hwif->pci_dev;
78 u8 port = hwif->channel;
79
80 base = pci_resource_start(pdev, port * 2) & ~3;
81 dmabase = pci_resource_start(pdev, 4) & ~3;
82
83 superio_ide_status[port] = base + IDE_STATUS_OFFSET;
84 superio_ide_select[port] = base + IDE_SELECT_OFFSET;
85 superio_ide_dma_status[port] = dmabase + (!port ? 2 : 0xa);
86
87 /* Clear error/interrupt, enable dma */
88 tmp = superio_ide_inb(superio_ide_dma_status[port]);
89 outb(tmp | 0x66, superio_ide_dma_status[port]);
90
91 /* We need to override inb to workaround a SuperIO errata */
92 hwif->INB = superio_ide_inb;
93}
94
95static void __devinit init_iops_ns87415(ide_hwif_t *hwif)
96{
97 if (PCI_SLOT(hwif->pci_dev->devfn) == 0xE) {
98 /* Built-in - assume it's under superio. */
99 superio_ide_init_iops(hwif);
100 }
101}
102#endif
103
104static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 };
105
106/*
107 * This routine either enables/disables (according to drive->present)
108 * the IRQ associated with the port (HWIF(drive)),
109 * and selects either PIO or DMA handshaking for the next I/O operation.
110 */
111static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
112{
113 ide_hwif_t *hwif = HWIF(drive);
114 unsigned int bit, other, new, *old = (unsigned int *) hwif->select_data;
115 struct pci_dev *dev = hwif->pci_dev;
116 unsigned long flags;
117
118 local_irq_save(flags);
119 new = *old;
120
121 /* Adjust IRQ enable bit */
122 bit = 1 << (8 + hwif->channel);
123 new = drive->present ? (new & ~bit) : (new | bit);
124
125 /* Select PIO or DMA, DMA may only be selected for one drive/channel. */
126 bit = 1 << (20 + drive->select.b.unit + (hwif->channel << 1));
127 other = 1 << (20 + (1 - drive->select.b.unit) + (hwif->channel << 1));
128 new = use_dma ? ((new & ~other) | bit) : (new & ~bit);
129
130 if (new != *old) {
131 unsigned char stat;
132
133 /*
134 * Don't change DMA engine settings while Write Buffers
135 * are busy.
136 */
137 (void) pci_read_config_byte(dev, 0x43, &stat);
138 while (stat & 0x03) {
139 udelay(1);
140 (void) pci_read_config_byte(dev, 0x43, &stat);
141 }
142
143 *old = new;
144 (void) pci_write_config_dword(dev, 0x40, new);
145
146 /*
147 * And let things settle...
148 */
149 udelay(10);
150 }
151
152 local_irq_restore(flags);
153}
154
155static void ns87415_selectproc (ide_drive_t *drive)
156{
157 ns87415_prepare_drive (drive, drive->using_dma);
158}
159
160static int ns87415_ide_dma_end (ide_drive_t *drive)
161{
162 ide_hwif_t *hwif = HWIF(drive);
163 u8 dma_stat = 0, dma_cmd = 0;
164
165 drive->waiting_for_dma = 0;
166 dma_stat = hwif->INB(hwif->dma_status);
167 /* get dma command mode */
168 dma_cmd = hwif->INB(hwif->dma_command);
169 /* stop DMA */
170 hwif->OUTB(dma_cmd & ~1, hwif->dma_command);
171 /* from ERRATA: clear the INTR & ERROR bits */
172 dma_cmd = hwif->INB(hwif->dma_command);
173 hwif->OUTB(dma_cmd|6, hwif->dma_command);
174 /* and free any DMA resources */
175 ide_destroy_dmatable(drive);
176 /* verify good DMA status */
177 return (dma_stat & 7) != 4;
178}
179
180static int ns87415_ide_dma_setup(ide_drive_t *drive)
181{
182 /* select DMA xfer */
183 ns87415_prepare_drive(drive, 1);
184 if (!ide_dma_setup(drive))
185 return 0;
186 /* DMA failed: select PIO xfer */
187 ns87415_prepare_drive(drive, 0);
188 return 1;
189}
190
191static int ns87415_ide_dma_check (ide_drive_t *drive)
192{
193 if (drive->media != ide_disk)
194 return HWIF(drive)->ide_dma_off_quietly(drive);
195 return __ide_dma_check(drive);
196}
197
198static void __init init_hwif_ns87415 (ide_hwif_t *hwif)
199{
200 struct pci_dev *dev = hwif->pci_dev;
201 unsigned int ctrl, using_inta;
202 u8 progif;
203#ifdef __sparc_v9__
204 int timeout;
205 u8 stat;
206#endif
207
208 hwif->autodma = 0;
209 hwif->selectproc = &ns87415_selectproc;
210
211 /*
212 * We cannot probe for IRQ: both ports share common IRQ on INTA.
213 * Also, leave IRQ masked during drive probing, to prevent infinite
214 * interrupts from a potentially floating INTA..
215 *
216 * IRQs get unmasked in selectproc when drive is first used.
217 */
218 (void) pci_read_config_dword(dev, 0x40, &ctrl);
219 (void) pci_read_config_byte(dev, 0x09, &progif);
220 /* is irq in "native" mode? */
221 using_inta = progif & (1 << (hwif->channel << 1));
222 if (!using_inta)
223 using_inta = ctrl & (1 << (4 + hwif->channel));
224 if (hwif->mate) {
225 hwif->select_data = hwif->mate->select_data;
226 } else {
227 hwif->select_data = (unsigned long)
228 &ns87415_control[ns87415_count++];
229 ctrl |= (1 << 8) | (1 << 9); /* mask both IRQs */
230 if (using_inta)
231 ctrl &= ~(1 << 6); /* unmask INTA */
232 *((unsigned int *)hwif->select_data) = ctrl;
233 (void) pci_write_config_dword(dev, 0x40, ctrl);
234
235 /*
236 * Set prefetch size to 512 bytes for both ports,
237 * but don't turn on/off prefetching here.
238 */
239 pci_write_config_byte(dev, 0x55, 0xee);
240
241#ifdef __sparc_v9__
242 /*
243 * XXX: Reset the device, if we don't it will not respond
244 * to SELECT_DRIVE() properly during first probe_hwif().
245 */
246 timeout = 10000;
247 hwif->OUTB(12, hwif->io_ports[IDE_CONTROL_OFFSET]);
248 udelay(10);
249 hwif->OUTB(8, hwif->io_ports[IDE_CONTROL_OFFSET]);
250 do {
251 udelay(50);
252 stat = hwif->INB(hwif->io_ports[IDE_STATUS_OFFSET]);
253 if (stat == 0xff)
254 break;
255 } while ((stat & BUSY_STAT) && --timeout);
256#endif
257 }
258
259 if (!using_inta)
260 hwif->irq = ide_default_irq(hwif->io_ports[IDE_DATA_OFFSET]);
261 else if (!hwif->irq && hwif->mate && hwif->mate->irq)
262 hwif->irq = hwif->mate->irq; /* share IRQ with mate */
263
264 if (!hwif->dma_base)
265 return;
266
267 hwif->OUTB(0x60, hwif->dma_status);
268 hwif->dma_setup = &ns87415_ide_dma_setup;
269 hwif->ide_dma_check = &ns87415_ide_dma_check;
270 hwif->ide_dma_end = &ns87415_ide_dma_end;
271
272 if (!noautodma)
273 hwif->autodma = 1;
274 hwif->drives[0].autodma = hwif->autodma;
275 hwif->drives[1].autodma = hwif->autodma;
276}
277
278static ide_pci_device_t ns87415_chipset __devinitdata = {
279 .name = "NS87415",
280#ifdef CONFIG_SUPERIO
281 .init_iops = init_iops_ns87415,
282#endif
283 .init_hwif = init_hwif_ns87415,
284 .channels = 2,
285 .autodma = AUTODMA,
286 .bootable = ON_BOARD,
287};
288
289static int __devinit ns87415_init_one(struct pci_dev *dev, const struct pci_device_id *id)
290{
291 return ide_setup_pci_device(dev, &ns87415_chipset);
292}
293
294static struct pci_device_id ns87415_pci_tbl[] = {
295 { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
296 { 0, },
297};
298MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl);
299
300static struct pci_driver driver = {
301 .name = "NS87415_IDE",
302 .id_table = ns87415_pci_tbl,
303 .probe = ns87415_init_one,
304};
305
306static int ns87415_ide_init(void)
307{
308 return ide_pci_register_driver(&driver);
309}
310
311module_init(ns87415_ide_init);
312
313MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick");
314MODULE_DESCRIPTION("PCI driver module for NS87415 IDE");
315MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/opti621.c b/drivers/ide/pci/opti621.c
new file mode 100644
index 000000000000..cf4fd91d396a
--- /dev/null
+++ b/drivers/ide/pci/opti621.c
@@ -0,0 +1,394 @@
1/*
2 * linux/drivers/ide/pci/opti621.c Version 0.7 Sept 10, 2002
3 *
4 * Copyright (C) 1996-1998 Linus Torvalds & authors (see below)
5 */
6
7/*
8 * Authors:
9 * Jaromir Koutek <miri@punknet.cz>,
10 * Jan Harkes <jaharkes@cwi.nl>,
11 * Mark Lord <mlord@pobox.com>
12 * Some parts of code are from ali14xx.c and from rz1000.c.
13 *
14 * OPTi is trademark of OPTi, Octek is trademark of Octek.
15 *
16 * I used docs from OPTi databook, from ftp.opti.com, file 9123-0002.ps
17 * and disassembled/traced setupvic.exe (DOS program).
18 * It increases kernel code about 2 kB.
19 * I don't have this card no more, but I hope I can get some in case
20 * of needed development.
21 * My card is Octek PIDE 1.01 (on card) or OPTiViC (program).
22 * It has a place for a secondary connector in circuit, but nothing
23 * is there. Also BIOS says no address for
24 * secondary controller (see bellow in ide_init_opti621).
25 * I've only tested this on my system, which only has one disk.
26 * It's Western Digital WDAC2850, with PIO mode 3. The PCI bus
27 * is at 20 MHz (I have DX2/80, I tried PCI at 40, but I got random
28 * lockups). I tried the OCTEK double speed CD-ROM and
29 * it does not work! But I can't boot DOS also, so it's probably
30 * hardware fault. I have connected Conner 80MB, the Seagate 850MB (no
31 * problems) and Seagate 1GB (as slave, WD as master). My experiences
32 * with the third, 1GB drive: I got 3MB/s (hdparm), but sometimes
33 * it slows to about 100kB/s! I don't know why and I have
34 * not this drive now, so I can't try it again.
35 * I write this driver because I lost the paper ("manual") with
36 * settings of jumpers on the card and I have to boot Linux with
37 * Loadlin except LILO, cause I have to run the setupvic.exe program
38 * already or I get disk errors (my test: rpm -Vf
39 * /usr/X11R6/bin/XF86_SVGA - or any big file).
40 * Some numbers from hdparm -t /dev/hda:
41 * Timing buffer-cache reads: 32 MB in 3.02 seconds =10.60 MB/sec
42 * Timing buffered disk reads: 16 MB in 5.52 seconds = 2.90 MB/sec
43 * I have 4 Megs/s before, but I don't know why (maybe changes
44 * in hdparm test).
45 * After release of 0.1, I got some successful reports, so it might work.
46 *
47 * The main problem with OPTi is that some timings for master
48 * and slave must be the same. For example, if you have master
49 * PIO 3 and slave PIO 0, driver have to set some timings of
50 * master for PIO 0. Second problem is that opti621_tune_drive
51 * got only one drive to set, but have to set both drives.
52 * This is solved in compute_pios. If you don't set
53 * the second drive, compute_pios use ide_get_best_pio_mode
54 * for autoselect mode (you can change it to PIO 0, if you want).
55 * If you then set the second drive to another PIO, the old value
56 * (automatically selected) will be overrided by yours.
57 * There is a 25/33MHz switch in configuration
58 * register, but driver is written for use at any frequency which get
59 * (use idebus=xx to select PCI bus speed).
60 * Use ide0=autotune for automatical tune of the PIO modes.
61 * If you get strange results, do not use this and set PIO manually
62 * by hdparm.
63 *
64 * Version 0.1, Nov 8, 1996
65 * by Jaromir Koutek, for 2.1.8.
66 * Initial version of driver.
67 *
68 * Version 0.2
69 * Number 0.2 skipped.
70 *
71 * Version 0.3, Nov 29, 1997
72 * by Mark Lord (probably), for 2.1.68
73 * Updates for use with new IDE block driver.
74 *
75 * Version 0.4, Dec 14, 1997
76 * by Jan Harkes
77 * Fixed some errors and cleaned the code.
78 *
79 * Version 0.5, Jan 2, 1998
80 * by Jaromir Koutek
81 * Updates for use with (again) new IDE block driver.
82 * Update of documentation.
83 *
84 * Version 0.6, Jan 2, 1999
85 * by Jaromir Koutek
86 * Reversed to version 0.3 of the driver, because
87 * 0.5 doesn't work.
88 */
89
90#undef REALLY_SLOW_IO /* most systems can safely undef this */
91#define OPTI621_DEBUG /* define for debug messages */
92
93#include <linux/types.h>
94#include <linux/module.h>
95#include <linux/kernel.h>
96#include <linux/delay.h>
97#include <linux/timer.h>
98#include <linux/mm.h>
99#include <linux/ioport.h>
100#include <linux/blkdev.h>
101#include <linux/pci.h>
102#include <linux/hdreg.h>
103#include <linux/ide.h>
104
105#include <asm/io.h>
106
107#define OPTI621_MAX_PIO 3
108/* In fact, I do not have any PIO 4 drive
109 * (address: 25 ns, data: 70 ns, recovery: 35 ns),
110 * but OPTi 82C621 is programmable and it can do (minimal values):
111 * on 40MHz PCI bus (pulse 25 ns):
112 * address: 25 ns, data: 25 ns, recovery: 50 ns;
113 * on 20MHz PCI bus (pulse 50 ns):
114 * address: 50 ns, data: 50 ns, recovery: 100 ns.
115 */
116
117/* #define READ_PREFETCH 0 */
118/* Uncomment for disable read prefetch.
119 * There is some readprefetch capatibility in hdparm,
120 * but when I type hdparm -P 1 /dev/hda, I got errors
121 * and till reset drive is inaccessible.
122 * This (hw) read prefetch is safe on my drive.
123 */
124
125#ifndef READ_PREFETCH
126#define READ_PREFETCH 0x40 /* read prefetch is enabled */
127#endif /* else read prefetch is disabled */
128
129#define READ_REG 0 /* index of Read cycle timing register */
130#define WRITE_REG 1 /* index of Write cycle timing register */
131#define CNTRL_REG 3 /* index of Control register */
132#define STRAP_REG 5 /* index of Strap register */
133#define MISC_REG 6 /* index of Miscellaneous register */
134
135static int reg_base;
136
137#define PIO_NOT_EXIST 254
138#define PIO_DONT_KNOW 255
139
140/* there are stored pio numbers from other calls of opti621_tune_drive */
141static void compute_pios(ide_drive_t *drive, u8 pio)
142/* Store values into drive->drive_data
143 * second_contr - 0 for primary controller, 1 for secondary
144 * slave_drive - 0 -> pio is for master, 1 -> pio is for slave
145 * pio - PIO mode for selected drive (for other we don't know)
146 */
147{
148 int d;
149 ide_hwif_t *hwif = HWIF(drive);
150
151 drive->drive_data = ide_get_best_pio_mode(drive, pio, OPTI621_MAX_PIO, NULL);
152 for (d = 0; d < 2; ++d) {
153 drive = &hwif->drives[d];
154 if (drive->present) {
155 if (drive->drive_data == PIO_DONT_KNOW)
156 drive->drive_data = ide_get_best_pio_mode(drive, 255, OPTI621_MAX_PIO, NULL);
157#ifdef OPTI621_DEBUG
158 printk("%s: Selected PIO mode %d\n",
159 drive->name, drive->drive_data);
160#endif
161 } else {
162 drive->drive_data = PIO_NOT_EXIST;
163 }
164 }
165}
166
167static int cmpt_clk(int time, int bus_speed)
168/* Returns (rounded up) time in clocks for time in ns,
169 * with bus_speed in MHz.
170 * Example: bus_speed = 40 MHz, time = 80 ns
171 * 1000/40 = 25 ns (clk value),
172 * 80/25 = 3.2, rounded up to 4 (I hope ;-)).
173 * Use idebus=xx to select right frequency.
174 */
175{
176 return ((time*bus_speed+999)/1000);
177}
178
179static void write_reg(ide_hwif_t *hwif, u8 value, int reg)
180/* Write value to register reg, base of register
181 * is at reg_base (0x1f0 primary, 0x170 secondary,
182 * if not changed by PCI configuration).
183 * This is from setupvic.exe program.
184 */
185{
186 hwif->INW(reg_base+1);
187 hwif->INW(reg_base+1);
188 hwif->OUTB(3, reg_base+2);
189 hwif->OUTB(value, reg_base+reg);
190 hwif->OUTB(0x83, reg_base+2);
191}
192
193static u8 read_reg(ide_hwif_t *hwif, int reg)
194/* Read value from register reg, base of register
195 * is at reg_base (0x1f0 primary, 0x170 secondary,
196 * if not changed by PCI configuration).
197 * This is from setupvic.exe program.
198 */
199{
200 u8 ret = 0;
201
202 hwif->INW(reg_base+1);
203 hwif->INW(reg_base+1);
204 hwif->OUTB(3, reg_base+2);
205 ret = hwif->INB(reg_base+reg);
206 hwif->OUTB(0x83, reg_base+2);
207 return ret;
208}
209
210typedef struct pio_clocks_s {
211 int address_time; /* Address setup (clocks) */
212 int data_time; /* Active/data pulse (clocks) */
213 int recovery_time; /* Recovery time (clocks) */
214} pio_clocks_t;
215
216static void compute_clocks(int pio, pio_clocks_t *clks)
217{
218 if (pio != PIO_NOT_EXIST) {
219 int adr_setup, data_pls;
220 int bus_speed = system_bus_clock();
221
222 adr_setup = ide_pio_timings[pio].setup_time;
223 data_pls = ide_pio_timings[pio].active_time;
224 clks->address_time = cmpt_clk(adr_setup, bus_speed);
225 clks->data_time = cmpt_clk(data_pls, bus_speed);
226 clks->recovery_time = cmpt_clk(ide_pio_timings[pio].cycle_time
227 - adr_setup-data_pls, bus_speed);
228 if (clks->address_time<1) clks->address_time = 1;
229 if (clks->address_time>4) clks->address_time = 4;
230 if (clks->data_time<1) clks->data_time = 1;
231 if (clks->data_time>16) clks->data_time = 16;
232 if (clks->recovery_time<2) clks->recovery_time = 2;
233 if (clks->recovery_time>17) clks->recovery_time = 17;
234 } else {
235 clks->address_time = 1;
236 clks->data_time = 1;
237 clks->recovery_time = 2;
238 /* minimal values */
239 }
240
241}
242
243/* Main tune procedure, called from tuneproc. */
244static void opti621_tune_drive (ide_drive_t *drive, u8 pio)
245{
246 /* primary and secondary drives share some registers,
247 * so we have to program both drives
248 */
249 unsigned long flags;
250 u8 pio1 = 0, pio2 = 0;
251 pio_clocks_t first, second;
252 int ax, drdy;
253 u8 cycle1, cycle2, misc;
254 ide_hwif_t *hwif = HWIF(drive);
255
256 /* sets drive->drive_data for both drives */
257 compute_pios(drive, pio);
258 pio1 = hwif->drives[0].drive_data;
259 pio2 = hwif->drives[1].drive_data;
260
261 compute_clocks(pio1, &first);
262 compute_clocks(pio2, &second);
263
264 /* ax = max(a1,a2) */
265 ax = (first.address_time < second.address_time) ? second.address_time : first.address_time;
266
267 drdy = 2; /* DRDY is default 2 (by OPTi Databook) */
268
269 cycle1 = ((first.data_time-1)<<4) | (first.recovery_time-2);
270 cycle2 = ((second.data_time-1)<<4) | (second.recovery_time-2);
271 misc = READ_PREFETCH | ((ax-1)<<4) | ((drdy-2)<<1);
272
273#ifdef OPTI621_DEBUG
274 printk("%s: master: address: %d, data: %d, "
275 "recovery: %d, drdy: %d [clk]\n",
276 hwif->name, ax, first.data_time,
277 first.recovery_time, drdy);
278 printk("%s: slave: address: %d, data: %d, "
279 "recovery: %d, drdy: %d [clk]\n",
280 hwif->name, ax, second.data_time,
281 second.recovery_time, drdy);
282#endif
283
284 spin_lock_irqsave(&ide_lock, flags);
285
286 reg_base = hwif->io_ports[IDE_DATA_OFFSET];
287
288 /* allow Register-B */
289 hwif->OUTB(0xc0, reg_base+CNTRL_REG);
290 /* hmm, setupvic.exe does this ;-) */
291 hwif->OUTB(0xff, reg_base+5);
292 /* if reads 0xff, adapter not exist? */
293 (void) hwif->INB(reg_base+CNTRL_REG);
294 /* if reads 0xc0, no interface exist? */
295 read_reg(hwif, CNTRL_REG);
296 /* read version, probably 0 */
297 read_reg(hwif, STRAP_REG);
298
299 /* program primary drive */
300 /* select Index-0 for Register-A */
301 write_reg(hwif, 0, MISC_REG);
302 /* set read cycle timings */
303 write_reg(hwif, cycle1, READ_REG);
304 /* set write cycle timings */
305 write_reg(hwif, cycle1, WRITE_REG);
306
307 /* program secondary drive */
308 /* select Index-1 for Register-B */
309 write_reg(hwif, 1, MISC_REG);
310 /* set read cycle timings */
311 write_reg(hwif, cycle2, READ_REG);
312 /* set write cycle timings */
313 write_reg(hwif, cycle2, WRITE_REG);
314
315 /* use Register-A for drive 0 */
316 /* use Register-B for drive 1 */
317 write_reg(hwif, 0x85, CNTRL_REG);
318
319 /* set address setup, DRDY timings, */
320 /* and read prefetch for both drives */
321 write_reg(hwif, misc, MISC_REG);
322
323 spin_unlock_irqrestore(&ide_lock, flags);
324}
325
326/*
327 * init_hwif_opti621() is called once for each hwif found at boot.
328 */
329static void __init init_hwif_opti621 (ide_hwif_t *hwif)
330{
331 hwif->autodma = 0;
332 hwif->drives[0].drive_data = PIO_DONT_KNOW;
333 hwif->drives[1].drive_data = PIO_DONT_KNOW;
334 hwif->tuneproc = &opti621_tune_drive;
335
336 if (!(hwif->dma_base))
337 return;
338
339 hwif->atapi_dma = 1;
340 hwif->mwdma_mask = 0x07;
341 hwif->swdma_mask = 0x07;
342
343 if (!noautodma)
344 hwif->autodma = 1;
345 hwif->drives[0].autodma = hwif->autodma;
346 hwif->drives[1].autodma = hwif->autodma;
347}
348
349static ide_pci_device_t opti621_chipsets[] __devinitdata = {
350 { /* 0 */
351 .name = "OPTI621",
352 .init_hwif = init_hwif_opti621,
353 .channels = 2,
354 .autodma = AUTODMA,
355 .enablebits = {{0x45,0x80,0x00}, {0x40,0x08,0x00}},
356 .bootable = ON_BOARD,
357 },{ /* 1 */
358 .name = "OPTI621X",
359 .init_hwif = init_hwif_opti621,
360 .channels = 2,
361 .autodma = AUTODMA,
362 .enablebits = {{0x45,0x80,0x00}, {0x40,0x08,0x00}},
363 .bootable = ON_BOARD,
364 }
365};
366
367static int __devinit opti621_init_one(struct pci_dev *dev, const struct pci_device_id *id)
368{
369 return ide_setup_pci_device(dev, &opti621_chipsets[id->driver_data]);
370}
371
372static struct pci_device_id opti621_pci_tbl[] = {
373 { PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
374 { PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
375 { 0, },
376};
377MODULE_DEVICE_TABLE(pci, opti621_pci_tbl);
378
379static struct pci_driver driver = {
380 .name = "Opti621_IDE",
381 .id_table = opti621_pci_tbl,
382 .probe = opti621_init_one,
383};
384
385static int opti621_ide_init(void)
386{
387 return ide_pci_register_driver(&driver);
388}
389
390module_init(opti621_ide_init);
391
392MODULE_AUTHOR("Jaromir Koutek, Jan Harkes, Mark Lord");
393MODULE_DESCRIPTION("PCI driver module for Opti621 IDE");
394MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/pdc202xx_new.c b/drivers/ide/pci/pdc202xx_new.c
new file mode 100644
index 000000000000..211641a54398
--- /dev/null
+++ b/drivers/ide/pci/pdc202xx_new.c
@@ -0,0 +1,508 @@
1/*
2 * Promise TX2/TX4/TX2000/133 IDE driver
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * Split from:
10 * linux/drivers/ide/pdc202xx.c Version 0.35 Mar. 30, 2002
11 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
12 * Portions Copyright (C) 1999 Promise Technology, Inc.
13 * Author: Frank Tiernan (frankt@promise.com)
14 * Released under terms of General Public License
15 */
16
17#include <linux/config.h>
18#include <linux/module.h>
19#include <linux/types.h>
20#include <linux/kernel.h>
21#include <linux/delay.h>
22#include <linux/timer.h>
23#include <linux/mm.h>
24#include <linux/ioport.h>
25#include <linux/blkdev.h>
26#include <linux/hdreg.h>
27#include <linux/interrupt.h>
28#include <linux/pci.h>
29#include <linux/init.h>
30#include <linux/ide.h>
31
32#include <asm/io.h>
33#include <asm/irq.h>
34
35#ifdef CONFIG_PPC_PMAC
36#include <asm/prom.h>
37#include <asm/pci-bridge.h>
38#endif
39
40#define PDC202_DEBUG_CABLE 0
41
42const static char *pdc_quirk_drives[] = {
43 "QUANTUM FIREBALLlct08 08",
44 "QUANTUM FIREBALLP KA6.4",
45 "QUANTUM FIREBALLP KA9.1",
46 "QUANTUM FIREBALLP LM20.4",
47 "QUANTUM FIREBALLP KX13.6",
48 "QUANTUM FIREBALLP KX20.5",
49 "QUANTUM FIREBALLP KX27.3",
50 "QUANTUM FIREBALLP LM20.5",
51 NULL
52};
53
54#define set_2regs(a, b) \
55 do { \
56 hwif->OUTB((a + adj), indexreg); \
57 hwif->OUTB(b, datareg); \
58 } while(0)
59
60#define set_ultra(a, b, c) \
61 do { \
62 set_2regs(0x10,(a)); \
63 set_2regs(0x11,(b)); \
64 set_2regs(0x12,(c)); \
65 } while(0)
66
67#define set_ata2(a, b) \
68 do { \
69 set_2regs(0x0e,(a)); \
70 set_2regs(0x0f,(b)); \
71 } while(0)
72
73#define set_pio(a, b, c) \
74 do { \
75 set_2regs(0x0c,(a)); \
76 set_2regs(0x0d,(b)); \
77 set_2regs(0x13,(c)); \
78 } while(0)
79
80static u8 pdcnew_ratemask (ide_drive_t *drive)
81{
82 u8 mode;
83
84 switch(HWIF(drive)->pci_dev->device) {
85 case PCI_DEVICE_ID_PROMISE_20277:
86 case PCI_DEVICE_ID_PROMISE_20276:
87 case PCI_DEVICE_ID_PROMISE_20275:
88 case PCI_DEVICE_ID_PROMISE_20271:
89 case PCI_DEVICE_ID_PROMISE_20269:
90 mode = 4;
91 break;
92 case PCI_DEVICE_ID_PROMISE_20270:
93 case PCI_DEVICE_ID_PROMISE_20268:
94 mode = 3;
95 break;
96 default:
97 return 0;
98 }
99 if (!eighty_ninty_three(drive))
100 mode = min(mode, (u8)1);
101 return mode;
102}
103
104static int check_in_drive_lists (ide_drive_t *drive, const char **list)
105{
106 struct hd_driveid *id = drive->id;
107
108 if (pdc_quirk_drives == list) {
109 while (*list) {
110 if (strstr(id->model, *list++)) {
111 return 2;
112 }
113 }
114 } else {
115 while (*list) {
116 if (!strcmp(*list++,id->model)) {
117 return 1;
118 }
119 }
120 }
121 return 0;
122}
123
124static int pdcnew_new_tune_chipset (ide_drive_t *drive, u8 xferspeed)
125{
126 ide_hwif_t *hwif = HWIF(drive);
127 unsigned long indexreg = hwif->dma_vendor1;
128 unsigned long datareg = hwif->dma_vendor3;
129 u8 thold = 0x10;
130 u8 adj = (drive->dn%2) ? 0x08 : 0x00;
131 u8 speed = ide_rate_filter(pdcnew_ratemask(drive), xferspeed);
132
133 if (speed == XFER_UDMA_2) {
134 hwif->OUTB((thold + adj), indexreg);
135 hwif->OUTB((hwif->INB(datareg) & 0x7f), datareg);
136 }
137
138 switch (speed) {
139 case XFER_UDMA_7:
140 speed = XFER_UDMA_6;
141 case XFER_UDMA_6: set_ultra(0x1a, 0x01, 0xcb); break;
142 case XFER_UDMA_5: set_ultra(0x1a, 0x02, 0xcb); break;
143 case XFER_UDMA_4: set_ultra(0x1a, 0x03, 0xcd); break;
144 case XFER_UDMA_3: set_ultra(0x1a, 0x05, 0xcd); break;
145 case XFER_UDMA_2: set_ultra(0x2a, 0x07, 0xcd); break;
146 case XFER_UDMA_1: set_ultra(0x3a, 0x0a, 0xd0); break;
147 case XFER_UDMA_0: set_ultra(0x4a, 0x0f, 0xd5); break;
148 case XFER_MW_DMA_2: set_ata2(0x69, 0x25); break;
149 case XFER_MW_DMA_1: set_ata2(0x6b, 0x27); break;
150 case XFER_MW_DMA_0: set_ata2(0xdf, 0x5f); break;
151 case XFER_PIO_4: set_pio(0x23, 0x09, 0x25); break;
152 case XFER_PIO_3: set_pio(0x27, 0x0d, 0x35); break;
153 case XFER_PIO_2: set_pio(0x23, 0x26, 0x64); break;
154 case XFER_PIO_1: set_pio(0x46, 0x29, 0xa4); break;
155 case XFER_PIO_0: set_pio(0xfb, 0x2b, 0xac); break;
156 default:
157 ;
158 }
159
160 return (ide_config_drive_speed(drive, speed));
161}
162
163/* 0 1 2 3 4 5 6 7 8
164 * 960, 480, 390, 300, 240, 180, 120, 90, 60
165 * 180, 150, 120, 90, 60
166 * DMA_Speed
167 * 180, 120, 90, 90, 90, 60, 30
168 * 11, 5, 4, 3, 2, 1, 0
169 */
170static void pdcnew_tune_drive(ide_drive_t *drive, u8 pio)
171{
172 u8 speed;
173
174 if (pio == 5) pio = 4;
175 speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, pio, NULL);
176
177 (void)pdcnew_new_tune_chipset(drive, speed);
178}
179
180static u8 pdcnew_new_cable_detect (ide_hwif_t *hwif)
181{
182 hwif->OUTB(0x0b, hwif->dma_vendor1);
183 return ((u8)((hwif->INB(hwif->dma_vendor3) & 0x04)));
184}
185static int config_chipset_for_dma (ide_drive_t *drive)
186{
187 struct hd_driveid *id = drive->id;
188 ide_hwif_t *hwif = HWIF(drive);
189 u8 speed = -1;
190 u8 cable;
191
192 u8 ultra_66 = ((id->dma_ultra & 0x0010) ||
193 (id->dma_ultra & 0x0008)) ? 1 : 0;
194
195 cable = pdcnew_new_cable_detect(hwif);
196
197 if (ultra_66 && cable) {
198 printk(KERN_WARNING "Warning: %s channel requires an 80-pin cable for operation.\n", hwif->channel ? "Secondary":"Primary");
199 printk(KERN_WARNING "%s reduced to Ultra33 mode.\n", drive->name);
200 }
201
202 if (drive->media != ide_disk)
203 return 0;
204 if (id->capability & 4) { /* IORDY_EN & PREFETCH_EN */
205 hwif->OUTB((0x13 + ((drive->dn%2) ? 0x08 : 0x00)), hwif->dma_vendor1);
206 hwif->OUTB((hwif->INB(hwif->dma_vendor3)|0x03), hwif->dma_vendor3);
207 }
208
209 speed = ide_dma_speed(drive, pdcnew_ratemask(drive));
210
211 if (!(speed)) {
212 hwif->tuneproc(drive, 5);
213 return 0;
214 }
215
216 (void) hwif->speedproc(drive, speed);
217 return ide_dma_enable(drive);
218}
219
220static int pdcnew_config_drive_xfer_rate (ide_drive_t *drive)
221{
222 ide_hwif_t *hwif = HWIF(drive);
223 struct hd_driveid *id = drive->id;
224
225 drive->init_speed = 0;
226
227 if (id && (id->capability & 1) && drive->autodma) {
228
229 if (ide_use_dma(drive)) {
230 if (config_chipset_for_dma(drive))
231 return hwif->ide_dma_on(drive);
232 }
233
234 goto fast_ata_pio;
235
236 } else if ((id->capability & 8) || (id->field_valid & 2)) {
237fast_ata_pio:
238 hwif->tuneproc(drive, 5);
239 return hwif->ide_dma_off_quietly(drive);
240 }
241 /* IORDY not supported */
242 return 0;
243}
244
245static int pdcnew_quirkproc (ide_drive_t *drive)
246{
247 return ((int) check_in_drive_lists(drive, pdc_quirk_drives));
248}
249
250static int pdcnew_ide_dma_lostirq(ide_drive_t *drive)
251{
252 if (HWIF(drive)->resetproc != NULL)
253 HWIF(drive)->resetproc(drive);
254 return __ide_dma_lostirq(drive);
255}
256
257static int pdcnew_ide_dma_timeout(ide_drive_t *drive)
258{
259 if (HWIF(drive)->resetproc != NULL)
260 HWIF(drive)->resetproc(drive);
261 return __ide_dma_timeout(drive);
262}
263
264static void pdcnew_new_reset (ide_drive_t *drive)
265{
266 /*
267 * Deleted this because it is redundant from the caller.
268 */
269 printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
270 HWIF(drive)->channel ? "Secondary" : "Primary");
271}
272
273#ifdef CONFIG_PPC_PMAC
274static void __devinit apple_kiwi_init(struct pci_dev *pdev)
275{
276 struct device_node *np = pci_device_to_OF_node(pdev);
277 unsigned int class_rev = 0;
278 void __iomem *mmio;
279 u8 conf;
280
281 if (np == NULL || !device_is_compatible(np, "kiwi-root"))
282 return;
283
284 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
285 class_rev &= 0xff;
286
287 if (class_rev >= 0x03) {
288 /* Setup chip magic config stuff (from darwin) */
289 pci_read_config_byte(pdev, 0x40, &conf);
290 pci_write_config_byte(pdev, 0x40, conf | 0x01);
291 }
292 mmio = ioremap(pci_resource_start(pdev, 5),
293 pci_resource_len(pdev, 5));
294
295 /* Setup some PLL stuffs */
296 switch (pdev->device) {
297 case PCI_DEVICE_ID_PROMISE_20270:
298 writew(0x0d2b, mmio + 0x1202);
299 mdelay(30);
300 break;
301 case PCI_DEVICE_ID_PROMISE_20271:
302 writew(0x0826, mmio + 0x1202);
303 mdelay(30);
304 break;
305 }
306
307 iounmap(mmio);
308}
309#endif /* CONFIG_PPC_PMAC */
310
311static unsigned int __devinit init_chipset_pdcnew(struct pci_dev *dev, const char *name)
312{
313 if (dev->resource[PCI_ROM_RESOURCE].start) {
314 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
315 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
316 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n",
317 name, dev->resource[PCI_ROM_RESOURCE].start);
318 }
319
320#ifdef CONFIG_PPC_PMAC
321 apple_kiwi_init(dev);
322#endif
323
324 return dev->irq;
325}
326
327static void __devinit init_hwif_pdc202new(ide_hwif_t *hwif)
328{
329 hwif->autodma = 0;
330
331 hwif->tuneproc = &pdcnew_tune_drive;
332 hwif->quirkproc = &pdcnew_quirkproc;
333 hwif->speedproc = &pdcnew_new_tune_chipset;
334 hwif->resetproc = &pdcnew_new_reset;
335
336 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
337
338 hwif->ultra_mask = 0x7f;
339 hwif->mwdma_mask = 0x07;
340
341 hwif->ide_dma_check = &pdcnew_config_drive_xfer_rate;
342 hwif->ide_dma_lostirq = &pdcnew_ide_dma_lostirq;
343 hwif->ide_dma_timeout = &pdcnew_ide_dma_timeout;
344 if (!(hwif->udma_four))
345 hwif->udma_four = (pdcnew_new_cable_detect(hwif)) ? 0 : 1;
346 if (!noautodma)
347 hwif->autodma = 1;
348 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
349#if PDC202_DEBUG_CABLE
350 printk(KERN_DEBUG "%s: %s-pin cable\n",
351 hwif->name, hwif->udma_four ? "80" : "40");
352#endif /* PDC202_DEBUG_CABLE */
353}
354
355static int __devinit init_setup_pdcnew(struct pci_dev *dev, ide_pci_device_t *d)
356{
357 return ide_setup_pci_device(dev, d);
358}
359
360static int __devinit init_setup_pdc20270(struct pci_dev *dev,
361 ide_pci_device_t *d)
362{
363 struct pci_dev *findev = NULL;
364
365 if ((dev->bus->self &&
366 dev->bus->self->vendor == PCI_VENDOR_ID_DEC) &&
367 (dev->bus->self->device == PCI_DEVICE_ID_DEC_21150)) {
368 if (PCI_SLOT(dev->devfn) & 2)
369 return -ENODEV;
370 d->extra = 0;
371 while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
372 if ((findev->vendor == dev->vendor) &&
373 (findev->device == dev->device) &&
374 (PCI_SLOT(findev->devfn) & 2)) {
375 if (findev->irq != dev->irq) {
376 findev->irq = dev->irq;
377 }
378 return ide_setup_pci_devices(dev, findev, d);
379 }
380 }
381 }
382 return ide_setup_pci_device(dev, d);
383}
384
385static int __devinit init_setup_pdc20276(struct pci_dev *dev,
386 ide_pci_device_t *d)
387{
388 if ((dev->bus->self) &&
389 (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
390 ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
391 (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
392 printk(KERN_INFO "ide: Skipping Promise PDC20276 "
393 "attached to I2O RAID controller.\n");
394 return -ENODEV;
395 }
396 return ide_setup_pci_device(dev, d);
397}
398
399static ide_pci_device_t pdcnew_chipsets[] __devinitdata = {
400 { /* 0 */
401 .name = "PDC20268",
402 .init_setup = init_setup_pdcnew,
403 .init_chipset = init_chipset_pdcnew,
404 .init_hwif = init_hwif_pdc202new,
405 .channels = 2,
406 .autodma = AUTODMA,
407 .bootable = OFF_BOARD,
408 },{ /* 1 */
409 .name = "PDC20269",
410 .init_setup = init_setup_pdcnew,
411 .init_chipset = init_chipset_pdcnew,
412 .init_hwif = init_hwif_pdc202new,
413 .channels = 2,
414 .autodma = AUTODMA,
415 .bootable = OFF_BOARD,
416 },{ /* 2 */
417 .name = "PDC20270",
418 .init_setup = init_setup_pdc20270,
419 .init_chipset = init_chipset_pdcnew,
420 .init_hwif = init_hwif_pdc202new,
421 .channels = 2,
422 .autodma = AUTODMA,
423#ifndef CONFIG_PDC202XX_FORCE
424 .enablebits = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
425#endif
426 .bootable = OFF_BOARD,
427 },{ /* 3 */
428 .name = "PDC20271",
429 .init_setup = init_setup_pdcnew,
430 .init_chipset = init_chipset_pdcnew,
431 .init_hwif = init_hwif_pdc202new,
432 .channels = 2,
433 .autodma = AUTODMA,
434 .bootable = OFF_BOARD,
435 },{ /* 4 */
436 .name = "PDC20275",
437 .init_setup = init_setup_pdcnew,
438 .init_chipset = init_chipset_pdcnew,
439 .init_hwif = init_hwif_pdc202new,
440 .channels = 2,
441 .autodma = AUTODMA,
442 .bootable = OFF_BOARD,
443 },{ /* 5 */
444 .name = "PDC20276",
445 .init_setup = init_setup_pdc20276,
446 .init_chipset = init_chipset_pdcnew,
447 .init_hwif = init_hwif_pdc202new,
448 .channels = 2,
449 .autodma = AUTODMA,
450#ifndef CONFIG_PDC202XX_FORCE
451 .enablebits = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
452#endif
453 .bootable = OFF_BOARD,
454 },{ /* 6 */
455 .name = "PDC20277",
456 .init_setup = init_setup_pdcnew,
457 .init_chipset = init_chipset_pdcnew,
458 .init_hwif = init_hwif_pdc202new,
459 .channels = 2,
460 .autodma = AUTODMA,
461 .bootable = OFF_BOARD,
462 }
463};
464
465/**
466 * pdc202new_init_one - called when a pdc202xx is found
467 * @dev: the pdc202new device
468 * @id: the matching pci id
469 *
470 * Called when the PCI registration layer (or the IDE initialization)
471 * finds a device matching our IDE device tables.
472 */
473
474static int __devinit pdc202new_init_one(struct pci_dev *dev, const struct pci_device_id *id)
475{
476 ide_pci_device_t *d = &pdcnew_chipsets[id->driver_data];
477
478 return d->init_setup(dev, d);
479}
480
481static struct pci_device_id pdc202new_pci_tbl[] = {
482 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20268, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
483 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20269, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
484 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20270, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
485 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20271, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
486 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20275, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
487 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20276, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
488 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20277, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6},
489 { 0, },
490};
491MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);
492
493static struct pci_driver driver = {
494 .name = "Promise_IDE",
495 .id_table = pdc202new_pci_tbl,
496 .probe = pdc202new_init_one,
497};
498
499static int pdc202new_ide_init(void)
500{
501 return ide_pci_register_driver(&driver);
502}
503
504module_init(pdc202new_ide_init);
505
506MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
507MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
508MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/pdc202xx_old.c b/drivers/ide/pci/pdc202xx_old.c
new file mode 100644
index 000000000000..ad9d95817f95
--- /dev/null
+++ b/drivers/ide/pci/pdc202xx_old.c
@@ -0,0 +1,892 @@
1/*
2 * linux/drivers/ide/pci/pdc202xx_old.c Version 0.36 Sept 11, 2002
3 *
4 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
5 *
6 * Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
7 * compiled into the kernel if you have more than one card installed.
8 * Note that BIOS v1.29 is reported to fix the problem. Since this is
9 * safe chipset tuning, including this support is harmless
10 *
11 * Promise Ultra66 cards with BIOS v1.11 this
12 * compiled into the kernel if you have more than one card installed.
13 *
14 * Promise Ultra100 cards.
15 *
16 * The latest chipset code will support the following ::
17 * Three Ultra33 controllers and 12 drives.
18 * 8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
19 * The 8/4 ratio is a BIOS code limit by promise.
20 *
21 * UNLESS you enable "CONFIG_PDC202XX_BURST"
22 *
23 */
24
25/*
26 * Portions Copyright (C) 1999 Promise Technology, Inc.
27 * Author: Frank Tiernan (frankt@promise.com)
28 * Released under terms of General Public License
29 */
30
31#include <linux/config.h>
32#include <linux/types.h>
33#include <linux/module.h>
34#include <linux/kernel.h>
35#include <linux/delay.h>
36#include <linux/timer.h>
37#include <linux/mm.h>
38#include <linux/ioport.h>
39#include <linux/blkdev.h>
40#include <linux/hdreg.h>
41#include <linux/interrupt.h>
42#include <linux/pci.h>
43#include <linux/init.h>
44#include <linux/ide.h>
45
46#include <asm/io.h>
47#include <asm/irq.h>
48
49#define PDC202_DEBUG_CABLE 0
50#define PDC202XX_DEBUG_DRIVE_INFO 0
51
52static const char *pdc_quirk_drives[] = {
53 "QUANTUM FIREBALLlct08 08",
54 "QUANTUM FIREBALLP KA6.4",
55 "QUANTUM FIREBALLP KA9.1",
56 "QUANTUM FIREBALLP LM20.4",
57 "QUANTUM FIREBALLP KX13.6",
58 "QUANTUM FIREBALLP KX20.5",
59 "QUANTUM FIREBALLP KX27.3",
60 "QUANTUM FIREBALLP LM20.5",
61 NULL
62};
63
64/* A Register */
65#define SYNC_ERRDY_EN 0xC0
66
67#define SYNC_IN 0x80 /* control bit, different for master vs. slave drives */
68#define ERRDY_EN 0x40 /* control bit, different for master vs. slave drives */
69#define IORDY_EN 0x20 /* PIO: IOREADY */
70#define PREFETCH_EN 0x10 /* PIO: PREFETCH */
71
72#define PA3 0x08 /* PIO"A" timing */
73#define PA2 0x04 /* PIO"A" timing */
74#define PA1 0x02 /* PIO"A" timing */
75#define PA0 0x01 /* PIO"A" timing */
76
77/* B Register */
78
79#define MB2 0x80 /* DMA"B" timing */
80#define MB1 0x40 /* DMA"B" timing */
81#define MB0 0x20 /* DMA"B" timing */
82
83#define PB4 0x10 /* PIO_FORCE 1:0 */
84
85#define PB3 0x08 /* PIO"B" timing */ /* PIO flow Control mode */
86#define PB2 0x04 /* PIO"B" timing */ /* PIO 4 */
87#define PB1 0x02 /* PIO"B" timing */ /* PIO 3 half */
88#define PB0 0x01 /* PIO"B" timing */ /* PIO 3 other half */
89
90/* C Register */
91#define IORDYp_NO_SPEED 0x4F
92#define SPEED_DIS 0x0F
93
94#define DMARQp 0x80
95#define IORDYp 0x40
96#define DMAR_EN 0x20
97#define DMAW_EN 0x10
98
99#define MC3 0x08 /* DMA"C" timing */
100#define MC2 0x04 /* DMA"C" timing */
101#define MC1 0x02 /* DMA"C" timing */
102#define MC0 0x01 /* DMA"C" timing */
103
104#if 0
105 unsigned long bibma = pci_resource_start(dev, 4);
106 u8 hi = 0, lo = 0;
107
108 u8 sc1c = inb_p((u16)bibma + 0x1c);
109 u8 sc1e = inb_p((u16)bibma + 0x1e);
110 u8 sc1f = inb_p((u16)bibma + 0x1f);
111
112 p += sprintf(p, "Host Mode : %s\n",
113 (sc1f & 0x08) ? "Tri-Stated" : "Normal");
114 p += sprintf(p, "Bus Clocking : %s\n",
115 ((sc1f & 0xC0) == 0xC0) ? "100 External" :
116 ((sc1f & 0x80) == 0x80) ? "66 External" :
117 ((sc1f & 0x40) == 0x40) ? "33 External" : "33 PCI Internal");
118 p += sprintf(p, "IO pad select : %s mA\n",
119 ((sc1c & 0x03) == 0x03) ? "10" :
120 ((sc1c & 0x02) == 0x02) ? "8" :
121 ((sc1c & 0x01) == 0x01) ? "6" :
122 ((sc1c & 0x00) == 0x00) ? "4" : "??");
123 hi = sc1e >> 4;
124 lo = sc1e & 0xf;
125 p += sprintf(p, "Status Polling Period : %d\n", hi);
126 p += sprintf(p, "Interrupt Check Status Polling Delay : %d\n", lo);
127#endif
128
129static u8 pdc202xx_ratemask (ide_drive_t *drive)
130{
131 u8 mode;
132
133 switch(HWIF(drive)->pci_dev->device) {
134 case PCI_DEVICE_ID_PROMISE_20267:
135 case PCI_DEVICE_ID_PROMISE_20265:
136 mode = 3;
137 break;
138 case PCI_DEVICE_ID_PROMISE_20263:
139 case PCI_DEVICE_ID_PROMISE_20262:
140 mode = 2;
141 break;
142 case PCI_DEVICE_ID_PROMISE_20246:
143 return 1;
144 default:
145 return 0;
146 }
147 if (!eighty_ninty_three(drive))
148 mode = min(mode, (u8)1);
149 return mode;
150}
151
152static int check_in_drive_lists (ide_drive_t *drive, const char **list)
153{
154 struct hd_driveid *id = drive->id;
155
156 if (pdc_quirk_drives == list) {
157 while (*list) {
158 if (strstr(id->model, *list++)) {
159 return 2;
160 }
161 }
162 } else {
163 while (*list) {
164 if (!strcmp(*list++,id->model)) {
165 return 1;
166 }
167 }
168 }
169 return 0;
170}
171
172static int pdc202xx_tune_chipset (ide_drive_t *drive, u8 xferspeed)
173{
174 ide_hwif_t *hwif = HWIF(drive);
175 struct pci_dev *dev = hwif->pci_dev;
176 u8 drive_pci = 0x60 + (drive->dn << 2);
177 u8 speed = ide_rate_filter(pdc202xx_ratemask(drive), xferspeed);
178
179 u32 drive_conf;
180 u8 AP, BP, CP, DP;
181 u8 TA = 0, TB = 0, TC = 0;
182
183 if ((drive->media != ide_disk) && (speed < XFER_SW_DMA_0))
184 return -1;
185
186 pci_read_config_dword(dev, drive_pci, &drive_conf);
187 pci_read_config_byte(dev, (drive_pci), &AP);
188 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
189 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
190 pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
191
192 if (speed < XFER_SW_DMA_0) {
193 if ((AP & 0x0F) || (BP & 0x07)) {
194 /* clear PIO modes of lower 8421 bits of A Register */
195 pci_write_config_byte(dev, (drive_pci), AP &~0x0F);
196 pci_read_config_byte(dev, (drive_pci), &AP);
197
198 /* clear PIO modes of lower 421 bits of B Register */
199 pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0x07);
200 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
201
202 pci_read_config_byte(dev, (drive_pci), &AP);
203 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
204 }
205 } else {
206 if ((BP & 0xF0) && (CP & 0x0F)) {
207 /* clear DMA modes of upper 842 bits of B Register */
208 /* clear PIO forced mode upper 1 bit of B Register */
209 pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0xF0);
210 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
211
212 /* clear DMA modes of lower 8421 bits of C Register */
213 pci_write_config_byte(dev, (drive_pci)|0x02, CP &~0x0F);
214 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
215 }
216 }
217
218 pci_read_config_byte(dev, (drive_pci), &AP);
219 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
220 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
221
222 switch(speed) {
223 case XFER_UDMA_6: speed = XFER_UDMA_5;
224 case XFER_UDMA_5:
225 case XFER_UDMA_4: TB = 0x20; TC = 0x01; break;
226 case XFER_UDMA_2: TB = 0x20; TC = 0x01; break;
227 case XFER_UDMA_3:
228 case XFER_UDMA_1: TB = 0x40; TC = 0x02; break;
229 case XFER_UDMA_0:
230 case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
231 case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
232 case XFER_MW_DMA_0:
233 case XFER_SW_DMA_2: TB = 0x60; TC = 0x05; break;
234 case XFER_SW_DMA_1: TB = 0x80; TC = 0x06; break;
235 case XFER_SW_DMA_0: TB = 0xC0; TC = 0x0B; break;
236 case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
237 case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
238 case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
239 case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
240 case XFER_PIO_0:
241 default: TA = 0x09; TB = 0x13; break;
242 }
243
244 if (speed < XFER_SW_DMA_0) {
245 pci_write_config_byte(dev, (drive_pci), AP|TA);
246 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
247 } else {
248 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
249 pci_write_config_byte(dev, (drive_pci)|0x02, CP|TC);
250 }
251
252#if PDC202XX_DEBUG_DRIVE_INFO
253 printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
254 drive->name, ide_xfer_verbose(speed),
255 drive->dn, drive_conf);
256 pci_read_config_dword(dev, drive_pci, &drive_conf);
257 printk("0x%08x\n", drive_conf);
258#endif /* PDC202XX_DEBUG_DRIVE_INFO */
259
260 return (ide_config_drive_speed(drive, speed));
261}
262
263
264/* 0 1 2 3 4 5 6 7 8
265 * 960, 480, 390, 300, 240, 180, 120, 90, 60
266 * 180, 150, 120, 90, 60
267 * DMA_Speed
268 * 180, 120, 90, 90, 90, 60, 30
269 * 11, 5, 4, 3, 2, 1, 0
270 */
271static void config_chipset_for_pio (ide_drive_t *drive, u8 pio)
272{
273 u8 speed = 0;
274
275 if (pio == 5) pio = 4;
276 speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, pio, NULL);
277
278 pdc202xx_tune_chipset(drive, speed);
279}
280
281static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
282{
283 u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);
284 pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
285 return (CIS & mask) ? 1 : 0;
286}
287
288/*
289 * Set the control register to use the 66MHz system
290 * clock for UDMA 3/4/5 mode operation when necessary.
291 *
292 * It may also be possible to leave the 66MHz clock on
293 * and readjust the timing parameters.
294 */
295static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
296{
297 unsigned long clock_reg = hwif->dma_master + 0x11;
298 u8 clock = hwif->INB(clock_reg);
299
300 hwif->OUTB(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
301}
302
303static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
304{
305 unsigned long clock_reg = hwif->dma_master + 0x11;
306 u8 clock = hwif->INB(clock_reg);
307
308 hwif->OUTB(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
309}
310
311static int config_chipset_for_dma (ide_drive_t *drive)
312{
313 struct hd_driveid *id = drive->id;
314 ide_hwif_t *hwif = HWIF(drive);
315 struct pci_dev *dev = hwif->pci_dev;
316 u32 drive_conf = 0;
317 u8 drive_pci = 0x60 + (drive->dn << 2);
318 u8 test1 = 0, test2 = 0, speed = -1;
319 u8 AP = 0, cable = 0;
320
321 u8 ultra_66 = ((id->dma_ultra & 0x0010) ||
322 (id->dma_ultra & 0x0008)) ? 1 : 0;
323
324 if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
325 cable = pdc202xx_old_cable_detect(hwif);
326 else
327 ultra_66 = 0;
328
329 if (ultra_66 && cable) {
330 printk(KERN_WARNING "Warning: %s channel requires an 80-pin cable for operation.\n", hwif->channel ? "Secondary":"Primary");
331 printk(KERN_WARNING "%s reduced to Ultra33 mode.\n", drive->name);
332 }
333
334 if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
335 pdc_old_disable_66MHz_clock(drive->hwif);
336
337 drive_pci = 0x60 + (drive->dn << 2);
338 pci_read_config_dword(dev, drive_pci, &drive_conf);
339 if ((drive_conf != 0x004ff304) && (drive_conf != 0x004ff3c4))
340 goto chipset_is_set;
341
342 pci_read_config_byte(dev, drive_pci, &test1);
343 if (!(test1 & SYNC_ERRDY_EN)) {
344 if (drive->select.b.unit & 0x01) {
345 pci_read_config_byte(dev, drive_pci - 4, &test2);
346 if ((test2 & SYNC_ERRDY_EN) &&
347 !(test1 & SYNC_ERRDY_EN)) {
348 pci_write_config_byte(dev, drive_pci,
349 test1|SYNC_ERRDY_EN);
350 }
351 } else {
352 pci_write_config_byte(dev, drive_pci,
353 test1|SYNC_ERRDY_EN);
354 }
355 }
356
357chipset_is_set:
358
359 if (drive->media == ide_disk) {
360 pci_read_config_byte(dev, (drive_pci), &AP);
361 if (id->capability & 4) /* IORDY_EN */
362 pci_write_config_byte(dev, (drive_pci), AP|IORDY_EN);
363 pci_read_config_byte(dev, (drive_pci), &AP);
364 if (drive->media == ide_disk) /* PREFETCH_EN */
365 pci_write_config_byte(dev, (drive_pci), AP|PREFETCH_EN);
366 }
367
368 speed = ide_dma_speed(drive, pdc202xx_ratemask(drive));
369
370 if (!(speed)) {
371 /* restore original pci-config space */
372 pci_write_config_dword(dev, drive_pci, drive_conf);
373 hwif->tuneproc(drive, 5);
374 return 0;
375 }
376
377 (void) hwif->speedproc(drive, speed);
378 return ide_dma_enable(drive);
379}
380
381static int pdc202xx_config_drive_xfer_rate (ide_drive_t *drive)
382{
383 ide_hwif_t *hwif = HWIF(drive);
384 struct hd_driveid *id = drive->id;
385
386 drive->init_speed = 0;
387
388 if (id && (id->capability & 1) && drive->autodma) {
389
390 if (ide_use_dma(drive)) {
391 if (config_chipset_for_dma(drive))
392 return hwif->ide_dma_on(drive);
393 }
394
395 goto fast_ata_pio;
396
397 } else if ((id->capability & 8) || (id->field_valid & 2)) {
398fast_ata_pio:
399 hwif->tuneproc(drive, 5);
400 return hwif->ide_dma_off_quietly(drive);
401 }
402 /* IORDY not supported */
403 return 0;
404}
405
406static int pdc202xx_quirkproc (ide_drive_t *drive)
407{
408 return ((int) check_in_drive_lists(drive, pdc_quirk_drives));
409}
410
411static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
412{
413 if (drive->current_speed > XFER_UDMA_2)
414 pdc_old_enable_66MHz_clock(drive->hwif);
415 if (drive->addressing == 1) {
416 struct request *rq = HWGROUP(drive)->rq;
417 ide_hwif_t *hwif = HWIF(drive);
418// struct pci_dev *dev = hwif->pci_dev;
419// unsgned long high_16 = pci_resource_start(dev, 4);
420 unsigned long high_16 = hwif->dma_master;
421 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
422 u32 word_count = 0;
423 u8 clock = hwif->INB(high_16 + 0x11);
424
425 hwif->OUTB(clock|(hwif->channel ? 0x08 : 0x02), high_16+0x11);
426 word_count = (rq->nr_sectors << 8);
427 word_count = (rq_data_dir(rq) == READ) ?
428 word_count | 0x05000000 :
429 word_count | 0x06000000;
430 hwif->OUTL(word_count, atapi_reg);
431 }
432 ide_dma_start(drive);
433}
434
435static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
436{
437 if (drive->addressing == 1) {
438 ide_hwif_t *hwif = HWIF(drive);
439// unsigned long high_16 = pci_resource_start(hwif->pci_dev, 4);
440 unsigned long high_16 = hwif->dma_master;
441 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
442 u8 clock = 0;
443
444 hwif->OUTL(0, atapi_reg); /* zero out extra */
445 clock = hwif->INB(high_16 + 0x11);
446 hwif->OUTB(clock & ~(hwif->channel ? 0x08:0x02), high_16+0x11);
447 }
448 if (drive->current_speed > XFER_UDMA_2)
449 pdc_old_disable_66MHz_clock(drive->hwif);
450 return __ide_dma_end(drive);
451}
452
453static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
454{
455 ide_hwif_t *hwif = HWIF(drive);
456// struct pci_dev *dev = hwif->pci_dev;
457// unsigned long high_16 = pci_resource_start(dev, 4);
458 unsigned long high_16 = hwif->dma_master;
459 u8 dma_stat = hwif->INB(hwif->dma_status);
460 u8 sc1d = hwif->INB((high_16 + 0x001d));
461
462 if (hwif->channel) {
463 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
464 if ((sc1d & 0x50) == 0x50)
465 goto somebody_else;
466 else if ((sc1d & 0x40) == 0x40)
467 return (dma_stat & 4) == 4;
468 } else {
469 /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
470 if ((sc1d & 0x05) == 0x05)
471 goto somebody_else;
472 else if ((sc1d & 0x04) == 0x04)
473 return (dma_stat & 4) == 4;
474 }
475somebody_else:
476 return (dma_stat & 4) == 4; /* return 1 if INTR asserted */
477}
478
479static int pdc202xx_ide_dma_lostirq(ide_drive_t *drive)
480{
481 if (HWIF(drive)->resetproc != NULL)
482 HWIF(drive)->resetproc(drive);
483 return __ide_dma_lostirq(drive);
484}
485
486static int pdc202xx_ide_dma_timeout(ide_drive_t *drive)
487{
488 if (HWIF(drive)->resetproc != NULL)
489 HWIF(drive)->resetproc(drive);
490 return __ide_dma_timeout(drive);
491}
492
493static void pdc202xx_reset_host (ide_hwif_t *hwif)
494{
495#ifdef CONFIG_BLK_DEV_IDEDMA
496// unsigned long high_16 = hwif->dma_base - (8*(hwif->channel));
497 unsigned long high_16 = hwif->dma_master;
498#else /* !CONFIG_BLK_DEV_IDEDMA */
499 unsigned long high_16 = pci_resource_start(hwif->pci_dev, 4);
500#endif /* CONFIG_BLK_DEV_IDEDMA */
501 u8 udma_speed_flag = hwif->INB(high_16|0x001f);
502
503 hwif->OUTB((udma_speed_flag | 0x10), (high_16|0x001f));
504 mdelay(100);
505 hwif->OUTB((udma_speed_flag & ~0x10), (high_16|0x001f));
506 mdelay(2000); /* 2 seconds ?! */
507
508 printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
509 hwif->channel ? "Secondary" : "Primary");
510}
511
512static void pdc202xx_reset (ide_drive_t *drive)
513{
514 ide_hwif_t *hwif = HWIF(drive);
515 ide_hwif_t *mate = hwif->mate;
516
517 pdc202xx_reset_host(hwif);
518 pdc202xx_reset_host(mate);
519#if 0
520 /*
521 * FIXME: Have to kick all the drives again :-/
522 * What a pain in the ACE!
523 */
524 if (hwif->present) {
525 u16 hunit = 0;
526 for (hunit = 0; hunit < MAX_DRIVES; ++hunit) {
527 ide_drive_t *hdrive = &hwif->drives[hunit];
528 if (hdrive->present) {
529 if (hwif->ide_dma_check)
530 hwif->ide_dma_check(hdrive);
531 else
532 hwif->tuneproc(hdrive, 5);
533 }
534 }
535 }
536 if (mate->present) {
537 u16 munit = 0;
538 for (munit = 0; munit < MAX_DRIVES; ++munit) {
539 ide_drive_t *mdrive = &mate->drives[munit];
540 if (mdrive->present) {
541 if (mate->ide_dma_check)
542 mate->ide_dma_check(mdrive);
543 else
544 mate->tuneproc(mdrive, 5);
545 }
546 }
547 }
548#else
549 hwif->tuneproc(drive, 5);
550#endif
551}
552
553/*
554 * Since SUN Cobalt is attempting to do this operation, I should disclose
555 * this has been a long time ago Thu Jul 27 16:40:57 2000 was the patch date
556 * HOTSWAP ATA Infrastructure.
557 */
558static int pdc202xx_tristate (ide_drive_t * drive, int state)
559{
560 ide_hwif_t *hwif = HWIF(drive);
561// unsigned long high_16 = hwif->dma_base - (8*(hwif->channel));
562 unsigned long high_16 = hwif->dma_master;
563 u8 sc1f = hwif->INB(high_16|0x001f);
564
565 if (!hwif)
566 return -EINVAL;
567
568// hwif->bus_state = state;
569
570 if (state) {
571 hwif->OUTB(sc1f | 0x08, (high_16|0x001f));
572 } else {
573 hwif->OUTB(sc1f & ~0x08, (high_16|0x001f));
574 }
575 return 0;
576}
577
578static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev, const char *name)
579{
580 if (dev->resource[PCI_ROM_RESOURCE].start) {
581 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
582 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
583 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n",
584 name, dev->resource[PCI_ROM_RESOURCE].start);
585 }
586
587 /*
588 * software reset - this is required because the bios
589 * will set UDMA timing on if the hdd supports it. The
590 * user may want to turn udma off. A bug in the pdc20262
591 * is that it cannot handle a downgrade in timing from
592 * UDMA to DMA. Disk accesses after issuing a set
593 * feature command will result in errors. A software
594 * reset leaves the timing registers intact,
595 * but resets the drives.
596 */
597#if 0
598 if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
599 (dev->device == PCI_DEVICE_ID_PROMISE_20265) ||
600 (dev->device == PCI_DEVICE_ID_PROMISE_20263) ||
601 (dev->device == PCI_DEVICE_ID_PROMISE_20262)) {
602 unsigned long high_16 = pci_resource_start(dev, 4);
603 byte udma_speed_flag = inb(high_16 + 0x001f);
604 outb(udma_speed_flag | 0x10, high_16 + 0x001f);
605 mdelay(100);
606 outb(udma_speed_flag & ~0x10, high_16 + 0x001f);
607 mdelay(2000); /* 2 seconds ?! */
608 }
609
610#endif
611 return dev->irq;
612}
613
614static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
615{
616 struct pci_dev *dev = hwif->pci_dev;
617
618 /* PDC20265 has problems with large LBA48 requests */
619 if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
620 (dev->device == PCI_DEVICE_ID_PROMISE_20265))
621 hwif->rqsize = 256;
622
623 hwif->autodma = 0;
624 hwif->tuneproc = &config_chipset_for_pio;
625 hwif->quirkproc = &pdc202xx_quirkproc;
626
627 if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
628 hwif->busproc = &pdc202xx_tristate;
629 hwif->resetproc = &pdc202xx_reset;
630 }
631
632 hwif->speedproc = &pdc202xx_tune_chipset;
633
634 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
635
636 hwif->ultra_mask = 0x3f;
637 hwif->mwdma_mask = 0x07;
638 hwif->swdma_mask = 0x07;
639
640 hwif->ide_dma_check = &pdc202xx_config_drive_xfer_rate;
641 hwif->ide_dma_lostirq = &pdc202xx_ide_dma_lostirq;
642 hwif->ide_dma_timeout = &pdc202xx_ide_dma_timeout;
643
644 if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
645 if (!(hwif->udma_four))
646 hwif->udma_four = (pdc202xx_old_cable_detect(hwif)) ? 0 : 1;
647 hwif->dma_start = &pdc202xx_old_ide_dma_start;
648 hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
649 }
650 hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
651
652 if (!noautodma)
653 hwif->autodma = 1;
654 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
655#if PDC202_DEBUG_CABLE
656 printk(KERN_DEBUG "%s: %s-pin cable\n",
657 hwif->name, hwif->udma_four ? "80" : "40");
658#endif /* PDC202_DEBUG_CABLE */
659}
660
661static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
662{
663 u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
664
665 if (hwif->channel) {
666 ide_setup_dma(hwif, dmabase, 8);
667 return;
668 }
669
670 udma_speed_flag = hwif->INB((dmabase|0x1f));
671 primary_mode = hwif->INB((dmabase|0x1a));
672 secondary_mode = hwif->INB((dmabase|0x1b));
673 printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
674 "Primary %s Mode " \
675 "Secondary %s Mode.\n", hwif->cds->name,
676 (udma_speed_flag & 1) ? "EN" : "DIS",
677 (primary_mode & 1) ? "MASTER" : "PCI",
678 (secondary_mode & 1) ? "MASTER" : "PCI" );
679
680#ifdef CONFIG_PDC202XX_BURST
681 if (!(udma_speed_flag & 1)) {
682 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
683 hwif->cds->name, udma_speed_flag,
684 (udma_speed_flag|1));
685 hwif->OUTB(udma_speed_flag|1,(dmabase|0x1f));
686 printk("%sACTIVE\n",
687 (hwif->INB(dmabase|0x1f)&1) ? "":"IN");
688 }
689#endif /* CONFIG_PDC202XX_BURST */
690#ifdef CONFIG_PDC202XX_MASTER
691 if (!(primary_mode & 1)) {
692 printk(KERN_INFO "%s: FORCING PRIMARY MODE BIT "
693 "0x%02x -> 0x%02x ", hwif->cds->name,
694 primary_mode, (primary_mode|1));
695 hwif->OUTB(primary_mode|1, (dmabase|0x1a));
696 printk("%s\n",
697 (hwif->INB((dmabase|0x1a)) & 1) ? "MASTER" : "PCI");
698 }
699
700 if (!(secondary_mode & 1)) {
701 printk(KERN_INFO "%s: FORCING SECONDARY MODE BIT "
702 "0x%02x -> 0x%02x ", hwif->cds->name,
703 secondary_mode, (secondary_mode|1));
704 hwif->OUTB(secondary_mode|1, (dmabase|0x1b));
705 printk("%s\n",
706 (hwif->INB((dmabase|0x1b)) & 1) ? "MASTER" : "PCI");
707 }
708#endif /* CONFIG_PDC202XX_MASTER */
709
710 ide_setup_dma(hwif, dmabase, 8);
711}
712
713static int __devinit init_setup_pdc202ata4(struct pci_dev *dev,
714 ide_pci_device_t *d)
715{
716 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
717 u8 irq = 0, irq2 = 0;
718 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
719 /* 0xbc */
720 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
721 if (irq != irq2) {
722 pci_write_config_byte(dev,
723 (PCI_INTERRUPT_LINE)|0x80, irq); /* 0xbc */
724 printk(KERN_INFO "%s: pci-config space interrupt "
725 "mirror fixed.\n", d->name);
726 }
727 }
728
729#if 0
730 if (dev->device == PCI_DEVICE_ID_PROMISE_20262)
731 if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) ||
732 (tmp & e->mask) != e->val))
733
734 if (d->enablebits[0].reg != d->enablebits[1].reg) {
735 d->enablebits[0].reg = d->enablebits[1].reg;
736 d->enablebits[0].mask = d->enablebits[1].mask;
737 d->enablebits[0].val = d->enablebits[1].val;
738 }
739#endif
740
741 return ide_setup_pci_device(dev, d);
742}
743
744static int __devinit init_setup_pdc20265(struct pci_dev *dev,
745 ide_pci_device_t *d)
746{
747 if ((dev->bus->self) &&
748 (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
749 ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
750 (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
751 printk(KERN_INFO "ide: Skipping Promise PDC20265 "
752 "attached to I2O RAID controller.\n");
753 return -ENODEV;
754 }
755
756#if 0
757 {
758 u8 pri = 0, sec = 0;
759
760 if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) ||
761 (tmp & e->mask) != e->val))
762
763 if (d->enablebits[0].reg != d->enablebits[1].reg) {
764 d->enablebits[0].reg = d->enablebits[1].reg;
765 d->enablebits[0].mask = d->enablebits[1].mask;
766 d->enablebits[0].val = d->enablebits[1].val;
767 }
768 }
769#endif
770
771 return ide_setup_pci_device(dev, d);
772}
773
774static int __devinit init_setup_pdc202xx(struct pci_dev *dev,
775 ide_pci_device_t *d)
776{
777 return ide_setup_pci_device(dev, d);
778}
779
780static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
781 { /* 0 */
782 .name = "PDC20246",
783 .init_setup = init_setup_pdc202ata4,
784 .init_chipset = init_chipset_pdc202xx,
785 .init_hwif = init_hwif_pdc202xx,
786 .init_dma = init_dma_pdc202xx,
787 .channels = 2,
788 .autodma = AUTODMA,
789#ifndef CONFIG_PDC202XX_FORCE
790 .enablebits = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
791#endif
792 .bootable = OFF_BOARD,
793 .extra = 16,
794 },{ /* 1 */
795 .name = "PDC20262",
796 .init_setup = init_setup_pdc202ata4,
797 .init_chipset = init_chipset_pdc202xx,
798 .init_hwif = init_hwif_pdc202xx,
799 .init_dma = init_dma_pdc202xx,
800 .channels = 2,
801 .autodma = AUTODMA,
802#ifndef CONFIG_PDC202XX_FORCE
803 .enablebits = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
804#endif
805 .bootable = OFF_BOARD,
806 .extra = 48,
807 .flags = IDEPCI_FLAG_FORCE_PDC,
808 },{ /* 2 */
809 .name = "PDC20263",
810 .init_setup = init_setup_pdc202ata4,
811 .init_chipset = init_chipset_pdc202xx,
812 .init_hwif = init_hwif_pdc202xx,
813 .init_dma = init_dma_pdc202xx,
814 .channels = 2,
815 .autodma = AUTODMA,
816#ifndef CONFIG_PDC202XX_FORCE
817 .enablebits = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
818#endif
819 .bootable = OFF_BOARD,
820 .extra = 48,
821 },{ /* 3 */
822 .name = "PDC20265",
823 .init_setup = init_setup_pdc20265,
824 .init_chipset = init_chipset_pdc202xx,
825 .init_hwif = init_hwif_pdc202xx,
826 .init_dma = init_dma_pdc202xx,
827 .channels = 2,
828 .autodma = AUTODMA,
829#ifndef CONFIG_PDC202XX_FORCE
830 .enablebits = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
831#endif
832 .bootable = OFF_BOARD,
833 .extra = 48,
834 .flags = IDEPCI_FLAG_FORCE_PDC,
835 },{ /* 4 */
836 .name = "PDC20267",
837 .init_setup = init_setup_pdc202xx,
838 .init_chipset = init_chipset_pdc202xx,
839 .init_hwif = init_hwif_pdc202xx,
840 .init_dma = init_dma_pdc202xx,
841 .channels = 2,
842 .autodma = AUTODMA,
843#ifndef CONFIG_PDC202XX_FORCE
844 .enablebits = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
845#endif
846 .bootable = OFF_BOARD,
847 .extra = 48,
848 }
849};
850
851/**
852 * pdc202xx_init_one - called when a PDC202xx is found
853 * @dev: the pdc202xx device
854 * @id: the matching pci id
855 *
856 * Called when the PCI registration layer (or the IDE initialization)
857 * finds a device matching our IDE device tables.
858 */
859
860static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
861{
862 ide_pci_device_t *d = &pdc202xx_chipsets[id->driver_data];
863
864 return d->init_setup(dev, d);
865}
866
867static struct pci_device_id pdc202xx_pci_tbl[] = {
868 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
869 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
870 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
871 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
872 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
873 { 0, },
874};
875MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
876
877static struct pci_driver driver = {
878 .name = "Promise_Old_IDE",
879 .id_table = pdc202xx_pci_tbl,
880 .probe = pdc202xx_init_one,
881};
882
883static int pdc202xx_ide_init(void)
884{
885 return ide_pci_register_driver(&driver);
886}
887
888module_init(pdc202xx_ide_init);
889
890MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
891MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
892MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/piix.c b/drivers/ide/pci/piix.c
new file mode 100644
index 000000000000..b5a20ae1ef3e
--- /dev/null
+++ b/drivers/ide/pci/piix.c
@@ -0,0 +1,670 @@
1/*
2 * linux/drivers/ide/pci/piix.c Version 0.44 March 20, 2003
3 *
4 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
5 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
6 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
7 *
8 * May be copied or modified under the terms of the GNU General Public License
9 *
10 * PIO mode setting function for Intel chipsets.
11 * For use instead of BIOS settings.
12 *
13 * 40-41
14 * 42-43
15 *
16 * 41
17 * 43
18 *
19 * | PIO 0 | c0 | 80 | 0 | piix_tune_drive(drive, 0);
20 * | PIO 2 | SW2 | d0 | 90 | 4 | piix_tune_drive(drive, 2);
21 * | PIO 3 | MW1 | e1 | a1 | 9 | piix_tune_drive(drive, 3);
22 * | PIO 4 | MW2 | e3 | a3 | b | piix_tune_drive(drive, 4);
23 *
24 * sitre = word40 & 0x4000; primary
25 * sitre = word42 & 0x4000; secondary
26 *
27 * 44 8421|8421 hdd|hdb
28 *
29 * 48 8421 hdd|hdc|hdb|hda udma enabled
30 *
31 * 0001 hda
32 * 0010 hdb
33 * 0100 hdc
34 * 1000 hdd
35 *
36 * 4a 84|21 hdb|hda
37 * 4b 84|21 hdd|hdc
38 *
39 * ata-33/82371AB
40 * ata-33/82371EB
41 * ata-33/82801AB ata-66/82801AA
42 * 00|00 udma 0 00|00 reserved
43 * 01|01 udma 1 01|01 udma 3
44 * 10|10 udma 2 10|10 udma 4
45 * 11|11 reserved 11|11 reserved
46 *
47 * 54 8421|8421 ata66 drive|ata66 enable
48 *
49 * pci_read_config_word(HWIF(drive)->pci_dev, 0x40, &reg40);
50 * pci_read_config_word(HWIF(drive)->pci_dev, 0x42, &reg42);
51 * pci_read_config_word(HWIF(drive)->pci_dev, 0x44, &reg44);
52 * pci_read_config_byte(HWIF(drive)->pci_dev, 0x48, &reg48);
53 * pci_read_config_word(HWIF(drive)->pci_dev, 0x4a, &reg4a);
54 * pci_read_config_byte(HWIF(drive)->pci_dev, 0x54, &reg54);
55 *
56 * Documentation
57 * Publically available from Intel web site. Errata documentation
58 * is also publically available. As an aide to anyone hacking on this
59 * driver the list of errata that are relevant is below.going back to
60 * PIIX4. Older device documentation is now a bit tricky to find.
61 *
62 * Errata of note:
63 *
64 * Unfixable
65 * PIIX4 errata #9 - Only on ultra obscure hw
66 * ICH3 errata #13 - Not observed to affect real hw
67 * by Intel
68 *
69 * Things we must deal with
70 * PIIX4 errata #10 - BM IDE hang with non UDMA
71 * (must stop/start dma to recover)
72 * 440MX errata #15 - As PIIX4 errata #10
73 * PIIX4 errata #15 - Must not read control registers
74 * during a PIO transfer
75 * 440MX errata #13 - As PIIX4 errata #15
76 * ICH2 errata #21 - DMA mode 0 doesn't work right
77 * ICH0/1 errata #55 - As ICH2 errata #21
78 * ICH2 spec c #9 - Extra operations needed to handle
79 * drive hotswap [NOT YET SUPPORTED]
80 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
81 * and must be dword aligned
82 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
83 *
84 * Should have been BIOS fixed:
85 * 450NX: errata #19 - DMA hangs on old 450NX
86 * 450NX: errata #20 - DMA hangs on old 450NX
87 * 450NX: errata #25 - Corruption with DMA on old 450NX
88 * ICH3 errata #15 - IDE deadlock under high load
89 * (BIOS must set dev 31 fn 0 bit 23)
90 * ICH3 errata #18 - Don't use native mode
91 */
92
93#include <linux/config.h>
94#include <linux/types.h>
95#include <linux/module.h>
96#include <linux/kernel.h>
97#include <linux/ioport.h>
98#include <linux/pci.h>
99#include <linux/hdreg.h>
100#include <linux/ide.h>
101#include <linux/delay.h>
102#include <linux/init.h>
103
104#include <asm/io.h>
105
106static int no_piix_dma;
107
108/**
109 * piix_ratemask - compute rate mask for PIIX IDE
110 * @drive: IDE drive to compute for
111 *
112 * Returns the available modes for the PIIX IDE controller.
113 */
114
115static u8 piix_ratemask (ide_drive_t *drive)
116{
117 struct pci_dev *dev = HWIF(drive)->pci_dev;
118 u8 mode;
119
120 switch(dev->device) {
121 case PCI_DEVICE_ID_INTEL_82801EB_1:
122 mode = 3;
123 break;
124 /* UDMA 100 capable */
125 case PCI_DEVICE_ID_INTEL_82801BA_8:
126 case PCI_DEVICE_ID_INTEL_82801BA_9:
127 case PCI_DEVICE_ID_INTEL_82801CA_10:
128 case PCI_DEVICE_ID_INTEL_82801CA_11:
129 case PCI_DEVICE_ID_INTEL_82801E_11:
130 case PCI_DEVICE_ID_INTEL_82801DB_1:
131 case PCI_DEVICE_ID_INTEL_82801DB_10:
132 case PCI_DEVICE_ID_INTEL_82801DB_11:
133 case PCI_DEVICE_ID_INTEL_82801EB_11:
134 case PCI_DEVICE_ID_INTEL_ESB_2:
135 case PCI_DEVICE_ID_INTEL_ICH6_19:
136 case PCI_DEVICE_ID_INTEL_ICH7_21:
137 mode = 3;
138 break;
139 /* UDMA 66 capable */
140 case PCI_DEVICE_ID_INTEL_82801AA_1:
141 case PCI_DEVICE_ID_INTEL_82372FB_1:
142 mode = 2;
143 break;
144 /* UDMA 33 capable */
145 case PCI_DEVICE_ID_INTEL_82371AB:
146 case PCI_DEVICE_ID_INTEL_82443MX_1:
147 case PCI_DEVICE_ID_INTEL_82451NX:
148 case PCI_DEVICE_ID_INTEL_82801AB_1:
149 return 1;
150 /* Non UDMA capable (MWDMA2) */
151 case PCI_DEVICE_ID_INTEL_82371SB_1:
152 case PCI_DEVICE_ID_INTEL_82371FB_1:
153 case PCI_DEVICE_ID_INTEL_82371FB_0:
154 case PCI_DEVICE_ID_INTEL_82371MX:
155 default:
156 return 0;
157 }
158
159 /*
160 * If we are UDMA66 capable fall back to UDMA33
161 * if the drive cannot see an 80pin cable.
162 */
163 if (!eighty_ninty_three(drive))
164 mode = min(mode, (u8)1);
165 return mode;
166}
167
168/**
169 * piix_dma_2_pio - return the PIO mode matching DMA
170 * @xfer_rate: transfer speed
171 *
172 * Returns the nearest equivalent PIO timing for the PIO or DMA
173 * mode requested by the controller.
174 */
175
176static u8 piix_dma_2_pio (u8 xfer_rate) {
177 switch(xfer_rate) {
178 case XFER_UDMA_6:
179 case XFER_UDMA_5:
180 case XFER_UDMA_4:
181 case XFER_UDMA_3:
182 case XFER_UDMA_2:
183 case XFER_UDMA_1:
184 case XFER_UDMA_0:
185 case XFER_MW_DMA_2:
186 case XFER_PIO_4:
187 return 4;
188 case XFER_MW_DMA_1:
189 case XFER_PIO_3:
190 return 3;
191 case XFER_SW_DMA_2:
192 case XFER_PIO_2:
193 return 2;
194 case XFER_MW_DMA_0:
195 case XFER_SW_DMA_1:
196 case XFER_SW_DMA_0:
197 case XFER_PIO_1:
198 case XFER_PIO_0:
199 case XFER_PIO_SLOW:
200 default:
201 return 0;
202 }
203}
204
205/**
206 * piix_tune_drive - tune a drive attached to a PIIX
207 * @drive: drive to tune
208 * @pio: desired PIO mode
209 *
210 * Set the interface PIO mode based upon the settings done by AMI BIOS
211 * (might be useful if drive is not registered in CMOS for any reason).
212 */
213static void piix_tune_drive (ide_drive_t *drive, u8 pio)
214{
215 ide_hwif_t *hwif = HWIF(drive);
216 struct pci_dev *dev = hwif->pci_dev;
217 int is_slave = (&hwif->drives[1] == drive);
218 int master_port = hwif->channel ? 0x42 : 0x40;
219 int slave_port = 0x44;
220 unsigned long flags;
221 u16 master_data;
222 u8 slave_data;
223 /* ISP RTC */
224 u8 timings[][2] = { { 0, 0 },
225 { 0, 0 },
226 { 1, 0 },
227 { 2, 1 },
228 { 2, 3 }, };
229
230 pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
231 spin_lock_irqsave(&ide_lock, flags);
232 pci_read_config_word(dev, master_port, &master_data);
233 if (is_slave) {
234 master_data = master_data | 0x4000;
235 if (pio > 1)
236 /* enable PPE, IE and TIME */
237 master_data = master_data | 0x0070;
238 pci_read_config_byte(dev, slave_port, &slave_data);
239 slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0);
240 slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0));
241 } else {
242 master_data = master_data & 0xccf8;
243 if (pio > 1)
244 /* enable PPE, IE and TIME */
245 master_data = master_data | 0x0007;
246 master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
247 }
248 pci_write_config_word(dev, master_port, master_data);
249 if (is_slave)
250 pci_write_config_byte(dev, slave_port, slave_data);
251 spin_unlock_irqrestore(&ide_lock, flags);
252}
253
254/**
255 * piix_tune_chipset - tune a PIIX interface
256 * @drive: IDE drive to tune
257 * @xferspeed: speed to configure
258 *
259 * Set a PIIX interface channel to the desired speeds. This involves
260 * requires the right timing data into the PIIX configuration space
261 * then setting the drive parameters appropriately
262 */
263
264static int piix_tune_chipset (ide_drive_t *drive, u8 xferspeed)
265{
266 ide_hwif_t *hwif = HWIF(drive);
267 struct pci_dev *dev = hwif->pci_dev;
268 u8 maslave = hwif->channel ? 0x42 : 0x40;
269 u8 speed = ide_rate_filter(piix_ratemask(drive), xferspeed);
270 int a_speed = 3 << (drive->dn * 4);
271 int u_flag = 1 << drive->dn;
272 int v_flag = 0x01 << drive->dn;
273 int w_flag = 0x10 << drive->dn;
274 int u_speed = 0;
275 int sitre;
276 u16 reg4042, reg4a;
277 u8 reg48, reg54, reg55;
278
279 pci_read_config_word(dev, maslave, &reg4042);
280 sitre = (reg4042 & 0x4000) ? 1 : 0;
281 pci_read_config_byte(dev, 0x48, &reg48);
282 pci_read_config_word(dev, 0x4a, &reg4a);
283 pci_read_config_byte(dev, 0x54, &reg54);
284 pci_read_config_byte(dev, 0x55, &reg55);
285
286 switch(speed) {
287 case XFER_UDMA_4:
288 case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break;
289 case XFER_UDMA_5:
290 case XFER_UDMA_3:
291 case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break;
292 case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;
293 case XFER_MW_DMA_2:
294 case XFER_MW_DMA_1:
295 case XFER_SW_DMA_2: break;
296 case XFER_PIO_4:
297 case XFER_PIO_3:
298 case XFER_PIO_2:
299 case XFER_PIO_0: break;
300 default: return -1;
301 }
302
303 if (speed >= XFER_UDMA_0) {
304 if (!(reg48 & u_flag))
305 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
306 if (speed == XFER_UDMA_5) {
307 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
308 } else {
309 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
310 }
311 if ((reg4a & a_speed) != u_speed)
312 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
313 if (speed > XFER_UDMA_2) {
314 if (!(reg54 & v_flag))
315 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
316 } else
317 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
318 } else {
319 if (reg48 & u_flag)
320 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
321 if (reg4a & a_speed)
322 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
323 if (reg54 & v_flag)
324 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
325 if (reg55 & w_flag)
326 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
327 }
328
329 piix_tune_drive(drive, piix_dma_2_pio(speed));
330 return (ide_config_drive_speed(drive, speed));
331}
332
333/**
334 * piix_faulty_dma0 - check for DMA0 errata
335 * @hwif: IDE interface to check
336 *
337 * If an ICH/ICH0/ICH2 interface is is operating in multi-word
338 * DMA mode with 600nS cycle time the IDE PIO prefetch buffer will
339 * inadvertently provide an extra piece of secondary data to the primary
340 * device resulting in data corruption.
341 *
342 * With such a device this test function returns true. This allows
343 * our tuning code to follow Intel recommendations and use PIO on
344 * such devices.
345 */
346
347static int piix_faulty_dma0(ide_hwif_t *hwif)
348{
349 switch(hwif->pci_dev->device)
350 {
351 case PCI_DEVICE_ID_INTEL_82801AA_1: /* ICH */
352 case PCI_DEVICE_ID_INTEL_82801AB_1: /* ICH0 */
353 case PCI_DEVICE_ID_INTEL_82801BA_8: /* ICH2 */
354 case PCI_DEVICE_ID_INTEL_82801BA_9: /* ICH2 */
355 return 1;
356 }
357 return 0;
358}
359
360/**
361 * piix_config_drive_for_dma - configure drive for DMA
362 * @drive: IDE drive to configure
363 *
364 * Set up a PIIX interface channel for the best available speed.
365 * We prefer UDMA if it is available and then MWDMA. If DMA is
366 * not available we switch to PIO and return 0.
367 */
368
369static int piix_config_drive_for_dma (ide_drive_t *drive)
370{
371 u8 speed = ide_dma_speed(drive, piix_ratemask(drive));
372
373 /* Some ICH devices cannot support DMA mode 0 */
374 if(speed == XFER_MW_DMA_0 && piix_faulty_dma0(HWIF(drive)))
375 speed = 0;
376
377 /* If no DMA speed was available or the chipset has DMA bugs
378 then disable DMA and use PIO */
379
380 if (!speed || no_piix_dma) {
381 u8 tspeed = ide_get_best_pio_mode(drive, 255, 5, NULL);
382 speed = piix_dma_2_pio(XFER_PIO_0 + tspeed);
383 }
384
385 (void) piix_tune_chipset(drive, speed);
386 return ide_dma_enable(drive);
387}
388
389/**
390 * piix_config_drive_xfer_rate - set up an IDE device
391 * @drive: IDE drive to configure
392 *
393 * Set up the PIIX interface for the best available speed on this
394 * interface, preferring DMA to PIO.
395 */
396
397static int piix_config_drive_xfer_rate (ide_drive_t *drive)
398{
399 ide_hwif_t *hwif = HWIF(drive);
400 struct hd_driveid *id = drive->id;
401
402 drive->init_speed = 0;
403
404 if ((id->capability & 1) && drive->autodma) {
405
406 if (ide_use_dma(drive)) {
407 if (piix_config_drive_for_dma(drive))
408 return hwif->ide_dma_on(drive);
409 }
410
411 goto fast_ata_pio;
412
413 } else if ((id->capability & 8) || (id->field_valid & 2)) {
414fast_ata_pio:
415 /* Find best PIO mode. */
416 hwif->tuneproc(drive, 255);
417 return hwif->ide_dma_off_quietly(drive);
418 }
419 /* IORDY not supported */
420 return 0;
421}
422
423/**
424 * init_chipset_piix - set up the PIIX chipset
425 * @dev: PCI device to set up
426 * @name: Name of the device
427 *
428 * Initialize the PCI device as required. For the PIIX this turns
429 * out to be nice and simple
430 */
431
432static unsigned int __devinit init_chipset_piix (struct pci_dev *dev, const char *name)
433{
434 switch(dev->device) {
435 case PCI_DEVICE_ID_INTEL_82801EB_1:
436 case PCI_DEVICE_ID_INTEL_82801AA_1:
437 case PCI_DEVICE_ID_INTEL_82801AB_1:
438 case PCI_DEVICE_ID_INTEL_82801BA_8:
439 case PCI_DEVICE_ID_INTEL_82801BA_9:
440 case PCI_DEVICE_ID_INTEL_82801CA_10:
441 case PCI_DEVICE_ID_INTEL_82801CA_11:
442 case PCI_DEVICE_ID_INTEL_82801DB_1:
443 case PCI_DEVICE_ID_INTEL_82801DB_10:
444 case PCI_DEVICE_ID_INTEL_82801DB_11:
445 case PCI_DEVICE_ID_INTEL_82801EB_11:
446 case PCI_DEVICE_ID_INTEL_82801E_11:
447 case PCI_DEVICE_ID_INTEL_ESB_2:
448 case PCI_DEVICE_ID_INTEL_ICH6_19:
449 case PCI_DEVICE_ID_INTEL_ICH7_21:
450 {
451 unsigned int extra = 0;
452 pci_read_config_dword(dev, 0x54, &extra);
453 pci_write_config_dword(dev, 0x54, extra|0x400);
454 }
455 default:
456 break;
457 }
458
459 return 0;
460}
461
462/**
463 * init_hwif_piix - fill in the hwif for the PIIX
464 * @hwif: IDE interface
465 *
466 * Set up the ide_hwif_t for the PIIX interface according to the
467 * capabilities of the hardware.
468 */
469
470static void __devinit init_hwif_piix(ide_hwif_t *hwif)
471{
472 u8 reg54h = 0, reg55h = 0, ata66 = 0;
473 u8 mask = hwif->channel ? 0xc0 : 0x30;
474
475#ifndef CONFIG_IA64
476 if (!hwif->irq)
477 hwif->irq = hwif->channel ? 15 : 14;
478#endif /* CONFIG_IA64 */
479
480 if (hwif->pci_dev->device == PCI_DEVICE_ID_INTEL_82371MX) {
481 /* This is a painful system best to let it self tune for now */
482 return;
483 }
484
485 hwif->autodma = 0;
486 hwif->tuneproc = &piix_tune_drive;
487 hwif->speedproc = &piix_tune_chipset;
488 hwif->drives[0].autotune = 1;
489 hwif->drives[1].autotune = 1;
490
491 if (!hwif->dma_base)
492 return;
493
494 hwif->atapi_dma = 1;
495 hwif->ultra_mask = 0x3f;
496 hwif->mwdma_mask = 0x06;
497 hwif->swdma_mask = 0x04;
498
499 switch(hwif->pci_dev->device) {
500 case PCI_DEVICE_ID_INTEL_82371MX:
501 hwif->mwdma_mask = 0x80;
502 hwif->swdma_mask = 0x80;
503 case PCI_DEVICE_ID_INTEL_82371FB_0:
504 case PCI_DEVICE_ID_INTEL_82371FB_1:
505 case PCI_DEVICE_ID_INTEL_82371SB_1:
506 hwif->ultra_mask = 0x80;
507 break;
508 case PCI_DEVICE_ID_INTEL_82371AB:
509 case PCI_DEVICE_ID_INTEL_82443MX_1:
510 case PCI_DEVICE_ID_INTEL_82451NX:
511 case PCI_DEVICE_ID_INTEL_82801AB_1:
512 hwif->ultra_mask = 0x07;
513 break;
514 default:
515 pci_read_config_byte(hwif->pci_dev, 0x54, &reg54h);
516 pci_read_config_byte(hwif->pci_dev, 0x55, &reg55h);
517 ata66 = (reg54h & mask) ? 1 : 0;
518 break;
519 }
520
521 if (!(hwif->udma_four))
522 hwif->udma_four = ata66;
523 hwif->ide_dma_check = &piix_config_drive_xfer_rate;
524 if (!noautodma)
525 hwif->autodma = 1;
526
527 hwif->drives[1].autodma = hwif->autodma;
528 hwif->drives[0].autodma = hwif->autodma;
529}
530
531#define DECLARE_PIIX_DEV(name_str) \
532 { \
533 .name = name_str, \
534 .init_chipset = init_chipset_piix, \
535 .init_hwif = init_hwif_piix, \
536 .channels = 2, \
537 .autodma = AUTODMA, \
538 .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
539 .bootable = ON_BOARD, \
540 }
541
542static ide_pci_device_t piix_pci_info[] __devinitdata = {
543 /* 0 */ DECLARE_PIIX_DEV("PIIXa"),
544 /* 1 */ DECLARE_PIIX_DEV("PIIXb"),
545
546 { /* 2 */
547 .name = "MPIIX",
548 .init_hwif = init_hwif_piix,
549 .channels = 2,
550 .autodma = NODMA,
551 .enablebits = {{0x6D,0x80,0x80}, {0x6F,0x80,0x80}},
552 .bootable = ON_BOARD,
553 },
554
555 /* 3 */ DECLARE_PIIX_DEV("PIIX3"),
556 /* 4 */ DECLARE_PIIX_DEV("PIIX4"),
557 /* 5 */ DECLARE_PIIX_DEV("ICH0"),
558 /* 6 */ DECLARE_PIIX_DEV("PIIX4"),
559 /* 7 */ DECLARE_PIIX_DEV("ICH"),
560 /* 8 */ DECLARE_PIIX_DEV("PIIX4"),
561 /* 9 */ DECLARE_PIIX_DEV("PIIX4"),
562 /* 10 */ DECLARE_PIIX_DEV("ICH2"),
563 /* 11 */ DECLARE_PIIX_DEV("ICH2M"),
564 /* 12 */ DECLARE_PIIX_DEV("ICH3M"),
565 /* 13 */ DECLARE_PIIX_DEV("ICH3"),
566 /* 14 */ DECLARE_PIIX_DEV("ICH4"),
567 /* 15 */ DECLARE_PIIX_DEV("ICH5"),
568 /* 16 */ DECLARE_PIIX_DEV("C-ICH"),
569 /* 17 */ DECLARE_PIIX_DEV("ICH4"),
570 /* 18 */ DECLARE_PIIX_DEV("ICH5-SATA"),
571 /* 19 */ DECLARE_PIIX_DEV("ICH5"),
572 /* 20 */ DECLARE_PIIX_DEV("ICH6"),
573 /* 21 */ DECLARE_PIIX_DEV("ICH7"),
574 /* 22 */ DECLARE_PIIX_DEV("ICH4"),
575};
576
577/**
578 * piix_init_one - called when a PIIX is found
579 * @dev: the piix device
580 * @id: the matching pci id
581 *
582 * Called when the PCI registration layer (or the IDE initialization)
583 * finds a device matching our IDE device tables.
584 */
585
586static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
587{
588 ide_pci_device_t *d = &piix_pci_info[id->driver_data];
589
590 return ide_setup_pci_device(dev, d);
591}
592
593/**
594 * piix_check_450nx - Check for problem 450NX setup
595 *
596 * Check for the present of 450NX errata #19 and errata #25. If
597 * they are found, disable use of DMA IDE
598 */
599
600static void __devinit piix_check_450nx(void)
601{
602 struct pci_dev *pdev = NULL;
603 u16 cfg;
604 u8 rev;
605 while((pdev=pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
606 {
607 /* Look for 450NX PXB. Check for problem configurations
608 A PCI quirk checks bit 6 already */
609 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
610 pci_read_config_word(pdev, 0x41, &cfg);
611 /* Only on the original revision: IDE DMA can hang */
612 if(rev == 0x00)
613 no_piix_dma = 1;
614 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
615 else if(cfg & (1<<14) && rev < 5)
616 no_piix_dma = 2;
617 }
618 if(no_piix_dma)
619 printk(KERN_WARNING "piix: 450NX errata present, disabling IDE DMA.\n");
620 if(no_piix_dma == 2)
621 printk(KERN_WARNING "piix: A BIOS update may resolve this.\n");
622}
623
624static struct pci_device_id piix_pci_tbl[] = {
625 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
626 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
627 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371MX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
628 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
629 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
630 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
631 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6},
632 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7},
633 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82372FB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8},
634 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9},
635 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10},
636 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11},
637 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12},
638 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 13},
639 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 14},
640 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_11,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 15},
641 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801E_11, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 16},
642 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_10,PCI_ANY_ID, PCI_ANY_ID, 0, 0, 17},
643#ifdef CONFIG_BLK_DEV_IDE_SATA
644 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 18},
645#endif
646 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 19},
647 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_19, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 20},
648 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 21},
649 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 22},
650 { 0, },
651};
652MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
653
654static struct pci_driver driver = {
655 .name = "PIIX_IDE",
656 .id_table = piix_pci_tbl,
657 .probe = piix_init_one,
658};
659
660static int __init piix_ide_init(void)
661{
662 piix_check_450nx();
663 return ide_pci_register_driver(&driver);
664}
665
666module_init(piix_ide_init);
667
668MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
669MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
670MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/rz1000.c b/drivers/ide/pci/rz1000.c
new file mode 100644
index 000000000000..608cd7609072
--- /dev/null
+++ b/drivers/ide/pci/rz1000.c
@@ -0,0 +1,91 @@
1/*
2 * linux/drivers/ide/pci/rz1000.c Version 0.06 January 12, 2003
3 *
4 * Copyright (C) 1995-1998 Linus Torvalds & author (see below)
5 */
6
7/*
8 * Principal Author: mlord@pobox.com (Mark Lord)
9 *
10 * See linux/MAINTAINERS for address of current maintainer.
11 *
12 * This file provides support for disabling the buggy read-ahead
13 * mode of the RZ1000 IDE chipset, commonly used on Intel motherboards.
14 *
15 * Dunno if this fixes both ports, or only the primary port (?).
16 */
17
18#undef REALLY_SLOW_IO /* most systems can safely undef this */
19
20#include <linux/config.h> /* for CONFIG_BLK_DEV_IDEPCI */
21#include <linux/types.h>
22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/delay.h>
25#include <linux/timer.h>
26#include <linux/mm.h>
27#include <linux/ioport.h>
28#include <linux/blkdev.h>
29#include <linux/hdreg.h>
30#include <linux/pci.h>
31#include <linux/ide.h>
32#include <linux/init.h>
33
34#include <asm/io.h>
35
36static void __devinit init_hwif_rz1000 (ide_hwif_t *hwif)
37{
38 u16 reg;
39 struct pci_dev *dev = hwif->pci_dev;
40
41 hwif->chipset = ide_rz1000;
42 if (!pci_read_config_word (dev, 0x40, &reg) &&
43 !pci_write_config_word(dev, 0x40, reg & 0xdfff)) {
44 printk(KERN_INFO "%s: disabled chipset read-ahead "
45 "(buggy RZ1000/RZ1001)\n", hwif->name);
46 } else {
47 hwif->serialized = 1;
48 hwif->drives[0].no_unmask = 1;
49 hwif->drives[1].no_unmask = 1;
50 printk(KERN_INFO "%s: serialized, disabled unmasking "
51 "(buggy RZ1000/RZ1001)\n", hwif->name);
52 }
53}
54
55static ide_pci_device_t rz1000_chipset __devinitdata = {
56 .name = "RZ100x",
57 .init_hwif = init_hwif_rz1000,
58 .channels = 2,
59 .autodma = NODMA,
60 .bootable = ON_BOARD,
61};
62
63static int __devinit rz1000_init_one(struct pci_dev *dev, const struct pci_device_id *id)
64{
65 return ide_setup_pci_device(dev, &rz1000_chipset);
66}
67
68static struct pci_device_id rz1000_pci_tbl[] = {
69 { PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_RZ1000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
70 { PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_RZ1001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
71 { 0, },
72};
73MODULE_DEVICE_TABLE(pci, rz1000_pci_tbl);
74
75static struct pci_driver driver = {
76 .name = "RZ1000_IDE",
77 .id_table = rz1000_pci_tbl,
78 .probe = rz1000_init_one,
79};
80
81static int rz1000_ide_init(void)
82{
83 return ide_pci_register_driver(&driver);
84}
85
86module_init(rz1000_ide_init);
87
88MODULE_AUTHOR("Andre Hedrick");
89MODULE_DESCRIPTION("PCI driver module for RZ1000 IDE");
90MODULE_LICENSE("GPL");
91
diff --git a/drivers/ide/pci/sc1200.c b/drivers/ide/pci/sc1200.c
new file mode 100644
index 000000000000..84fda21e4dbd
--- /dev/null
+++ b/drivers/ide/pci/sc1200.c
@@ -0,0 +1,518 @@
1/*
2 * linux/drivers/ide/pci/sc1200.c Version 0.91 28-Jan-2003
3 *
4 * Copyright (C) 2000-2002 Mark Lord <mlord@pobox.com>
5 * May be copied or modified under the terms of the GNU General Public License
6 *
7 * Development of this chipset driver was funded
8 * by the nice folks at National Semiconductor.
9 *
10 * Documentation:
11 * Available from National Semiconductor
12 */
13
14#include <linux/config.h>
15#include <linux/module.h>
16#include <linux/types.h>
17#include <linux/kernel.h>
18#include <linux/delay.h>
19#include <linux/timer.h>
20#include <linux/mm.h>
21#include <linux/ioport.h>
22#include <linux/blkdev.h>
23#include <linux/hdreg.h>
24#include <linux/interrupt.h>
25#include <linux/pci.h>
26#include <linux/init.h>
27#include <linux/ide.h>
28#include <linux/pm.h>
29#include <asm/io.h>
30#include <asm/irq.h>
31
32#define SC1200_REV_A 0x00
33#define SC1200_REV_B1 0x01
34#define SC1200_REV_B3 0x02
35#define SC1200_REV_C1 0x03
36#define SC1200_REV_D1 0x04
37
38#define PCI_CLK_33 0x00
39#define PCI_CLK_48 0x01
40#define PCI_CLK_66 0x02
41#define PCI_CLK_33A 0x03
42
43static unsigned short sc1200_get_pci_clock (void)
44{
45 unsigned char chip_id, silicon_revision;
46 unsigned int pci_clock;
47 /*
48 * Check the silicon revision, as not all versions of the chip
49 * have the register with the fast PCI bus timings.
50 */
51 chip_id = inb (0x903c);
52 silicon_revision = inb (0x903d);
53
54 // Read the fast pci clock frequency
55 if (chip_id == 0x04 && silicon_revision < SC1200_REV_B1) {
56 pci_clock = PCI_CLK_33;
57 } else {
58 // check clock generator configuration (cfcc)
59 // the clock is in bits 8 and 9 of this word
60
61 pci_clock = inw (0x901e);
62 pci_clock >>= 8;
63 pci_clock &= 0x03;
64 if (pci_clock == PCI_CLK_33A)
65 pci_clock = PCI_CLK_33;
66 }
67 return pci_clock;
68}
69
70extern char *ide_xfer_verbose (byte xfer_rate);
71
72/*
73 * Set a new transfer mode at the drive
74 */
75static int sc1200_set_xfer_mode (ide_drive_t *drive, byte mode)
76{
77 printk("%s: sc1200_set_xfer_mode(%s)\n", drive->name, ide_xfer_verbose(mode));
78 return ide_config_drive_speed(drive, mode);
79}
80
81/*
82 * Here are the standard PIO mode 0-4 timings for each "format".
83 * Format-0 uses fast data reg timings, with slower command reg timings.
84 * Format-1 uses fast timings for all registers, but won't work with all drives.
85 */
86static const unsigned int sc1200_pio_timings[4][5] =
87 {{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010}, // format0 33Mhz
88 {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}, // format1, 33Mhz
89 {0xfaa3f4f3, 0xc23232b2, 0x513101c1, 0x31213121, 0x10211021}, // format1, 48Mhz
90 {0xfff4fff4, 0xf35353d3, 0x814102f1, 0x42314231, 0x11311131}}; // format1, 66Mhz
91
92/*
93 * After chip reset, the PIO timings are set to 0x00009172, which is not valid.
94 */
95//#define SC1200_BAD_PIO(timings) (((timings)&~0x80000000)==0x00009172)
96
97static int sc1200_autoselect_dma_mode (ide_drive_t *drive)
98{
99 int udma_ok = 1, mode = 0;
100 ide_hwif_t *hwif = HWIF(drive);
101 int unit = drive->select.b.unit;
102 ide_drive_t *mate = &hwif->drives[unit^1];
103 struct hd_driveid *id = drive->id;
104
105 /*
106 * The SC1200 specifies that two drives sharing a cable cannot
107 * mix UDMA/MDMA. It has to be one or the other, for the pair,
108 * though different timings can still be chosen for each drive.
109 * We could set the appropriate timing bits on the fly,
110 * but that might be a bit confusing. So, for now we statically
111 * handle this requirement by looking at our mate drive to see
112 * what it is capable of, before choosing a mode for our own drive.
113 */
114 if (mate->present) {
115 struct hd_driveid *mateid = mate->id;
116 if (mateid && (mateid->capability & 1) && !__ide_dma_bad_drive(mate)) {
117 if ((mateid->field_valid & 4) && (mateid->dma_ultra & 7))
118 udma_ok = 1;
119 else if ((mateid->field_valid & 2) && (mateid->dma_mword & 7))
120 udma_ok = 0;
121 else
122 udma_ok = 1;
123 }
124 }
125 /*
126 * Now see what the current drive is capable of,
127 * selecting UDMA only if the mate said it was ok.
128 */
129 if (id && (id->capability & 1) && hwif->autodma && !__ide_dma_bad_drive(drive)) {
130 if (udma_ok && (id->field_valid & 4) && (id->dma_ultra & 7)) {
131 if (id->dma_ultra & 4)
132 mode = XFER_UDMA_2;
133 else if (id->dma_ultra & 2)
134 mode = XFER_UDMA_1;
135 else if (id->dma_ultra & 1)
136 mode = XFER_UDMA_0;
137 }
138 if (!mode && (id->field_valid & 2) && (id->dma_mword & 7)) {
139 if (id->dma_mword & 4)
140 mode = XFER_MW_DMA_2;
141 else if (id->dma_mword & 2)
142 mode = XFER_MW_DMA_1;
143 else if (id->dma_mword & 1)
144 mode = XFER_MW_DMA_0;
145 }
146 }
147 return mode;
148}
149
150/*
151 * sc1200_config_dma2() handles selection/setting of DMA/UDMA modes
152 * for both the chipset and drive.
153 */
154static int sc1200_config_dma2 (ide_drive_t *drive, int mode)
155{
156 ide_hwif_t *hwif = HWIF(drive);
157 int unit = drive->select.b.unit;
158 unsigned int reg, timings;
159 unsigned short pci_clock;
160 unsigned int basereg = hwif->channel ? 0x50 : 0x40;
161
162 /*
163 * Default to DMA-off in case we run into trouble here.
164 */
165 hwif->ide_dma_off_quietly(drive); /* turn off DMA while we fiddle */
166 outb(inb(hwif->dma_base+2)&~(unit?0x40:0x20), hwif->dma_base+2); /* clear DMA_capable bit */
167
168 /*
169 * Tell the drive to switch to the new mode; abort on failure.
170 */
171 if (!mode || sc1200_set_xfer_mode(drive, mode)) {
172 printk("SC1200: set xfer mode failure\n");
173 return 1; /* failure */
174 }
175
176 pci_clock = sc1200_get_pci_clock();
177
178 /*
179 * Now tune the chipset to match the drive:
180 *
181 * Note that each DMA mode has several timings associated with it.
182 * The correct timing depends on the fast PCI clock freq.
183 */
184 timings = 0;
185 switch (mode) {
186 case XFER_UDMA_0:
187 switch (pci_clock) {
188 case PCI_CLK_33: timings = 0x00921250; break;
189 case PCI_CLK_48: timings = 0x00932470; break;
190 case PCI_CLK_66: timings = 0x009436a1; break;
191 }
192 break;
193 case XFER_UDMA_1:
194 switch (pci_clock) {
195 case PCI_CLK_33: timings = 0x00911140; break;
196 case PCI_CLK_48: timings = 0x00922260; break;
197 case PCI_CLK_66: timings = 0x00933481; break;
198 }
199 break;
200 case XFER_UDMA_2:
201 switch (pci_clock) {
202 case PCI_CLK_33: timings = 0x00911030; break;
203 case PCI_CLK_48: timings = 0x00922140; break;
204 case PCI_CLK_66: timings = 0x00923261; break;
205 }
206 break;
207 case XFER_MW_DMA_0:
208 switch (pci_clock) {
209 case PCI_CLK_33: timings = 0x00077771; break;
210 case PCI_CLK_48: timings = 0x000bbbb2; break;
211 case PCI_CLK_66: timings = 0x000ffff3; break;
212 }
213 break;
214 case XFER_MW_DMA_1:
215 switch (pci_clock) {
216 case PCI_CLK_33: timings = 0x00012121; break;
217 case PCI_CLK_48: timings = 0x00024241; break;
218 case PCI_CLK_66: timings = 0x00035352; break;
219 }
220 break;
221 case XFER_MW_DMA_2:
222 switch (pci_clock) {
223 case PCI_CLK_33: timings = 0x00002020; break;
224 case PCI_CLK_48: timings = 0x00013131; break;
225 case PCI_CLK_66: timings = 0x00015151; break;
226 }
227 break;
228 }
229
230 if (timings == 0) {
231 printk("%s: sc1200_config_dma: huh? mode=%02x clk=%x \n", drive->name, mode, pci_clock);
232 return 1; /* failure */
233 }
234
235 if (unit == 0) { /* are we configuring drive0? */
236 pci_read_config_dword(hwif->pci_dev, basereg+4, &reg);
237 timings |= reg & 0x80000000; /* preserve PIO format bit */
238 pci_write_config_dword(hwif->pci_dev, basereg+4, timings);
239 } else {
240 pci_write_config_dword(hwif->pci_dev, basereg+12, timings);
241 }
242
243 outb(inb(hwif->dma_base+2)|(unit?0x40:0x20), hwif->dma_base+2); /* set DMA_capable bit */
244
245 /*
246 * Finally, turn DMA on in software, and exit.
247 */
248 return hwif->ide_dma_on(drive); /* success */
249}
250
251/*
252 * sc1200_config_dma() handles selection/setting of DMA/UDMA modes
253 * for both the chipset and drive.
254 */
255static int sc1200_config_dma (ide_drive_t *drive)
256{
257 return sc1200_config_dma2(drive, sc1200_autoselect_dma_mode(drive));
258}
259
260
261/* Replacement for the standard ide_dma_end action in
262 * dma_proc.
263 *
264 * returns 1 on error, 0 otherwise
265 */
266static int sc1200_ide_dma_end (ide_drive_t *drive)
267{
268 ide_hwif_t *hwif = HWIF(drive);
269 unsigned long dma_base = hwif->dma_base;
270 byte dma_stat;
271
272 dma_stat = inb(dma_base+2); /* get DMA status */
273
274 if (!(dma_stat & 4))
275 printk(" ide_dma_end dma_stat=%0x err=%x newerr=%x\n",
276 dma_stat, ((dma_stat&7)!=4), ((dma_stat&2)==2));
277
278 outb(dma_stat|0x1b, dma_base+2); /* clear the INTR & ERROR bits */
279 outb(inb(dma_base)&~1, dma_base); /* !! DO THIS HERE !! stop DMA */
280
281 drive->waiting_for_dma = 0;
282 ide_destroy_dmatable(drive); /* purge DMA mappings */
283
284 return (dma_stat & 7) != 4; /* verify good DMA status */
285}
286
287/*
288 * sc1200_tuneproc() handles selection/setting of PIO modes
289 * for both the chipset and drive.
290 *
291 * All existing BIOSs for this chipset guarantee that all drives
292 * will have valid default PIO timings set up before we get here.
293 */
294static void sc1200_tuneproc (ide_drive_t *drive, byte pio) /* mode=255 means "autotune" */
295{
296 ide_hwif_t *hwif = HWIF(drive);
297 unsigned int format;
298 static byte modes[5] = {XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3, XFER_PIO_4};
299 int mode = -1;
300
301 switch (pio) {
302 case 200: mode = XFER_UDMA_0; break;
303 case 201: mode = XFER_UDMA_1; break;
304 case 202: mode = XFER_UDMA_2; break;
305 case 100: mode = XFER_MW_DMA_0; break;
306 case 101: mode = XFER_MW_DMA_1; break;
307 case 102: mode = XFER_MW_DMA_2; break;
308 }
309 if (mode != -1) {
310 printk("SC1200: %s: changing (U)DMA mode\n", drive->name);
311 (void)sc1200_config_dma2(drive, mode);
312 return;
313 }
314
315 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
316 printk("SC1200: %s: setting PIO mode%d\n", drive->name, pio);
317 if (!sc1200_set_xfer_mode(drive, modes[pio])) {
318 unsigned int basereg = hwif->channel ? 0x50 : 0x40;
319 pci_read_config_dword (hwif->pci_dev, basereg+4, &format);
320 format = (format >> 31) & 1;
321 if (format)
322 format += sc1200_get_pci_clock();
323 pci_write_config_dword(hwif->pci_dev, basereg + (drive->select.b.unit << 3), sc1200_pio_timings[format][pio]);
324 }
325}
326
327static ide_hwif_t *lookup_pci_dev (ide_hwif_t *prev, struct pci_dev *dev)
328{
329 int h;
330
331 for (h = 0; h < MAX_HWIFS; h++) {
332 ide_hwif_t *hwif = &ide_hwifs[h];
333 if (prev) {
334 if (hwif == prev)
335 prev = NULL; // found previous, now look for next match
336 } else {
337 if (hwif && hwif->pci_dev == dev)
338 return hwif; // found next match
339 }
340 }
341 return NULL; // not found
342}
343
344typedef struct sc1200_saved_state_s {
345 __u32 regs[4];
346} sc1200_saved_state_t;
347
348
349static int sc1200_suspend (struct pci_dev *dev, u32 state)
350{
351 ide_hwif_t *hwif = NULL;
352
353 printk("SC1200: suspend(%u)\n", state);
354
355 if (state == 0) {
356 // we only save state when going from full power to less
357
358 //
359 // Loop over all interfaces that are part of this PCI device:
360 //
361 while ((hwif = lookup_pci_dev(hwif, dev)) != NULL) {
362 sc1200_saved_state_t *ss;
363 unsigned int basereg, r;
364 //
365 // allocate a permanent save area, if not already allocated
366 //
367 ss = (sc1200_saved_state_t *)hwif->config_data;
368 if (ss == NULL) {
369 ss = kmalloc(sizeof(sc1200_saved_state_t), GFP_KERNEL);
370 if (ss == NULL)
371 return -ENOMEM;
372 hwif->config_data = (unsigned long)ss;
373 }
374 ss = (sc1200_saved_state_t *)hwif->config_data;
375 //
376 // Save timing registers: this may be unnecessary if
377 // BIOS also does it
378 //
379 basereg = hwif->channel ? 0x50 : 0x40;
380 for (r = 0; r < 4; ++r) {
381 pci_read_config_dword (hwif->pci_dev, basereg + (r<<2), &ss->regs[r]);
382 }
383 }
384 }
385
386 /* You don't need to iterate over disks -- sysfs should have done that for you already */
387
388 pci_disable_device(dev);
389 pci_set_power_state(dev,state);
390 dev->current_state = state;
391 return 0;
392}
393
394static int sc1200_resume (struct pci_dev *dev)
395{
396 ide_hwif_t *hwif = NULL;
397
398printk("SC1200: resume\n");
399 pci_set_power_state(dev,0); // bring chip back from sleep state
400 dev->current_state = 0;
401 pci_enable_device(dev);
402 //
403 // loop over all interfaces that are part of this pci device:
404 //
405 while ((hwif = lookup_pci_dev(hwif, dev)) != NULL) {
406 unsigned int basereg, r, d, format;
407 sc1200_saved_state_t *ss = (sc1200_saved_state_t *)hwif->config_data;
408printk("%s: SC1200: resume\n", hwif->name);
409
410 //
411 // Restore timing registers: this may be unnecessary if BIOS also does it
412 //
413 basereg = hwif->channel ? 0x50 : 0x40;
414 if (ss != NULL) {
415 for (r = 0; r < 4; ++r) {
416 pci_write_config_dword(hwif->pci_dev, basereg + (r<<2), ss->regs[r]);
417 }
418 }
419 //
420 // Re-program drive PIO modes
421 //
422 pci_read_config_dword(hwif->pci_dev, basereg+4, &format);
423 format = (format >> 31) & 1;
424 if (format)
425 format += sc1200_get_pci_clock();
426 for (d = 0; d < 2; ++d) {
427 ide_drive_t *drive = &(hwif->drives[d]);
428 if (drive->present) {
429 unsigned int pio, timings;
430 pci_read_config_dword(hwif->pci_dev, basereg+(drive->select.b.unit << 3), &timings);
431 for (pio = 0; pio <= 4; ++pio) {
432 if (sc1200_pio_timings[format][pio] == timings)
433 break;
434 }
435 if (pio > 4)
436 pio = 255; /* autotune */
437 (void)sc1200_tuneproc(drive, pio);
438 }
439 }
440 //
441 // Re-program drive DMA modes
442 //
443 for (d = 0; d < MAX_DRIVES; ++d) {
444 ide_drive_t *drive = &(hwif->drives[d]);
445 if (drive->present && !__ide_dma_bad_drive(drive)) {
446 int was_using_dma = drive->using_dma;
447 hwif->ide_dma_off_quietly(drive);
448 sc1200_config_dma(drive);
449 if (!was_using_dma && drive->using_dma) {
450 hwif->ide_dma_off_quietly(drive);
451 }
452 }
453 }
454 }
455 return 0;
456}
457
458/*
459 * This gets invoked by the IDE driver once for each channel,
460 * and performs channel-specific pre-initialization before drive probing.
461 */
462static void __init init_hwif_sc1200 (ide_hwif_t *hwif)
463{
464 if (hwif->mate)
465 hwif->serialized = hwif->mate->serialized = 1;
466 hwif->autodma = 0;
467 if (hwif->dma_base) {
468 hwif->ide_dma_check = &sc1200_config_dma;
469 hwif->ide_dma_end = &sc1200_ide_dma_end;
470 if (!noautodma)
471 hwif->autodma = 1;
472 hwif->tuneproc = &sc1200_tuneproc;
473 }
474 hwif->atapi_dma = 1;
475 hwif->ultra_mask = 0x07;
476 hwif->mwdma_mask = 0x07;
477
478 hwif->drives[0].autodma = hwif->autodma;
479 hwif->drives[1].autodma = hwif->autodma;
480}
481
482static ide_pci_device_t sc1200_chipset __devinitdata = {
483 .name = "SC1200",
484 .init_hwif = init_hwif_sc1200,
485 .channels = 2,
486 .autodma = AUTODMA,
487 .bootable = ON_BOARD,
488};
489
490static int __devinit sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id)
491{
492 return ide_setup_pci_device(dev, &sc1200_chipset);
493}
494
495static struct pci_device_id sc1200_pci_tbl[] = {
496 { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SCx200_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
497 { 0, },
498};
499MODULE_DEVICE_TABLE(pci, sc1200_pci_tbl);
500
501static struct pci_driver driver = {
502 .name = "SC1200_IDE",
503 .id_table = sc1200_pci_tbl,
504 .probe = sc1200_init_one,
505 .suspend = sc1200_suspend,
506 .resume = sc1200_resume,
507};
508
509static int sc1200_ide_init(void)
510{
511 return ide_pci_register_driver(&driver);
512}
513
514module_init(sc1200_ide_init);
515
516MODULE_AUTHOR("Mark Lord");
517MODULE_DESCRIPTION("PCI driver module for NS SC1200 IDE");
518MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/serverworks.c b/drivers/ide/pci/serverworks.c
new file mode 100644
index 000000000000..82a1103b2413
--- /dev/null
+++ b/drivers/ide/pci/serverworks.c
@@ -0,0 +1,675 @@
1/*
2 * linux/drivers/ide/pci/serverworks.c Version 0.8 25 Ebr 2003
3 *
4 * Copyright (C) 1998-2000 Michel Aubry
5 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
6 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
7 * Portions copyright (c) 2001 Sun Microsystems
8 *
9 *
10 * RCC/ServerWorks IDE driver for Linux
11 *
12 * OSB4: `Open South Bridge' IDE Interface (fn 1)
13 * supports UDMA mode 2 (33 MB/s)
14 *
15 * CSB5: `Champion South Bridge' IDE Interface (fn 1)
16 * all revisions support UDMA mode 4 (66 MB/s)
17 * revision A2.0 and up support UDMA mode 5 (100 MB/s)
18 *
19 * *** The CSB5 does not provide ANY register ***
20 * *** to detect 80-conductor cable presence. ***
21 *
22 * CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
23 *
24 * Documentation:
25 * Available under NDA only. Errata info very hard to get.
26 *
27 */
28
29#include <linux/config.h>
30#include <linux/types.h>
31#include <linux/module.h>
32#include <linux/kernel.h>
33#include <linux/ioport.h>
34#include <linux/pci.h>
35#include <linux/hdreg.h>
36#include <linux/ide.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39
40#include <asm/io.h>
41
42#define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
43#define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
44
45/* Seagate Barracuda ATA IV Family drives in UDMA mode 5
46 * can overrun their FIFOs when used with the CSB5 */
47static const char *svwks_bad_ata100[] = {
48 "ST320011A",
49 "ST340016A",
50 "ST360021A",
51 "ST380021A",
52 NULL
53};
54
55static u8 svwks_revision = 0;
56static struct pci_dev *isa_dev;
57
58static int check_in_drive_lists (ide_drive_t *drive, const char **list)
59{
60 while (*list)
61 if (!strcmp(*list++, drive->id->model))
62 return 1;
63 return 0;
64}
65
66static u8 svwks_ratemask (ide_drive_t *drive)
67{
68 struct pci_dev *dev = HWIF(drive)->pci_dev;
69 u8 mode;
70
71 if (!svwks_revision)
72 pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
73
74 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
75 u32 reg = 0;
76 if (isa_dev)
77 pci_read_config_dword(isa_dev, 0x64, &reg);
78
79 /*
80 * Don't enable UDMA on disk devices for the moment
81 */
82 if(drive->media == ide_disk)
83 return 0;
84 /* Check the OSB4 DMA33 enable bit */
85 return ((reg & 0x00004000) == 0x00004000) ? 1 : 0;
86 } else if (svwks_revision < SVWKS_CSB5_REVISION_NEW) {
87 return 1;
88 } else if (svwks_revision >= SVWKS_CSB5_REVISION_NEW) {
89 u8 btr = 0;
90 pci_read_config_byte(dev, 0x5A, &btr);
91 mode = btr & 0x3;
92 if (!eighty_ninty_three(drive))
93 mode = min(mode, (u8)1);
94 /* If someone decides to do UDMA133 on CSB5 the same
95 issue will bite so be inclusive */
96 if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
97 mode = 2;
98 }
99 if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
100 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
101 (!(PCI_FUNC(dev->devfn) & 1)))
102 mode = 2;
103 return mode;
104}
105
106static u8 svwks_csb_check (struct pci_dev *dev)
107{
108 switch (dev->device) {
109 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
110 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
111 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
112 return 1;
113 default:
114 break;
115 }
116 return 0;
117}
118static int svwks_tune_chipset (ide_drive_t *drive, u8 xferspeed)
119{
120 u8 udma_modes[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
121 u8 dma_modes[] = { 0x77, 0x21, 0x20 };
122 u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
123 u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };
124 u8 drive_pci2[] = { 0x45, 0x44, 0x47, 0x46 };
125
126 ide_hwif_t *hwif = HWIF(drive);
127 struct pci_dev *dev = hwif->pci_dev;
128 u8 speed;
129 u8 pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
130 u8 unit = (drive->select.b.unit & 0x01);
131 u8 csb5 = svwks_csb_check(dev);
132 u8 ultra_enable = 0, ultra_timing = 0;
133 u8 dma_timing = 0, pio_timing = 0;
134 u16 csb5_pio = 0;
135
136 if (xferspeed == 255) /* PIO auto-tuning */
137 speed = XFER_PIO_0 + pio;
138 else
139 speed = ide_rate_filter(svwks_ratemask(drive), xferspeed);
140
141 /* If we are about to put a disk into UDMA mode we screwed up.
142 Our code assumes we never _ever_ do this on an OSB4 */
143
144 if(dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4 &&
145 drive->media == ide_disk && speed >= XFER_UDMA_0)
146 BUG();
147
148 pci_read_config_byte(dev, drive_pci[drive->dn], &pio_timing);
149 pci_read_config_byte(dev, drive_pci2[drive->dn], &dma_timing);
150 pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
151 pci_read_config_word(dev, 0x4A, &csb5_pio);
152 pci_read_config_byte(dev, 0x54, &ultra_enable);
153
154 /* Per Specified Design by OEM, and ASIC Architect */
155 if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
156 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
157 if (!drive->init_speed) {
158 u8 dma_stat = hwif->INB(hwif->dma_status);
159
160dma_pio:
161 if (((ultra_enable << (7-drive->dn) & 0x80) == 0x80) &&
162 ((dma_stat & (1<<(5+unit))) == (1<<(5+unit)))) {
163 drive->current_speed = drive->init_speed = XFER_UDMA_0 + udma_modes[(ultra_timing >> (4*unit)) & ~(0xF0)];
164 return 0;
165 } else if ((dma_timing) &&
166 ((dma_stat&(1<<(5+unit)))==(1<<(5+unit)))) {
167 u8 dmaspeed = dma_timing;
168
169 dma_timing &= ~0xFF;
170 if ((dmaspeed & 0x20) == 0x20)
171 dmaspeed = XFER_MW_DMA_2;
172 else if ((dmaspeed & 0x21) == 0x21)
173 dmaspeed = XFER_MW_DMA_1;
174 else if ((dmaspeed & 0x77) == 0x77)
175 dmaspeed = XFER_MW_DMA_0;
176 else
177 goto dma_pio;
178 drive->current_speed = drive->init_speed = dmaspeed;
179 return 0;
180 } else if (pio_timing) {
181 u8 piospeed = pio_timing;
182
183 pio_timing &= ~0xFF;
184 if ((piospeed & 0x20) == 0x20)
185 piospeed = XFER_PIO_4;
186 else if ((piospeed & 0x22) == 0x22)
187 piospeed = XFER_PIO_3;
188 else if ((piospeed & 0x34) == 0x34)
189 piospeed = XFER_PIO_2;
190 else if ((piospeed & 0x47) == 0x47)
191 piospeed = XFER_PIO_1;
192 else if ((piospeed & 0x5d) == 0x5d)
193 piospeed = XFER_PIO_0;
194 else
195 goto oem_setup_failed;
196 drive->current_speed = drive->init_speed = piospeed;
197 return 0;
198 }
199 }
200 }
201
202oem_setup_failed:
203
204 pio_timing &= ~0xFF;
205 dma_timing &= ~0xFF;
206 ultra_timing &= ~(0x0F << (4*unit));
207 ultra_enable &= ~(0x01 << drive->dn);
208 csb5_pio &= ~(0x0F << (4*drive->dn));
209
210 switch(speed) {
211 case XFER_PIO_4:
212 case XFER_PIO_3:
213 case XFER_PIO_2:
214 case XFER_PIO_1:
215 case XFER_PIO_0:
216 pio_timing |= pio_modes[speed - XFER_PIO_0];
217 csb5_pio |= ((speed - XFER_PIO_0) << (4*drive->dn));
218 break;
219
220 case XFER_MW_DMA_2:
221 case XFER_MW_DMA_1:
222 case XFER_MW_DMA_0:
223 pio_timing |= pio_modes[pio];
224 csb5_pio |= (pio << (4*drive->dn));
225 dma_timing |= dma_modes[speed - XFER_MW_DMA_0];
226 break;
227
228 case XFER_UDMA_5:
229 case XFER_UDMA_4:
230 case XFER_UDMA_3:
231 case XFER_UDMA_2:
232 case XFER_UDMA_1:
233 case XFER_UDMA_0:
234 pio_timing |= pio_modes[pio];
235 csb5_pio |= (pio << (4*drive->dn));
236 dma_timing |= dma_modes[2];
237 ultra_timing |= ((udma_modes[speed - XFER_UDMA_0]) << (4*unit));
238 ultra_enable |= (0x01 << drive->dn);
239 default:
240 break;
241 }
242
243 pci_write_config_byte(dev, drive_pci[drive->dn], pio_timing);
244 if (csb5)
245 pci_write_config_word(dev, 0x4A, csb5_pio);
246
247 pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
248 pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
249 pci_write_config_byte(dev, 0x54, ultra_enable);
250
251 return (ide_config_drive_speed(drive, speed));
252}
253
254static void config_chipset_for_pio (ide_drive_t *drive)
255{
256 u16 eide_pio_timing[6] = {960, 480, 240, 180, 120, 90};
257 u16 xfer_pio = drive->id->eide_pio_modes;
258 u8 timing, speed, pio;
259
260 pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
261
262 if (xfer_pio > 4)
263 xfer_pio = 0;
264
265 if (drive->id->eide_pio_iordy > 0)
266 for (xfer_pio = 5;
267 xfer_pio>0 &&
268 drive->id->eide_pio_iordy>eide_pio_timing[xfer_pio];
269 xfer_pio--);
270 else
271 xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
272 (drive->id->eide_pio_modes & 2) ? 0x04 :
273 (drive->id->eide_pio_modes & 1) ? 0x03 :
274 (drive->id->tPIO & 2) ? 0x02 :
275 (drive->id->tPIO & 1) ? 0x01 : xfer_pio;
276
277 timing = (xfer_pio >= pio) ? xfer_pio : pio;
278
279 switch(timing) {
280 case 4: speed = XFER_PIO_4;break;
281 case 3: speed = XFER_PIO_3;break;
282 case 2: speed = XFER_PIO_2;break;
283 case 1: speed = XFER_PIO_1;break;
284 default:
285 speed = (!drive->id->tPIO) ? XFER_PIO_0 : XFER_PIO_SLOW;
286 break;
287 }
288 (void) svwks_tune_chipset(drive, speed);
289 drive->current_speed = speed;
290}
291
292static void svwks_tune_drive (ide_drive_t *drive, u8 pio)
293{
294 if(pio == 255)
295 (void) svwks_tune_chipset(drive, 255);
296 else
297 (void) svwks_tune_chipset(drive, (XFER_PIO_0 + pio));
298}
299
300static int config_chipset_for_dma (ide_drive_t *drive)
301{
302 u8 speed = ide_dma_speed(drive, svwks_ratemask(drive));
303
304 if (!(speed))
305 speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL);
306
307 (void) svwks_tune_chipset(drive, speed);
308 return ide_dma_enable(drive);
309}
310
311static int svwks_config_drive_xfer_rate (ide_drive_t *drive)
312{
313 ide_hwif_t *hwif = HWIF(drive);
314 struct hd_driveid *id = drive->id;
315
316 drive->init_speed = 0;
317
318 if ((id->capability & 1) && drive->autodma) {
319
320 if (ide_use_dma(drive)) {
321 if (config_chipset_for_dma(drive))
322 return hwif->ide_dma_on(drive);
323 }
324
325 goto fast_ata_pio;
326
327 } else if ((id->capability & 8) || (id->field_valid & 2)) {
328fast_ata_pio:
329 config_chipset_for_pio(drive);
330 // hwif->tuneproc(drive, 5);
331 return hwif->ide_dma_off_quietly(drive);
332 }
333 /* IORDY not supported */
334 return 0;
335}
336
337/* This can go soon */
338
339static int svwks_ide_dma_end (ide_drive_t *drive)
340{
341 return __ide_dma_end(drive);
342}
343
344static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const char *name)
345{
346 unsigned int reg;
347 u8 btr;
348
349 /* save revision id to determine DMA capability */
350 pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
351
352 /* force Master Latency Timer value to 64 PCICLKs */
353 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
354
355 /* OSB4 : South Bridge and IDE */
356 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
357 isa_dev = pci_find_device(PCI_VENDOR_ID_SERVERWORKS,
358 PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
359 if (isa_dev) {
360 pci_read_config_dword(isa_dev, 0x64, &reg);
361 reg &= ~0x00002000; /* disable 600ns interrupt mask */
362 if(!(reg & 0x00004000))
363 printk(KERN_DEBUG "%s: UDMA not BIOS enabled.\n", name);
364 reg |= 0x00004000; /* enable UDMA/33 support */
365 pci_write_config_dword(isa_dev, 0x64, reg);
366 }
367 }
368
369 /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
370 else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
371 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
372 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
373
374 /* Third Channel Test */
375 if (!(PCI_FUNC(dev->devfn) & 1)) {
376 struct pci_dev * findev = NULL;
377 u32 reg4c = 0;
378 findev = pci_find_device(PCI_VENDOR_ID_SERVERWORKS,
379 PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
380 if (findev) {
381 pci_read_config_dword(findev, 0x4C, &reg4c);
382 reg4c &= ~0x000007FF;
383 reg4c |= 0x00000040;
384 reg4c |= 0x00000020;
385 pci_write_config_dword(findev, 0x4C, reg4c);
386 }
387 outb_p(0x06, 0x0c00);
388 dev->irq = inb_p(0x0c01);
389#if 0
390 printk("%s: device class (0x%04x)\n",
391 name, dev->class);
392 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
393 dev->class &= ~0x000F0F00;
394 // dev->class |= ~0x00000400;
395 dev->class |= ~0x00010100;
396 /**/
397 }
398#endif
399 } else {
400 struct pci_dev * findev = NULL;
401 u8 reg41 = 0;
402
403 findev = pci_find_device(PCI_VENDOR_ID_SERVERWORKS,
404 PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
405 if (findev) {
406 pci_read_config_byte(findev, 0x41, &reg41);
407 reg41 &= ~0x40;
408 pci_write_config_byte(findev, 0x41, reg41);
409 }
410 /*
411 * This is a device pin issue on CSB6.
412 * Since there will be a future raid mode,
413 * early versions of the chipset require the
414 * interrupt pin to be set, and it is a compatibility
415 * mode issue.
416 */
417 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
418 dev->irq = 0;
419 }
420// pci_read_config_dword(dev, 0x40, &pioreg)
421// pci_write_config_dword(dev, 0x40, 0x99999999);
422// pci_read_config_dword(dev, 0x44, &dmareg);
423// pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
424 /* setup the UDMA Control register
425 *
426 * 1. clear bit 6 to enable DMA
427 * 2. enable DMA modes with bits 0-1
428 * 00 : legacy
429 * 01 : udma2
430 * 10 : udma2/udma4
431 * 11 : udma2/udma4/udma5
432 */
433 pci_read_config_byte(dev, 0x5A, &btr);
434 btr &= ~0x40;
435 if (!(PCI_FUNC(dev->devfn) & 1))
436 btr |= 0x2;
437 else
438 btr |= (svwks_revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
439 pci_write_config_byte(dev, 0x5A, btr);
440 }
441
442 return (dev->irq) ? dev->irq : 0;
443}
444
445static unsigned int __init ata66_svwks_svwks (ide_hwif_t *hwif)
446{
447 return 1;
448}
449
450/* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
451 * of the subsystem device ID indicate presence of an 80-pin cable.
452 * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
453 * Bit 15 set = secondary IDE channel has 80-pin cable.
454 * Bit 14 clear = primary IDE channel does not have 80-pin cable.
455 * Bit 14 set = primary IDE channel has 80-pin cable.
456 */
457static unsigned int __init ata66_svwks_dell (ide_hwif_t *hwif)
458{
459 struct pci_dev *dev = hwif->pci_dev;
460 if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
461 dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
462 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
463 dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
464 return ((1 << (hwif->channel + 14)) &
465 dev->subsystem_device) ? 1 : 0;
466 return 0;
467}
468
469/* Sun Cobalt Alpine hardware avoids the 80-pin cable
470 * detect issue by attaching the drives directly to the board.
471 * This check follows the Dell precedent (how scary is that?!)
472 *
473 * WARNING: this only works on Alpine hardware!
474 */
475static unsigned int __init ata66_svwks_cobalt (ide_hwif_t *hwif)
476{
477 struct pci_dev *dev = hwif->pci_dev;
478 if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
479 dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
480 dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
481 return ((1 << (hwif->channel + 14)) &
482 dev->subsystem_device) ? 1 : 0;
483 return 0;
484}
485
486static unsigned int __init ata66_svwks (ide_hwif_t *hwif)
487{
488 struct pci_dev *dev = hwif->pci_dev;
489
490 /* Per Specified Design by OEM, and ASIC Architect */
491 if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
492 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
493 return 1;
494
495 /* Server Works */
496 if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
497 return ata66_svwks_svwks (hwif);
498
499 /* Dell PowerEdge */
500 if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
501 return ata66_svwks_dell (hwif);
502
503 /* Cobalt Alpine */
504 if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
505 return ata66_svwks_cobalt (hwif);
506
507 return 0;
508}
509
510#undef CAN_SW_DMA
511static void __devinit init_hwif_svwks (ide_hwif_t *hwif)
512{
513 u8 dma_stat = 0;
514
515 if (!hwif->irq)
516 hwif->irq = hwif->channel ? 15 : 14;
517
518 hwif->tuneproc = &svwks_tune_drive;
519 hwif->speedproc = &svwks_tune_chipset;
520
521 hwif->atapi_dma = 1;
522
523 if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE)
524 hwif->ultra_mask = 0x3f;
525
526 hwif->mwdma_mask = 0x07;
527#ifdef CAN_SW_DMA
528 hwif->swdma_mask = 0x07;
529#endif /* CAN_SW_DMA */
530
531 hwif->autodma = 0;
532
533 if (!hwif->dma_base) {
534 hwif->drives[0].autotune = 1;
535 hwif->drives[1].autotune = 1;
536 return;
537 }
538
539 hwif->ide_dma_check = &svwks_config_drive_xfer_rate;
540 if (hwif->pci_dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE)
541 hwif->ide_dma_end = &svwks_ide_dma_end;
542 else if (!(hwif->udma_four))
543 hwif->udma_four = ata66_svwks(hwif);
544 if (!noautodma)
545 hwif->autodma = 1;
546
547 dma_stat = hwif->INB(hwif->dma_status);
548 hwif->drives[0].autodma = (dma_stat & 0x20);
549 hwif->drives[1].autodma = (dma_stat & 0x40);
550 hwif->drives[0].autotune = (!(dma_stat & 0x20));
551 hwif->drives[1].autotune = (!(dma_stat & 0x40));
552// hwif->drives[0].autodma = hwif->autodma;
553// hwif->drives[1].autodma = hwif->autodma;
554}
555
556/*
557 * We allow the BM-DMA driver to only work on enabled interfaces.
558 */
559static void __devinit init_dma_svwks (ide_hwif_t *hwif, unsigned long dmabase)
560{
561 struct pci_dev *dev = hwif->pci_dev;
562
563 if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
564 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
565 (!(PCI_FUNC(dev->devfn) & 1)) && (hwif->channel))
566 return;
567
568 ide_setup_dma(hwif, dmabase, 8);
569}
570
571static int __devinit init_setup_svwks (struct pci_dev *dev, ide_pci_device_t *d)
572{
573 return ide_setup_pci_device(dev, d);
574}
575
576static int __init init_setup_csb6 (struct pci_dev *dev, ide_pci_device_t *d)
577{
578 if (!(PCI_FUNC(dev->devfn) & 1)) {
579 d->bootable = NEVER_BOARD;
580 if (dev->resource[0].start == 0x01f1)
581 d->bootable = ON_BOARD;
582 }
583#if 0
584 if ((IDE_PCI_DEVID_EQ(d->devid, DEVID_CSB6) &&
585 (!(PCI_FUNC(dev->devfn) & 1)))
586 d->autodma = AUTODMA;
587#endif
588
589 d->channels = ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE ||
590 dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2) &&
591 (!(PCI_FUNC(dev->devfn) & 1))) ? 1 : 2;
592
593 return ide_setup_pci_device(dev, d);
594}
595
596static ide_pci_device_t serverworks_chipsets[] __devinitdata = {
597 { /* 0 */
598 .name = "SvrWks OSB4",
599 .init_setup = init_setup_svwks,
600 .init_chipset = init_chipset_svwks,
601 .init_hwif = init_hwif_svwks,
602 .channels = 2,
603 .autodma = AUTODMA,
604 .bootable = ON_BOARD,
605 },{ /* 1 */
606 .name = "SvrWks CSB5",
607 .init_setup = init_setup_svwks,
608 .init_chipset = init_chipset_svwks,
609 .init_hwif = init_hwif_svwks,
610 .init_dma = init_dma_svwks,
611 .channels = 2,
612 .autodma = AUTODMA,
613 .bootable = ON_BOARD,
614 },{ /* 2 */
615 .name = "SvrWks CSB6",
616 .init_setup = init_setup_csb6,
617 .init_chipset = init_chipset_svwks,
618 .init_hwif = init_hwif_svwks,
619 .init_dma = init_dma_svwks,
620 .channels = 2,
621 .autodma = AUTODMA,
622 .bootable = ON_BOARD,
623 },{ /* 3 */
624 .name = "SvrWks CSB6",
625 .init_setup = init_setup_csb6,
626 .init_chipset = init_chipset_svwks,
627 .init_hwif = init_hwif_svwks,
628 .init_dma = init_dma_svwks,
629 .channels = 1, /* 2 */
630 .autodma = AUTODMA,
631 .bootable = ON_BOARD,
632 }
633};
634
635/**
636 * svwks_init_one - called when a OSB/CSB is found
637 * @dev: the svwks device
638 * @id: the matching pci id
639 *
640 * Called when the PCI registration layer (or the IDE initialization)
641 * finds a device matching our IDE device tables.
642 */
643
644static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
645{
646 ide_pci_device_t *d = &serverworks_chipsets[id->driver_data];
647
648 return d->init_setup(dev, d);
649}
650
651static struct pci_device_id svwks_pci_tbl[] = {
652 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
653 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
654 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
655 { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
656 { 0, },
657};
658MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);
659
660static struct pci_driver driver = {
661 .name = "Serverworks_IDE",
662 .id_table = svwks_pci_tbl,
663 .probe = svwks_init_one,
664};
665
666static int svwks_ide_init(void)
667{
668 return ide_pci_register_driver(&driver);
669}
670
671module_init(svwks_ide_init);
672
673MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick");
674MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
675MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/sgiioc4.c b/drivers/ide/pci/sgiioc4.c
new file mode 100644
index 000000000000..4651a22bf12e
--- /dev/null
+++ b/drivers/ide/pci/sgiioc4.c
@@ -0,0 +1,728 @@
1/*
2 * Copyright (c) 2003 Silicon Graphics, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it would be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
11 *
12 * You should have received a copy of the GNU General Public
13 * License along with this program; if not, write the Free Software
14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
15 *
16 * Contact information: Silicon Graphics, Inc., 1600 Amphitheatre Pkwy,
17 * Mountain View, CA 94043, or:
18 *
19 * http://www.sgi.com
20 *
21 * For further information regarding this notice, see:
22 *
23 * http://oss.sgi.com/projects/GenInfo/NoticeExplan
24 */
25
26#include <linux/module.h>
27#include <linux/types.h>
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/hdreg.h>
31#include <linux/init.h>
32#include <linux/kernel.h>
33#include <linux/timer.h>
34#include <linux/mm.h>
35#include <linux/ioport.h>
36#include <linux/blkdev.h>
37#include <linux/ioc4_common.h>
38#include <asm/io.h>
39
40#include <linux/ide.h>
41
42/* IOC4 Specific Definitions */
43#define IOC4_CMD_OFFSET 0x100
44#define IOC4_CTRL_OFFSET 0x120
45#define IOC4_DMA_OFFSET 0x140
46#define IOC4_INTR_OFFSET 0x0
47
48#define IOC4_TIMING 0x00
49#define IOC4_DMA_PTR_L 0x01
50#define IOC4_DMA_PTR_H 0x02
51#define IOC4_DMA_ADDR_L 0x03
52#define IOC4_DMA_ADDR_H 0x04
53#define IOC4_BC_DEV 0x05
54#define IOC4_BC_MEM 0x06
55#define IOC4_DMA_CTRL 0x07
56#define IOC4_DMA_END_ADDR 0x08
57
58/* Bits in the IOC4 Control/Status Register */
59#define IOC4_S_DMA_START 0x01
60#define IOC4_S_DMA_STOP 0x02
61#define IOC4_S_DMA_DIR 0x04
62#define IOC4_S_DMA_ACTIVE 0x08
63#define IOC4_S_DMA_ERROR 0x10
64#define IOC4_ATA_MEMERR 0x02
65
66/* Read/Write Directions */
67#define IOC4_DMA_WRITE 0x04
68#define IOC4_DMA_READ 0x00
69
70/* Interrupt Register Offsets */
71#define IOC4_INTR_REG 0x03
72#define IOC4_INTR_SET 0x05
73#define IOC4_INTR_CLEAR 0x07
74
75#define IOC4_IDE_CACHELINE_SIZE 128
76#define IOC4_CMD_CTL_BLK_SIZE 0x20
77#define IOC4_SUPPORTED_FIRMWARE_REV 46
78
79typedef struct {
80 u32 timing_reg0;
81 u32 timing_reg1;
82 u32 low_mem_ptr;
83 u32 high_mem_ptr;
84 u32 low_mem_addr;
85 u32 high_mem_addr;
86 u32 dev_byte_count;
87 u32 mem_byte_count;
88 u32 status;
89} ioc4_dma_regs_t;
90
91/* Each Physical Region Descriptor Entry size is 16 bytes (2 * 64 bits) */
92/* IOC4 has only 1 IDE channel */
93#define IOC4_PRD_BYTES 16
94#define IOC4_PRD_ENTRIES (PAGE_SIZE /(4*IOC4_PRD_BYTES))
95
96
97static void
98sgiioc4_init_hwif_ports(hw_regs_t * hw, unsigned long data_port,
99 unsigned long ctrl_port, unsigned long irq_port)
100{
101 unsigned long reg = data_port;
102 int i;
103
104 /* Registers are word (32 bit) aligned */
105 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++)
106 hw->io_ports[i] = reg + i * 4;
107
108 if (ctrl_port)
109 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
110
111 if (irq_port)
112 hw->io_ports[IDE_IRQ_OFFSET] = irq_port;
113}
114
115static void
116sgiioc4_maskproc(ide_drive_t * drive, int mask)
117{
118 ide_hwif_t *hwif = HWIF(drive);
119 hwif->OUTB(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
120 IDE_CONTROL_REG);
121}
122
123
124static int
125sgiioc4_checkirq(ide_hwif_t * hwif)
126{
127 u8 intr_reg =
128 hwif->INL(hwif->io_ports[IDE_IRQ_OFFSET] + IOC4_INTR_REG * 4);
129
130 if (intr_reg & 0x03)
131 return 1;
132
133 return 0;
134}
135
136
137static int
138sgiioc4_clearirq(ide_drive_t * drive)
139{
140 u32 intr_reg;
141 ide_hwif_t *hwif = HWIF(drive);
142 unsigned long other_ir =
143 hwif->io_ports[IDE_IRQ_OFFSET] + (IOC4_INTR_REG << 2);
144
145 /* Code to check for PCI error conditions */
146 intr_reg = hwif->INL(other_ir);
147 if (intr_reg & 0x03) { /* Valid IOC4-IDE interrupt */
148 /*
149 * Using hwif->INB to read the IDE_STATUS_REG has a side effect
150 * of clearing the interrupt. The first read should clear it
151 * if it is set. The second read should return a "clear" status
152 * if it got cleared. If not, then spin for a bit trying to
153 * clear it.
154 */
155 u8 stat = hwif->INB(IDE_STATUS_REG);
156 int count = 0;
157 stat = hwif->INB(IDE_STATUS_REG);
158 while ((stat & 0x80) && (count++ < 100)) {
159 udelay(1);
160 stat = hwif->INB(IDE_STATUS_REG);
161 }
162
163 if (intr_reg & 0x02) {
164 /* Error when transferring DMA data on PCI bus */
165 u32 pci_err_addr_low, pci_err_addr_high,
166 pci_stat_cmd_reg;
167
168 pci_err_addr_low =
169 hwif->INL(hwif->io_ports[IDE_IRQ_OFFSET]);
170 pci_err_addr_high =
171 hwif->INL(hwif->io_ports[IDE_IRQ_OFFSET] + 4);
172 pci_read_config_dword(hwif->pci_dev, PCI_COMMAND,
173 &pci_stat_cmd_reg);
174 printk(KERN_ERR
175 "%s(%s) : PCI Bus Error when doing DMA:"
176 " status-cmd reg is 0x%x\n",
177 __FUNCTION__, drive->name, pci_stat_cmd_reg);
178 printk(KERN_ERR
179 "%s(%s) : PCI Error Address is 0x%x%x\n",
180 __FUNCTION__, drive->name,
181 pci_err_addr_high, pci_err_addr_low);
182 /* Clear the PCI Error indicator */
183 pci_write_config_dword(hwif->pci_dev, PCI_COMMAND,
184 0x00000146);
185 }
186
187 /* Clear the Interrupt, Error bits on the IOC4 */
188 hwif->OUTL(0x03, other_ir);
189
190 intr_reg = hwif->INL(other_ir);
191 }
192
193 return intr_reg & 3;
194}
195
196static void sgiioc4_ide_dma_start(ide_drive_t * drive)
197{
198 ide_hwif_t *hwif = HWIF(drive);
199 unsigned int reg = hwif->INL(hwif->dma_base + IOC4_DMA_CTRL * 4);
200 unsigned int temp_reg = reg | IOC4_S_DMA_START;
201
202 hwif->OUTL(temp_reg, hwif->dma_base + IOC4_DMA_CTRL * 4);
203}
204
205static u32
206sgiioc4_ide_dma_stop(ide_hwif_t *hwif, u64 dma_base)
207{
208 u32 ioc4_dma;
209 int count;
210
211 count = 0;
212 ioc4_dma = hwif->INL(dma_base + IOC4_DMA_CTRL * 4);
213 while ((ioc4_dma & IOC4_S_DMA_STOP) && (count++ < 200)) {
214 udelay(1);
215 ioc4_dma = hwif->INL(dma_base + IOC4_DMA_CTRL * 4);
216 }
217 return ioc4_dma;
218}
219
220/* Stops the IOC4 DMA Engine */
221static int
222sgiioc4_ide_dma_end(ide_drive_t * drive)
223{
224 u32 ioc4_dma, bc_dev, bc_mem, num, valid = 0, cnt = 0;
225 ide_hwif_t *hwif = HWIF(drive);
226 u64 dma_base = hwif->dma_base;
227 int dma_stat = 0;
228 unsigned long *ending_dma = (unsigned long *) hwif->dma_base2;
229
230 hwif->OUTL(IOC4_S_DMA_STOP, dma_base + IOC4_DMA_CTRL * 4);
231
232 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
233
234 if (ioc4_dma & IOC4_S_DMA_STOP) {
235 printk(KERN_ERR
236 "%s(%s): IOC4 DMA STOP bit is still 1 :"
237 "ioc4_dma_reg 0x%x\n",
238 __FUNCTION__, drive->name, ioc4_dma);
239 dma_stat = 1;
240 }
241
242 /*
243 * The IOC4 will DMA 1's to the ending dma area to indicate that
244 * previous data DMA is complete. This is necessary because of relaxed
245 * ordering between register reads and DMA writes on the Altix.
246 */
247 while ((cnt++ < 200) && (!valid)) {
248 for (num = 0; num < 16; num++) {
249 if (ending_dma[num]) {
250 valid = 1;
251 break;
252 }
253 }
254 udelay(1);
255 }
256 if (!valid) {
257 printk(KERN_ERR "%s(%s) : DMA incomplete\n", __FUNCTION__,
258 drive->name);
259 dma_stat = 1;
260 }
261
262 bc_dev = hwif->INL(dma_base + IOC4_BC_DEV * 4);
263 bc_mem = hwif->INL(dma_base + IOC4_BC_MEM * 4);
264
265 if ((bc_dev & 0x01FF) || (bc_mem & 0x1FF)) {
266 if (bc_dev > bc_mem + 8) {
267 printk(KERN_ERR
268 "%s(%s): WARNING!! byte_count_dev %d "
269 "!= byte_count_mem %d\n",
270 __FUNCTION__, drive->name, bc_dev, bc_mem);
271 }
272 }
273
274 drive->waiting_for_dma = 0;
275 ide_destroy_dmatable(drive);
276
277 return dma_stat;
278}
279
280static int
281sgiioc4_ide_dma_check(ide_drive_t * drive)
282{
283 if (ide_config_drive_speed(drive, XFER_MW_DMA_2) != 0) {
284 printk(KERN_INFO
285 "Couldnot set %s in Multimode-2 DMA mode | "
286 "Drive %s using PIO instead\n",
287 drive->name, drive->name);
288 drive->using_dma = 0;
289 } else
290 drive->using_dma = 1;
291
292 return 0;
293}
294
295static int
296sgiioc4_ide_dma_on(ide_drive_t * drive)
297{
298 drive->using_dma = 1;
299
300 return HWIF(drive)->ide_dma_host_on(drive);
301}
302
303static int
304sgiioc4_ide_dma_off_quietly(ide_drive_t * drive)
305{
306 drive->using_dma = 0;
307
308 return HWIF(drive)->ide_dma_host_off(drive);
309}
310
311/* returns 1 if dma irq issued, 0 otherwise */
312static int
313sgiioc4_ide_dma_test_irq(ide_drive_t * drive)
314{
315 return sgiioc4_checkirq(HWIF(drive));
316}
317
318static int
319sgiioc4_ide_dma_host_on(ide_drive_t * drive)
320{
321 if (drive->using_dma)
322 return 0;
323
324 return 1;
325}
326
327static int
328sgiioc4_ide_dma_host_off(ide_drive_t * drive)
329{
330 sgiioc4_clearirq(drive);
331
332 return 0;
333}
334
335static int
336sgiioc4_ide_dma_lostirq(ide_drive_t * drive)
337{
338 HWIF(drive)->resetproc(drive);
339
340 return __ide_dma_lostirq(drive);
341}
342
343static void
344sgiioc4_resetproc(ide_drive_t * drive)
345{
346 sgiioc4_ide_dma_end(drive);
347 sgiioc4_clearirq(drive);
348}
349
350static u8
351sgiioc4_INB(unsigned long port)
352{
353 u8 reg = (u8) inb(port);
354
355 if ((port & 0xFFF) == 0x11C) { /* Status register of IOC4 */
356 if (reg & 0x51) { /* Not busy...check for interrupt */
357 unsigned long other_ir = port - 0x110;
358 unsigned int intr_reg = (u32) inl(other_ir);
359
360 /* Clear the Interrupt, Error bits on the IOC4 */
361 if (intr_reg & 0x03) {
362 outl(0x03, other_ir);
363 intr_reg = (u32) inl(other_ir);
364 }
365 }
366 }
367
368 return reg;
369}
370
371/* Creates a dma map for the scatter-gather list entries */
372static void __devinit
373ide_dma_sgiioc4(ide_hwif_t * hwif, unsigned long dma_base)
374{
375 int num_ports = sizeof (ioc4_dma_regs_t);
376
377 printk(KERN_INFO "%s: BM-DMA at 0x%04lx-0x%04lx\n", hwif->name,
378 dma_base, dma_base + num_ports - 1);
379
380 if (!request_region(dma_base, num_ports, hwif->name)) {
381 printk(KERN_ERR
382 "%s(%s) -- ERROR, Addresses 0x%p to 0x%p "
383 "ALREADY in use\n",
384 __FUNCTION__, hwif->name, (void *) dma_base,
385 (void *) dma_base + num_ports - 1);
386 goto dma_alloc_failure;
387 }
388
389 hwif->dma_base = dma_base;
390 hwif->dmatable_cpu = pci_alloc_consistent(hwif->pci_dev,
391 IOC4_PRD_ENTRIES * IOC4_PRD_BYTES,
392 &hwif->dmatable_dma);
393
394 if (!hwif->dmatable_cpu)
395 goto dma_alloc_failure;
396
397 hwif->sg_max_nents = IOC4_PRD_ENTRIES;
398
399 hwif->dma_base2 = (unsigned long)
400 pci_alloc_consistent(hwif->pci_dev,
401 IOC4_IDE_CACHELINE_SIZE,
402 (dma_addr_t *) &(hwif->dma_status));
403
404 if (!hwif->dma_base2)
405 goto dma_base2alloc_failure;
406
407 return;
408
409dma_base2alloc_failure:
410 pci_free_consistent(hwif->pci_dev,
411 IOC4_PRD_ENTRIES * IOC4_PRD_BYTES,
412 hwif->dmatable_cpu, hwif->dmatable_dma);
413 printk(KERN_INFO
414 "%s() -- Error! Unable to allocate DMA Maps for drive %s\n",
415 __FUNCTION__, hwif->name);
416 printk(KERN_INFO
417 "Changing from DMA to PIO mode for Drive %s\n", hwif->name);
418
419dma_alloc_failure:
420 /* Disable DMA because we couldnot allocate any DMA maps */
421 hwif->autodma = 0;
422 hwif->atapi_dma = 0;
423}
424
425/* Initializes the IOC4 DMA Engine */
426static void
427sgiioc4_configure_for_dma(int dma_direction, ide_drive_t * drive)
428{
429 u32 ioc4_dma;
430 ide_hwif_t *hwif = HWIF(drive);
431 u64 dma_base = hwif->dma_base;
432 u32 dma_addr, ending_dma_addr;
433
434 ioc4_dma = hwif->INL(dma_base + IOC4_DMA_CTRL * 4);
435
436 if (ioc4_dma & IOC4_S_DMA_ACTIVE) {
437 printk(KERN_WARNING
438 "%s(%s):Warning!! DMA from previous transfer was still active\n",
439 __FUNCTION__, drive->name);
440 hwif->OUTL(IOC4_S_DMA_STOP, dma_base + IOC4_DMA_CTRL * 4);
441 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
442
443 if (ioc4_dma & IOC4_S_DMA_STOP)
444 printk(KERN_ERR
445 "%s(%s) : IOC4 Dma STOP bit is still 1\n",
446 __FUNCTION__, drive->name);
447 }
448
449 ioc4_dma = hwif->INL(dma_base + IOC4_DMA_CTRL * 4);
450 if (ioc4_dma & IOC4_S_DMA_ERROR) {
451 printk(KERN_WARNING
452 "%s(%s) : Warning!! - DMA Error during Previous"
453 " transfer | status 0x%x\n",
454 __FUNCTION__, drive->name, ioc4_dma);
455 hwif->OUTL(IOC4_S_DMA_STOP, dma_base + IOC4_DMA_CTRL * 4);
456 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
457
458 if (ioc4_dma & IOC4_S_DMA_STOP)
459 printk(KERN_ERR
460 "%s(%s) : IOC4 DMA STOP bit is still 1\n",
461 __FUNCTION__, drive->name);
462 }
463
464 /* Address of the Scatter Gather List */
465 dma_addr = cpu_to_le32(hwif->dmatable_dma);
466 hwif->OUTL(dma_addr, dma_base + IOC4_DMA_PTR_L * 4);
467
468 /* Address of the Ending DMA */
469 memset((unsigned int *) hwif->dma_base2, 0, IOC4_IDE_CACHELINE_SIZE);
470 ending_dma_addr = cpu_to_le32(hwif->dma_status);
471 hwif->OUTL(ending_dma_addr, dma_base + IOC4_DMA_END_ADDR * 4);
472
473 hwif->OUTL(dma_direction, dma_base + IOC4_DMA_CTRL * 4);
474 drive->waiting_for_dma = 1;
475}
476
477/* IOC4 Scatter Gather list Format */
478/* 128 Bit entries to support 64 bit addresses in the future */
479/* The Scatter Gather list Entry should be in the BIG-ENDIAN Format */
480/* --------------------------------------------------------------------- */
481/* | Upper 32 bits - Zero | Lower 32 bits- address | */
482/* --------------------------------------------------------------------- */
483/* | Upper 32 bits - Zero |EOL| 15 unused | 16 Bit Length| */
484/* --------------------------------------------------------------------- */
485/* Creates the scatter gather list, DMA Table */
486static unsigned int
487sgiioc4_build_dma_table(ide_drive_t * drive, struct request *rq, int ddir)
488{
489 ide_hwif_t *hwif = HWIF(drive);
490 unsigned int *table = hwif->dmatable_cpu;
491 unsigned int count = 0, i = 1;
492 struct scatterlist *sg;
493
494 hwif->sg_nents = i = ide_build_sglist(drive, rq);
495
496 if (!i)
497 return 0; /* sglist of length Zero */
498
499 sg = hwif->sg_table;
500 while (i && sg_dma_len(sg)) {
501 dma_addr_t cur_addr;
502 int cur_len;
503 cur_addr = sg_dma_address(sg);
504 cur_len = sg_dma_len(sg);
505
506 while (cur_len) {
507 if (count++ >= IOC4_PRD_ENTRIES) {
508 printk(KERN_WARNING
509 "%s: DMA table too small\n",
510 drive->name);
511 goto use_pio_instead;
512 } else {
513 u32 xcount, bcount =
514 0x10000 - (cur_addr & 0xffff);
515
516 if (bcount > cur_len)
517 bcount = cur_len;
518
519 /* put the addr, length in
520 * the IOC4 dma-table format */
521 *table = 0x0;
522 table++;
523 *table = cpu_to_be32(cur_addr);
524 table++;
525 *table = 0x0;
526 table++;
527
528 xcount = bcount & 0xffff;
529 *table = cpu_to_be32(xcount);
530 table++;
531
532 cur_addr += bcount;
533 cur_len -= bcount;
534 }
535 }
536
537 sg++;
538 i--;
539 }
540
541 if (count) {
542 table--;
543 *table |= cpu_to_be32(0x80000000);
544 return count;
545 }
546
547use_pio_instead:
548 pci_unmap_sg(hwif->pci_dev, hwif->sg_table, hwif->sg_nents,
549 hwif->sg_dma_direction);
550
551 return 0; /* revert to PIO for this request */
552}
553
554static int sgiioc4_ide_dma_setup(ide_drive_t *drive)
555{
556 struct request *rq = HWGROUP(drive)->rq;
557 unsigned int count = 0;
558 int ddir;
559
560 if (rq_data_dir(rq))
561 ddir = PCI_DMA_TODEVICE;
562 else
563 ddir = PCI_DMA_FROMDEVICE;
564
565 if (!(count = sgiioc4_build_dma_table(drive, rq, ddir))) {
566 /* try PIO instead of DMA */
567 ide_map_sg(drive, rq);
568 return 1;
569 }
570
571 if (rq_data_dir(rq))
572 /* Writes TO the IOC4 FROM Main Memory */
573 ddir = IOC4_DMA_READ;
574 else
575 /* Writes FROM the IOC4 TO Main Memory */
576 ddir = IOC4_DMA_WRITE;
577
578 sgiioc4_configure_for_dma(ddir, drive);
579
580 return 0;
581}
582
583static void __devinit
584ide_init_sgiioc4(ide_hwif_t * hwif)
585{
586 hwif->mmio = 2;
587 hwif->autodma = 1;
588 hwif->atapi_dma = 1;
589 hwif->ultra_mask = 0x0; /* Disable Ultra DMA */
590 hwif->mwdma_mask = 0x2; /* Multimode-2 DMA */
591 hwif->swdma_mask = 0x2;
592 hwif->tuneproc = NULL; /* Sets timing for PIO mode */
593 hwif->speedproc = NULL; /* Sets timing for DMA &/or PIO modes */
594 hwif->selectproc = NULL;/* Use the default routine to select drive */
595 hwif->reset_poll = NULL;/* No HBA specific reset_poll needed */
596 hwif->pre_reset = NULL; /* No HBA specific pre_set needed */
597 hwif->resetproc = &sgiioc4_resetproc;/* Reset DMA engine,
598 clear interrupts */
599 hwif->intrproc = NULL; /* Enable or Disable interrupt from drive */
600 hwif->maskproc = &sgiioc4_maskproc; /* Mask on/off NIEN register */
601 hwif->quirkproc = NULL;
602 hwif->busproc = NULL;
603
604 hwif->dma_setup = &sgiioc4_ide_dma_setup;
605 hwif->dma_start = &sgiioc4_ide_dma_start;
606 hwif->ide_dma_end = &sgiioc4_ide_dma_end;
607 hwif->ide_dma_check = &sgiioc4_ide_dma_check;
608 hwif->ide_dma_on = &sgiioc4_ide_dma_on;
609 hwif->ide_dma_off_quietly = &sgiioc4_ide_dma_off_quietly;
610 hwif->ide_dma_test_irq = &sgiioc4_ide_dma_test_irq;
611 hwif->ide_dma_host_on = &sgiioc4_ide_dma_host_on;
612 hwif->ide_dma_host_off = &sgiioc4_ide_dma_host_off;
613 hwif->ide_dma_lostirq = &sgiioc4_ide_dma_lostirq;
614 hwif->ide_dma_timeout = &__ide_dma_timeout;
615 hwif->INB = &sgiioc4_INB;
616}
617
618static int __devinit
619sgiioc4_ide_setup_pci_device(struct pci_dev *dev, ide_pci_device_t * d)
620{
621 unsigned long base, ctl, dma_base, irqport;
622 ide_hwif_t *hwif;
623 int h;
624
625 for (h = 0; h < MAX_HWIFS; ++h) {
626 hwif = &ide_hwifs[h];
627 /* Find an empty HWIF */
628 if (hwif->chipset == ide_unknown)
629 break;
630 }
631
632 /* Get the CmdBlk and CtrlBlk Base Registers */
633 base = pci_resource_start(dev, 0) + IOC4_CMD_OFFSET;
634 ctl = pci_resource_start(dev, 0) + IOC4_CTRL_OFFSET;
635 irqport = pci_resource_start(dev, 0) + IOC4_INTR_OFFSET;
636 dma_base = pci_resource_start(dev, 0) + IOC4_DMA_OFFSET;
637
638 if (!request_region(base, IOC4_CMD_CTL_BLK_SIZE, hwif->name)) {
639 printk(KERN_ERR
640 "%s : %s -- ERROR, Port Addresses "
641 "0x%p to 0x%p ALREADY in use\n",
642 __FUNCTION__, hwif->name, (void *) base,
643 (void *) base + IOC4_CMD_CTL_BLK_SIZE);
644 return -ENOMEM;
645 }
646
647 if (hwif->io_ports[IDE_DATA_OFFSET] != base) {
648 /* Initialize the IO registers */
649 sgiioc4_init_hwif_ports(&hwif->hw, base, ctl, irqport);
650 memcpy(hwif->io_ports, hwif->hw.io_ports,
651 sizeof (hwif->io_ports));
652 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET];
653 }
654
655 hwif->irq = dev->irq;
656 hwif->chipset = ide_pci;
657 hwif->pci_dev = dev;
658 hwif->channel = 0; /* Single Channel chip */
659 hwif->cds = (struct ide_pci_device_s *) d;
660 hwif->gendev.parent = &dev->dev;/* setup proper ancestral information */
661
662 /* Initializing chipset IRQ Registers */
663 hwif->OUTL(0x03, irqport + IOC4_INTR_SET * 4);
664
665 ide_init_sgiioc4(hwif);
666
667 if (dma_base)
668 ide_dma_sgiioc4(hwif, dma_base);
669 else
670 printk(KERN_INFO "%s: %s Bus-Master DMA disabled\n",
671 hwif->name, d->name);
672
673 if (probe_hwif_init(hwif))
674 return -EIO;
675
676 /* Create /proc/ide entries */
677 create_proc_ide_interfaces();
678
679 return 0;
680}
681
682static unsigned int __devinit
683pci_init_sgiioc4(struct pci_dev *dev, ide_pci_device_t * d)
684{
685 unsigned int class_rev;
686 int ret;
687
688 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
689 class_rev &= 0xff;
690 printk(KERN_INFO "%s: IDE controller at PCI slot %s, revision %d\n",
691 d->name, pci_name(dev), class_rev);
692 if (class_rev < IOC4_SUPPORTED_FIRMWARE_REV) {
693 printk(KERN_ERR "Skipping %s IDE controller in slot %s: "
694 "firmware is obsolete - please upgrade to revision"
695 "46 or higher\n", d->name, pci_name(dev));
696 ret = -EAGAIN;
697 goto out;
698 }
699 ret = sgiioc4_ide_setup_pci_device(dev, d);
700out:
701 return ret;
702}
703
704static ide_pci_device_t sgiioc4_chipsets[] __devinitdata = {
705 {
706 /* Channel 0 */
707 .name = "SGIIOC4",
708 .init_hwif = ide_init_sgiioc4,
709 .init_dma = ide_dma_sgiioc4,
710 .channels = 1,
711 .autodma = AUTODMA,
712 /* SGI IOC4 doesn't have enablebits. */
713 .bootable = ON_BOARD,
714 }
715};
716
717int
718ioc4_ide_attach_one(struct pci_dev *dev, const struct pci_device_id *id)
719{
720 return pci_init_sgiioc4(dev, &sgiioc4_chipsets[id->driver_data]);
721}
722
723
724MODULE_AUTHOR("Aniket Malatpure - Silicon Graphics Inc. (SGI)");
725MODULE_DESCRIPTION("IDE PCI driver module for SGI IOC4 Base-IO Card");
726MODULE_LICENSE("GPL");
727
728EXPORT_SYMBOL(ioc4_ide_attach_one);
diff --git a/drivers/ide/pci/siimage.c b/drivers/ide/pci/siimage.c
new file mode 100644
index 000000000000..2b9961b88135
--- /dev/null
+++ b/drivers/ide/pci/siimage.c
@@ -0,0 +1,1133 @@
1/*
2 * linux/drivers/ide/pci/siimage.c Version 1.07 Nov 30, 2003
3 *
4 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2003 Red Hat <alan@redhat.com>
6 *
7 * May be copied or modified under the terms of the GNU General Public License
8 *
9 * Documentation available under NDA only
10 *
11 *
12 * FAQ Items:
13 * If you are using Marvell SATA-IDE adapters with Maxtor drives
14 * ensure the system is set up for ATA100/UDMA5 not UDMA6.
15 *
16 * If you are using WD drives with SATA bridges you must set the
17 * drive to "Single". "Master" will hang
18 *
19 * If you have strange problems with nVidia chipset systems please
20 * see the SI support documentation and update your system BIOS
21 * if neccessary
22 */
23
24#include <linux/config.h>
25#include <linux/types.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28#include <linux/delay.h>
29#include <linux/hdreg.h>
30#include <linux/ide.h>
31#include <linux/init.h>
32
33#include <asm/io.h>
34
35#undef SIIMAGE_VIRTUAL_DMAPIO
36#undef SIIMAGE_LARGE_DMA
37
38/**
39 * pdev_is_sata - check if device is SATA
40 * @pdev: PCI device to check
41 *
42 * Returns true if this is a SATA controller
43 */
44
45static int pdev_is_sata(struct pci_dev *pdev)
46{
47 switch(pdev->device)
48 {
49 case PCI_DEVICE_ID_SII_3112:
50 case PCI_DEVICE_ID_SII_1210SA:
51 return 1;
52 case PCI_DEVICE_ID_SII_680:
53 return 0;
54 }
55 BUG();
56 return 0;
57}
58
59/**
60 * is_sata - check if hwif is SATA
61 * @hwif: interface to check
62 *
63 * Returns true if this is a SATA controller
64 */
65
66static inline int is_sata(ide_hwif_t *hwif)
67{
68 return pdev_is_sata(hwif->pci_dev);
69}
70
71/**
72 * siimage_selreg - return register base
73 * @hwif: interface
74 * @r: config offset
75 *
76 * Turn a config register offset into the right address in either
77 * PCI space or MMIO space to access the control register in question
78 * Thankfully this is a configuration operation so isnt performance
79 * criticial.
80 */
81
82static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
83{
84 unsigned long base = (unsigned long)hwif->hwif_data;
85 base += 0xA0 + r;
86 if(hwif->mmio)
87 base += (hwif->channel << 6);
88 else
89 base += (hwif->channel << 4);
90 return base;
91}
92
93/**
94 * siimage_seldev - return register base
95 * @hwif: interface
96 * @r: config offset
97 *
98 * Turn a config register offset into the right address in either
99 * PCI space or MMIO space to access the control register in question
100 * including accounting for the unit shift.
101 */
102
103static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
104{
105 ide_hwif_t *hwif = HWIF(drive);
106 unsigned long base = (unsigned long)hwif->hwif_data;
107 base += 0xA0 + r;
108 if(hwif->mmio)
109 base += (hwif->channel << 6);
110 else
111 base += (hwif->channel << 4);
112 base |= drive->select.b.unit << drive->select.b.unit;
113 return base;
114}
115
116/**
117 * siimage_ratemask - Compute available modes
118 * @drive: IDE drive
119 *
120 * Compute the available speeds for the devices on the interface.
121 * For the CMD680 this depends on the clocking mode (scsc), for the
122 * SI3312 SATA controller life is a bit simpler. Enforce UDMA33
123 * as a limit if there is no 80pin cable present.
124 */
125
126static byte siimage_ratemask (ide_drive_t *drive)
127{
128 ide_hwif_t *hwif = HWIF(drive);
129 u8 mode = 0, scsc = 0;
130 unsigned long base = (unsigned long) hwif->hwif_data;
131
132 if (hwif->mmio)
133 scsc = hwif->INB(base + 0x4A);
134 else
135 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc);
136
137 if(is_sata(hwif))
138 {
139 if(strstr(drive->id->model, "Maxtor"))
140 return 3;
141 return 4;
142 }
143
144 if ((scsc & 0x30) == 0x10) /* 133 */
145 mode = 4;
146 else if ((scsc & 0x30) == 0x20) /* 2xPCI */
147 mode = 4;
148 else if ((scsc & 0x30) == 0x00) /* 100 */
149 mode = 3;
150 else /* Disabled ? */
151 BUG();
152
153 if (!eighty_ninty_three(drive))
154 mode = min(mode, (u8)1);
155 return mode;
156}
157
158/**
159 * siimage_taskfile_timing - turn timing data to a mode
160 * @hwif: interface to query
161 *
162 * Read the timing data for the interface and return the
163 * mode that is being used.
164 */
165
166static byte siimage_taskfile_timing (ide_hwif_t *hwif)
167{
168 u16 timing = 0x328a;
169 unsigned long addr = siimage_selreg(hwif, 2);
170
171 if (hwif->mmio)
172 timing = hwif->INW(addr);
173 else
174 pci_read_config_word(hwif->pci_dev, addr, &timing);
175
176 switch (timing) {
177 case 0x10c1: return 4;
178 case 0x10c3: return 3;
179 case 0x1104:
180 case 0x1281: return 2;
181 case 0x2283: return 1;
182 case 0x328a:
183 default: return 0;
184 }
185}
186
187/**
188 * simmage_tuneproc - tune a drive
189 * @drive: drive to tune
190 * @mode_wanted: the target operating mode
191 *
192 * Load the timing settings for this device mode into the
193 * controller. If we are in PIO mode 3 or 4 turn on IORDY
194 * monitoring (bit 9). The TF timing is bits 31:16
195 */
196
197static void siimage_tuneproc (ide_drive_t *drive, byte mode_wanted)
198{
199 ide_hwif_t *hwif = HWIF(drive);
200 u32 speedt = 0;
201 u16 speedp = 0;
202 unsigned long addr = siimage_seldev(drive, 0x04);
203 unsigned long tfaddr = siimage_selreg(hwif, 0x02);
204
205 /* cheat for now and use the docs */
206 switch(mode_wanted) {
207 case 4:
208 speedp = 0x10c1;
209 speedt = 0x10c1;
210 break;
211 case 3:
212 speedp = 0x10C3;
213 speedt = 0x10C3;
214 break;
215 case 2:
216 speedp = 0x1104;
217 speedt = 0x1281;
218 break;
219 case 1:
220 speedp = 0x2283;
221 speedt = 0x1281;
222 break;
223 case 0:
224 default:
225 speedp = 0x328A;
226 speedt = 0x328A;
227 break;
228 }
229 if (hwif->mmio)
230 {
231 hwif->OUTW(speedt, addr);
232 hwif->OUTW(speedp, tfaddr);
233 /* Now set up IORDY */
234 if(mode_wanted == 3 || mode_wanted == 4)
235 hwif->OUTW(hwif->INW(tfaddr-2)|0x200, tfaddr-2);
236 else
237 hwif->OUTW(hwif->INW(tfaddr-2)&~0x200, tfaddr-2);
238 }
239 else
240 {
241 pci_write_config_word(hwif->pci_dev, addr, speedp);
242 pci_write_config_word(hwif->pci_dev, tfaddr, speedt);
243 pci_read_config_word(hwif->pci_dev, tfaddr-2, &speedp);
244 speedp &= ~0x200;
245 /* Set IORDY for mode 3 or 4 */
246 if(mode_wanted == 3 || mode_wanted == 4)
247 speedp |= 0x200;
248 pci_write_config_word(hwif->pci_dev, tfaddr-2, speedp);
249 }
250}
251
252/**
253 * config_siimage_chipset_for_pio - set drive timings
254 * @drive: drive to tune
255 * @speed we want
256 *
257 * Compute the best pio mode we can for a given device. Also honour
258 * the timings for the driver when dealing with mixed devices. Some
259 * of this is ugly but its all wrapped up here
260 *
261 * The SI680 can also do VDMA - we need to start using that
262 *
263 * FIXME: we use the BIOS channel timings to avoid driving the task
264 * files too fast at the disk. We need to compute the master/slave
265 * drive PIO mode properly so that we can up the speed on a hotplug
266 * system.
267 */
268
269static void config_siimage_chipset_for_pio (ide_drive_t *drive, byte set_speed)
270{
271 u8 channel_timings = siimage_taskfile_timing(HWIF(drive));
272 u8 speed = 0, set_pio = ide_get_best_pio_mode(drive, 4, 5, NULL);
273
274 /* WARNING PIO timing mess is going to happen b/w devices, argh */
275 if ((channel_timings != set_pio) && (set_pio > channel_timings))
276 set_pio = channel_timings;
277
278 siimage_tuneproc(drive, set_pio);
279 speed = XFER_PIO_0 + set_pio;
280 if (set_speed)
281 (void) ide_config_drive_speed(drive, speed);
282}
283
284static void config_chipset_for_pio (ide_drive_t *drive, byte set_speed)
285{
286 config_siimage_chipset_for_pio(drive, set_speed);
287}
288
289/**
290 * siimage_tune_chipset - set controller timings
291 * @drive: Drive to set up
292 * @xferspeed: speed we want to achieve
293 *
294 * Tune the SII chipset for the desired mode. If we can't achieve
295 * the desired mode then tune for a lower one, but ultimately
296 * make the thing work.
297 */
298
299static int siimage_tune_chipset (ide_drive_t *drive, byte xferspeed)
300{
301 u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
302 u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
303 u16 dma[] = { 0x2208, 0x10C2, 0x10C1 };
304
305 ide_hwif_t *hwif = HWIF(drive);
306 u16 ultra = 0, multi = 0;
307 u8 mode = 0, unit = drive->select.b.unit;
308 u8 speed = ide_rate_filter(siimage_ratemask(drive), xferspeed);
309 unsigned long base = (unsigned long)hwif->hwif_data;
310 u8 scsc = 0, addr_mask = ((hwif->channel) ?
311 ((hwif->mmio) ? 0xF4 : 0x84) :
312 ((hwif->mmio) ? 0xB4 : 0x80));
313
314 unsigned long ma = siimage_seldev(drive, 0x08);
315 unsigned long ua = siimage_seldev(drive, 0x0C);
316
317 if (hwif->mmio) {
318 scsc = hwif->INB(base + 0x4A);
319 mode = hwif->INB(base + addr_mask);
320 multi = hwif->INW(ma);
321 ultra = hwif->INW(ua);
322 } else {
323 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc);
324 pci_read_config_byte(hwif->pci_dev, addr_mask, &mode);
325 pci_read_config_word(hwif->pci_dev, ma, &multi);
326 pci_read_config_word(hwif->pci_dev, ua, &ultra);
327 }
328
329 mode &= ~((unit) ? 0x30 : 0x03);
330 ultra &= ~0x3F;
331 scsc = ((scsc & 0x30) == 0x00) ? 0 : 1;
332
333 scsc = is_sata(hwif) ? 1 : scsc;
334
335 switch(speed) {
336 case XFER_PIO_4:
337 case XFER_PIO_3:
338 case XFER_PIO_2:
339 case XFER_PIO_1:
340 case XFER_PIO_0:
341 siimage_tuneproc(drive, (speed - XFER_PIO_0));
342 mode |= ((unit) ? 0x10 : 0x01);
343 break;
344 case XFER_MW_DMA_2:
345 case XFER_MW_DMA_1:
346 case XFER_MW_DMA_0:
347 multi = dma[speed - XFER_MW_DMA_0];
348 mode |= ((unit) ? 0x20 : 0x02);
349 config_siimage_chipset_for_pio(drive, 0);
350 break;
351 case XFER_UDMA_6:
352 case XFER_UDMA_5:
353 case XFER_UDMA_4:
354 case XFER_UDMA_3:
355 case XFER_UDMA_2:
356 case XFER_UDMA_1:
357 case XFER_UDMA_0:
358 multi = dma[2];
359 ultra |= ((scsc) ? (ultra6[speed - XFER_UDMA_0]) :
360 (ultra5[speed - XFER_UDMA_0]));
361 mode |= ((unit) ? 0x30 : 0x03);
362 config_siimage_chipset_for_pio(drive, 0);
363 break;
364 default:
365 return 1;
366 }
367
368 if (hwif->mmio) {
369 hwif->OUTB(mode, base + addr_mask);
370 hwif->OUTW(multi, ma);
371 hwif->OUTW(ultra, ua);
372 } else {
373 pci_write_config_byte(hwif->pci_dev, addr_mask, mode);
374 pci_write_config_word(hwif->pci_dev, ma, multi);
375 pci_write_config_word(hwif->pci_dev, ua, ultra);
376 }
377 return (ide_config_drive_speed(drive, speed));
378}
379
380/**
381 * config_chipset_for_dma - configure for DMA
382 * @drive: drive to configure
383 *
384 * Called by the IDE layer when it wants the timings set up.
385 * For the CMD680 we also need to set up the PIO timings and
386 * enable DMA.
387 */
388
389static int config_chipset_for_dma (ide_drive_t *drive)
390{
391 u8 speed = ide_dma_speed(drive, siimage_ratemask(drive));
392
393 config_chipset_for_pio(drive, !speed);
394
395 if (!speed)
396 return 0;
397
398 if (ide_set_xfer_rate(drive, speed))
399 return 0;
400
401 if (!drive->init_speed)
402 drive->init_speed = speed;
403
404 return ide_dma_enable(drive);
405}
406
407/**
408 * siimage_configure_drive_for_dma - set up for DMA transfers
409 * @drive: drive we are going to set up
410 *
411 * Set up the drive for DMA, tune the controller and drive as
412 * required. If the drive isn't suitable for DMA or we hit
413 * other problems then we will drop down to PIO and set up
414 * PIO appropriately
415 */
416
417static int siimage_config_drive_for_dma (ide_drive_t *drive)
418{
419 ide_hwif_t *hwif = HWIF(drive);
420 struct hd_driveid *id = drive->id;
421
422 if ((id->capability & 1) != 0 && drive->autodma) {
423
424 if (ide_use_dma(drive)) {
425 if (config_chipset_for_dma(drive))
426 return hwif->ide_dma_on(drive);
427 }
428
429 goto fast_ata_pio;
430
431 } else if ((id->capability & 8) || (id->field_valid & 2)) {
432fast_ata_pio:
433 config_chipset_for_pio(drive, 1);
434 return hwif->ide_dma_off_quietly(drive);
435 }
436 /* IORDY not supported */
437 return 0;
438}
439
440/* returns 1 if dma irq issued, 0 otherwise */
441static int siimage_io_ide_dma_test_irq (ide_drive_t *drive)
442{
443 ide_hwif_t *hwif = HWIF(drive);
444 u8 dma_altstat = 0;
445 unsigned long addr = siimage_selreg(hwif, 1);
446
447 /* return 1 if INTR asserted */
448 if ((hwif->INB(hwif->dma_status) & 4) == 4)
449 return 1;
450
451 /* return 1 if Device INTR asserted */
452 pci_read_config_byte(hwif->pci_dev, addr, &dma_altstat);
453 if (dma_altstat & 8)
454 return 0; //return 1;
455 return 0;
456}
457
458#if 0
459/**
460 * siimage_mmio_ide_dma_count - DMA bytes done
461 * @drive
462 *
463 * If we are doing VDMA the CMD680 requires a little bit
464 * of more careful handling and we have to read the counts
465 * off ourselves. For non VDMA life is normal.
466 */
467
468static int siimage_mmio_ide_dma_count (ide_drive_t *drive)
469{
470#ifdef SIIMAGE_VIRTUAL_DMAPIO
471 struct request *rq = HWGROUP(drive)->rq;
472 ide_hwif_t *hwif = HWIF(drive);
473 u32 count = (rq->nr_sectors * SECTOR_SIZE);
474 u32 rcount = 0;
475 unsigned long addr = siimage_selreg(hwif, 0x1C);
476
477 hwif->OUTL(count, addr);
478 rcount = hwif->INL(addr);
479
480 printk("\n%s: count = %d, rcount = %d, nr_sectors = %lu\n",
481 drive->name, count, rcount, rq->nr_sectors);
482
483#endif /* SIIMAGE_VIRTUAL_DMAPIO */
484 return __ide_dma_count(drive);
485}
486#endif
487
488/**
489 * siimage_mmio_ide_dma_test_irq - check we caused an IRQ
490 * @drive: drive we are testing
491 *
492 * Check if we caused an IDE DMA interrupt. We may also have caused
493 * SATA status interrupts, if so we clean them up and continue.
494 */
495
496static int siimage_mmio_ide_dma_test_irq (ide_drive_t *drive)
497{
498 ide_hwif_t *hwif = HWIF(drive);
499 unsigned long base = (unsigned long)hwif->hwif_data;
500 unsigned long addr = siimage_selreg(hwif, 0x1);
501
502 if (SATA_ERROR_REG) {
503 u32 ext_stat = hwif->INL(base + 0x10);
504 u8 watchdog = 0;
505 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
506 u32 sata_error = hwif->INL(SATA_ERROR_REG);
507 hwif->OUTL(sata_error, SATA_ERROR_REG);
508 watchdog = (sata_error & 0x00680000) ? 1 : 0;
509#if 1
510 printk(KERN_WARNING "%s: sata_error = 0x%08x, "
511 "watchdog = %d, %s\n",
512 drive->name, sata_error, watchdog,
513 __FUNCTION__);
514#endif
515
516 } else {
517 watchdog = (ext_stat & 0x8000) ? 1 : 0;
518 }
519 ext_stat >>= 16;
520
521 if (!(ext_stat & 0x0404) && !watchdog)
522 return 0;
523 }
524
525 /* return 1 if INTR asserted */
526 if ((hwif->INB(hwif->dma_status) & 0x04) == 0x04)
527 return 1;
528
529 /* return 1 if Device INTR asserted */
530 if ((hwif->INB(addr) & 8) == 8)
531 return 0; //return 1;
532
533 return 0;
534}
535
536/**
537 * siimage_busproc - bus isolation ioctl
538 * @drive: drive to isolate/restore
539 * @state: bus state to set
540 *
541 * Used by the SII3112 to handle bus isolation. As this is a
542 * SATA controller the work required is quite limited, we
543 * just have to clean up the statistics
544 */
545
546static int siimage_busproc (ide_drive_t * drive, int state)
547{
548 ide_hwif_t *hwif = HWIF(drive);
549 u32 stat_config = 0;
550 unsigned long addr = siimage_selreg(hwif, 0);
551
552 if (hwif->mmio) {
553 stat_config = hwif->INL(addr);
554 } else
555 pci_read_config_dword(hwif->pci_dev, addr, &stat_config);
556
557 switch (state) {
558 case BUSSTATE_ON:
559 hwif->drives[0].failures = 0;
560 hwif->drives[1].failures = 0;
561 break;
562 case BUSSTATE_OFF:
563 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
564 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
565 break;
566 case BUSSTATE_TRISTATE:
567 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
568 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
569 break;
570 default:
571 return -EINVAL;
572 }
573 hwif->bus_state = state;
574 return 0;
575}
576
577/**
578 * siimage_reset_poll - wait for sata reset
579 * @drive: drive we are resetting
580 *
581 * Poll the SATA phy and see whether it has come back from the dead
582 * yet.
583 */
584
585static int siimage_reset_poll (ide_drive_t *drive)
586{
587 if (SATA_STATUS_REG) {
588 ide_hwif_t *hwif = HWIF(drive);
589
590 if ((hwif->INL(SATA_STATUS_REG) & 0x03) != 0x03) {
591 printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
592 hwif->name, hwif->INL(SATA_STATUS_REG));
593 HWGROUP(drive)->polling = 0;
594 return ide_started;
595 }
596 return 0;
597 } else {
598 return 0;
599 }
600}
601
602/**
603 * siimage_pre_reset - reset hook
604 * @drive: IDE device being reset
605 *
606 * For the SATA devices we need to handle recalibration/geometry
607 * differently
608 */
609
610static void siimage_pre_reset (ide_drive_t *drive)
611{
612 if (drive->media != ide_disk)
613 return;
614
615 if (is_sata(HWIF(drive)))
616 {
617 drive->special.b.set_geometry = 0;
618 drive->special.b.recalibrate = 0;
619 }
620}
621
622/**
623 * siimage_reset - reset a device on an siimage controller
624 * @drive: drive to reset
625 *
626 * Perform a controller level reset fo the device. For
627 * SATA we must also check the PHY.
628 */
629
630static void siimage_reset (ide_drive_t *drive)
631{
632 ide_hwif_t *hwif = HWIF(drive);
633 u8 reset = 0;
634 unsigned long addr = siimage_selreg(hwif, 0);
635
636 if (hwif->mmio) {
637 reset = hwif->INB(addr);
638 hwif->OUTB((reset|0x03), addr);
639 /* FIXME:posting */
640 udelay(25);
641 hwif->OUTB(reset, addr);
642 (void) hwif->INB(addr);
643 } else {
644 pci_read_config_byte(hwif->pci_dev, addr, &reset);
645 pci_write_config_byte(hwif->pci_dev, addr, reset|0x03);
646 udelay(25);
647 pci_write_config_byte(hwif->pci_dev, addr, reset);
648 pci_read_config_byte(hwif->pci_dev, addr, &reset);
649 }
650
651 if (SATA_STATUS_REG) {
652 u32 sata_stat = hwif->INL(SATA_STATUS_REG);
653 printk(KERN_WARNING "%s: reset phy, status=0x%08x, %s\n",
654 hwif->name, sata_stat, __FUNCTION__);
655 if (!(sata_stat)) {
656 printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
657 hwif->name, sata_stat);
658 drive->failures++;
659 }
660 }
661
662}
663
664/**
665 * proc_reports_siimage - add siimage controller to proc
666 * @dev: PCI device
667 * @clocking: SCSC value
668 * @name: controller name
669 *
670 * Report the clocking mode of the controller and add it to
671 * the /proc interface layer
672 */
673
674static void proc_reports_siimage (struct pci_dev *dev, u8 clocking, const char *name)
675{
676 if (!pdev_is_sata(dev)) {
677 printk(KERN_INFO "%s: BASE CLOCK ", name);
678 clocking &= 0x03;
679 switch (clocking) {
680 case 0x03: printk("DISABLED!\n"); break;
681 case 0x02: printk("== 2X PCI\n"); break;
682 case 0x01: printk("== 133\n"); break;
683 case 0x00: printk("== 100\n"); break;
684 }
685 }
686}
687
688/**
689 * setup_mmio_siimage - switch an SI controller into MMIO
690 * @dev: PCI device we are configuring
691 * @name: device name
692 *
693 * Attempt to put the device into mmio mode. There are some slight
694 * complications here with certain systems where the mmio bar isnt
695 * mapped so we have to be sure we can fall back to I/O.
696 */
697
698static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name)
699{
700 unsigned long bar5 = pci_resource_start(dev, 5);
701 unsigned long barsize = pci_resource_len(dev, 5);
702 u8 tmpbyte = 0;
703 void __iomem *ioaddr;
704
705 /*
706 * Drop back to PIO if we can't map the mmio. Some
707 * systems seem to get terminally confused in the PCI
708 * spaces.
709 */
710
711 if(!request_mem_region(bar5, barsize, name))
712 {
713 printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n");
714 return 0;
715 }
716
717 ioaddr = ioremap(bar5, barsize);
718
719 if (ioaddr == NULL)
720 {
721 release_mem_region(bar5, barsize);
722 return 0;
723 }
724
725 pci_set_master(dev);
726 pci_set_drvdata(dev, (void *) ioaddr);
727
728 if (pdev_is_sata(dev)) {
729 writel(0, ioaddr + 0x148);
730 writel(0, ioaddr + 0x1C8);
731 }
732
733 writeb(0, ioaddr + 0xB4);
734 writeb(0, ioaddr + 0xF4);
735 tmpbyte = readb(ioaddr + 0x4A);
736
737 switch(tmpbyte & 0x30) {
738 case 0x00:
739 /* In 100 MHz clocking, try and switch to 133 */
740 writeb(tmpbyte|0x10, ioaddr + 0x4A);
741 break;
742 case 0x10:
743 /* On 133Mhz clocking */
744 break;
745 case 0x20:
746 /* On PCIx2 clocking */
747 break;
748 case 0x30:
749 /* Clocking is disabled */
750 /* 133 clock attempt to force it on */
751 writeb(tmpbyte & ~0x20, ioaddr + 0x4A);
752 break;
753 }
754
755 writeb( 0x72, ioaddr + 0xA1);
756 writew( 0x328A, ioaddr + 0xA2);
757 writel(0x62DD62DD, ioaddr + 0xA4);
758 writel(0x43924392, ioaddr + 0xA8);
759 writel(0x40094009, ioaddr + 0xAC);
760 writeb( 0x72, ioaddr + 0xE1);
761 writew( 0x328A, ioaddr + 0xE2);
762 writel(0x62DD62DD, ioaddr + 0xE4);
763 writel(0x43924392, ioaddr + 0xE8);
764 writel(0x40094009, ioaddr + 0xEC);
765
766 if (pdev_is_sata(dev)) {
767 writel(0xFFFF0000, ioaddr + 0x108);
768 writel(0xFFFF0000, ioaddr + 0x188);
769 writel(0x00680000, ioaddr + 0x148);
770 writel(0x00680000, ioaddr + 0x1C8);
771 }
772
773 tmpbyte = readb(ioaddr + 0x4A);
774
775 proc_reports_siimage(dev, (tmpbyte>>4), name);
776 return 1;
777}
778
779/**
780 * init_chipset_siimage - set up an SI device
781 * @dev: PCI device
782 * @name: device name
783 *
784 * Perform the initial PCI set up for this device. Attempt to switch
785 * to 133MHz clocking if the system isn't already set up to do it.
786 */
787
788static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const char *name)
789{
790 u32 class_rev = 0;
791 u8 tmpbyte = 0;
792 u8 BA5_EN = 0;
793
794 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
795 class_rev &= 0xff;
796 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255);
797
798 pci_read_config_byte(dev, 0x8A, &BA5_EN);
799 if ((BA5_EN & 0x01) || (pci_resource_start(dev, 5))) {
800 if (setup_mmio_siimage(dev, name)) {
801 return 0;
802 }
803 }
804
805 pci_write_config_byte(dev, 0x80, 0x00);
806 pci_write_config_byte(dev, 0x84, 0x00);
807 pci_read_config_byte(dev, 0x8A, &tmpbyte);
808 switch(tmpbyte & 0x30) {
809 case 0x00:
810 /* 133 clock attempt to force it on */
811 pci_write_config_byte(dev, 0x8A, tmpbyte|0x10);
812 case 0x30:
813 /* if clocking is disabled */
814 /* 133 clock attempt to force it on */
815 pci_write_config_byte(dev, 0x8A, tmpbyte & ~0x20);
816 case 0x10:
817 /* 133 already */
818 break;
819 case 0x20:
820 /* BIOS set PCI x2 clocking */
821 break;
822 }
823
824 pci_read_config_byte(dev, 0x8A, &tmpbyte);
825
826 pci_write_config_byte(dev, 0xA1, 0x72);
827 pci_write_config_word(dev, 0xA2, 0x328A);
828 pci_write_config_dword(dev, 0xA4, 0x62DD62DD);
829 pci_write_config_dword(dev, 0xA8, 0x43924392);
830 pci_write_config_dword(dev, 0xAC, 0x40094009);
831 pci_write_config_byte(dev, 0xB1, 0x72);
832 pci_write_config_word(dev, 0xB2, 0x328A);
833 pci_write_config_dword(dev, 0xB4, 0x62DD62DD);
834 pci_write_config_dword(dev, 0xB8, 0x43924392);
835 pci_write_config_dword(dev, 0xBC, 0x40094009);
836
837 proc_reports_siimage(dev, (tmpbyte>>4), name);
838 return 0;
839}
840
841/**
842 * init_mmio_iops_siimage - set up the iops for MMIO
843 * @hwif: interface to set up
844 *
845 * The basic setup here is fairly simple, we can use standard MMIO
846 * operations. However we do have to set the taskfile register offsets
847 * by hand as there isnt a standard defined layout for them this
848 * time.
849 *
850 * The hardware supports buffered taskfiles and also some rather nice
851 * extended PRD tables. Unfortunately right now we don't.
852 */
853
854static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
855{
856 struct pci_dev *dev = hwif->pci_dev;
857 void *addr = pci_get_drvdata(dev);
858 u8 ch = hwif->channel;
859 hw_regs_t hw;
860 unsigned long base;
861
862 /*
863 * Fill in the basic HWIF bits
864 */
865
866 default_hwif_mmiops(hwif);
867 hwif->hwif_data = addr;
868
869 /*
870 * Now set up the hw. We have to do this ourselves as
871 * the MMIO layout isnt the same as the the standard port
872 * based I/O
873 */
874
875 memset(&hw, 0, sizeof(hw_regs_t));
876
877 base = (unsigned long)addr;
878 if (ch)
879 base += 0xC0;
880 else
881 base += 0x80;
882
883 /*
884 * The buffered task file doesn't have status/control
885 * so we can't currently use it sanely since we want to
886 * use LBA48 mode.
887 */
888// base += 0x10;
889// hwif->no_lba48 = 1;
890
891 hw.io_ports[IDE_DATA_OFFSET] = base;
892 hw.io_ports[IDE_ERROR_OFFSET] = base + 1;
893 hw.io_ports[IDE_NSECTOR_OFFSET] = base + 2;
894 hw.io_ports[IDE_SECTOR_OFFSET] = base + 3;
895 hw.io_ports[IDE_LCYL_OFFSET] = base + 4;
896 hw.io_ports[IDE_HCYL_OFFSET] = base + 5;
897 hw.io_ports[IDE_SELECT_OFFSET] = base + 6;
898 hw.io_ports[IDE_STATUS_OFFSET] = base + 7;
899 hw.io_ports[IDE_CONTROL_OFFSET] = base + 10;
900
901 hw.io_ports[IDE_IRQ_OFFSET] = 0;
902
903 if (pdev_is_sata(dev)) {
904 base = (unsigned long)addr;
905 if (ch)
906 base += 0x80;
907 hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104;
908 hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108;
909 hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100;
910 hwif->sata_misc[SATA_MISC_OFFSET] = base + 0x140;
911 hwif->sata_misc[SATA_PHY_OFFSET] = base + 0x144;
912 hwif->sata_misc[SATA_IEN_OFFSET] = base + 0x148;
913 }
914
915 hw.irq = hwif->pci_dev->irq;
916
917 memcpy(&hwif->hw, &hw, sizeof(hw));
918 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->hw.io_ports));
919
920 hwif->irq = hw.irq;
921
922 base = (unsigned long) addr;
923
924#ifdef SIIMAGE_LARGE_DMA
925/* Watch the brackets - even Ken and Dennis get some language design wrong */
926 hwif->dma_base = base + (ch ? 0x18 : 0x10);
927 hwif->dma_base2 = base + (ch ? 0x08 : 0x00);
928 hwif->dma_prdtable = hwif->dma_base2 + 4;
929#else /* ! SIIMAGE_LARGE_DMA */
930 hwif->dma_base = base + (ch ? 0x08 : 0x00);
931 hwif->dma_base2 = base + (ch ? 0x18 : 0x10);
932#endif /* SIIMAGE_LARGE_DMA */
933 hwif->mmio = 2;
934}
935
936static int is_dev_seagate_sata(ide_drive_t *drive)
937{
938 const char *s = &drive->id->model[0];
939 unsigned len;
940
941 if (!drive->present)
942 return 0;
943
944 len = strnlen(s, sizeof(drive->id->model));
945
946 if ((len > 4) && (!memcmp(s, "ST", 2))) {
947 if ((!memcmp(s + len - 2, "AS", 2)) ||
948 (!memcmp(s + len - 3, "ASL", 3))) {
949 printk(KERN_INFO "%s: applying pessimistic Seagate "
950 "errata fix\n", drive->name);
951 return 1;
952 }
953 }
954 return 0;
955}
956
957/**
958 * siimage_fixup - post probe fixups
959 * @hwif: interface to fix up
960 *
961 * Called after drive probe we use this to decide whether the
962 * Seagate fixup must be applied. This used to be in init_iops but
963 * that can occur before we know what drives are present.
964 */
965
966static void __devinit siimage_fixup(ide_hwif_t *hwif)
967{
968 /* Try and raise the rqsize */
969 if (!is_sata(hwif) || !is_dev_seagate_sata(&hwif->drives[0]))
970 hwif->rqsize = 128;
971}
972
973/**
974 * init_iops_siimage - set up iops
975 * @hwif: interface to set up
976 *
977 * Do the basic setup for the SIIMAGE hardware interface
978 * and then do the MMIO setup if we can. This is the first
979 * look in we get for setting up the hwif so that we
980 * can get the iops right before using them.
981 */
982
983static void __devinit init_iops_siimage(ide_hwif_t *hwif)
984{
985 struct pci_dev *dev = hwif->pci_dev;
986 u32 class_rev = 0;
987
988 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
989 class_rev &= 0xff;
990
991 hwif->hwif_data = NULL;
992
993 /* Pessimal until we finish probing */
994 hwif->rqsize = 15;
995
996 if (pci_get_drvdata(dev) == NULL)
997 return;
998 init_mmio_iops_siimage(hwif);
999}
1000
1001/**
1002 * ata66_siimage - check for 80 pin cable
1003 * @hwif: interface to check
1004 *
1005 * Check for the presence of an ATA66 capable cable on the
1006 * interface.
1007 */
1008
1009static unsigned int __devinit ata66_siimage(ide_hwif_t *hwif)
1010{
1011 unsigned long addr = siimage_selreg(hwif, 0);
1012 if (pci_get_drvdata(hwif->pci_dev) == NULL) {
1013 u8 ata66 = 0;
1014 pci_read_config_byte(hwif->pci_dev, addr, &ata66);
1015 return (ata66 & 0x01) ? 1 : 0;
1016 }
1017
1018 return (hwif->INB(addr) & 0x01) ? 1 : 0;
1019}
1020
1021/**
1022 * init_hwif_siimage - set up hwif structs
1023 * @hwif: interface to set up
1024 *
1025 * We do the basic set up of the interface structure. The SIIMAGE
1026 * requires several custom handlers so we override the default
1027 * ide DMA handlers appropriately
1028 */
1029
1030static void __devinit init_hwif_siimage(ide_hwif_t *hwif)
1031{
1032 hwif->autodma = 0;
1033
1034 hwif->resetproc = &siimage_reset;
1035 hwif->speedproc = &siimage_tune_chipset;
1036 hwif->tuneproc = &siimage_tuneproc;
1037 hwif->reset_poll = &siimage_reset_poll;
1038 hwif->pre_reset = &siimage_pre_reset;
1039
1040 if(is_sata(hwif))
1041 hwif->busproc = &siimage_busproc;
1042
1043 if (!hwif->dma_base) {
1044 hwif->drives[0].autotune = 1;
1045 hwif->drives[1].autotune = 1;
1046 return;
1047 }
1048
1049 hwif->ultra_mask = 0x7f;
1050 hwif->mwdma_mask = 0x07;
1051 hwif->swdma_mask = 0x07;
1052
1053 if (!is_sata(hwif))
1054 hwif->atapi_dma = 1;
1055
1056 hwif->ide_dma_check = &siimage_config_drive_for_dma;
1057 if (!(hwif->udma_four))
1058 hwif->udma_four = ata66_siimage(hwif);
1059
1060 if (hwif->mmio) {
1061 hwif->ide_dma_test_irq = &siimage_mmio_ide_dma_test_irq;
1062 } else {
1063 hwif->ide_dma_test_irq = & siimage_io_ide_dma_test_irq;
1064 }
1065
1066 /*
1067 * The BIOS often doesn't set up DMA on this controller
1068 * so we always do it.
1069 */
1070
1071 hwif->autodma = 1;
1072 hwif->drives[0].autodma = hwif->autodma;
1073 hwif->drives[1].autodma = hwif->autodma;
1074}
1075
1076#define DECLARE_SII_DEV(name_str) \
1077 { \
1078 .name = name_str, \
1079 .init_chipset = init_chipset_siimage, \
1080 .init_iops = init_iops_siimage, \
1081 .init_hwif = init_hwif_siimage, \
1082 .fixup = siimage_fixup, \
1083 .channels = 2, \
1084 .autodma = AUTODMA, \
1085 .bootable = ON_BOARD, \
1086 }
1087
1088static ide_pci_device_t siimage_chipsets[] __devinitdata = {
1089 /* 0 */ DECLARE_SII_DEV("SiI680"),
1090 /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA"),
1091 /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA")
1092};
1093
1094/**
1095 * siimage_init_one - pci layer discovery entry
1096 * @dev: PCI device
1097 * @id: ident table entry
1098 *
1099 * Called by the PCI code when it finds an SI680 or SI3112 controller.
1100 * We then use the IDE PCI generic helper to do most of the work.
1101 */
1102
1103static int __devinit siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1104{
1105 return ide_setup_pci_device(dev, &siimage_chipsets[id->driver_data]);
1106}
1107
1108static struct pci_device_id siimage_pci_tbl[] = {
1109 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1110#ifdef CONFIG_BLK_DEV_IDE_SATA
1111 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1112 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_1210SA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1113#endif
1114 { 0, },
1115};
1116MODULE_DEVICE_TABLE(pci, siimage_pci_tbl);
1117
1118static struct pci_driver driver = {
1119 .name = "SiI_IDE",
1120 .id_table = siimage_pci_tbl,
1121 .probe = siimage_init_one,
1122};
1123
1124static int siimage_ide_init(void)
1125{
1126 return ide_pci_register_driver(&driver);
1127}
1128
1129module_init(siimage_ide_init);
1130
1131MODULE_AUTHOR("Andre Hedrick, Alan Cox");
1132MODULE_DESCRIPTION("PCI driver module for SiI IDE");
1133MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/sis5513.c b/drivers/ide/pci/sis5513.c
new file mode 100644
index 000000000000..9d70ba5ea59b
--- /dev/null
+++ b/drivers/ide/pci/sis5513.c
@@ -0,0 +1,984 @@
1/*
2 * linux/drivers/ide/pci/sis5513.c Version 0.16ac+vp Jun 18, 2003
3 *
4 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
6 * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz>
7 * May be copied or modified under the terms of the GNU General Public License
8 *
9 *
10 * Thanks :
11 *
12 * SiS Taiwan : for direct support and hardware.
13 * Daniela Engert : for initial ATA100 advices and numerous others.
14 * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt :
15 * for checking code correctness, providing patches.
16 *
17 *
18 * Original tests and design on the SiS620 chipset.
19 * ATA100 tests and design on the SiS735 chipset.
20 * ATA16/33 support from specs
21 * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
22 * ATA133 961/962/963 fixes by Vojtech Pavlik <vojtech@suse.cz>
23 *
24 * Documentation:
25 * SiS chipset documentation available under NDA to companies only
26 * (not to individuals).
27 */
28
29/*
30 * The original SiS5513 comes from a SiS5511/55112/5513 chipset. The original
31 * SiS5513 was also used in the SiS5596/5513 chipset. Thus if we see a SiS5511
32 * or SiS5596, we can assume we see the first MWDMA-16 capable SiS5513 chip.
33 *
34 * Later SiS chipsets integrated the 5513 functionality into the NorthBridge,
35 * starting with SiS5571 and up to SiS745. The PCI ID didn't change, though. We
36 * can figure out that we have a more modern and more capable 5513 by looking
37 * for the respective NorthBridge IDs.
38 *
39 * Even later (96x family) SiS chipsets use the MuTIOL link and place the 5513
40 * into the SouthBrige. Here we cannot rely on looking up the NorthBridge PCI
41 * ID, while the now ATA-133 capable 5513 still has the same PCI ID.
42 * Fortunately the 5513 can be 'unmasked' by fiddling with some config space
43 * bits, changing its device id to the true one - 5517 for 961 and 5518 for
44 * 962/963.
45 */
46
47#include <linux/config.h>
48#include <linux/types.h>
49#include <linux/module.h>
50#include <linux/kernel.h>
51#include <linux/delay.h>
52#include <linux/timer.h>
53#include <linux/mm.h>
54#include <linux/ioport.h>
55#include <linux/blkdev.h>
56#include <linux/hdreg.h>
57
58#include <linux/interrupt.h>
59#include <linux/pci.h>
60#include <linux/init.h>
61#include <linux/ide.h>
62
63#include <asm/irq.h>
64
65#include "ide-timing.h"
66
67#define DISPLAY_SIS_TIMINGS
68
69/* registers layout and init values are chipset family dependant */
70
71#define ATA_16 0x01
72#define ATA_33 0x02
73#define ATA_66 0x03
74#define ATA_100a 0x04 // SiS730/SiS550 is ATA100 with ATA66 layout
75#define ATA_100 0x05
76#define ATA_133a 0x06 // SiS961b with 133 support
77#define ATA_133 0x07 // SiS962/963
78
79static u8 chipset_family;
80
81/*
82 * Devices supported
83 */
84static const struct {
85 const char *name;
86 u16 host_id;
87 u8 chipset_family;
88 u8 flags;
89} SiSHostChipInfo[] = {
90 { "SiS745", PCI_DEVICE_ID_SI_745, ATA_100 },
91 { "SiS735", PCI_DEVICE_ID_SI_735, ATA_100 },
92 { "SiS733", PCI_DEVICE_ID_SI_733, ATA_100 },
93 { "SiS635", PCI_DEVICE_ID_SI_635, ATA_100 },
94 { "SiS633", PCI_DEVICE_ID_SI_633, ATA_100 },
95
96 { "SiS730", PCI_DEVICE_ID_SI_730, ATA_100a },
97 { "SiS550", PCI_DEVICE_ID_SI_550, ATA_100a },
98
99 { "SiS640", PCI_DEVICE_ID_SI_640, ATA_66 },
100 { "SiS630", PCI_DEVICE_ID_SI_630, ATA_66 },
101 { "SiS620", PCI_DEVICE_ID_SI_620, ATA_66 },
102 { "SiS540", PCI_DEVICE_ID_SI_540, ATA_66 },
103 { "SiS530", PCI_DEVICE_ID_SI_530, ATA_66 },
104
105 { "SiS5600", PCI_DEVICE_ID_SI_5600, ATA_33 },
106 { "SiS5598", PCI_DEVICE_ID_SI_5598, ATA_33 },
107 { "SiS5597", PCI_DEVICE_ID_SI_5597, ATA_33 },
108 { "SiS5591/2", PCI_DEVICE_ID_SI_5591, ATA_33 },
109 { "SiS5582", PCI_DEVICE_ID_SI_5582, ATA_33 },
110 { "SiS5581", PCI_DEVICE_ID_SI_5581, ATA_33 },
111
112 { "SiS5596", PCI_DEVICE_ID_SI_5596, ATA_16 },
113 { "SiS5571", PCI_DEVICE_ID_SI_5571, ATA_16 },
114 { "SiS551x", PCI_DEVICE_ID_SI_5511, ATA_16 },
115};
116
117/* Cycle time bits and values vary across chip dma capabilities
118 These three arrays hold the register layout and the values to set.
119 Indexed by chipset_family and (dma_mode - XFER_UDMA_0) */
120
121/* {0, ATA_16, ATA_33, ATA_66, ATA_100a, ATA_100, ATA_133} */
122static u8 cycle_time_offset[] = {0,0,5,4,4,0,0};
123static u8 cycle_time_range[] = {0,0,2,3,3,4,4};
124static u8 cycle_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
125 {0,0,0,0,0,0,0}, /* no udma */
126 {0,0,0,0,0,0,0}, /* no udma */
127 {3,2,1,0,0,0,0}, /* ATA_33 */
128 {7,5,3,2,1,0,0}, /* ATA_66 */
129 {7,5,3,2,1,0,0}, /* ATA_100a (730 specific), differences are on cycle_time range and offset */
130 {11,7,5,4,2,1,0}, /* ATA_100 */
131 {15,10,7,5,3,2,1}, /* ATA_133a (earliest 691 southbridges) */
132 {15,10,7,5,3,2,1}, /* ATA_133 */
133};
134/* CRC Valid Setup Time vary across IDE clock setting 33/66/100/133
135 See SiS962 data sheet for more detail */
136static u8 cvs_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
137 {0,0,0,0,0,0,0}, /* no udma */
138 {0,0,0,0,0,0,0}, /* no udma */
139 {2,1,1,0,0,0,0},
140 {4,3,2,1,0,0,0},
141 {4,3,2,1,0,0,0},
142 {6,4,3,1,1,1,0},
143 {9,6,4,2,2,2,2},
144 {9,6,4,2,2,2,2},
145};
146/* Initialize time, Active time, Recovery time vary across
147 IDE clock settings. These 3 arrays hold the register value
148 for PIO0/1/2/3/4 and DMA0/1/2 mode in order */
149static u8 ini_time_value[][8] = {
150 {0,0,0,0,0,0,0,0},
151 {0,0,0,0,0,0,0,0},
152 {2,1,0,0,0,1,0,0},
153 {4,3,1,1,1,3,1,1},
154 {4,3,1,1,1,3,1,1},
155 {6,4,2,2,2,4,2,2},
156 {9,6,3,3,3,6,3,3},
157 {9,6,3,3,3,6,3,3},
158};
159static u8 act_time_value[][8] = {
160 {0,0,0,0,0,0,0,0},
161 {0,0,0,0,0,0,0,0},
162 {9,9,9,2,2,7,2,2},
163 {19,19,19,5,4,14,5,4},
164 {19,19,19,5,4,14,5,4},
165 {28,28,28,7,6,21,7,6},
166 {38,38,38,10,9,28,10,9},
167 {38,38,38,10,9,28,10,9},
168};
169static u8 rco_time_value[][8] = {
170 {0,0,0,0,0,0,0,0},
171 {0,0,0,0,0,0,0,0},
172 {9,2,0,2,0,7,1,1},
173 {19,5,1,5,2,16,3,2},
174 {19,5,1,5,2,16,3,2},
175 {30,9,3,9,4,25,6,4},
176 {40,12,4,12,5,34,12,5},
177 {40,12,4,12,5,34,12,5},
178};
179
180/*
181 * Printing configuration
182 */
183/* Used for chipset type printing at boot time */
184static char* chipset_capability[] = {
185 "ATA", "ATA 16",
186 "ATA 33", "ATA 66",
187 "ATA 100 (1st gen)", "ATA 100 (2nd gen)",
188 "ATA 133 (1st gen)", "ATA 133 (2nd gen)"
189};
190
191#if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS)
192#include <linux/stat.h>
193#include <linux/proc_fs.h>
194
195static u8 sis_proc = 0;
196
197static struct pci_dev *bmide_dev;
198
199static char* cable_type[] = {
200 "80 pins",
201 "40 pins"
202};
203
204static char* recovery_time[] ={
205 "12 PCICLK", "1 PCICLK",
206 "2 PCICLK", "3 PCICLK",
207 "4 PCICLK", "5 PCICLCK",
208 "6 PCICLK", "7 PCICLCK",
209 "8 PCICLK", "9 PCICLCK",
210 "10 PCICLK", "11 PCICLK",
211 "13 PCICLK", "14 PCICLK",
212 "15 PCICLK", "15 PCICLK"
213};
214
215static char* active_time[] = {
216 "8 PCICLK", "1 PCICLCK",
217 "2 PCICLK", "3 PCICLK",
218 "4 PCICLK", "5 PCICLK",
219 "6 PCICLK", "12 PCICLK"
220};
221
222static char* cycle_time[] = {
223 "Reserved", "2 CLK",
224 "3 CLK", "4 CLK",
225 "5 CLK", "6 CLK",
226 "7 CLK", "8 CLK",
227 "9 CLK", "10 CLK",
228 "11 CLK", "12 CLK",
229 "13 CLK", "14 CLK",
230 "15 CLK", "16 CLK"
231};
232
233/* Generic add master or slave info function */
234static char* get_drives_info (char *buffer, u8 pos)
235{
236 u8 reg00, reg01, reg10, reg11; /* timing registers */
237 u32 regdw0, regdw1;
238 char* p = buffer;
239
240/* Postwrite/Prefetch */
241 if (chipset_family < ATA_133) {
242 pci_read_config_byte(bmide_dev, 0x4b, &reg00);
243 p += sprintf(p, "Drive %d: Postwrite %s \t \t Postwrite %s\n",
244 pos, (reg00 & (0x10 << pos)) ? "Enabled" : "Disabled",
245 (reg00 & (0x40 << pos)) ? "Enabled" : "Disabled");
246 p += sprintf(p, " Prefetch %s \t \t Prefetch %s\n",
247 (reg00 & (0x01 << pos)) ? "Enabled" : "Disabled",
248 (reg00 & (0x04 << pos)) ? "Enabled" : "Disabled");
249 pci_read_config_byte(bmide_dev, 0x40+2*pos, &reg00);
250 pci_read_config_byte(bmide_dev, 0x41+2*pos, &reg01);
251 pci_read_config_byte(bmide_dev, 0x44+2*pos, &reg10);
252 pci_read_config_byte(bmide_dev, 0x45+2*pos, &reg11);
253 } else {
254 u32 reg54h;
255 u8 drive_pci = 0x40;
256 pci_read_config_dword(bmide_dev, 0x54, &reg54h);
257 if (reg54h & 0x40000000) {
258 // Configuration space remapped to 0x70
259 drive_pci = 0x70;
260 }
261 pci_read_config_dword(bmide_dev, (unsigned long)drive_pci+4*pos, &regdw0);
262 pci_read_config_dword(bmide_dev, (unsigned long)drive_pci+4*pos+8, &regdw1);
263
264 p += sprintf(p, "Drive %d:\n", pos);
265 }
266
267
268/* UDMA */
269 if (chipset_family >= ATA_133) {
270 p += sprintf(p, " UDMA %s \t \t \t UDMA %s\n",
271 (regdw0 & 0x04) ? "Enabled" : "Disabled",
272 (regdw1 & 0x04) ? "Enabled" : "Disabled");
273 p += sprintf(p, " UDMA Cycle Time %s \t UDMA Cycle Time %s\n",
274 cycle_time[(regdw0 & 0xF0) >> 4],
275 cycle_time[(regdw1 & 0xF0) >> 4]);
276 } else if (chipset_family >= ATA_33) {
277 p += sprintf(p, " UDMA %s \t \t \t UDMA %s\n",
278 (reg01 & 0x80) ? "Enabled" : "Disabled",
279 (reg11 & 0x80) ? "Enabled" : "Disabled");
280
281 p += sprintf(p, " UDMA Cycle Time ");
282 switch(chipset_family) {
283 case ATA_33: p += sprintf(p, cycle_time[(reg01 & 0x60) >> 5]); break;
284 case ATA_66:
285 case ATA_100a: p += sprintf(p, cycle_time[(reg01 & 0x70) >> 4]); break;
286 case ATA_100:
287 case ATA_133a: p += sprintf(p, cycle_time[reg01 & 0x0F]); break;
288 default: p += sprintf(p, "?"); break;
289 }
290 p += sprintf(p, " \t UDMA Cycle Time ");
291 switch(chipset_family) {
292 case ATA_33: p += sprintf(p, cycle_time[(reg11 & 0x60) >> 5]); break;
293 case ATA_66:
294 case ATA_100a: p += sprintf(p, cycle_time[(reg11 & 0x70) >> 4]); break;
295 case ATA_100:
296 case ATA_133a: p += sprintf(p, cycle_time[reg11 & 0x0F]); break;
297 default: p += sprintf(p, "?"); break;
298 }
299 p += sprintf(p, "\n");
300 }
301
302
303 if (chipset_family < ATA_133) { /* else case TODO */
304
305/* Data Active */
306 p += sprintf(p, " Data Active Time ");
307 switch(chipset_family) {
308 case ATA_16: /* confirmed */
309 case ATA_33:
310 case ATA_66:
311 case ATA_100a: p += sprintf(p, active_time[reg01 & 0x07]); break;
312 case ATA_100:
313 case ATA_133a: p += sprintf(p, active_time[(reg00 & 0x70) >> 4]); break;
314 default: p += sprintf(p, "?"); break;
315 }
316 p += sprintf(p, " \t Data Active Time ");
317 switch(chipset_family) {
318 case ATA_16:
319 case ATA_33:
320 case ATA_66:
321 case ATA_100a: p += sprintf(p, active_time[reg11 & 0x07]); break;
322 case ATA_100:
323 case ATA_133a: p += sprintf(p, active_time[(reg10 & 0x70) >> 4]); break;
324 default: p += sprintf(p, "?"); break;
325 }
326 p += sprintf(p, "\n");
327
328/* Data Recovery */
329 /* warning: may need (reg&0x07) for pre ATA66 chips */
330 p += sprintf(p, " Data Recovery Time %s \t Data Recovery Time %s\n",
331 recovery_time[reg00 & 0x0f], recovery_time[reg10 & 0x0f]);
332 }
333
334 return p;
335}
336
337static char* get_masters_info(char* buffer)
338{
339 return get_drives_info(buffer, 0);
340}
341
342static char* get_slaves_info(char* buffer)
343{
344 return get_drives_info(buffer, 1);
345}
346
347/* Main get_info, called on /proc/ide/sis reads */
348static int sis_get_info (char *buffer, char **addr, off_t offset, int count)
349{
350 char *p = buffer;
351 int len;
352 u8 reg;
353 u16 reg2, reg3;
354
355 p += sprintf(p, "\nSiS 5513 ");
356 switch(chipset_family) {
357 case ATA_16: p += sprintf(p, "DMA 16"); break;
358 case ATA_33: p += sprintf(p, "Ultra 33"); break;
359 case ATA_66: p += sprintf(p, "Ultra 66"); break;
360 case ATA_100a:
361 case ATA_100: p += sprintf(p, "Ultra 100"); break;
362 case ATA_133a:
363 case ATA_133: p += sprintf(p, "Ultra 133"); break;
364 default: p+= sprintf(p, "Unknown???"); break;
365 }
366 p += sprintf(p, " chipset\n");
367 p += sprintf(p, "--------------- Primary Channel "
368 "---------------- Secondary Channel "
369 "-------------\n");
370
371/* Status */
372 pci_read_config_byte(bmide_dev, 0x4a, &reg);
373 if (chipset_family == ATA_133) {
374 pci_read_config_word(bmide_dev, 0x50, &reg2);
375 pci_read_config_word(bmide_dev, 0x52, &reg3);
376 }
377 p += sprintf(p, "Channel Status: ");
378 if (chipset_family < ATA_66) {
379 p += sprintf(p, "%s \t \t \t \t %s\n",
380 (reg & 0x04) ? "On" : "Off",
381 (reg & 0x02) ? "On" : "Off");
382 } else if (chipset_family < ATA_133) {
383 p += sprintf(p, "%s \t \t \t \t %s \n",
384 (reg & 0x02) ? "On" : "Off",
385 (reg & 0x04) ? "On" : "Off");
386 } else { /* ATA_133 */
387 p += sprintf(p, "%s \t \t \t \t %s \n",
388 (reg2 & 0x02) ? "On" : "Off",
389 (reg3 & 0x02) ? "On" : "Off");
390 }
391
392/* Operation Mode */
393 pci_read_config_byte(bmide_dev, 0x09, &reg);
394 p += sprintf(p, "Operation Mode: %s \t \t \t %s \n",
395 (reg & 0x01) ? "Native" : "Compatible",
396 (reg & 0x04) ? "Native" : "Compatible");
397
398/* 80-pin cable ? */
399 if (chipset_family >= ATA_133) {
400 p += sprintf(p, "Cable Type: %s \t \t \t %s\n",
401 (reg2 & 0x01) ? cable_type[1] : cable_type[0],
402 (reg3 & 0x01) ? cable_type[1] : cable_type[0]);
403 } else if (chipset_family > ATA_33) {
404 pci_read_config_byte(bmide_dev, 0x48, &reg);
405 p += sprintf(p, "Cable Type: %s \t \t \t %s\n",
406 (reg & 0x10) ? cable_type[1] : cable_type[0],
407 (reg & 0x20) ? cable_type[1] : cable_type[0]);
408 }
409
410/* Prefetch Count */
411 if (chipset_family < ATA_133) {
412 pci_read_config_word(bmide_dev, 0x4c, &reg2);
413 pci_read_config_word(bmide_dev, 0x4e, &reg3);
414 p += sprintf(p, "Prefetch Count: %d \t \t \t \t %d\n",
415 reg2, reg3);
416 }
417
418 p = get_masters_info(p);
419 p = get_slaves_info(p);
420
421 len = (p - buffer) - offset;
422 *addr = buffer + offset;
423
424 return len > count ? count : len;
425}
426#endif /* defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS) */
427
428static u8 sis5513_ratemask (ide_drive_t *drive)
429{
430 u8 rates[] = { 0, 0, 1, 2, 3, 3, 4, 4 };
431 u8 mode = rates[chipset_family];
432
433 if (!eighty_ninty_three(drive))
434 mode = min(mode, (u8)1);
435 return mode;
436}
437
438/*
439 * Configuration functions
440 */
441/* Enables per-drive prefetch and postwrite */
442static void config_drive_art_rwp (ide_drive_t *drive)
443{
444 ide_hwif_t *hwif = HWIF(drive);
445 struct pci_dev *dev = hwif->pci_dev;
446
447 u8 reg4bh = 0;
448 u8 rw_prefetch = (0x11 << drive->dn);
449
450 if (drive->media != ide_disk)
451 return;
452 pci_read_config_byte(dev, 0x4b, &reg4bh);
453
454 if ((reg4bh & rw_prefetch) != rw_prefetch)
455 pci_write_config_byte(dev, 0x4b, reg4bh|rw_prefetch);
456}
457
458
459/* Set per-drive active and recovery time */
460static void config_art_rwp_pio (ide_drive_t *drive, u8 pio)
461{
462 ide_hwif_t *hwif = HWIF(drive);
463 struct pci_dev *dev = hwif->pci_dev;
464
465 u8 timing, drive_pci, test1, test2;
466
467 u16 eide_pio_timing[6] = {600, 390, 240, 180, 120, 90};
468 u16 xfer_pio = drive->id->eide_pio_modes;
469
470 config_drive_art_rwp(drive);
471 pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
472
473 if (xfer_pio> 4)
474 xfer_pio = 0;
475
476 if (drive->id->eide_pio_iordy > 0) {
477 for (xfer_pio = 5;
478 (xfer_pio > 0) &&
479 (drive->id->eide_pio_iordy > eide_pio_timing[xfer_pio]);
480 xfer_pio--);
481 } else {
482 xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
483 (drive->id->eide_pio_modes & 2) ? 0x04 :
484 (drive->id->eide_pio_modes & 1) ? 0x03 : xfer_pio;
485 }
486
487 timing = (xfer_pio >= pio) ? xfer_pio : pio;
488
489 /* In pre ATA_133 case, drives sit at 0x40 + 4*drive->dn */
490 drive_pci = 0x40;
491 /* In SiS962 case drives sit at (0x40 or 0x70) + 8*drive->dn) */
492 if (chipset_family >= ATA_133) {
493 u32 reg54h;
494 pci_read_config_dword(dev, 0x54, &reg54h);
495 if (reg54h & 0x40000000) drive_pci = 0x70;
496 drive_pci += ((drive->dn)*0x4);
497 } else {
498 drive_pci += ((drive->dn)*0x2);
499 }
500
501 /* register layout changed with newer ATA100 chips */
502 if (chipset_family < ATA_100) {
503 pci_read_config_byte(dev, drive_pci, &test1);
504 pci_read_config_byte(dev, drive_pci+1, &test2);
505
506 /* Clear active and recovery timings */
507 test1 &= ~0x0F;
508 test2 &= ~0x07;
509
510 switch(timing) {
511 case 4: test1 |= 0x01; test2 |= 0x03; break;
512 case 3: test1 |= 0x03; test2 |= 0x03; break;
513 case 2: test1 |= 0x04; test2 |= 0x04; break;
514 case 1: test1 |= 0x07; test2 |= 0x06; break;
515 default: break;
516 }
517 pci_write_config_byte(dev, drive_pci, test1);
518 pci_write_config_byte(dev, drive_pci+1, test2);
519 } else if (chipset_family < ATA_133) {
520 switch(timing) { /* active recovery
521 v v */
522 case 4: test1 = 0x30|0x01; break;
523 case 3: test1 = 0x30|0x03; break;
524 case 2: test1 = 0x40|0x04; break;
525 case 1: test1 = 0x60|0x07; break;
526 default: break;
527 }
528 pci_write_config_byte(dev, drive_pci, test1);
529 } else { /* ATA_133 */
530 u32 test3;
531 pci_read_config_dword(dev, drive_pci, &test3);
532 test3 &= 0xc0c00fff;
533 if (test3 & 0x08) {
534 test3 |= (unsigned long)ini_time_value[ATA_133][timing] << 12;
535 test3 |= (unsigned long)act_time_value[ATA_133][timing] << 16;
536 test3 |= (unsigned long)rco_time_value[ATA_133][timing] << 24;
537 } else {
538 test3 |= (unsigned long)ini_time_value[ATA_100][timing] << 12;
539 test3 |= (unsigned long)act_time_value[ATA_100][timing] << 16;
540 test3 |= (unsigned long)rco_time_value[ATA_100][timing] << 24;
541 }
542 pci_write_config_dword(dev, drive_pci, test3);
543 }
544}
545
546static int config_chipset_for_pio (ide_drive_t *drive, u8 pio)
547{
548 if (pio == 255)
549 pio = ide_find_best_mode(drive, XFER_PIO | XFER_EPIO) - XFER_PIO_0;
550 config_art_rwp_pio(drive, pio);
551 return ide_config_drive_speed(drive, XFER_PIO_0 + min_t(u8, pio, 4));
552}
553
554static int sis5513_tune_chipset (ide_drive_t *drive, u8 xferspeed)
555{
556 ide_hwif_t *hwif = HWIF(drive);
557 struct pci_dev *dev = hwif->pci_dev;
558
559 u8 drive_pci, reg, speed;
560 u32 regdw;
561
562 speed = ide_rate_filter(sis5513_ratemask(drive), xferspeed);
563
564 /* See config_art_rwp_pio for drive pci config registers */
565 drive_pci = 0x40;
566 if (chipset_family >= ATA_133) {
567 u32 reg54h;
568 pci_read_config_dword(dev, 0x54, &reg54h);
569 if (reg54h & 0x40000000) drive_pci = 0x70;
570 drive_pci += ((drive->dn)*0x4);
571 pci_read_config_dword(dev, (unsigned long)drive_pci, &regdw);
572 /* Disable UDMA bit for non UDMA modes on UDMA chips */
573 if (speed < XFER_UDMA_0) {
574 regdw &= 0xfffffffb;
575 pci_write_config_dword(dev, (unsigned long)drive_pci, regdw);
576 }
577
578 } else {
579 drive_pci += ((drive->dn)*0x2);
580 pci_read_config_byte(dev, drive_pci+1, &reg);
581 /* Disable UDMA bit for non UDMA modes on UDMA chips */
582 if ((speed < XFER_UDMA_0) && (chipset_family > ATA_16)) {
583 reg &= 0x7F;
584 pci_write_config_byte(dev, drive_pci+1, reg);
585 }
586 }
587
588 /* Config chip for mode */
589 switch(speed) {
590 case XFER_UDMA_6:
591 case XFER_UDMA_5:
592 case XFER_UDMA_4:
593 case XFER_UDMA_3:
594 case XFER_UDMA_2:
595 case XFER_UDMA_1:
596 case XFER_UDMA_0:
597 if (chipset_family >= ATA_133) {
598 regdw |= 0x04;
599 regdw &= 0xfffff00f;
600 /* check if ATA133 enable */
601 if (regdw & 0x08) {
602 regdw |= (unsigned long)cycle_time_value[ATA_133][speed-XFER_UDMA_0] << 4;
603 regdw |= (unsigned long)cvs_time_value[ATA_133][speed-XFER_UDMA_0] << 8;
604 } else {
605 /* if ATA133 disable, we should not set speed above UDMA5 */
606 if (speed > XFER_UDMA_5)
607 speed = XFER_UDMA_5;
608 regdw |= (unsigned long)cycle_time_value[ATA_100][speed-XFER_UDMA_0] << 4;
609 regdw |= (unsigned long)cvs_time_value[ATA_100][speed-XFER_UDMA_0] << 8;
610 }
611 pci_write_config_dword(dev, (unsigned long)drive_pci, regdw);
612 } else {
613 /* Force the UDMA bit on if we want to use UDMA */
614 reg |= 0x80;
615 /* clean reg cycle time bits */
616 reg &= ~((0xFF >> (8 - cycle_time_range[chipset_family]))
617 << cycle_time_offset[chipset_family]);
618 /* set reg cycle time bits */
619 reg |= cycle_time_value[chipset_family][speed-XFER_UDMA_0]
620 << cycle_time_offset[chipset_family];
621 pci_write_config_byte(dev, drive_pci+1, reg);
622 }
623 break;
624 case XFER_MW_DMA_2:
625 case XFER_MW_DMA_1:
626 case XFER_MW_DMA_0:
627 case XFER_SW_DMA_2:
628 case XFER_SW_DMA_1:
629 case XFER_SW_DMA_0:
630 break;
631 case XFER_PIO_4: return((int) config_chipset_for_pio(drive, 4));
632 case XFER_PIO_3: return((int) config_chipset_for_pio(drive, 3));
633 case XFER_PIO_2: return((int) config_chipset_for_pio(drive, 2));
634 case XFER_PIO_1: return((int) config_chipset_for_pio(drive, 1));
635 case XFER_PIO_0:
636 default: return((int) config_chipset_for_pio(drive, 0));
637 }
638
639 return ((int) ide_config_drive_speed(drive, speed));
640}
641
642static void sis5513_tune_drive (ide_drive_t *drive, u8 pio)
643{
644 (void) config_chipset_for_pio(drive, pio);
645}
646
647/*
648 * ((id->hw_config & 0x4000|0x2000) && (HWIF(drive)->udma_four))
649 */
650static int config_chipset_for_dma (ide_drive_t *drive)
651{
652 u8 speed = ide_dma_speed(drive, sis5513_ratemask(drive));
653
654#ifdef DEBUG
655 printk("SIS5513: config_chipset_for_dma, drive %d, ultra %x\n",
656 drive->dn, drive->id->dma_ultra);
657#endif
658
659 if (!(speed))
660 return 0;
661
662 sis5513_tune_chipset(drive, speed);
663 return ide_dma_enable(drive);
664}
665
666static int sis5513_config_drive_xfer_rate (ide_drive_t *drive)
667{
668 ide_hwif_t *hwif = HWIF(drive);
669 struct hd_driveid *id = drive->id;
670
671 drive->init_speed = 0;
672
673 if (id && (id->capability & 1) && drive->autodma) {
674
675 if (ide_use_dma(drive)) {
676 if (config_chipset_for_dma(drive))
677 return hwif->ide_dma_on(drive);
678 }
679
680 goto fast_ata_pio;
681
682 } else if ((id->capability & 8) || (id->field_valid & 2)) {
683fast_ata_pio:
684 sis5513_tune_drive(drive, 5);
685 return hwif->ide_dma_off_quietly(drive);
686 }
687 /* IORDY not supported */
688 return 0;
689}
690
691/* initiates/aborts (U)DMA read/write operations on a drive. */
692static int sis5513_config_xfer_rate (ide_drive_t *drive)
693{
694 config_drive_art_rwp(drive);
695 config_art_rwp_pio(drive, 5);
696 return sis5513_config_drive_xfer_rate(drive);
697}
698
699/*
700 Future simpler config_xfer_rate :
701 When ide_find_best_mode is made bad-drive aware
702 - remove config_drive_xfer_rate and config_chipset_for_dma,
703 - replace config_xfer_rate with the following
704
705static int sis5513_config_xfer_rate (ide_drive_t *drive)
706{
707 u16 w80 = HWIF(drive)->udma_four;
708 u16 speed;
709
710 config_drive_art_rwp(drive);
711 config_art_rwp_pio(drive, 5);
712
713 speed = ide_find_best_mode(drive,
714 XFER_PIO | XFER_EPIO | XFER_SWDMA | XFER_MWDMA |
715 (chipset_family >= ATA_33 ? XFER_UDMA : 0) |
716 (w80 && chipset_family >= ATA_66 ? XFER_UDMA_66 : 0) |
717 (w80 && chipset_family >= ATA_100a ? XFER_UDMA_100 : 0) |
718 (w80 && chipset_family >= ATA_133a ? XFER_UDMA_133 : 0));
719
720 sis5513_tune_chipset(drive, speed);
721
722 if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
723 return HWIF(drive)->ide_dma_on(drive);
724 return HWIF(drive)->ide_dma_off_quietly(drive);
725}
726*/
727
728/* Chip detection and general config */
729static unsigned int __init init_chipset_sis5513 (struct pci_dev *dev, const char *name)
730{
731 struct pci_dev *host;
732 int i = 0;
733
734 chipset_family = 0;
735
736 for (i = 0; i < ARRAY_SIZE(SiSHostChipInfo) && !chipset_family; i++) {
737
738 host = pci_find_device(PCI_VENDOR_ID_SI, SiSHostChipInfo[i].host_id, NULL);
739
740 if (!host)
741 continue;
742
743 chipset_family = SiSHostChipInfo[i].chipset_family;
744
745 /* Special case for SiS630 : 630S/ET is ATA_100a */
746 if (SiSHostChipInfo[i].host_id == PCI_DEVICE_ID_SI_630) {
747 u8 hostrev;
748 pci_read_config_byte(host, PCI_REVISION_ID, &hostrev);
749 if (hostrev >= 0x30)
750 chipset_family = ATA_100a;
751 }
752
753 printk(KERN_INFO "SIS5513: %s %s controller\n",
754 SiSHostChipInfo[i].name, chipset_capability[chipset_family]);
755 }
756
757 if (!chipset_family) { /* Belongs to pci-quirks */
758
759 u32 idemisc;
760 u16 trueid;
761
762 /* Disable ID masking and register remapping */
763 pci_read_config_dword(dev, 0x54, &idemisc);
764 pci_write_config_dword(dev, 0x54, (idemisc & 0x7fffffff));
765 pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
766 pci_write_config_dword(dev, 0x54, idemisc);
767
768 if (trueid == 0x5518) {
769 printk(KERN_INFO "SIS5513: SiS 962/963 MuTIOL IDE UDMA133 controller\n");
770 chipset_family = ATA_133;
771
772 /* Check for 5513 compability mapping
773 * We must use this, else the port enabled code will fail,
774 * as it expects the enablebits at 0x4a.
775 */
776 if ((idemisc & 0x40000000) == 0) {
777 pci_write_config_dword(dev, 0x54, idemisc | 0x40000000);
778 printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n");
779 }
780 }
781 }
782
783 if (!chipset_family) { /* Belongs to pci-quirks */
784
785 struct pci_dev *lpc_bridge;
786 u16 trueid;
787 u8 prefctl;
788 u8 idecfg;
789 u8 sbrev;
790
791 pci_read_config_byte(dev, 0x4a, &idecfg);
792 pci_write_config_byte(dev, 0x4a, idecfg | 0x10);
793 pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
794 pci_write_config_byte(dev, 0x4a, idecfg);
795
796 if (trueid == 0x5517) { /* SiS 961/961B */
797
798 lpc_bridge = pci_find_slot(0x00, 0x10); /* Bus 0, Dev 2, Fn 0 */
799 pci_read_config_byte(lpc_bridge, PCI_REVISION_ID, &sbrev);
800 pci_read_config_byte(dev, 0x49, &prefctl);
801
802 if (sbrev == 0x10 && (prefctl & 0x80)) {
803 printk(KERN_INFO "SIS5513: SiS 961B MuTIOL IDE UDMA133 controller\n");
804 chipset_family = ATA_133a;
805 } else {
806 printk(KERN_INFO "SIS5513: SiS 961 MuTIOL IDE UDMA100 controller\n");
807 chipset_family = ATA_100;
808 }
809 }
810 }
811
812 if (!chipset_family)
813 return -1;
814
815 /* Make general config ops here
816 1/ tell IDE channels to operate in Compatibility mode only
817 2/ tell old chips to allow per drive IDE timings */
818
819 {
820 u8 reg;
821 u16 regw;
822
823 switch(chipset_family) {
824 case ATA_133:
825 /* SiS962 operation mode */
826 pci_read_config_word(dev, 0x50, &regw);
827 if (regw & 0x08)
828 pci_write_config_word(dev, 0x50, regw&0xfff7);
829 pci_read_config_word(dev, 0x52, &regw);
830 if (regw & 0x08)
831 pci_write_config_word(dev, 0x52, regw&0xfff7);
832 break;
833 case ATA_133a:
834 case ATA_100:
835 /* Fixup latency */
836 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80);
837 /* Set compatibility bit */
838 pci_read_config_byte(dev, 0x49, &reg);
839 if (!(reg & 0x01)) {
840 pci_write_config_byte(dev, 0x49, reg|0x01);
841 }
842 break;
843 case ATA_100a:
844 case ATA_66:
845 /* Fixup latency */
846 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10);
847
848 /* On ATA_66 chips the bit was elsewhere */
849 pci_read_config_byte(dev, 0x52, &reg);
850 if (!(reg & 0x04)) {
851 pci_write_config_byte(dev, 0x52, reg|0x04);
852 }
853 break;
854 case ATA_33:
855 /* On ATA_33 we didn't have a single bit to set */
856 pci_read_config_byte(dev, 0x09, &reg);
857 if ((reg & 0x0f) != 0x00) {
858 pci_write_config_byte(dev, 0x09, reg&0xf0);
859 }
860 case ATA_16:
861 /* force per drive recovery and active timings
862 needed on ATA_33 and below chips */
863 pci_read_config_byte(dev, 0x52, &reg);
864 if (!(reg & 0x08)) {
865 pci_write_config_byte(dev, 0x52, reg|0x08);
866 }
867 break;
868 }
869
870#if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS)
871 if (!sis_proc) {
872 sis_proc = 1;
873 bmide_dev = dev;
874 ide_pci_create_host_proc("sis", sis_get_info);
875 }
876#endif
877 }
878
879 return 0;
880}
881
882static unsigned int __init ata66_sis5513 (ide_hwif_t *hwif)
883{
884 u8 ata66 = 0;
885
886 if (chipset_family >= ATA_133) {
887 u16 regw = 0;
888 u16 reg_addr = hwif->channel ? 0x52: 0x50;
889 pci_read_config_word(hwif->pci_dev, reg_addr, &regw);
890 ata66 = (regw & 0x8000) ? 0 : 1;
891 } else if (chipset_family >= ATA_66) {
892 u8 reg48h = 0;
893 u8 mask = hwif->channel ? 0x20 : 0x10;
894 pci_read_config_byte(hwif->pci_dev, 0x48, &reg48h);
895 ata66 = (reg48h & mask) ? 0 : 1;
896 }
897 return ata66;
898}
899
900static void __init init_hwif_sis5513 (ide_hwif_t *hwif)
901{
902 hwif->autodma = 0;
903
904 if (!hwif->irq)
905 hwif->irq = hwif->channel ? 15 : 14;
906
907 hwif->tuneproc = &sis5513_tune_drive;
908 hwif->speedproc = &sis5513_tune_chipset;
909
910 if (!(hwif->dma_base)) {
911 hwif->drives[0].autotune = 1;
912 hwif->drives[1].autotune = 1;
913 return;
914 }
915
916 hwif->atapi_dma = 1;
917 hwif->ultra_mask = 0x7f;
918 hwif->mwdma_mask = 0x07;
919 hwif->swdma_mask = 0x07;
920
921 if (!chipset_family)
922 return;
923
924 if (!(hwif->udma_four))
925 hwif->udma_four = ata66_sis5513(hwif);
926
927 if (chipset_family > ATA_16) {
928 hwif->ide_dma_check = &sis5513_config_xfer_rate;
929 if (!noautodma)
930 hwif->autodma = 1;
931 }
932 hwif->drives[0].autodma = hwif->autodma;
933 hwif->drives[1].autodma = hwif->autodma;
934 return;
935}
936
937static ide_pci_device_t sis5513_chipset __devinitdata = {
938 .name = "SIS5513",
939 .init_chipset = init_chipset_sis5513,
940 .init_hwif = init_hwif_sis5513,
941 .channels = 2,
942 .autodma = NOAUTODMA,
943 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
944 .bootable = ON_BOARD,
945};
946
947static int __devinit sis5513_init_one(struct pci_dev *dev, const struct pci_device_id *id)
948{
949 return ide_setup_pci_device(dev, &sis5513_chipset);
950}
951
952static struct pci_device_id sis5513_pci_tbl[] = {
953 { PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
954 { PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5518, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
955 { 0, },
956};
957MODULE_DEVICE_TABLE(pci, sis5513_pci_tbl);
958
959static struct pci_driver driver = {
960 .name = "SIS_IDE",
961 .id_table = sis5513_pci_tbl,
962 .probe = sis5513_init_one,
963};
964
965static int sis5513_ide_init(void)
966{
967 return ide_pci_register_driver(&driver);
968}
969
970module_init(sis5513_ide_init);
971
972MODULE_AUTHOR("Lionel Bouton, L C Chang, Andre Hedrick, Vojtech Pavlik");
973MODULE_DESCRIPTION("PCI driver module for SIS IDE");
974MODULE_LICENSE("GPL");
975
976/*
977 * TODO:
978 * - CLEANUP
979 * - Use drivers/ide/ide-timing.h !
980 * - More checks in the config registers (force values instead of
981 * relying on the BIOS setting them correctly).
982 * - Further optimisations ?
983 * . for example ATA66+ regs 0x48 & 0x4A
984 */
diff --git a/drivers/ide/pci/sl82c105.c b/drivers/ide/pci/sl82c105.c
new file mode 100644
index 000000000000..1d970a0de21a
--- /dev/null
+++ b/drivers/ide/pci/sl82c105.c
@@ -0,0 +1,516 @@
1/*
2 * linux/drivers/ide/pci/sl82c105.c
3 *
4 * SL82C105/Winbond 553 IDE driver
5 *
6 * Maintainer unknown.
7 *
8 * Drive tuning added from Rebel.com's kernel sources
9 * -- Russell King (15/11/98) linux@arm.linux.org.uk
10 *
11 * Merge in Russell's HW workarounds, fix various problems
12 * with the timing registers setup.
13 * -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org
14 */
15
16#include <linux/config.h>
17#include <linux/types.h>
18#include <linux/module.h>
19#include <linux/kernel.h>
20#include <linux/timer.h>
21#include <linux/mm.h>
22#include <linux/ioport.h>
23#include <linux/interrupt.h>
24#include <linux/blkdev.h>
25#include <linux/hdreg.h>
26#include <linux/pci.h>
27#include <linux/ide.h>
28
29#include <asm/io.h>
30#include <asm/dma.h>
31
32#undef DEBUG
33
34#ifdef DEBUG
35#define DBG(arg) printk arg
36#else
37#define DBG(fmt,...)
38#endif
39/*
40 * SL82C105 PCI config register 0x40 bits.
41 */
42#define CTRL_IDE_IRQB (1 << 30)
43#define CTRL_IDE_IRQA (1 << 28)
44#define CTRL_LEGIRQ (1 << 11)
45#define CTRL_P1F16 (1 << 5)
46#define CTRL_P1EN (1 << 4)
47#define CTRL_P0F16 (1 << 1)
48#define CTRL_P0EN (1 << 0)
49
50/*
51 * Convert a PIO mode and cycle time to the required on/off
52 * times for the interface. This has protection against run-away
53 * timings.
54 */
55static unsigned int get_timing_sl82c105(ide_pio_data_t *p)
56{
57 unsigned int cmd_on;
58 unsigned int cmd_off;
59
60 cmd_on = (ide_pio_timings[p->pio_mode].active_time + 29) / 30;
61 cmd_off = (p->cycle_time - 30 * cmd_on + 29) / 30;
62
63 if (cmd_on > 32)
64 cmd_on = 32;
65 if (cmd_on == 0)
66 cmd_on = 1;
67
68 if (cmd_off > 32)
69 cmd_off = 32;
70 if (cmd_off == 0)
71 cmd_off = 1;
72
73 return (cmd_on - 1) << 8 | (cmd_off - 1) | (p->use_iordy ? 0x40 : 0x00);
74}
75
76/*
77 * Configure the drive and chipset for PIO
78 */
79static void config_for_pio(ide_drive_t *drive, int pio, int report, int chipset_only)
80{
81 ide_hwif_t *hwif = HWIF(drive);
82 struct pci_dev *dev = hwif->pci_dev;
83 ide_pio_data_t p;
84 u16 drv_ctrl = 0x909;
85 unsigned int xfer_mode, reg;
86
87 DBG(("config_for_pio(drive:%s, pio:%d, report:%d, chipset_only:%d)\n",
88 drive->name, pio, report, chipset_only));
89
90 reg = (hwif->channel ? 0x4c : 0x44) + (drive->select.b.unit ? 4 : 0);
91
92 pio = ide_get_best_pio_mode(drive, pio, 5, &p);
93
94 xfer_mode = XFER_PIO_0 + pio;
95
96 if (chipset_only || ide_config_drive_speed(drive, xfer_mode) == 0) {
97 drv_ctrl = get_timing_sl82c105(&p);
98 drive->pio_speed = xfer_mode;
99 } else
100 drive->pio_speed = XFER_PIO_0;
101
102 if (drive->using_dma == 0) {
103 /*
104 * If we are actually using MW DMA, then we can not
105 * reprogram the interface drive control register.
106 */
107 pci_write_config_word(dev, reg, drv_ctrl);
108 pci_read_config_word(dev, reg, &drv_ctrl);
109
110 if (report) {
111 printk("%s: selected %s (%dns) (%04X)\n", drive->name,
112 ide_xfer_verbose(xfer_mode), p.cycle_time, drv_ctrl);
113 }
114 }
115}
116
117/*
118 * Configure the drive and the chipset for DMA
119 */
120static int config_for_dma (ide_drive_t *drive)
121{
122 ide_hwif_t *hwif = HWIF(drive);
123 struct pci_dev *dev = hwif->pci_dev;
124 unsigned int reg;
125
126 DBG(("config_for_dma(drive:%s)\n", drive->name));
127
128 reg = (hwif->channel ? 0x4c : 0x44) + (drive->select.b.unit ? 4 : 0);
129
130 if (ide_config_drive_speed(drive, XFER_MW_DMA_2) != 0)
131 return 1;
132
133 pci_write_config_word(dev, reg, 0x0240);
134
135 return 0;
136}
137
138/*
139 * Check to see if the drive and
140 * chipset is capable of DMA mode
141 */
142
143static int sl82c105_check_drive (ide_drive_t *drive)
144{
145 ide_hwif_t *hwif = HWIF(drive);
146
147 DBG(("sl82c105_check_drive(drive:%s)\n", drive->name));
148
149 do {
150 struct hd_driveid *id = drive->id;
151
152 if (!drive->autodma)
153 break;
154
155 if (!id || !(id->capability & 1))
156 break;
157
158 /* Consult the list of known "bad" drives */
159 if (__ide_dma_bad_drive(drive))
160 break;
161
162 if (id->field_valid & 2) {
163 if ((id->dma_mword & hwif->mwdma_mask) ||
164 (id->dma_1word & hwif->swdma_mask))
165 return hwif->ide_dma_on(drive);
166 }
167
168 if (__ide_dma_good_drive(drive))
169 return hwif->ide_dma_on(drive);
170 } while (0);
171
172 return hwif->ide_dma_off_quietly(drive);
173}
174
175/*
176 * The SL82C105 holds off all IDE interrupts while in DMA mode until
177 * all DMA activity is completed. Sometimes this causes problems (eg,
178 * when the drive wants to report an error condition).
179 *
180 * 0x7e is a "chip testing" register. Bit 2 resets the DMA controller
181 * state machine. We need to kick this to work around various bugs.
182 */
183static inline void sl82c105_reset_host(struct pci_dev *dev)
184{
185 u16 val;
186
187 pci_read_config_word(dev, 0x7e, &val);
188 pci_write_config_word(dev, 0x7e, val | (1 << 2));
189 pci_write_config_word(dev, 0x7e, val & ~(1 << 2));
190}
191
192/*
193 * If we get an IRQ timeout, it might be that the DMA state machine
194 * got confused. Fix from Todd Inglett. Details from Winbond.
195 *
196 * This function is called when the IDE timer expires, the drive
197 * indicates that it is READY, and we were waiting for DMA to complete.
198 */
199static int sl82c105_ide_dma_lost_irq(ide_drive_t *drive)
200{
201 ide_hwif_t *hwif = HWIF(drive);
202 struct pci_dev *dev = hwif->pci_dev;
203 u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
204 unsigned long dma_base = hwif->dma_base;
205
206 printk("sl82c105: lost IRQ: resetting host\n");
207
208 /*
209 * Check the raw interrupt from the drive.
210 */
211 pci_read_config_dword(dev, 0x40, &val);
212 if (val & mask)
213 printk("sl82c105: drive was requesting IRQ, but host lost it\n");
214
215 /*
216 * Was DMA enabled? If so, disable it - we're resetting the
217 * host. The IDE layer will be handling the drive for us.
218 */
219 val = hwif->INB(dma_base);
220 if (val & 1) {
221 outb(val & ~1, dma_base);
222 printk("sl82c105: DMA was enabled\n");
223 }
224
225 sl82c105_reset_host(dev);
226
227 /* ide_dmaproc would return 1, so we do as well */
228 return 1;
229}
230
231/*
232 * ATAPI devices can cause the SL82C105 DMA state machine to go gaga.
233 * Winbond recommend that the DMA state machine is reset prior to
234 * setting the bus master DMA enable bit.
235 *
236 * The generic IDE core will have disabled the BMEN bit before this
237 * function is called.
238 */
239static void sl82c105_ide_dma_start(ide_drive_t *drive)
240{
241 ide_hwif_t *hwif = HWIF(drive);
242 struct pci_dev *dev = hwif->pci_dev;
243
244 sl82c105_reset_host(dev);
245 ide_dma_start(drive);
246}
247
248static int sl82c105_ide_dma_timeout(ide_drive_t *drive)
249{
250 ide_hwif_t *hwif = HWIF(drive);
251 struct pci_dev *dev = hwif->pci_dev;
252
253 DBG(("sl82c105_ide_dma_timeout(drive:%s)\n", drive->name));
254
255 sl82c105_reset_host(dev);
256 return __ide_dma_timeout(drive);
257}
258
259static int sl82c105_ide_dma_on (ide_drive_t *drive)
260{
261 DBG(("sl82c105_ide_dma_on(drive:%s)\n", drive->name));
262
263 if (config_for_dma(drive)) {
264 config_for_pio(drive, 4, 0, 0);
265 return HWIF(drive)->ide_dma_off_quietly(drive);
266 }
267 printk(KERN_INFO "%s: DMA enabled\n", drive->name);
268 return __ide_dma_on(drive);
269}
270
271static int sl82c105_ide_dma_off_quietly (ide_drive_t *drive)
272{
273 u8 speed = XFER_PIO_0;
274 int rc;
275
276 DBG(("sl82c105_ide_dma_off_quietly(drive:%s)\n", drive->name));
277
278 rc = __ide_dma_off_quietly(drive);
279 if (drive->pio_speed)
280 speed = drive->pio_speed - XFER_PIO_0;
281 config_for_pio(drive, speed, 0, 1);
282 drive->current_speed = drive->pio_speed;
283
284 return rc;
285}
286
287/*
288 * Ok, that is nasty, but we must make sure the DMA timings
289 * won't be used for a PIO access. The solution here is
290 * to make sure the 16 bits mode is diabled on the channel
291 * when DMA is enabled, thus causing the chip to use PIO0
292 * timings for those operations.
293 */
294static void sl82c105_selectproc(ide_drive_t *drive)
295{
296 ide_hwif_t *hwif = HWIF(drive);
297 struct pci_dev *dev = hwif->pci_dev;
298 u32 val, old, mask;
299
300 //DBG(("sl82c105_selectproc(drive:%s)\n", drive->name));
301
302 mask = hwif->channel ? CTRL_P1F16 : CTRL_P0F16;
303 old = val = *((u32 *)&hwif->hwif_data);
304 if (drive->using_dma)
305 val &= ~mask;
306 else
307 val |= mask;
308 if (old != val) {
309 pci_write_config_dword(dev, 0x40, val);
310 *((u32 *)&hwif->hwif_data) = val;
311 }
312}
313
314/*
315 * ATA reset will clear the 16 bits mode in the control
316 * register, we need to update our cache
317 */
318static void sl82c105_resetproc(ide_drive_t *drive)
319{
320 ide_hwif_t *hwif = HWIF(drive);
321 struct pci_dev *dev = hwif->pci_dev;
322 u32 val;
323
324 DBG(("sl82c105_resetproc(drive:%s)\n", drive->name));
325
326 pci_read_config_dword(dev, 0x40, &val);
327 *((u32 *)&hwif->hwif_data) = val;
328}
329
330/*
331 * We only deal with PIO mode here - DMA mode 'using_dma' is not
332 * initialised at the point that this function is called.
333 */
334static void tune_sl82c105(ide_drive_t *drive, u8 pio)
335{
336 DBG(("tune_sl82c105(drive:%s)\n", drive->name));
337
338 config_for_pio(drive, pio, 1, 0);
339
340 /*
341 * We support 32-bit I/O on this interface, and it
342 * doesn't have problems with interrupts.
343 */
344 drive->io_32bit = 1;
345 drive->unmask = 1;
346}
347
348/*
349 * Return the revision of the Winbond bridge
350 * which this function is part of.
351 */
352static unsigned int sl82c105_bridge_revision(struct pci_dev *dev)
353{
354 struct pci_dev *bridge;
355 u8 rev;
356
357 /*
358 * The bridge should be part of the same device, but function 0.
359 */
360 bridge = pci_find_slot(dev->bus->number,
361 PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
362 if (!bridge)
363 return -1;
364
365 /*
366 * Make sure it is a Winbond 553 and is an ISA bridge.
367 */
368 if (bridge->vendor != PCI_VENDOR_ID_WINBOND ||
369 bridge->device != PCI_DEVICE_ID_WINBOND_83C553 ||
370 bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA)
371 return -1;
372
373 /*
374 * We need to find function 0's revision, not function 1
375 */
376 pci_read_config_byte(bridge, PCI_REVISION_ID, &rev);
377
378 return rev;
379}
380
381/*
382 * Enable the PCI device
383 *
384 * --BenH: It's arch fixup code that should enable channels that
385 * have not been enabled by firmware. I decided we can still enable
386 * channel 0 here at least, but channel 1 has to be enabled by
387 * firmware or arch code. We still set both to 16 bits mode.
388 */
389static unsigned int __init init_chipset_sl82c105(struct pci_dev *dev, const char *msg)
390{
391 u32 val;
392
393 DBG(("init_chipset_sl82c105()\n"));
394
395 pci_read_config_dword(dev, 0x40, &val);
396 val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
397 pci_write_config_dword(dev, 0x40, val);
398
399 return dev->irq;
400}
401
402static void __init init_dma_sl82c105(ide_hwif_t *hwif, unsigned long dma_base)
403{
404 unsigned int rev;
405 u8 dma_state;
406
407 DBG(("init_dma_sl82c105(hwif: ide%d, dma_base: 0x%08x)\n", hwif->index, dma_base));
408
409 hwif->autodma = 0;
410
411 if (!dma_base)
412 return;
413
414 dma_state = hwif->INB(dma_base + 2);
415 rev = sl82c105_bridge_revision(hwif->pci_dev);
416 if (rev <= 5) {
417 printk(" %s: Winbond 553 bridge revision %d, BM-DMA disabled\n",
418 hwif->name, rev);
419 dma_state &= ~0x60;
420 } else {
421 dma_state |= 0x60;
422 if (!noautodma)
423 hwif->autodma = 1;
424 }
425 hwif->OUTB(dma_state, dma_base + 2);
426
427 ide_setup_dma(hwif, dma_base, 8);
428}
429
430/*
431 * Initialise the chip
432 */
433
434static void __init init_hwif_sl82c105(ide_hwif_t *hwif)
435{
436 struct pci_dev *dev = hwif->pci_dev;
437 u32 val;
438
439 DBG(("init_hwif_sl82c105(hwif: ide%d)\n", hwif->index));
440
441 hwif->tuneproc = tune_sl82c105;
442 hwif->selectproc = sl82c105_selectproc;
443 hwif->resetproc = sl82c105_resetproc;
444
445 /* Default to PIO 0 for fallback unless tuned otherwise,
446 * we always autotune PIO, this is done before DMA is
447 * checked, so there is no risk of accidentally disabling
448 * DMA
449 */
450 hwif->drives[0].pio_speed = XFER_PIO_0;
451 hwif->drives[0].autotune = 1;
452 hwif->drives[1].pio_speed = XFER_PIO_1;
453 hwif->drives[1].autotune = 1;
454
455 pci_read_config_dword(dev, 0x40, &val);
456 *((u32 *)&hwif->hwif_data) = val;
457
458 if (!hwif->dma_base)
459 return;
460
461 hwif->atapi_dma = 1;
462 hwif->mwdma_mask = 0x07;
463 hwif->swdma_mask = 0x07;
464
465#ifdef CONFIG_BLK_DEV_IDEDMA
466 hwif->ide_dma_check = &sl82c105_check_drive;
467 hwif->ide_dma_on = &sl82c105_ide_dma_on;
468 hwif->ide_dma_off_quietly = &sl82c105_ide_dma_off_quietly;
469 hwif->ide_dma_lostirq = &sl82c105_ide_dma_lost_irq;
470 hwif->dma_start = &sl82c105_ide_dma_start;
471 hwif->ide_dma_timeout = &sl82c105_ide_dma_timeout;
472
473 if (!noautodma)
474 hwif->autodma = 1;
475 hwif->drives[0].autodma = hwif->autodma;
476 hwif->drives[1].autodma = hwif->autodma;
477#endif /* CONFIG_BLK_DEV_IDEDMA */
478}
479
480static ide_pci_device_t sl82c105_chipset __devinitdata = {
481 .name = "W82C105",
482 .init_chipset = init_chipset_sl82c105,
483 .init_hwif = init_hwif_sl82c105,
484 .init_dma = init_dma_sl82c105,
485 .channels = 2,
486 .autodma = NOAUTODMA,
487 .enablebits = {{0x40,0x01,0x01}, {0x40,0x10,0x10}},
488 .bootable = ON_BOARD,
489};
490
491static int __devinit sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
492{
493 return ide_setup_pci_device(dev, &sl82c105_chipset);
494}
495
496static struct pci_device_id sl82c105_pci_tbl[] = {
497 { PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
498 { 0, },
499};
500MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl);
501
502static struct pci_driver driver = {
503 .name = "W82C105_IDE",
504 .id_table = sl82c105_pci_tbl,
505 .probe = sl82c105_init_one,
506};
507
508static int sl82c105_ide_init(void)
509{
510 return ide_pci_register_driver(&driver);
511}
512
513module_init(sl82c105_ide_init);
514
515MODULE_DESCRIPTION("PCI driver module for W82C105 IDE");
516MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/slc90e66.c b/drivers/ide/pci/slc90e66.c
new file mode 100644
index 000000000000..7fbf36342f73
--- /dev/null
+++ b/drivers/ide/pci/slc90e66.c
@@ -0,0 +1,273 @@
1/*
2 * linux/drivers/ide/pci/slc90e66.c Version 0.11 September 11, 2002
3 *
4 * Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
5 *
6 * This a look-a-like variation of the ICH0 PIIX4 Ultra-66,
7 * but this keeps the ISA-Bridge and slots alive.
8 *
9 */
10
11#include <linux/config.h>
12#include <linux/types.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/ioport.h>
16#include <linux/pci.h>
17#include <linux/hdreg.h>
18#include <linux/ide.h>
19#include <linux/delay.h>
20#include <linux/init.h>
21
22#include <asm/io.h>
23
24static u8 slc90e66_ratemask (ide_drive_t *drive)
25{
26 u8 mode = 2;
27
28 if (!eighty_ninty_three(drive))
29 mode = min(mode, (u8)1);
30 return mode;
31}
32
33static u8 slc90e66_dma_2_pio (u8 xfer_rate) {
34 switch(xfer_rate) {
35 case XFER_UDMA_4:
36 case XFER_UDMA_3:
37 case XFER_UDMA_2:
38 case XFER_UDMA_1:
39 case XFER_UDMA_0:
40 case XFER_MW_DMA_2:
41 case XFER_PIO_4:
42 return 4;
43 case XFER_MW_DMA_1:
44 case XFER_PIO_3:
45 return 3;
46 case XFER_SW_DMA_2:
47 case XFER_PIO_2:
48 return 2;
49 case XFER_MW_DMA_0:
50 case XFER_SW_DMA_1:
51 case XFER_SW_DMA_0:
52 case XFER_PIO_1:
53 case XFER_PIO_0:
54 case XFER_PIO_SLOW:
55 default:
56 return 0;
57 }
58}
59
60/*
61 * Based on settings done by AMI BIOS
62 * (might be useful if drive is not registered in CMOS for any reason).
63 */
64static void slc90e66_tune_drive (ide_drive_t *drive, u8 pio)
65{
66 ide_hwif_t *hwif = HWIF(drive);
67 struct pci_dev *dev = hwif->pci_dev;
68 int is_slave = (&hwif->drives[1] == drive);
69 int master_port = hwif->channel ? 0x42 : 0x40;
70 int slave_port = 0x44;
71 unsigned long flags;
72 u16 master_data;
73 u8 slave_data;
74 /* ISP RTC */
75 u8 timings[][2] = { { 0, 0 },
76 { 0, 0 },
77 { 1, 0 },
78 { 2, 1 },
79 { 2, 3 }, };
80
81 pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
82 spin_lock_irqsave(&ide_lock, flags);
83 pci_read_config_word(dev, master_port, &master_data);
84 if (is_slave) {
85 master_data = master_data | 0x4000;
86 if (pio > 1)
87 /* enable PPE, IE and TIME */
88 master_data = master_data | 0x0070;
89 pci_read_config_byte(dev, slave_port, &slave_data);
90 slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0);
91 slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0));
92 } else {
93 master_data = master_data & 0xccf8;
94 if (pio > 1)
95 /* enable PPE, IE and TIME */
96 master_data = master_data | 0x0007;
97 master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
98 }
99 pci_write_config_word(dev, master_port, master_data);
100 if (is_slave)
101 pci_write_config_byte(dev, slave_port, slave_data);
102 spin_unlock_irqrestore(&ide_lock, flags);
103}
104
105static int slc90e66_tune_chipset (ide_drive_t *drive, u8 xferspeed)
106{
107 ide_hwif_t *hwif = HWIF(drive);
108 struct pci_dev *dev = hwif->pci_dev;
109 u8 maslave = hwif->channel ? 0x42 : 0x40;
110 u8 speed = ide_rate_filter(slc90e66_ratemask(drive), xferspeed);
111 int sitre = 0, a_speed = 7 << (drive->dn * 4);
112 int u_speed = 0, u_flag = 1 << drive->dn;
113 u16 reg4042, reg44, reg48, reg4a;
114
115 pci_read_config_word(dev, maslave, &reg4042);
116 sitre = (reg4042 & 0x4000) ? 1 : 0;
117 pci_read_config_word(dev, 0x44, &reg44);
118 pci_read_config_word(dev, 0x48, &reg48);
119 pci_read_config_word(dev, 0x4a, &reg4a);
120
121 switch(speed) {
122#ifdef CONFIG_BLK_DEV_IDEDMA
123 case XFER_UDMA_4: u_speed = 4 << (drive->dn * 4); break;
124 case XFER_UDMA_3: u_speed = 3 << (drive->dn * 4); break;
125 case XFER_UDMA_2: u_speed = 2 << (drive->dn * 4); break;
126 case XFER_UDMA_1: u_speed = 1 << (drive->dn * 4); break;
127 case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;
128 case XFER_MW_DMA_2:
129 case XFER_MW_DMA_1:
130 case XFER_SW_DMA_2: break;
131#endif /* CONFIG_BLK_DEV_IDEDMA */
132 case XFER_PIO_4:
133 case XFER_PIO_3:
134 case XFER_PIO_2:
135 case XFER_PIO_0: break;
136 default: return -1;
137 }
138
139 if (speed >= XFER_UDMA_0) {
140 if (!(reg48 & u_flag))
141 pci_write_config_word(dev, 0x48, reg48|u_flag);
142 /* FIXME: (reg4a & a_speed) ? */
143 if ((reg4a & u_speed) != u_speed) {
144 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
145 pci_read_config_word(dev, 0x4a, &reg4a);
146 pci_write_config_word(dev, 0x4a, reg4a|u_speed);
147 }
148 } else {
149 if (reg48 & u_flag)
150 pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
151 if (reg4a & a_speed)
152 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
153 }
154
155 slc90e66_tune_drive(drive, slc90e66_dma_2_pio(speed));
156 return (ide_config_drive_speed(drive, speed));
157}
158
159#ifdef CONFIG_BLK_DEV_IDEDMA
160static int slc90e66_config_drive_for_dma (ide_drive_t *drive)
161{
162 u8 speed = ide_dma_speed(drive, slc90e66_ratemask(drive));
163
164 if (!(speed)) {
165 u8 tspeed = ide_get_best_pio_mode(drive, 255, 5, NULL);
166 speed = slc90e66_dma_2_pio(XFER_PIO_0 + tspeed);
167 }
168
169 (void) slc90e66_tune_chipset(drive, speed);
170 return ide_dma_enable(drive);
171}
172
173static int slc90e66_config_drive_xfer_rate (ide_drive_t *drive)
174{
175 ide_hwif_t *hwif = HWIF(drive);
176 struct hd_driveid *id = drive->id;
177
178 drive->init_speed = 0;
179
180 if (id && (id->capability & 1) && drive->autodma) {
181
182 if (ide_use_dma(drive)) {
183 if (slc90e66_config_drive_for_dma(drive))
184 return hwif->ide_dma_on(drive);
185 }
186
187 goto fast_ata_pio;
188
189 } else if ((id->capability & 8) || (id->field_valid & 2)) {
190fast_ata_pio:
191 hwif->tuneproc(drive, 5);
192 return hwif->ide_dma_off_quietly(drive);
193 }
194 /* IORDY not supported */
195 return 0;
196}
197#endif /* CONFIG_BLK_DEV_IDEDMA */
198
199static void __init init_hwif_slc90e66 (ide_hwif_t *hwif)
200{
201 u8 reg47 = 0;
202 u8 mask = hwif->channel ? 0x01 : 0x02; /* bit0:Primary */
203
204 hwif->autodma = 0;
205
206 if (!hwif->irq)
207 hwif->irq = hwif->channel ? 15 : 14;
208
209 hwif->speedproc = &slc90e66_tune_chipset;
210 hwif->tuneproc = &slc90e66_tune_drive;
211
212 pci_read_config_byte(hwif->pci_dev, 0x47, &reg47);
213
214 if (!hwif->dma_base) {
215 hwif->drives[0].autotune = 1;
216 hwif->drives[1].autotune = 1;
217 return;
218 }
219
220 hwif->atapi_dma = 1;
221 hwif->ultra_mask = 0x1f;
222 hwif->mwdma_mask = 0x07;
223 hwif->swdma_mask = 0x07;
224
225#ifdef CONFIG_BLK_DEV_IDEDMA
226 if (!(hwif->udma_four))
227 /* bit[0(1)]: 0:80, 1:40 */
228 hwif->udma_four = (reg47 & mask) ? 0 : 1;
229
230 hwif->ide_dma_check = &slc90e66_config_drive_xfer_rate;
231 if (!noautodma)
232 hwif->autodma = 1;
233 hwif->drives[0].autodma = hwif->autodma;
234 hwif->drives[1].autodma = hwif->autodma;
235#endif /* !CONFIG_BLK_DEV_IDEDMA */
236}
237
238static ide_pci_device_t slc90e66_chipset __devinitdata = {
239 .name = "SLC90E66",
240 .init_hwif = init_hwif_slc90e66,
241 .channels = 2,
242 .autodma = AUTODMA,
243 .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
244 .bootable = ON_BOARD,
245};
246
247static int __devinit slc90e66_init_one(struct pci_dev *dev, const struct pci_device_id *id)
248{
249 return ide_setup_pci_device(dev, &slc90e66_chipset);
250}
251
252static struct pci_device_id slc90e66_pci_tbl[] = {
253 { PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
254 { 0, },
255};
256MODULE_DEVICE_TABLE(pci, slc90e66_pci_tbl);
257
258static struct pci_driver driver = {
259 .name = "SLC90e66_IDE",
260 .id_table = slc90e66_pci_tbl,
261 .probe = slc90e66_init_one,
262};
263
264static int slc90e66_ide_init(void)
265{
266 return ide_pci_register_driver(&driver);
267}
268
269module_init(slc90e66_ide_init);
270
271MODULE_AUTHOR("Andre Hedrick");
272MODULE_DESCRIPTION("PCI driver module for SLC90E66 IDE");
273MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/triflex.c b/drivers/ide/pci/triflex.c
new file mode 100644
index 000000000000..a1df2bfe3631
--- /dev/null
+++ b/drivers/ide/pci/triflex.c
@@ -0,0 +1,188 @@
1/*
2 * triflex.c
3 *
4 * IDE Chipset driver for the Compaq TriFlex IDE controller.
5 *
6 * Known to work with the Compaq Workstation 5x00 series.
7 *
8 * Copyright (C) 2002 Hewlett-Packard Development Group, L.P.
9 * Author: Torben Mathiasen <torben.mathiasen@hp.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 * Loosely based on the piix & svwks drivers.
25 *
26 * Documentation:
27 * Not publically available.
28 */
29
30#include <linux/config.h>
31#include <linux/types.h>
32#include <linux/module.h>
33#include <linux/kernel.h>
34#include <linux/delay.h>
35#include <linux/timer.h>
36#include <linux/mm.h>
37#include <linux/ioport.h>
38#include <linux/blkdev.h>
39#include <linux/hdreg.h>
40#include <linux/pci.h>
41#include <linux/ide.h>
42#include <linux/init.h>
43
44static int triflex_tune_chipset(ide_drive_t *drive, u8 xferspeed)
45{
46 ide_hwif_t *hwif = HWIF(drive);
47 struct pci_dev *dev = hwif->pci_dev;
48 u8 channel_offset = hwif->channel ? 0x74 : 0x70;
49 u16 timing = 0;
50 u32 triflex_timings = 0;
51 u8 unit = (drive->select.b.unit & 0x01);
52 u8 speed = ide_rate_filter(0, xferspeed);
53
54 pci_read_config_dword(dev, channel_offset, &triflex_timings);
55
56 switch(speed) {
57 case XFER_MW_DMA_2:
58 timing = 0x0103;
59 break;
60 case XFER_MW_DMA_1:
61 timing = 0x0203;
62 break;
63 case XFER_MW_DMA_0:
64 timing = 0x0808;
65 break;
66 case XFER_SW_DMA_2:
67 case XFER_SW_DMA_1:
68 case XFER_SW_DMA_0:
69 timing = 0x0f0f;
70 break;
71 case XFER_PIO_4:
72 timing = 0x0202;
73 break;
74 case XFER_PIO_3:
75 timing = 0x0204;
76 break;
77 case XFER_PIO_2:
78 timing = 0x0404;
79 break;
80 case XFER_PIO_1:
81 timing = 0x0508;
82 break;
83 case XFER_PIO_0:
84 timing = 0x0808;
85 break;
86 default:
87 return -1;
88 }
89
90 triflex_timings &= ~(0xFFFF << (16 * unit));
91 triflex_timings |= (timing << (16 * unit));
92
93 pci_write_config_dword(dev, channel_offset, triflex_timings);
94
95 return (ide_config_drive_speed(drive, speed));
96}
97
98static void triflex_tune_drive(ide_drive_t *drive, u8 pio)
99{
100 int use_pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
101 (void) triflex_tune_chipset(drive, (XFER_PIO_0 + use_pio));
102}
103
104static int triflex_config_drive_for_dma(ide_drive_t *drive)
105{
106 int speed = ide_dma_speed(drive, 0); /* No ultra speeds */
107
108 if (!speed) {
109 u8 pspeed = ide_get_best_pio_mode(drive, 255, 4, NULL);
110 speed = XFER_PIO_0 + pspeed;
111 }
112
113 (void) triflex_tune_chipset(drive, speed);
114 return ide_dma_enable(drive);
115}
116
117static int triflex_config_drive_xfer_rate(ide_drive_t *drive)
118{
119 ide_hwif_t *hwif = HWIF(drive);
120 struct hd_driveid *id = drive->id;
121
122 if ((id->capability & 1) && drive->autodma) {
123 if (ide_use_dma(drive)) {
124 if (triflex_config_drive_for_dma(drive))
125 return hwif->ide_dma_on(drive);
126 }
127 }
128
129 hwif->tuneproc(drive, 255);
130 return hwif->ide_dma_off_quietly(drive);
131}
132
133static void __init init_hwif_triflex(ide_hwif_t *hwif)
134{
135 hwif->tuneproc = &triflex_tune_drive;
136 hwif->speedproc = &triflex_tune_chipset;
137
138 hwif->atapi_dma = 1;
139 hwif->mwdma_mask = 0x07;
140 hwif->swdma_mask = 0x07;
141 hwif->ide_dma_check = &triflex_config_drive_xfer_rate;
142
143 if (!noautodma)
144 hwif->autodma = 1;
145 hwif->drives[0].autodma = hwif->autodma;
146 hwif->drives[1].autodma = hwif->autodma;
147}
148
149static ide_pci_device_t triflex_device __devinitdata = {
150 .name = "TRIFLEX",
151 .init_hwif = init_hwif_triflex,
152 .channels = 2,
153 .autodma = AUTODMA,
154 .enablebits = {{0x80, 0x01, 0x01}, {0x80, 0x02, 0x02}},
155 .bootable = ON_BOARD,
156};
157
158static int __devinit triflex_init_one(struct pci_dev *dev,
159 const struct pci_device_id *id)
160{
161 return ide_setup_pci_device(dev, &triflex_device);
162}
163
164static struct pci_device_id triflex_pci_tbl[] = {
165 { PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_TRIFLEX_IDE,
166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
167 { 0, },
168};
169MODULE_DEVICE_TABLE(pci, triflex_pci_tbl);
170
171static struct pci_driver driver = {
172 .name = "TRIFLEX_IDE",
173 .id_table = triflex_pci_tbl,
174 .probe = triflex_init_one,
175};
176
177static int triflex_ide_init(void)
178{
179 return ide_pci_register_driver(&driver);
180}
181
182module_init(triflex_ide_init);
183
184MODULE_AUTHOR("Torben Mathiasen");
185MODULE_DESCRIPTION("PCI driver module for Compaq Triflex IDE");
186MODULE_LICENSE("GPL");
187
188
diff --git a/drivers/ide/pci/trm290.c b/drivers/ide/pci/trm290.c
new file mode 100644
index 000000000000..8b5eea5405ef
--- /dev/null
+++ b/drivers/ide/pci/trm290.c
@@ -0,0 +1,369 @@
1/*
2 * linux/drivers/ide/pci/trm290.c Version 1.02 Mar. 18, 2000
3 *
4 * Copyright (c) 1997-1998 Mark Lord
5 * May be copied or modified under the terms of the GNU General Public License
6 *
7 * June 22, 2004 - get rid of check_region
8 * Jesper Juhl <juhl-lkml@dif.dk>
9 *
10 */
11
12/*
13 * This module provides support for the bus-master IDE DMA function
14 * of the Tekram TRM290 chip, used on a variety of PCI IDE add-on boards,
15 * including a "Precision Instruments" board. The TRM290 pre-dates
16 * the sff-8038 standard (ide-dma.c) by a few months, and differs
17 * significantly enough to warrant separate routines for some functions,
18 * while re-using others from ide-dma.c.
19 *
20 * EXPERIMENTAL! It works for me (a sample of one).
21 *
22 * Works reliably for me in DMA mode (READs only),
23 * DMA WRITEs are disabled by default (see #define below);
24 *
25 * DMA is not enabled automatically for this chipset,
26 * but can be turned on manually (with "hdparm -d1") at run time.
27 *
28 * I need volunteers with "spare" drives for further testing
29 * and development, and maybe to help figure out the peculiarities.
30 * Even knowing the registers (below), some things behave strangely.
31 */
32
33#define TRM290_NO_DMA_WRITES /* DMA writes seem unreliable sometimes */
34
35/*
36 * TRM-290 PCI-IDE2 Bus Master Chip
37 * ================================
38 * The configuration registers are addressed in normal I/O port space
39 * and are used as follows:
40 *
41 * trm290_base depends on jumper settings, and is probed for by ide-dma.c
42 *
43 * trm290_base+2 when WRITTEN: chiptest register (byte, write-only)
44 * bit7 must always be written as "1"
45 * bits6-2 undefined
46 * bit1 1=legacy_compatible_mode, 0=native_pci_mode
47 * bit0 1=test_mode, 0=normal(default)
48 *
49 * trm290_base+2 when READ: status register (byte, read-only)
50 * bits7-2 undefined
51 * bit1 channel0 busmaster interrupt status 0=none, 1=asserted
52 * bit0 channel0 interrupt status 0=none, 1=asserted
53 *
54 * trm290_base+3 Interrupt mask register
55 * bits7-5 undefined
56 * bit4 legacy_header: 1=present, 0=absent
57 * bit3 channel1 busmaster interrupt status 0=none, 1=asserted (read only)
58 * bit2 channel1 interrupt status 0=none, 1=asserted (read only)
59 * bit1 channel1 interrupt mask: 1=masked, 0=unmasked(default)
60 * bit0 channel0 interrupt mask: 1=masked, 0=unmasked(default)
61 *
62 * trm290_base+1 "CPR" Config Pointer Register (byte)
63 * bit7 1=autoincrement CPR bits 2-0 after each access of CDR
64 * bit6 1=min. 1 wait-state posted write cycle (default), 0=0 wait-state
65 * bit5 0=enabled master burst access (default), 1=disable (write only)
66 * bit4 PCI DEVSEL# timing select: 1=medium(default), 0=fast
67 * bit3 0=primary IDE channel, 1=secondary IDE channel
68 * bits2-0 register index for accesses through CDR port
69 *
70 * trm290_base+0 "CDR" Config Data Register (word)
71 * two sets of seven config registers,
72 * selected by CPR bit 3 (channel) and CPR bits 2-0 (index 0 to 6),
73 * each index defined below:
74 *
75 * Index-0 Base address register for command block (word)
76 * defaults: 0x1f0 for primary, 0x170 for secondary
77 *
78 * Index-1 general config register (byte)
79 * bit7 1=DMA enable, 0=DMA disable
80 * bit6 1=activate IDE_RESET, 0=no action (default)
81 * bit5 1=enable IORDY, 0=disable IORDY (default)
82 * bit4 0=16-bit data port(default), 1=8-bit (XT) data port
83 * bit3 interrupt polarity: 1=active_low, 0=active_high(default)
84 * bit2 power-saving-mode(?): 1=enable, 0=disable(default) (write only)
85 * bit1 bus_master_mode(?): 1=enable, 0=disable(default)
86 * bit0 enable_io_ports: 1=enable(default), 0=disable
87 *
88 * Index-2 read-ahead counter preload bits 0-7 (byte, write only)
89 * bits7-0 bits7-0 of readahead count
90 *
91 * Index-3 read-ahead config register (byte, write only)
92 * bit7 1=enable_readahead, 0=disable_readahead(default)
93 * bit6 1=clear_FIFO, 0=no_action
94 * bit5 undefined
95 * bit4 mode4 timing control: 1=enable, 0=disable(default)
96 * bit3 undefined
97 * bit2 undefined
98 * bits1-0 bits9-8 of read-ahead count
99 *
100 * Index-4 base address register for control block (word)
101 * defaults: 0x3f6 for primary, 0x376 for secondary
102 *
103 * Index-5 data port timings (shared by both drives) (byte)
104 * standard PCI "clk" (clock) counts, default value = 0xf5
105 *
106 * bits7-6 setup time: 00=1clk, 01=2clk, 10=3clk, 11=4clk
107 * bits5-3 hold time: 000=1clk, 001=2clk, 010=3clk,
108 * 011=4clk, 100=5clk, 101=6clk,
109 * 110=8clk, 111=12clk
110 * bits2-0 active time: 000=2clk, 001=3clk, 010=4clk,
111 * 011=5clk, 100=6clk, 101=8clk,
112 * 110=12clk, 111=16clk
113 *
114 * Index-6 command/control port timings (shared by both drives) (byte)
115 * same layout as Index-5, default value = 0xde
116 *
117 * Suggested CDR programming for PIO mode0 (600ns):
118 * 0x01f0,0x21,0xff,0x80,0x03f6,0xf5,0xde ; primary
119 * 0x0170,0x21,0xff,0x80,0x0376,0xf5,0xde ; secondary
120 *
121 * Suggested CDR programming for PIO mode3 (180ns):
122 * 0x01f0,0x21,0xff,0x80,0x03f6,0x09,0xde ; primary
123 * 0x0170,0x21,0xff,0x80,0x0376,0x09,0xde ; secondary
124 *
125 * Suggested CDR programming for PIO mode4 (120ns):
126 * 0x01f0,0x21,0xff,0x80,0x03f6,0x00,0xde ; primary
127 * 0x0170,0x21,0xff,0x80,0x0376,0x00,0xde ; secondary
128 *
129 */
130
131#include <linux/config.h>
132#include <linux/types.h>
133#include <linux/module.h>
134#include <linux/kernel.h>
135#include <linux/mm.h>
136#include <linux/ioport.h>
137#include <linux/interrupt.h>
138#include <linux/blkdev.h>
139#include <linux/init.h>
140#include <linux/hdreg.h>
141#include <linux/pci.h>
142#include <linux/delay.h>
143#include <linux/ide.h>
144
145#include <asm/io.h>
146
147static void trm290_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
148{
149 ide_hwif_t *hwif = HWIF(drive);
150 u16 reg = 0;
151 unsigned long flags;
152
153 /* select PIO or DMA */
154 reg = use_dma ? (0x21 | 0x82) : (0x21 & ~0x82);
155
156 local_irq_save(flags);
157
158 if (reg != hwif->select_data) {
159 hwif->select_data = reg;
160 /* set PIO/DMA */
161 hwif->OUTB(0x51|(hwif->channel<<3), hwif->config_data+1);
162 hwif->OUTW(reg & 0xff, hwif->config_data);
163 }
164
165 /* enable IRQ if not probing */
166 if (drive->present) {
167 reg = hwif->INW(hwif->config_data + 3);
168 reg &= 0x13;
169 reg &= ~(1 << hwif->channel);
170 hwif->OUTW(reg, hwif->config_data+3);
171 }
172
173 local_irq_restore(flags);
174}
175
176static void trm290_selectproc (ide_drive_t *drive)
177{
178 trm290_prepare_drive(drive, drive->using_dma);
179}
180
181#ifdef CONFIG_BLK_DEV_IDEDMA
182static void trm290_ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
183{
184 ide_hwif_t *hwif = HWIF(drive);
185
186 if (HWGROUP(drive)->handler != NULL) /* paranoia check */
187 BUG();
188 ide_set_handler(drive, &ide_dma_intr, WAIT_CMD, NULL);
189 /* issue cmd to drive */
190 hwif->OUTB(command, IDE_COMMAND_REG);
191}
192
193static int trm290_ide_dma_setup(ide_drive_t *drive)
194{
195 ide_hwif_t *hwif = drive->hwif;
196 struct request *rq = hwif->hwgroup->rq;
197 unsigned int count, rw;
198
199 if (rq_data_dir(rq)) {
200#ifdef TRM290_NO_DMA_WRITES
201 /* always use PIO for writes */
202 trm290_prepare_drive(drive, 0); /* select PIO xfer */
203 return 1;
204#endif
205 rw = 1;
206 } else
207 rw = 2;
208
209 if (!(count = ide_build_dmatable(drive, rq))) {
210 /* try PIO instead of DMA */
211 trm290_prepare_drive(drive, 0); /* select PIO xfer */
212 return 1;
213 }
214 /* select DMA xfer */
215 trm290_prepare_drive(drive, 1);
216 hwif->OUTL(hwif->dmatable_dma|rw, hwif->dma_command);
217 drive->waiting_for_dma = 1;
218 /* start DMA */
219 hwif->OUTW((count * 2) - 1, hwif->dma_status);
220 return 0;
221}
222
223static void trm290_ide_dma_start(ide_drive_t *drive)
224{
225}
226
227static int trm290_ide_dma_end (ide_drive_t *drive)
228{
229 ide_hwif_t *hwif = HWIF(drive);
230 u16 status = 0;
231
232 drive->waiting_for_dma = 0;
233 /* purge DMA mappings */
234 ide_destroy_dmatable(drive);
235 status = hwif->INW(hwif->dma_status);
236 return (status != 0x00ff);
237}
238
239static int trm290_ide_dma_test_irq (ide_drive_t *drive)
240{
241 ide_hwif_t *hwif = HWIF(drive);
242 u16 status = 0;
243
244 status = hwif->INW(hwif->dma_status);
245 return (status == 0x00ff);
246}
247#endif /* CONFIG_BLK_DEV_IDEDMA */
248
249/*
250 * Invoked from ide-dma.c at boot time.
251 */
252static void __devinit init_hwif_trm290(ide_hwif_t *hwif)
253{
254 unsigned int cfgbase = 0;
255 unsigned long flags;
256 u8 reg = 0;
257 struct pci_dev *dev = hwif->pci_dev;
258
259 hwif->no_lba48 = 1;
260 hwif->chipset = ide_trm290;
261 cfgbase = pci_resource_start(dev, 4);
262 if ((dev->class & 5) && cfgbase) {
263 hwif->config_data = cfgbase;
264 printk(KERN_INFO "TRM290: chip config base at 0x%04lx\n",
265 hwif->config_data);
266 } else {
267 hwif->config_data = 0x3df0;
268 printk(KERN_INFO "TRM290: using default config base at 0x%04lx\n",
269 hwif->config_data);
270 }
271
272 local_irq_save(flags);
273 /* put config reg into first byte of hwif->select_data */
274 hwif->OUTB(0x51|(hwif->channel<<3), hwif->config_data+1);
275 /* select PIO as default */
276 hwif->select_data = 0x21;
277 hwif->OUTB(hwif->select_data, hwif->config_data);
278 /* get IRQ info */
279 reg = hwif->INB(hwif->config_data+3);
280 /* mask IRQs for both ports */
281 reg = (reg & 0x10) | 0x03;
282 hwif->OUTB(reg, hwif->config_data+3);
283 local_irq_restore(flags);
284
285 if ((reg & 0x10))
286 /* legacy mode */
287 hwif->irq = hwif->channel ? 15 : 14;
288 else if (!hwif->irq && hwif->mate && hwif->mate->irq)
289 /* sharing IRQ with mate */
290 hwif->irq = hwif->mate->irq;
291
292 ide_setup_dma(hwif, (hwif->config_data + 4) ^ (hwif->channel ? 0x0080 : 0x0000), 3);
293
294#ifdef CONFIG_BLK_DEV_IDEDMA
295 hwif->dma_setup = &trm290_ide_dma_setup;
296 hwif->dma_exec_cmd = &trm290_ide_dma_exec_cmd;
297 hwif->dma_start = &trm290_ide_dma_start;
298 hwif->ide_dma_end = &trm290_ide_dma_end;
299 hwif->ide_dma_test_irq = &trm290_ide_dma_test_irq;
300#endif /* CONFIG_BLK_DEV_IDEDMA */
301
302 hwif->selectproc = &trm290_selectproc;
303 hwif->autodma = 0; /* play it safe for now */
304 hwif->drives[0].autodma = hwif->autodma;
305 hwif->drives[1].autodma = hwif->autodma;
306#if 1
307 {
308 /*
309 * My trm290-based card doesn't seem to work with all possible values
310 * for the control basereg, so this kludge ensures that we use only
311 * values that are known to work. Ugh. -ml
312 */
313 u16 new, old, compat = hwif->channel ? 0x374 : 0x3f4;
314 static u16 next_offset = 0;
315 u8 old_mask;
316
317 hwif->OUTB(0x54|(hwif->channel<<3), hwif->config_data+1);
318 old = hwif->INW(hwif->config_data);
319 old &= ~1;
320 old_mask = hwif->INB(old+2);
321 if (old != compat && old_mask == 0xff) {
322 /* leave lower 10 bits untouched */
323 compat += (next_offset += 0x400);
324 hwif->io_ports[IDE_CONTROL_OFFSET] = compat + 2;
325 hwif->OUTW(compat|1, hwif->config_data);
326 new = hwif->INW(hwif->config_data);
327 printk(KERN_INFO "%s: control basereg workaround: "
328 "old=0x%04x, new=0x%04x\n",
329 hwif->name, old, new & ~1);
330 }
331 }
332#endif
333}
334
335static ide_pci_device_t trm290_chipset __devinitdata = {
336 .name = "TRM290",
337 .init_hwif = init_hwif_trm290,
338 .channels = 2,
339 .autodma = NOAUTODMA,
340 .bootable = ON_BOARD,
341};
342
343static int __devinit trm290_init_one(struct pci_dev *dev, const struct pci_device_id *id)
344{
345 return ide_setup_pci_device(dev, &trm290_chipset);
346}
347
348static struct pci_device_id trm290_pci_tbl[] = {
349 { PCI_VENDOR_ID_TEKRAM, PCI_DEVICE_ID_TEKRAM_DC290, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
350 { 0, },
351};
352MODULE_DEVICE_TABLE(pci, trm290_pci_tbl);
353
354static struct pci_driver driver = {
355 .name = "TRM290_IDE",
356 .id_table = trm290_pci_tbl,
357 .probe = trm290_init_one,
358};
359
360static int trm290_ide_init(void)
361{
362 return ide_pci_register_driver(&driver);
363}
364
365module_init(trm290_ide_init);
366
367MODULE_AUTHOR("Mark Lord");
368MODULE_DESCRIPTION("PCI driver module for Tekram TRM290 IDE");
369MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/via82cxxx.c b/drivers/ide/pci/via82cxxx.c
new file mode 100644
index 000000000000..069dbffe2116
--- /dev/null
+++ b/drivers/ide/pci/via82cxxx.c
@@ -0,0 +1,656 @@
1/*
2 *
3 * Version 3.38
4 *
5 * VIA IDE driver for Linux. Supported southbridges:
6 *
7 * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
8 * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
9 * vt8235, vt8237
10 *
11 * Copyright (c) 2000-2002 Vojtech Pavlik
12 *
13 * Based on the work of:
14 * Michel Aubry
15 * Jeff Garzik
16 * Andre Hedrick
17 *
18 * Documentation:
19 * Obsolete device documentation publically available from via.com.tw
20 * Current device documentation available under NDA only
21 */
22
23/*
24 * This program is free software; you can redistribute it and/or modify it
25 * under the terms of the GNU General Public License version 2 as published by
26 * the Free Software Foundation.
27 */
28
29#include <linux/config.h>
30#include <linux/module.h>
31#include <linux/kernel.h>
32#include <linux/ioport.h>
33#include <linux/blkdev.h>
34#include <linux/pci.h>
35#include <linux/init.h>
36#include <linux/ide.h>
37#include <asm/io.h>
38
39#ifdef CONFIG_PPC_MULTIPLATFORM
40#include <asm/processor.h>
41#endif
42
43#include "ide-timing.h"
44
45#define DISPLAY_VIA_TIMINGS
46
47#define VIA_IDE_ENABLE 0x40
48#define VIA_IDE_CONFIG 0x41
49#define VIA_FIFO_CONFIG 0x43
50#define VIA_MISC_1 0x44
51#define VIA_MISC_2 0x45
52#define VIA_MISC_3 0x46
53#define VIA_DRIVE_TIMING 0x48
54#define VIA_8BIT_TIMING 0x4e
55#define VIA_ADDRESS_SETUP 0x4c
56#define VIA_UDMA_TIMING 0x50
57
58#define VIA_UDMA 0x007
59#define VIA_UDMA_NONE 0x000
60#define VIA_UDMA_33 0x001
61#define VIA_UDMA_66 0x002
62#define VIA_UDMA_100 0x003
63#define VIA_UDMA_133 0x004
64#define VIA_BAD_PREQ 0x010 /* Crashes if PREQ# till DDACK# set */
65#define VIA_BAD_CLK66 0x020 /* 66 MHz clock doesn't work correctly */
66#define VIA_SET_FIFO 0x040 /* Needs to have FIFO split set */
67#define VIA_NO_UNMASK 0x080 /* Doesn't work with IRQ unmasking on */
68#define VIA_BAD_ID 0x100 /* Has wrong vendor ID (0x1107) */
69#define VIA_BAD_AST 0x200 /* Don't touch Address Setup Timing */
70
71/*
72 * VIA SouthBridge chips.
73 */
74
75static struct via_isa_bridge {
76 char *name;
77 u16 id;
78 u8 rev_min;
79 u8 rev_max;
80 u16 flags;
81} via_isa_bridges[] = {
82 { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
83 { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
84 { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
85 { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, VIA_UDMA_100 },
86 { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, VIA_UDMA_100 },
87 { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, VIA_UDMA_100 },
88 { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, VIA_UDMA_100 },
89 { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, VIA_UDMA_66 },
90 { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
91 { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, VIA_UDMA_66 },
92 { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
93 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, VIA_UDMA_33 | VIA_SET_FIFO },
94 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, VIA_UDMA_33 | VIA_SET_FIFO | VIA_BAD_PREQ },
95 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, VIA_UDMA_33 | VIA_SET_FIFO },
96 { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, VIA_UDMA_33 | VIA_SET_FIFO },
97 { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE | VIA_SET_FIFO },
98 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK },
99 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
100 { NULL }
101};
102
103static struct via_isa_bridge *via_config;
104static unsigned int via_80w;
105static unsigned int via_clock;
106static char *via_dma[] = { "MWDMA16", "UDMA33", "UDMA66", "UDMA100", "UDMA133" };
107
108/*
109 * VIA /proc entry.
110 */
111
112#if defined(DISPLAY_VIA_TIMINGS) && defined(CONFIG_PROC_FS)
113
114#include <linux/stat.h>
115#include <linux/proc_fs.h>
116
117static u8 via_proc = 0;
118static unsigned long via_base;
119static struct pci_dev *bmide_dev, *isa_dev;
120
121static char *via_control3[] = { "No limit", "64", "128", "192" };
122
123#define via_print(format, arg...) p += sprintf(p, format "\n" , ## arg)
124#define via_print_drive(name, format, arg...)\
125 p += sprintf(p, name); for (i = 0; i < 4; i++) p += sprintf(p, format, ## arg); p += sprintf(p, "\n");
126
127
128/**
129 * via_get_info - generate via /proc file
130 * @buffer: buffer for data
131 * @addr: set to start of data to use
132 * @offset: current file offset
133 * @count: size of read
134 *
135 * Fills in buffer with the debugging/configuration information for
136 * the VIA chipset tuning and attached drives
137 */
138
139static int via_get_info(char *buffer, char **addr, off_t offset, int count)
140{
141 int speed[4], cycle[4], setup[4], active[4], recover[4], den[4],
142 uen[4], udma[4], umul[4], active8b[4], recover8b[4];
143 struct pci_dev *dev = bmide_dev;
144 unsigned int v, u, i;
145 int len;
146 u16 c, w;
147 u8 t, x;
148 char *p = buffer;
149
150 via_print("----------VIA BusMastering IDE Configuration"
151 "----------------");
152
153 via_print("Driver Version: 3.38");
154 via_print("South Bridge: VIA %s",
155 via_config->name);
156
157 pci_read_config_byte(isa_dev, PCI_REVISION_ID, &t);
158 pci_read_config_byte(dev, PCI_REVISION_ID, &x);
159 via_print("Revision: ISA %#x IDE %#x", t, x);
160 via_print("Highest DMA rate: %s",
161 via_dma[via_config->flags & VIA_UDMA]);
162
163 via_print("BM-DMA base: %#lx", via_base);
164 via_print("PCI clock: %d.%dMHz",
165 via_clock / 1000, via_clock / 100 % 10);
166
167 pci_read_config_byte(dev, VIA_MISC_1, &t);
168 via_print("Master Read Cycle IRDY: %dws",
169 (t & 64) >> 6);
170 via_print("Master Write Cycle IRDY: %dws",
171 (t & 32) >> 5);
172 via_print("BM IDE Status Register Read Retry: %s",
173 (t & 8) ? "yes" : "no");
174
175 pci_read_config_byte(dev, VIA_MISC_3, &t);
176 via_print("Max DRDY Pulse Width: %s%s",
177 via_control3[(t & 0x03)], (t & 0x03) ? " PCI clocks" : "");
178
179 via_print("-----------------------Primary IDE"
180 "-------Secondary IDE------");
181 via_print("Read DMA FIFO flush: %10s%20s",
182 (t & 0x80) ? "yes" : "no", (t & 0x40) ? "yes" : "no");
183 via_print("End Sector FIFO flush: %10s%20s",
184 (t & 0x20) ? "yes" : "no", (t & 0x10) ? "yes" : "no");
185
186 pci_read_config_byte(dev, VIA_IDE_CONFIG, &t);
187 via_print("Prefetch Buffer: %10s%20s",
188 (t & 0x80) ? "yes" : "no", (t & 0x20) ? "yes" : "no");
189 via_print("Post Write Buffer: %10s%20s",
190 (t & 0x40) ? "yes" : "no", (t & 0x10) ? "yes" : "no");
191
192 pci_read_config_byte(dev, VIA_IDE_ENABLE, &t);
193 via_print("Enabled: %10s%20s",
194 (t & 0x02) ? "yes" : "no", (t & 0x01) ? "yes" : "no");
195
196 c = inb(via_base + 0x02) | (inb(via_base + 0x0a) << 8);
197 via_print("Simplex only: %10s%20s",
198 (c & 0x80) ? "yes" : "no", (c & 0x8000) ? "yes" : "no");
199
200 via_print("Cable Type: %10s%20s",
201 (via_80w & 1) ? "80w" : "40w", (via_80w & 2) ? "80w" : "40w");
202
203 via_print("-------------------drive0----drive1"
204 "----drive2----drive3-----");
205
206 pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
207 pci_read_config_dword(dev, VIA_DRIVE_TIMING, &v);
208 pci_read_config_word(dev, VIA_8BIT_TIMING, &w);
209
210 if (via_config->flags & VIA_UDMA)
211 pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
212 else u = 0;
213
214 for (i = 0; i < 4; i++) {
215
216 setup[i] = ((t >> ((3 - i) << 1)) & 0x3) + 1;
217 recover8b[i] = ((w >> ((1 - (i >> 1)) << 3)) & 0xf) + 1;
218 active8b[i] = ((w >> (((1 - (i >> 1)) << 3) + 4)) & 0xf) + 1;
219 active[i] = ((v >> (((3 - i) << 3) + 4)) & 0xf) + 1;
220 recover[i] = ((v >> ((3 - i) << 3)) & 0xf) + 1;
221 udma[i] = ((u >> ((3 - i) << 3)) & 0x7) + 2;
222 umul[i] = ((u >> (((3 - i) & 2) << 3)) & 0x8) ? 1 : 2;
223 uen[i] = ((u >> ((3 - i) << 3)) & 0x20);
224 den[i] = (c & ((i & 1) ? 0x40 : 0x20) << ((i & 2) << 2));
225
226 speed[i] = 2 * via_clock / (active[i] + recover[i]);
227 cycle[i] = 1000000 * (active[i] + recover[i]) / via_clock;
228
229 if (!uen[i] || !den[i])
230 continue;
231
232 switch (via_config->flags & VIA_UDMA) {
233
234 case VIA_UDMA_33:
235 speed[i] = 2 * via_clock / udma[i];
236 cycle[i] = 1000000 * udma[i] / via_clock;
237 break;
238
239 case VIA_UDMA_66:
240 speed[i] = 4 * via_clock / (udma[i] * umul[i]);
241 cycle[i] = 500000 * (udma[i] * umul[i]) / via_clock;
242 break;
243
244 case VIA_UDMA_100:
245 speed[i] = 6 * via_clock / udma[i];
246 cycle[i] = 333333 * udma[i] / via_clock;
247 break;
248
249 case VIA_UDMA_133:
250 speed[i] = 8 * via_clock / udma[i];
251 cycle[i] = 250000 * udma[i] / via_clock;
252 break;
253 }
254 }
255
256 via_print_drive("Transfer Mode: ", "%10s",
257 den[i] ? (uen[i] ? "UDMA" : "DMA") : "PIO");
258
259 via_print_drive("Address Setup: ", "%8dns",
260 1000000 * setup[i] / via_clock);
261 via_print_drive("Cmd Active: ", "%8dns",
262 1000000 * active8b[i] / via_clock);
263 via_print_drive("Cmd Recovery: ", "%8dns",
264 1000000 * recover8b[i] / via_clock);
265 via_print_drive("Data Active: ", "%8dns",
266 1000000 * active[i] / via_clock);
267 via_print_drive("Data Recovery: ", "%8dns",
268 1000000 * recover[i] / via_clock);
269 via_print_drive("Cycle Time: ", "%8dns",
270 cycle[i]);
271 via_print_drive("Transfer Rate: ", "%4d.%dMB/s",
272 speed[i] / 1000, speed[i] / 100 % 10);
273
274 /* hoping it is less than 4K... */
275 len = (p - buffer) - offset;
276 *addr = buffer + offset;
277
278 return len > count ? count : len;
279}
280
281#endif /* DISPLAY_VIA_TIMINGS && CONFIG_PROC_FS */
282
283/**
284 * via_set_speed - write timing registers
285 * @dev: PCI device
286 * @dn: device
287 * @timing: IDE timing data to use
288 *
289 * via_set_speed writes timing values to the chipset registers
290 */
291
292static void via_set_speed(struct pci_dev *dev, u8 dn, struct ide_timing *timing)
293{
294 u8 t;
295
296 if (~via_config->flags & VIA_BAD_AST) {
297 pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
298 t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
299 pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t);
300 }
301
302 pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)),
303 ((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1));
304
305 pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn),
306 ((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1));
307
308 switch (via_config->flags & VIA_UDMA) {
309 case VIA_UDMA_33: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
310 case VIA_UDMA_66: t = timing->udma ? (0xe8 | (FIT(timing->udma, 2, 9) - 2)) : 0x0f; break;
311 case VIA_UDMA_100: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
312 case VIA_UDMA_133: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
313 default: return;
314 }
315
316 pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t);
317}
318
319/**
320 * via_set_drive - configure transfer mode
321 * @drive: Drive to set up
322 * @speed: desired speed
323 *
324 * via_set_drive() computes timing values configures the drive and
325 * the chipset to a desired transfer mode. It also can be called
326 * by upper layers.
327 */
328
329static int via_set_drive(ide_drive_t *drive, u8 speed)
330{
331 ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1);
332 struct ide_timing t, p;
333 unsigned int T, UT;
334
335 if (speed != XFER_PIO_SLOW)
336 ide_config_drive_speed(drive, speed);
337
338 T = 1000000000 / via_clock;
339
340 switch (via_config->flags & VIA_UDMA) {
341 case VIA_UDMA_33: UT = T; break;
342 case VIA_UDMA_66: UT = T/2; break;
343 case VIA_UDMA_100: UT = T/3; break;
344 case VIA_UDMA_133: UT = T/4; break;
345 default: UT = T;
346 }
347
348 ide_timing_compute(drive, speed, &t, T, UT);
349
350 if (peer->present) {
351 ide_timing_compute(peer, peer->current_speed, &p, T, UT);
352 ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
353 }
354
355 via_set_speed(HWIF(drive)->pci_dev, drive->dn, &t);
356
357 if (!drive->init_speed)
358 drive->init_speed = speed;
359 drive->current_speed = speed;
360
361 return 0;
362}
363
364/**
365 * via82cxxx_tune_drive - PIO setup
366 * @drive: drive to set up
367 * @pio: mode to use (255 for 'best possible')
368 *
369 * A callback from the upper layers for PIO-only tuning.
370 */
371
372static void via82cxxx_tune_drive(ide_drive_t *drive, u8 pio)
373{
374 if (pio == 255) {
375 via_set_drive(drive,
376 ide_find_best_mode(drive, XFER_PIO | XFER_EPIO));
377 return;
378 }
379
380 via_set_drive(drive, XFER_PIO_0 + min_t(u8, pio, 5));
381}
382
383/**
384 * via82cxxx_ide_dma_check - set up for DMA if possible
385 * @drive: IDE drive to set up
386 *
387 * Set up the drive for the highest supported speed considering the
388 * driver, controller and cable
389 */
390
391static int via82cxxx_ide_dma_check (ide_drive_t *drive)
392{
393 u16 w80 = HWIF(drive)->udma_four;
394
395 u16 speed = ide_find_best_mode(drive,
396 XFER_PIO | XFER_EPIO | XFER_SWDMA | XFER_MWDMA |
397 (via_config->flags & VIA_UDMA ? XFER_UDMA : 0) |
398 (w80 && (via_config->flags & VIA_UDMA) >= VIA_UDMA_66 ? XFER_UDMA_66 : 0) |
399 (w80 && (via_config->flags & VIA_UDMA) >= VIA_UDMA_100 ? XFER_UDMA_100 : 0) |
400 (w80 && (via_config->flags & VIA_UDMA) >= VIA_UDMA_133 ? XFER_UDMA_133 : 0));
401
402 via_set_drive(drive, speed);
403
404 if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
405 return HWIF(drive)->ide_dma_on(drive);
406 return HWIF(drive)->ide_dma_off_quietly(drive);
407}
408
409/**
410 * init_chipset_via82cxxx - initialization handler
411 * @dev: PCI device
412 * @name: Name of interface
413 *
414 * The initialization callback. Here we determine the IDE chip type
415 * and initialize its drive independent registers.
416 */
417
418static unsigned int __init init_chipset_via82cxxx(struct pci_dev *dev, const char *name)
419{
420 struct pci_dev *isa = NULL;
421 u8 t, v;
422 unsigned int u;
423 int i;
424
425 /*
426 * Find the ISA bridge to see how good the IDE is.
427 */
428
429 for (via_config = via_isa_bridges; via_config->id; via_config++)
430 if ((isa = pci_find_device(PCI_VENDOR_ID_VIA +
431 !!(via_config->flags & VIA_BAD_ID),
432 via_config->id, NULL))) {
433
434 pci_read_config_byte(isa, PCI_REVISION_ID, &t);
435 if (t >= via_config->rev_min &&
436 t <= via_config->rev_max)
437 break;
438 }
439
440 if (!via_config->id) {
441 printk(KERN_WARNING "VP_IDE: Unknown VIA SouthBridge, disabling DMA.\n");
442 return -ENODEV;
443 }
444
445 /*
446 * Check 80-wire cable presence and setup Clk66.
447 */
448
449 switch (via_config->flags & VIA_UDMA) {
450
451 case VIA_UDMA_66:
452 /* Enable Clk66 */
453 pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
454 pci_write_config_dword(dev, VIA_UDMA_TIMING, u|0x80008);
455 for (i = 24; i >= 0; i -= 8)
456 if (((u >> (i & 16)) & 8) &&
457 ((u >> i) & 0x20) &&
458 (((u >> i) & 7) < 2)) {
459 /*
460 * 2x PCI clock and
461 * UDMA w/ < 3T/cycle
462 */
463 via_80w |= (1 << (1 - (i >> 4)));
464 }
465 break;
466
467 case VIA_UDMA_100:
468 pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
469 for (i = 24; i >= 0; i -= 8)
470 if (((u >> i) & 0x10) ||
471 (((u >> i) & 0x20) &&
472 (((u >> i) & 7) < 4))) {
473 /* BIOS 80-wire bit or
474 * UDMA w/ < 60ns/cycle
475 */
476 via_80w |= (1 << (1 - (i >> 4)));
477 }
478 break;
479
480 case VIA_UDMA_133:
481 pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
482 for (i = 24; i >= 0; i -= 8)
483 if (((u >> i) & 0x10) ||
484 (((u >> i) & 0x20) &&
485 (((u >> i) & 7) < 6))) {
486 /* BIOS 80-wire bit or
487 * UDMA w/ < 60ns/cycle
488 */
489 via_80w |= (1 << (1 - (i >> 4)));
490 }
491 break;
492
493 }
494
495 /* Disable Clk66 */
496 if (via_config->flags & VIA_BAD_CLK66) {
497 /* Would cause trouble on 596a and 686 */
498 pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
499 pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008);
500 }
501
502 /*
503 * Check whether interfaces are enabled.
504 */
505
506 pci_read_config_byte(dev, VIA_IDE_ENABLE, &v);
507
508 /*
509 * Set up FIFO sizes and thresholds.
510 */
511
512 pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t);
513
514 /* Disable PREQ# till DDACK# */
515 if (via_config->flags & VIA_BAD_PREQ) {
516 /* Would crash on 586b rev 41 */
517 t &= 0x7f;
518 }
519
520 /* Fix FIFO split between channels */
521 if (via_config->flags & VIA_SET_FIFO) {
522 t &= (t & 0x9f);
523 switch (v & 3) {
524 case 2: t |= 0x00; break; /* 16 on primary */
525 case 1: t |= 0x60; break; /* 16 on secondary */
526 case 3: t |= 0x20; break; /* 8 pri 8 sec */
527 }
528 }
529
530 pci_write_config_byte(dev, VIA_FIFO_CONFIG, t);
531
532 /*
533 * Determine system bus clock.
534 */
535
536 via_clock = system_bus_clock() * 1000;
537
538 switch (via_clock) {
539 case 33000: via_clock = 33333; break;
540 case 37000: via_clock = 37500; break;
541 case 41000: via_clock = 41666; break;
542 }
543
544 if (via_clock < 20000 || via_clock > 50000) {
545 printk(KERN_WARNING "VP_IDE: User given PCI clock speed "
546 "impossible (%d), using 33 MHz instead.\n", via_clock);
547 printk(KERN_WARNING "VP_IDE: Use ide0=ata66 if you want "
548 "to assume 80-wire cable.\n");
549 via_clock = 33333;
550 }
551
552 /*
553 * Print the boot message.
554 */
555
556 pci_read_config_byte(isa, PCI_REVISION_ID, &t);
557 printk(KERN_INFO "VP_IDE: VIA %s (rev %02x) IDE %s "
558 "controller on pci%s\n",
559 via_config->name, t,
560 via_dma[via_config->flags & VIA_UDMA],
561 pci_name(dev));
562
563 /*
564 * Setup /proc/ide/via entry.
565 */
566
567#if defined(DISPLAY_VIA_TIMINGS) && defined(CONFIG_PROC_FS)
568 if (!via_proc) {
569 via_base = pci_resource_start(dev, 4);
570 bmide_dev = dev;
571 isa_dev = isa;
572 ide_pci_create_host_proc("via", via_get_info);
573 via_proc = 1;
574 }
575#endif /* DISPLAY_VIA_TIMINGS && CONFIG_PROC_FS */
576 return 0;
577}
578
579static void __init init_hwif_via82cxxx(ide_hwif_t *hwif)
580{
581 int i;
582
583 hwif->autodma = 0;
584
585 hwif->tuneproc = &via82cxxx_tune_drive;
586 hwif->speedproc = &via_set_drive;
587
588
589#if defined(CONFIG_PPC_MULTIPLATFORM) && defined(CONFIG_PPC32)
590 if(_machine == _MACH_chrp && _chrp_type == _CHRP_Pegasos) {
591 hwif->irq = hwif->channel ? 15 : 14;
592 }
593#endif
594
595 for (i = 0; i < 2; i++) {
596 hwif->drives[i].io_32bit = 1;
597 hwif->drives[i].unmask = (via_config->flags & VIA_NO_UNMASK) ? 0 : 1;
598 hwif->drives[i].autotune = 1;
599 hwif->drives[i].dn = hwif->channel * 2 + i;
600 }
601
602 if (!hwif->dma_base)
603 return;
604
605 hwif->atapi_dma = 1;
606 hwif->ultra_mask = 0x7f;
607 hwif->mwdma_mask = 0x07;
608 hwif->swdma_mask = 0x07;
609
610 if (!hwif->udma_four)
611 hwif->udma_four = (via_80w >> hwif->channel) & 1;
612 hwif->ide_dma_check = &via82cxxx_ide_dma_check;
613 if (!noautodma)
614 hwif->autodma = 1;
615 hwif->drives[0].autodma = hwif->autodma;
616 hwif->drives[1].autodma = hwif->autodma;
617}
618
619static ide_pci_device_t via82cxxx_chipset __devinitdata = {
620 .name = "VP_IDE",
621 .init_chipset = init_chipset_via82cxxx,
622 .init_hwif = init_hwif_via82cxxx,
623 .channels = 2,
624 .autodma = NOAUTODMA,
625 .enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}},
626 .bootable = ON_BOARD,
627};
628
629static int __devinit via_init_one(struct pci_dev *dev, const struct pci_device_id *id)
630{
631 return ide_setup_pci_device(dev, &via82cxxx_chipset);
632}
633
634static struct pci_device_id via_pci_tbl[] = {
635 { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
636 { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
637 { 0, },
638};
639MODULE_DEVICE_TABLE(pci, via_pci_tbl);
640
641static struct pci_driver driver = {
642 .name = "VIA_IDE",
643 .id_table = via_pci_tbl,
644 .probe = via_init_one,
645};
646
647static int via_ide_init(void)
648{
649 return ide_pci_register_driver(&driver);
650}
651
652module_init(via_ide_init);
653
654MODULE_AUTHOR("Vojtech Pavlik, Michel Aubry, Jeff Garzik, Andre Hedrick");
655MODULE_DESCRIPTION("PCI driver module for VIA IDE");
656MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 03:29:12 -0500