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authorBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2008-10-21 14:57:23 -0400
committerBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2008-10-21 14:57:23 -0400
commit2bfba3c444fe8b2ab1c38112a89d8f03b61136ca (patch)
tree17580eee63d868c9d6b97a6bc956a08f25631532 /drivers/ide/pci
parent2515ddc6db8eb49a79f0fe5e67ff09ac7c81eab4 (diff)
ide: remove useless subdirs from drivers/ide/
Suggested-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Diffstat (limited to 'drivers/ide/pci')
-rw-r--r--drivers/ide/pci/Makefile43
-rw-r--r--drivers/ide/pci/aec62xx.c329
-rw-r--r--drivers/ide/pci/alim15x3.c602
-rw-r--r--drivers/ide/pci/amd74xx.c346
-rw-r--r--drivers/ide/pci/atiixp.c209
-rw-r--r--drivers/ide/pci/cmd640.c836
-rw-r--r--drivers/ide/pci/cmd64x.c532
-rw-r--r--drivers/ide/pci/cs5520.c165
-rw-r--r--drivers/ide/pci/cs5530.c294
-rw-r--r--drivers/ide/pci/cs5535.c219
-rw-r--r--drivers/ide/pci/cy82c693.c358
-rw-r--r--drivers/ide/pci/delkin_cb.c192
-rw-r--r--drivers/ide/pci/generic.c193
-rw-r--r--drivers/ide/pci/hpt366.c1643
-rw-r--r--drivers/ide/pci/it8213.c216
-rw-r--r--drivers/ide/pci/it821x.c706
-rw-r--r--drivers/ide/pci/jmicron.c176
-rw-r--r--drivers/ide/pci/ns87415.c366
-rw-r--r--drivers/ide/pci/opti621.c247
-rw-r--r--drivers/ide/pci/pdc202xx_new.c588
-rw-r--r--drivers/ide/pci/pdc202xx_old.c453
-rw-r--r--drivers/ide/pci/piix.c480
-rw-r--r--drivers/ide/pci/rz1000.c85
-rw-r--r--drivers/ide/pci/sc1200.c357
-rw-r--r--drivers/ide/pci/scc_pata.c966
-rw-r--r--drivers/ide/pci/serverworks.c470
-rw-r--r--drivers/ide/pci/sgiioc4.c674
-rw-r--r--drivers/ide/pci/siimage.c857
-rw-r--r--drivers/ide/pci/sis5513.c641
-rw-r--r--drivers/ide/pci/sl82c105.c371
-rw-r--r--drivers/ide/pci/slc90e66.c181
-rw-r--r--drivers/ide/pci/tc86c001.c270
-rw-r--r--drivers/ide/pci/triflex.c142
-rw-r--r--drivers/ide/pci/trm290.c375
-rw-r--r--drivers/ide/pci/via82cxxx.c514
35 files changed, 0 insertions, 15096 deletions
diff --git a/drivers/ide/pci/Makefile b/drivers/ide/pci/Makefile
deleted file mode 100644
index ab44a1f5f5a9..000000000000
--- a/drivers/ide/pci/Makefile
+++ /dev/null
@@ -1,43 +0,0 @@
1
2obj-$(CONFIG_BLK_DEV_AEC62XX) += aec62xx.o
3obj-$(CONFIG_BLK_DEV_ALI15X3) += alim15x3.o
4obj-$(CONFIG_BLK_DEV_AMD74XX) += amd74xx.o
5obj-$(CONFIG_BLK_DEV_ATIIXP) += atiixp.o
6obj-$(CONFIG_BLK_DEV_CELLEB) += scc_pata.o
7obj-$(CONFIG_BLK_DEV_CMD64X) += cmd64x.o
8obj-$(CONFIG_BLK_DEV_CS5520) += cs5520.o
9obj-$(CONFIG_BLK_DEV_CS5530) += cs5530.o
10obj-$(CONFIG_BLK_DEV_CS5535) += cs5535.o
11obj-$(CONFIG_BLK_DEV_SC1200) += sc1200.o
12obj-$(CONFIG_BLK_DEV_CY82C693) += cy82c693.o
13obj-$(CONFIG_BLK_DEV_DELKIN) += delkin_cb.o
14obj-$(CONFIG_BLK_DEV_HPT366) += hpt366.o
15obj-$(CONFIG_BLK_DEV_IT8213) += it8213.o
16obj-$(CONFIG_BLK_DEV_IT821X) += it821x.o
17obj-$(CONFIG_BLK_DEV_JMICRON) += jmicron.o
18obj-$(CONFIG_BLK_DEV_NS87415) += ns87415.o
19obj-$(CONFIG_BLK_DEV_OPTI621) += opti621.o
20obj-$(CONFIG_BLK_DEV_PDC202XX_OLD) += pdc202xx_old.o
21obj-$(CONFIG_BLK_DEV_PDC202XX_NEW) += pdc202xx_new.o
22obj-$(CONFIG_BLK_DEV_PIIX) += piix.o
23obj-$(CONFIG_BLK_DEV_RZ1000) += rz1000.o
24obj-$(CONFIG_BLK_DEV_SVWKS) += serverworks.o
25obj-$(CONFIG_BLK_DEV_SGIIOC4) += sgiioc4.o
26obj-$(CONFIG_BLK_DEV_SIIMAGE) += siimage.o
27obj-$(CONFIG_BLK_DEV_SIS5513) += sis5513.o
28obj-$(CONFIG_BLK_DEV_SL82C105) += sl82c105.o
29obj-$(CONFIG_BLK_DEV_SLC90E66) += slc90e66.o
30obj-$(CONFIG_BLK_DEV_TC86C001) += tc86c001.o
31obj-$(CONFIG_BLK_DEV_TRIFLEX) += triflex.o
32obj-$(CONFIG_BLK_DEV_TRM290) += trm290.o
33obj-$(CONFIG_BLK_DEV_VIA82CXXX) += via82cxxx.o
34
35# Must appear at the end of the block
36obj-$(CONFIG_BLK_DEV_GENERIC) += ide-pci-generic.o
37ide-pci-generic-y += generic.o
38
39ifeq ($(CONFIG_BLK_DEV_CMD640), m)
40 obj-m += cmd640.o
41endif
42
43EXTRA_CFLAGS := -Idrivers/ide
diff --git a/drivers/ide/pci/aec62xx.c b/drivers/ide/pci/aec62xx.c
deleted file mode 100644
index 4142c698e0d3..000000000000
--- a/drivers/ide/pci/aec62xx.c
+++ /dev/null
@@ -1,329 +0,0 @@
1/*
2 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
3 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
4 *
5 */
6
7#include <linux/module.h>
8#include <linux/types.h>
9#include <linux/pci.h>
10#include <linux/ide.h>
11#include <linux/init.h>
12
13#include <asm/io.h>
14
15#define DRV_NAME "aec62xx"
16
17struct chipset_bus_clock_list_entry {
18 u8 xfer_speed;
19 u8 chipset_settings;
20 u8 ultra_settings;
21};
22
23static const struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
24 { XFER_UDMA_6, 0x31, 0x07 },
25 { XFER_UDMA_5, 0x31, 0x06 },
26 { XFER_UDMA_4, 0x31, 0x05 },
27 { XFER_UDMA_3, 0x31, 0x04 },
28 { XFER_UDMA_2, 0x31, 0x03 },
29 { XFER_UDMA_1, 0x31, 0x02 },
30 { XFER_UDMA_0, 0x31, 0x01 },
31
32 { XFER_MW_DMA_2, 0x31, 0x00 },
33 { XFER_MW_DMA_1, 0x31, 0x00 },
34 { XFER_MW_DMA_0, 0x0a, 0x00 },
35 { XFER_PIO_4, 0x31, 0x00 },
36 { XFER_PIO_3, 0x33, 0x00 },
37 { XFER_PIO_2, 0x08, 0x00 },
38 { XFER_PIO_1, 0x0a, 0x00 },
39 { XFER_PIO_0, 0x00, 0x00 },
40 { 0, 0x00, 0x00 }
41};
42
43static const struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
44 { XFER_UDMA_6, 0x41, 0x06 },
45 { XFER_UDMA_5, 0x41, 0x05 },
46 { XFER_UDMA_4, 0x41, 0x04 },
47 { XFER_UDMA_3, 0x41, 0x03 },
48 { XFER_UDMA_2, 0x41, 0x02 },
49 { XFER_UDMA_1, 0x41, 0x01 },
50 { XFER_UDMA_0, 0x41, 0x01 },
51
52 { XFER_MW_DMA_2, 0x41, 0x00 },
53 { XFER_MW_DMA_1, 0x42, 0x00 },
54 { XFER_MW_DMA_0, 0x7a, 0x00 },
55 { XFER_PIO_4, 0x41, 0x00 },
56 { XFER_PIO_3, 0x43, 0x00 },
57 { XFER_PIO_2, 0x78, 0x00 },
58 { XFER_PIO_1, 0x7a, 0x00 },
59 { XFER_PIO_0, 0x70, 0x00 },
60 { 0, 0x00, 0x00 }
61};
62
63/*
64 * TO DO: active tuning and correction of cards without a bios.
65 */
66static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
67{
68 for ( ; chipset_table->xfer_speed ; chipset_table++)
69 if (chipset_table->xfer_speed == speed) {
70 return chipset_table->chipset_settings;
71 }
72 return chipset_table->chipset_settings;
73}
74
75static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
76{
77 for ( ; chipset_table->xfer_speed ; chipset_table++)
78 if (chipset_table->xfer_speed == speed) {
79 return chipset_table->ultra_settings;
80 }
81 return chipset_table->ultra_settings;
82}
83
84static void aec6210_set_mode(ide_drive_t *drive, const u8 speed)
85{
86 ide_hwif_t *hwif = HWIF(drive);
87 struct pci_dev *dev = to_pci_dev(hwif->dev);
88 struct ide_host *host = pci_get_drvdata(dev);
89 struct chipset_bus_clock_list_entry *bus_clock = host->host_priv;
90 u16 d_conf = 0;
91 u8 ultra = 0, ultra_conf = 0;
92 u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
93 unsigned long flags;
94
95 local_irq_save(flags);
96 /* 0x40|(2*drive->dn): Active, 0x41|(2*drive->dn): Recovery */
97 pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf);
98 tmp0 = pci_bus_clock_list(speed, bus_clock);
99 d_conf = ((tmp0 & 0xf0) << 4) | (tmp0 & 0xf);
100 pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf);
101
102 tmp1 = 0x00;
103 tmp2 = 0x00;
104 pci_read_config_byte(dev, 0x54, &ultra);
105 tmp1 = ((0x00 << (2*drive->dn)) | (ultra & ~(3 << (2*drive->dn))));
106 ultra_conf = pci_bus_clock_list_ultra(speed, bus_clock);
107 tmp2 = ((ultra_conf << (2*drive->dn)) | (tmp1 & ~(3 << (2*drive->dn))));
108 pci_write_config_byte(dev, 0x54, tmp2);
109 local_irq_restore(flags);
110}
111
112static void aec6260_set_mode(ide_drive_t *drive, const u8 speed)
113{
114 ide_hwif_t *hwif = HWIF(drive);
115 struct pci_dev *dev = to_pci_dev(hwif->dev);
116 struct ide_host *host = pci_get_drvdata(dev);
117 struct chipset_bus_clock_list_entry *bus_clock = host->host_priv;
118 u8 unit = drive->dn & 1;
119 u8 tmp1 = 0, tmp2 = 0;
120 u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
121 unsigned long flags;
122
123 local_irq_save(flags);
124 /* high 4-bits: Active, low 4-bits: Recovery */
125 pci_read_config_byte(dev, 0x40|drive->dn, &drive_conf);
126 drive_conf = pci_bus_clock_list(speed, bus_clock);
127 pci_write_config_byte(dev, 0x40|drive->dn, drive_conf);
128
129 pci_read_config_byte(dev, (0x44|hwif->channel), &ultra);
130 tmp1 = ((0x00 << (4*unit)) | (ultra & ~(7 << (4*unit))));
131 ultra_conf = pci_bus_clock_list_ultra(speed, bus_clock);
132 tmp2 = ((ultra_conf << (4*unit)) | (tmp1 & ~(7 << (4*unit))));
133 pci_write_config_byte(dev, (0x44|hwif->channel), tmp2);
134 local_irq_restore(flags);
135}
136
137static void aec_set_pio_mode(ide_drive_t *drive, const u8 pio)
138{
139 drive->hwif->port_ops->set_dma_mode(drive, pio + XFER_PIO_0);
140}
141
142static unsigned int init_chipset_aec62xx(struct pci_dev *dev)
143{
144 /* These are necessary to get AEC6280 Macintosh cards to work */
145 if ((dev->device == PCI_DEVICE_ID_ARTOP_ATP865) ||
146 (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)) {
147 u8 reg49h = 0, reg4ah = 0;
148 /* Clear reset and test bits. */
149 pci_read_config_byte(dev, 0x49, &reg49h);
150 pci_write_config_byte(dev, 0x49, reg49h & ~0x30);
151 /* Enable chip interrupt output. */
152 pci_read_config_byte(dev, 0x4a, &reg4ah);
153 pci_write_config_byte(dev, 0x4a, reg4ah & ~0x01);
154 /* Enable burst mode. */
155 pci_read_config_byte(dev, 0x4a, &reg4ah);
156 pci_write_config_byte(dev, 0x4a, reg4ah | 0x80);
157 }
158
159 return dev->irq;
160}
161
162static u8 atp86x_cable_detect(ide_hwif_t *hwif)
163{
164 struct pci_dev *dev = to_pci_dev(hwif->dev);
165 u8 ata66 = 0, mask = hwif->channel ? 0x02 : 0x01;
166
167 pci_read_config_byte(dev, 0x49, &ata66);
168
169 return (ata66 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
170}
171
172static const struct ide_port_ops atp850_port_ops = {
173 .set_pio_mode = aec_set_pio_mode,
174 .set_dma_mode = aec6210_set_mode,
175};
176
177static const struct ide_port_ops atp86x_port_ops = {
178 .set_pio_mode = aec_set_pio_mode,
179 .set_dma_mode = aec6260_set_mode,
180 .cable_detect = atp86x_cable_detect,
181};
182
183static const struct ide_port_info aec62xx_chipsets[] __devinitdata = {
184 { /* 0: AEC6210 */
185 .name = DRV_NAME,
186 .init_chipset = init_chipset_aec62xx,
187 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
188 .port_ops = &atp850_port_ops,
189 .host_flags = IDE_HFLAG_SERIALIZE |
190 IDE_HFLAG_NO_ATAPI_DMA |
191 IDE_HFLAG_NO_DSC |
192 IDE_HFLAG_OFF_BOARD,
193 .pio_mask = ATA_PIO4,
194 .mwdma_mask = ATA_MWDMA2,
195 .udma_mask = ATA_UDMA2,
196 },
197 { /* 1: AEC6260 */
198 .name = DRV_NAME,
199 .init_chipset = init_chipset_aec62xx,
200 .port_ops = &atp86x_port_ops,
201 .host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_NO_AUTODMA |
202 IDE_HFLAG_OFF_BOARD,
203 .pio_mask = ATA_PIO4,
204 .mwdma_mask = ATA_MWDMA2,
205 .udma_mask = ATA_UDMA4,
206 },
207 { /* 2: AEC6260R */
208 .name = DRV_NAME,
209 .init_chipset = init_chipset_aec62xx,
210 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
211 .port_ops = &atp86x_port_ops,
212 .host_flags = IDE_HFLAG_NO_ATAPI_DMA |
213 IDE_HFLAG_NON_BOOTABLE,
214 .pio_mask = ATA_PIO4,
215 .mwdma_mask = ATA_MWDMA2,
216 .udma_mask = ATA_UDMA4,
217 },
218 { /* 3: AEC6280 */
219 .name = DRV_NAME,
220 .init_chipset = init_chipset_aec62xx,
221 .port_ops = &atp86x_port_ops,
222 .host_flags = IDE_HFLAG_NO_ATAPI_DMA |
223 IDE_HFLAG_OFF_BOARD,
224 .pio_mask = ATA_PIO4,
225 .mwdma_mask = ATA_MWDMA2,
226 .udma_mask = ATA_UDMA5,
227 },
228 { /* 4: AEC6280R */
229 .name = DRV_NAME,
230 .init_chipset = init_chipset_aec62xx,
231 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
232 .port_ops = &atp86x_port_ops,
233 .host_flags = IDE_HFLAG_NO_ATAPI_DMA |
234 IDE_HFLAG_OFF_BOARD,
235 .pio_mask = ATA_PIO4,
236 .mwdma_mask = ATA_MWDMA2,
237 .udma_mask = ATA_UDMA5,
238 }
239};
240
241/**
242 * aec62xx_init_one - called when a AEC is found
243 * @dev: the aec62xx device
244 * @id: the matching pci id
245 *
246 * Called when the PCI registration layer (or the IDE initialization)
247 * finds a device matching our IDE device tables.
248 *
249 * NOTE: since we're going to modify the 'name' field for AEC-6[26]80[R]
250 * chips, pass a local copy of 'struct ide_port_info' down the call chain.
251 */
252
253static int __devinit aec62xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
254{
255 const struct chipset_bus_clock_list_entry *bus_clock;
256 struct ide_port_info d;
257 u8 idx = id->driver_data;
258 int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
259 int err;
260
261 if (bus_speed <= 33)
262 bus_clock = aec6xxx_33_base;
263 else
264 bus_clock = aec6xxx_34_base;
265
266 err = pci_enable_device(dev);
267 if (err)
268 return err;
269
270 d = aec62xx_chipsets[idx];
271
272 if (idx == 3 || idx == 4) {
273 unsigned long dma_base = pci_resource_start(dev, 4);
274
275 if (inb(dma_base + 2) & 0x10) {
276 printk(KERN_INFO DRV_NAME " %s: AEC6880%s card detected"
277 "\n", pci_name(dev), (idx == 4) ? "R" : "");
278 d.udma_mask = ATA_UDMA6;
279 }
280 }
281
282 err = ide_pci_init_one(dev, &d, (void *)bus_clock);
283 if (err)
284 pci_disable_device(dev);
285
286 return err;
287}
288
289static void __devexit aec62xx_remove(struct pci_dev *dev)
290{
291 ide_pci_remove(dev);
292 pci_disable_device(dev);
293}
294
295static const struct pci_device_id aec62xx_pci_tbl[] = {
296 { PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF), 0 },
297 { PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP860), 1 },
298 { PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R), 2 },
299 { PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP865), 3 },
300 { PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R), 4 },
301 { 0, },
302};
303MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl);
304
305static struct pci_driver aec62xx_pci_driver = {
306 .name = "AEC62xx_IDE",
307 .id_table = aec62xx_pci_tbl,
308 .probe = aec62xx_init_one,
309 .remove = __devexit_p(aec62xx_remove),
310 .suspend = ide_pci_suspend,
311 .resume = ide_pci_resume,
312};
313
314static int __init aec62xx_ide_init(void)
315{
316 return ide_pci_register_driver(&aec62xx_pci_driver);
317}
318
319static void __exit aec62xx_ide_exit(void)
320{
321 pci_unregister_driver(&aec62xx_pci_driver);
322}
323
324module_init(aec62xx_ide_init);
325module_exit(aec62xx_ide_exit);
326
327MODULE_AUTHOR("Andre Hedrick");
328MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE");
329MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/alim15x3.c b/drivers/ide/pci/alim15x3.c
deleted file mode 100644
index daf9dce39e52..000000000000
--- a/drivers/ide/pci/alim15x3.c
+++ /dev/null
@@ -1,602 +0,0 @@
1/*
2 * Copyright (C) 1998-2000 Michel Aubry, Maintainer
3 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer
4 * Copyright (C) 1999-2000 CJ, cjtsai@ali.com.tw, Maintainer
5 *
6 * Copyright (C) 1998-2000 Andre Hedrick (andre@linux-ide.org)
7 * May be copied or modified under the terms of the GNU General Public License
8 * Copyright (C) 2002 Alan Cox <alan@redhat.com>
9 * ALi (now ULi M5228) support by Clear Zhang <Clear.Zhang@ali.com.tw>
10 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
11 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
12 *
13 * (U)DMA capable version of ali 1533/1543(C), 1535(D)
14 *
15 **********************************************************************
16 * 9/7/99 --Parts from the above author are included and need to be
17 * converted into standard interface, once I finish the thought.
18 *
19 * Recent changes
20 * Don't use LBA48 mode on ALi <= 0xC4
21 * Don't poke 0x79 with a non ALi northbridge
22 * Don't flip undefined bits on newer chipsets (fix Fujitsu laptop hang)
23 * Allow UDMA6 on revisions > 0xC4
24 *
25 * Documentation
26 * Chipset documentation available under NDA only
27 *
28 */
29
30#include <linux/module.h>
31#include <linux/types.h>
32#include <linux/kernel.h>
33#include <linux/pci.h>
34#include <linux/ide.h>
35#include <linux/init.h>
36#include <linux/dmi.h>
37
38#include <asm/io.h>
39
40#define DRV_NAME "alim15x3"
41
42/*
43 * Allow UDMA on M1543C-E chipset for WDC disks that ignore CRC checking
44 * (this is DANGEROUS and could result in data corruption).
45 */
46static int wdc_udma;
47
48module_param(wdc_udma, bool, 0);
49MODULE_PARM_DESC(wdc_udma,
50 "allow UDMA on M1543C-E chipset for WDC disks (DANGEROUS)");
51
52/*
53 * ALi devices are not plug in. Otherwise these static values would
54 * need to go. They ought to go away anyway
55 */
56
57static u8 m5229_revision;
58static u8 chip_is_1543c_e;
59static struct pci_dev *isa_dev;
60
61/**
62 * ali_set_pio_mode - set host controller for PIO mode
63 * @drive: drive
64 * @pio: PIO mode number
65 *
66 * Program the controller for the given PIO mode.
67 */
68
69static void ali_set_pio_mode(ide_drive_t *drive, const u8 pio)
70{
71 ide_hwif_t *hwif = HWIF(drive);
72 struct pci_dev *dev = to_pci_dev(hwif->dev);
73 struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
74 int s_time = t->setup, a_time = t->active, c_time = t->cycle;
75 u8 s_clc, a_clc, r_clc;
76 unsigned long flags;
77 int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
78 int port = hwif->channel ? 0x5c : 0x58;
79 int portFIFO = hwif->channel ? 0x55 : 0x54;
80 u8 cd_dma_fifo = 0, unit = drive->dn & 1;
81
82 if ((s_clc = (s_time * bus_speed + 999) / 1000) >= 8)
83 s_clc = 0;
84 if ((a_clc = (a_time * bus_speed + 999) / 1000) >= 8)
85 a_clc = 0;
86
87 if (!(r_clc = (c_time * bus_speed + 999) / 1000 - a_clc - s_clc)) {
88 r_clc = 1;
89 } else {
90 if (r_clc >= 16)
91 r_clc = 0;
92 }
93 local_irq_save(flags);
94
95 /*
96 * PIO mode => ATA FIFO on, ATAPI FIFO off
97 */
98 pci_read_config_byte(dev, portFIFO, &cd_dma_fifo);
99 if (drive->media==ide_disk) {
100 if (unit) {
101 pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0x0F) | 0x50);
102 } else {
103 pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0xF0) | 0x05);
104 }
105 } else {
106 if (unit) {
107 pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0x0F);
108 } else {
109 pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0xF0);
110 }
111 }
112
113 pci_write_config_byte(dev, port, s_clc);
114 pci_write_config_byte(dev, port + unit + 2, (a_clc << 4) | r_clc);
115 local_irq_restore(flags);
116}
117
118/**
119 * ali_udma_filter - compute UDMA mask
120 * @drive: IDE device
121 *
122 * Return available UDMA modes.
123 *
124 * The actual rules for the ALi are:
125 * No UDMA on revisions <= 0x20
126 * Disk only for revisions < 0xC2
127 * Not WDC drives on M1543C-E (?)
128 */
129
130static u8 ali_udma_filter(ide_drive_t *drive)
131{
132 if (m5229_revision > 0x20 && m5229_revision < 0xC2) {
133 if (drive->media != ide_disk)
134 return 0;
135 if (wdc_udma == 0 && chip_is_1543c_e &&
136 strstr((char *)&drive->id[ATA_ID_PROD], "WDC "))
137 return 0;
138 }
139
140 return drive->hwif->ultra_mask;
141}
142
143/**
144 * ali_set_dma_mode - set host controller for DMA mode
145 * @drive: drive
146 * @speed: DMA mode
147 *
148 * Configure the hardware for the desired IDE transfer mode.
149 */
150
151static void ali_set_dma_mode(ide_drive_t *drive, const u8 speed)
152{
153 ide_hwif_t *hwif = HWIF(drive);
154 struct pci_dev *dev = to_pci_dev(hwif->dev);
155 u8 speed1 = speed;
156 u8 unit = drive->dn & 1;
157 u8 tmpbyte = 0x00;
158 int m5229_udma = (hwif->channel) ? 0x57 : 0x56;
159
160 if (speed == XFER_UDMA_6)
161 speed1 = 0x47;
162
163 if (speed < XFER_UDMA_0) {
164 u8 ultra_enable = (unit) ? 0x7f : 0xf7;
165 /*
166 * clear "ultra enable" bit
167 */
168 pci_read_config_byte(dev, m5229_udma, &tmpbyte);
169 tmpbyte &= ultra_enable;
170 pci_write_config_byte(dev, m5229_udma, tmpbyte);
171
172 /*
173 * FIXME: Oh, my... DMA timings are never set.
174 */
175 } else {
176 pci_read_config_byte(dev, m5229_udma, &tmpbyte);
177 tmpbyte &= (0x0f << ((1-unit) << 2));
178 /*
179 * enable ultra dma and set timing
180 */
181 tmpbyte |= ((0x08 | ((4-speed1)&0x07)) << (unit << 2));
182 pci_write_config_byte(dev, m5229_udma, tmpbyte);
183 if (speed >= XFER_UDMA_3) {
184 pci_read_config_byte(dev, 0x4b, &tmpbyte);
185 tmpbyte |= 1;
186 pci_write_config_byte(dev, 0x4b, tmpbyte);
187 }
188 }
189}
190
191/**
192 * ali15x3_dma_setup - begin a DMA phase
193 * @drive: target device
194 *
195 * Returns 1 if the DMA cannot be performed, zero on success.
196 */
197
198static int ali15x3_dma_setup(ide_drive_t *drive)
199{
200 if (m5229_revision < 0xC2 && drive->media != ide_disk) {
201 if (rq_data_dir(drive->hwif->hwgroup->rq))
202 return 1; /* try PIO instead of DMA */
203 }
204 return ide_dma_setup(drive);
205}
206
207/**
208 * init_chipset_ali15x3 - Initialise an ALi IDE controller
209 * @dev: PCI device
210 *
211 * This function initializes the ALI IDE controller and where
212 * appropriate also sets up the 1533 southbridge.
213 */
214
215static unsigned int init_chipset_ali15x3(struct pci_dev *dev)
216{
217 unsigned long flags;
218 u8 tmpbyte;
219 struct pci_dev *north = pci_get_slot(dev->bus, PCI_DEVFN(0,0));
220
221 m5229_revision = dev->revision;
222
223 isa_dev = pci_get_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL);
224
225 local_irq_save(flags);
226
227 if (m5229_revision < 0xC2) {
228 /*
229 * revision 0x20 (1543-E, 1543-F)
230 * revision 0xC0, 0xC1 (1543C-C, 1543C-D, 1543C-E)
231 * clear CD-ROM DMA write bit, m5229, 0x4b, bit 7
232 */
233 pci_read_config_byte(dev, 0x4b, &tmpbyte);
234 /*
235 * clear bit 7
236 */
237 pci_write_config_byte(dev, 0x4b, tmpbyte & 0x7F);
238 /*
239 * check m1533, 0x5e, bit 1~4 == 1001 => & 00011110 = 00010010
240 */
241 if (m5229_revision >= 0x20 && isa_dev) {
242 pci_read_config_byte(isa_dev, 0x5e, &tmpbyte);
243 chip_is_1543c_e = ((tmpbyte & 0x1e) == 0x12) ? 1: 0;
244 }
245 goto out;
246 }
247
248 /*
249 * 1543C-B?, 1535, 1535D, 1553
250 * Note 1: not all "motherboard" support this detection
251 * Note 2: if no udma 66 device, the detection may "error".
252 * but in this case, we will not set the device to
253 * ultra 66, the detection result is not important
254 */
255
256 /*
257 * enable "Cable Detection", m5229, 0x4b, bit3
258 */
259 pci_read_config_byte(dev, 0x4b, &tmpbyte);
260 pci_write_config_byte(dev, 0x4b, tmpbyte | 0x08);
261
262 /*
263 * We should only tune the 1533 enable if we are using an ALi
264 * North bridge. We might have no north found on some zany
265 * box without a device at 0:0.0. The ALi bridge will be at
266 * 0:0.0 so if we didn't find one we know what is cooking.
267 */
268 if (north && north->vendor != PCI_VENDOR_ID_AL)
269 goto out;
270
271 if (m5229_revision < 0xC5 && isa_dev)
272 {
273 /*
274 * set south-bridge's enable bit, m1533, 0x79
275 */
276
277 pci_read_config_byte(isa_dev, 0x79, &tmpbyte);
278 if (m5229_revision == 0xC2) {
279 /*
280 * 1543C-B0 (m1533, 0x79, bit 2)
281 */
282 pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x04);
283 } else if (m5229_revision >= 0xC3) {
284 /*
285 * 1553/1535 (m1533, 0x79, bit 1)
286 */
287 pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x02);
288 }
289 }
290
291out:
292 /*
293 * CD_ROM DMA on (m5229, 0x53, bit0)
294 * Enable this bit even if we want to use PIO.
295 * PIO FIFO off (m5229, 0x53, bit1)
296 * The hardware will use 0x54h and 0x55h to control PIO FIFO.
297 * (Not on later devices it seems)
298 *
299 * 0x53 changes meaning on later revs - we must no touch
300 * bit 1 on them. Need to check if 0x20 is the right break.
301 */
302 if (m5229_revision >= 0x20) {
303 pci_read_config_byte(dev, 0x53, &tmpbyte);
304
305 if (m5229_revision <= 0x20)
306 tmpbyte = (tmpbyte & (~0x02)) | 0x01;
307 else if (m5229_revision == 0xc7 || m5229_revision == 0xc8)
308 tmpbyte |= 0x03;
309 else
310 tmpbyte |= 0x01;
311
312 pci_write_config_byte(dev, 0x53, tmpbyte);
313 }
314 pci_dev_put(north);
315 pci_dev_put(isa_dev);
316 local_irq_restore(flags);
317 return 0;
318}
319
320/*
321 * Cable special cases
322 */
323
324static const struct dmi_system_id cable_dmi_table[] = {
325 {
326 .ident = "HP Pavilion N5430",
327 .matches = {
328 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
329 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
330 },
331 },
332 {
333 .ident = "Toshiba Satellite S1800-814",
334 .matches = {
335 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
336 DMI_MATCH(DMI_PRODUCT_NAME, "S1800-814"),
337 },
338 },
339 { }
340};
341
342static int ali_cable_override(struct pci_dev *pdev)
343{
344 /* Fujitsu P2000 */
345 if (pdev->subsystem_vendor == 0x10CF &&
346 pdev->subsystem_device == 0x10AF)
347 return 1;
348
349 /* Mitac 8317 (Winbook-A) and relatives */
350 if (pdev->subsystem_vendor == 0x1071 &&
351 pdev->subsystem_device == 0x8317)
352 return 1;
353
354 /* Systems by DMI */
355 if (dmi_check_system(cable_dmi_table))
356 return 1;
357
358 return 0;
359}
360
361/**
362 * ali_cable_detect - cable detection
363 * @hwif: IDE interface
364 *
365 * This checks if the controller and the cable are capable
366 * of UDMA66 transfers. It doesn't check the drives.
367 * But see note 2 below!
368 *
369 * FIXME: frobs bits that are not defined on newer ALi devicea
370 */
371
372static u8 ali_cable_detect(ide_hwif_t *hwif)
373{
374 struct pci_dev *dev = to_pci_dev(hwif->dev);
375 unsigned long flags;
376 u8 cbl = ATA_CBL_PATA40, tmpbyte;
377
378 local_irq_save(flags);
379
380 if (m5229_revision >= 0xC2) {
381 /*
382 * m5229 80-pin cable detection (from Host View)
383 *
384 * 0x4a bit0 is 0 => primary channel has 80-pin
385 * 0x4a bit1 is 0 => secondary channel has 80-pin
386 *
387 * Certain laptops use short but suitable cables
388 * and don't implement the detect logic.
389 */
390 if (ali_cable_override(dev))
391 cbl = ATA_CBL_PATA40_SHORT;
392 else {
393 pci_read_config_byte(dev, 0x4a, &tmpbyte);
394 if ((tmpbyte & (1 << hwif->channel)) == 0)
395 cbl = ATA_CBL_PATA80;
396 }
397 }
398
399 local_irq_restore(flags);
400
401 return cbl;
402}
403
404#if !defined(CONFIG_SPARC64) && !defined(CONFIG_PPC)
405/**
406 * init_hwif_ali15x3 - Initialize the ALI IDE x86 stuff
407 * @hwif: interface to configure
408 *
409 * Obtain the IRQ tables for an ALi based IDE solution on the PC
410 * class platforms. This part of the code isn't applicable to the
411 * Sparc and PowerPC systems.
412 */
413
414static void __devinit init_hwif_ali15x3 (ide_hwif_t *hwif)
415{
416 struct pci_dev *dev = to_pci_dev(hwif->dev);
417 u8 ideic, inmir;
418 s8 irq_routing_table[] = { -1, 9, 3, 10, 4, 5, 7, 6,
419 1, 11, 0, 12, 0, 14, 0, 15 };
420 int irq = -1;
421
422 if (dev->device == PCI_DEVICE_ID_AL_M5229)
423 hwif->irq = hwif->channel ? 15 : 14;
424
425 if (isa_dev) {
426 /*
427 * read IDE interface control
428 */
429 pci_read_config_byte(isa_dev, 0x58, &ideic);
430
431 /* bit0, bit1 */
432 ideic = ideic & 0x03;
433
434 /* get IRQ for IDE Controller */
435 if ((hwif->channel && ideic == 0x03) ||
436 (!hwif->channel && !ideic)) {
437 /*
438 * get SIRQ1 routing table
439 */
440 pci_read_config_byte(isa_dev, 0x44, &inmir);
441 inmir = inmir & 0x0f;
442 irq = irq_routing_table[inmir];
443 } else if (hwif->channel && !(ideic & 0x01)) {
444 /*
445 * get SIRQ2 routing table
446 */
447 pci_read_config_byte(isa_dev, 0x75, &inmir);
448 inmir = inmir & 0x0f;
449 irq = irq_routing_table[inmir];
450 }
451 if(irq >= 0)
452 hwif->irq = irq;
453 }
454}
455#else
456#define init_hwif_ali15x3 NULL
457#endif /* !defined(CONFIG_SPARC64) && !defined(CONFIG_PPC) */
458
459/**
460 * init_dma_ali15x3 - set up DMA on ALi15x3
461 * @hwif: IDE interface
462 * @d: IDE port info
463 *
464 * Set up the DMA functionality on the ALi 15x3.
465 */
466
467static int __devinit init_dma_ali15x3(ide_hwif_t *hwif,
468 const struct ide_port_info *d)
469{
470 struct pci_dev *dev = to_pci_dev(hwif->dev);
471 unsigned long base = ide_pci_dma_base(hwif, d);
472
473 if (base == 0)
474 return -1;
475
476 hwif->dma_base = base;
477
478 if (ide_pci_check_simplex(hwif, d) < 0)
479 return -1;
480
481 if (ide_pci_set_master(dev, d->name) < 0)
482 return -1;
483
484 if (!hwif->channel)
485 outb(inb(base + 2) & 0x60, base + 2);
486
487 printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n",
488 hwif->name, base, base + 7);
489
490 if (ide_allocate_dma_engine(hwif))
491 return -1;
492
493 hwif->dma_ops = &sff_dma_ops;
494
495 return 0;
496}
497
498static const struct ide_port_ops ali_port_ops = {
499 .set_pio_mode = ali_set_pio_mode,
500 .set_dma_mode = ali_set_dma_mode,
501 .udma_filter = ali_udma_filter,
502 .cable_detect = ali_cable_detect,
503};
504
505static const struct ide_dma_ops ali_dma_ops = {
506 .dma_host_set = ide_dma_host_set,
507 .dma_setup = ali15x3_dma_setup,
508 .dma_exec_cmd = ide_dma_exec_cmd,
509 .dma_start = ide_dma_start,
510 .dma_end = ide_dma_end,
511 .dma_test_irq = ide_dma_test_irq,
512 .dma_lost_irq = ide_dma_lost_irq,
513 .dma_timeout = ide_dma_timeout,
514};
515
516static const struct ide_port_info ali15x3_chipset __devinitdata = {
517 .name = DRV_NAME,
518 .init_chipset = init_chipset_ali15x3,
519 .init_hwif = init_hwif_ali15x3,
520 .init_dma = init_dma_ali15x3,
521 .port_ops = &ali_port_ops,
522 .pio_mask = ATA_PIO5,
523 .swdma_mask = ATA_SWDMA2,
524 .mwdma_mask = ATA_MWDMA2,
525};
526
527/**
528 * alim15x3_init_one - set up an ALi15x3 IDE controller
529 * @dev: PCI device to set up
530 *
531 * Perform the actual set up for an ALi15x3 that has been found by the
532 * hot plug layer.
533 */
534
535static int __devinit alim15x3_init_one(struct pci_dev *dev, const struct pci_device_id *id)
536{
537 struct ide_port_info d = ali15x3_chipset;
538 u8 rev = dev->revision, idx = id->driver_data;
539
540 /* don't use LBA48 DMA on ALi devices before rev 0xC5 */
541 if (rev <= 0xC4)
542 d.host_flags |= IDE_HFLAG_NO_LBA48_DMA;
543
544 if (rev >= 0x20) {
545 if (rev == 0x20)
546 d.host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
547
548 if (rev < 0xC2)
549 d.udma_mask = ATA_UDMA2;
550 else if (rev == 0xC2 || rev == 0xC3)
551 d.udma_mask = ATA_UDMA4;
552 else if (rev == 0xC4)
553 d.udma_mask = ATA_UDMA5;
554 else
555 d.udma_mask = ATA_UDMA6;
556
557 d.dma_ops = &ali_dma_ops;
558 } else {
559 d.host_flags |= IDE_HFLAG_NO_DMA;
560
561 d.mwdma_mask = d.swdma_mask = 0;
562 }
563
564 if (idx == 0)
565 d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX;
566
567 return ide_pci_init_one(dev, &d, NULL);
568}
569
570
571static const struct pci_device_id alim15x3_pci_tbl[] = {
572 { PCI_VDEVICE(AL, PCI_DEVICE_ID_AL_M5229), 0 },
573 { PCI_VDEVICE(AL, PCI_DEVICE_ID_AL_M5228), 1 },
574 { 0, },
575};
576MODULE_DEVICE_TABLE(pci, alim15x3_pci_tbl);
577
578static struct pci_driver alim15x3_pci_driver = {
579 .name = "ALI15x3_IDE",
580 .id_table = alim15x3_pci_tbl,
581 .probe = alim15x3_init_one,
582 .remove = ide_pci_remove,
583 .suspend = ide_pci_suspend,
584 .resume = ide_pci_resume,
585};
586
587static int __init ali15x3_ide_init(void)
588{
589 return ide_pci_register_driver(&alim15x3_pci_driver);
590}
591
592static void __exit ali15x3_ide_exit(void)
593{
594 return pci_unregister_driver(&alim15x3_pci_driver);
595}
596
597module_init(ali15x3_ide_init);
598module_exit(ali15x3_ide_exit);
599
600MODULE_AUTHOR("Michael Aubry, Andrzej Krzysztofowicz, CJ, Andre Hedrick, Alan Cox");
601MODULE_DESCRIPTION("PCI driver module for ALi 15x3 IDE");
602MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/amd74xx.c b/drivers/ide/pci/amd74xx.c
deleted file mode 100644
index 81ec73134eda..000000000000
--- a/drivers/ide/pci/amd74xx.c
+++ /dev/null
@@ -1,346 +0,0 @@
1/*
2 * AMD 755/756/766/8111 and nVidia nForce/2/2s/3/3s/CK804/MCP04
3 * IDE driver for Linux.
4 *
5 * Copyright (c) 2000-2002 Vojtech Pavlik
6 * Copyright (c) 2007 Bartlomiej Zolnierkiewicz
7 *
8 * Based on the work of:
9 * Andre Hedrick
10 */
11
12/*
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License version 2 as published by
15 * the Free Software Foundation.
16 */
17
18#include <linux/module.h>
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/ide.h>
23
24#define DRV_NAME "amd74xx"
25
26enum {
27 AMD_IDE_CONFIG = 0x41,
28 AMD_CABLE_DETECT = 0x42,
29 AMD_DRIVE_TIMING = 0x48,
30 AMD_8BIT_TIMING = 0x4e,
31 AMD_ADDRESS_SETUP = 0x4c,
32 AMD_UDMA_TIMING = 0x50,
33};
34
35static unsigned int amd_80w;
36static unsigned int amd_clock;
37
38static char *amd_dma[] = { "16", "25", "33", "44", "66", "100", "133" };
39static unsigned char amd_cyc2udma[] = { 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 };
40
41static inline u8 amd_offset(struct pci_dev *dev)
42{
43 return (dev->vendor == PCI_VENDOR_ID_NVIDIA) ? 0x10 : 0;
44}
45
46/*
47 * amd_set_speed() writes timing values to the chipset registers
48 */
49
50static void amd_set_speed(struct pci_dev *dev, u8 dn, u8 udma_mask,
51 struct ide_timing *timing)
52{
53 u8 t = 0, offset = amd_offset(dev);
54
55 pci_read_config_byte(dev, AMD_ADDRESS_SETUP + offset, &t);
56 t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
57 pci_write_config_byte(dev, AMD_ADDRESS_SETUP + offset, t);
58
59 pci_write_config_byte(dev, AMD_8BIT_TIMING + offset + (1 - (dn >> 1)),
60 ((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1));
61
62 pci_write_config_byte(dev, AMD_DRIVE_TIMING + offset + (3 - dn),
63 ((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing->recover, 1, 16) - 1));
64
65 switch (udma_mask) {
66 case ATA_UDMA2: t = timing->udma ? (0xc0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break;
67 case ATA_UDMA4: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 2, 10)]) : 0x03; break;
68 case ATA_UDMA5: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 1, 10)]) : 0x03; break;
69 case ATA_UDMA6: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 1, 15)]) : 0x03; break;
70 default: return;
71 }
72
73 pci_write_config_byte(dev, AMD_UDMA_TIMING + offset + (3 - dn), t);
74}
75
76/*
77 * amd_set_drive() computes timing values and configures the chipset
78 * to a desired transfer mode. It also can be called by upper layers.
79 */
80
81static void amd_set_drive(ide_drive_t *drive, const u8 speed)
82{
83 ide_hwif_t *hwif = drive->hwif;
84 struct pci_dev *dev = to_pci_dev(hwif->dev);
85 ide_drive_t *peer = hwif->drives + (~drive->dn & 1);
86 struct ide_timing t, p;
87 int T, UT;
88 u8 udma_mask = hwif->ultra_mask;
89
90 T = 1000000000 / amd_clock;
91 UT = (udma_mask == ATA_UDMA2) ? T : (T / 2);
92
93 ide_timing_compute(drive, speed, &t, T, UT);
94
95 if (peer->dev_flags & IDE_DFLAG_PRESENT) {
96 ide_timing_compute(peer, peer->current_speed, &p, T, UT);
97 ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
98 }
99
100 if (speed == XFER_UDMA_5 && amd_clock <= 33333) t.udma = 1;
101 if (speed == XFER_UDMA_6 && amd_clock <= 33333) t.udma = 15;
102
103 amd_set_speed(dev, drive->dn, udma_mask, &t);
104}
105
106/*
107 * amd_set_pio_mode() is a callback from upper layers for PIO-only tuning.
108 */
109
110static void amd_set_pio_mode(ide_drive_t *drive, const u8 pio)
111{
112 amd_set_drive(drive, XFER_PIO_0 + pio);
113}
114
115static void amd7409_cable_detect(struct pci_dev *dev)
116{
117 /* no host side cable detection */
118 amd_80w = 0x03;
119}
120
121static void amd7411_cable_detect(struct pci_dev *dev)
122{
123 int i;
124 u32 u = 0;
125 u8 t = 0, offset = amd_offset(dev);
126
127 pci_read_config_byte(dev, AMD_CABLE_DETECT + offset, &t);
128 pci_read_config_dword(dev, AMD_UDMA_TIMING + offset, &u);
129 amd_80w = ((t & 0x3) ? 1 : 0) | ((t & 0xc) ? 2 : 0);
130 for (i = 24; i >= 0; i -= 8)
131 if (((u >> i) & 4) && !(amd_80w & (1 << (1 - (i >> 4))))) {
132 printk(KERN_WARNING DRV_NAME " %s: BIOS didn't set "
133 "cable bits correctly. Enabling workaround.\n",
134 pci_name(dev));
135 amd_80w |= (1 << (1 - (i >> 4)));
136 }
137}
138
139/*
140 * The initialization callback. Initialize drive independent registers.
141 */
142
143static unsigned int init_chipset_amd74xx(struct pci_dev *dev)
144{
145 u8 t = 0, offset = amd_offset(dev);
146
147/*
148 * Check 80-wire cable presence.
149 */
150
151 if (dev->vendor == PCI_VENDOR_ID_AMD &&
152 dev->device == PCI_DEVICE_ID_AMD_COBRA_7401)
153 ; /* no UDMA > 2 */
154 else if (dev->vendor == PCI_VENDOR_ID_AMD &&
155 dev->device == PCI_DEVICE_ID_AMD_VIPER_7409)
156 amd7409_cable_detect(dev);
157 else
158 amd7411_cable_detect(dev);
159
160/*
161 * Take care of prefetch & postwrite.
162 */
163
164 pci_read_config_byte(dev, AMD_IDE_CONFIG + offset, &t);
165 /*
166 * Check for broken FIFO support.
167 */
168 if (dev->vendor == PCI_VENDOR_ID_AMD &&
169 dev->vendor == PCI_DEVICE_ID_AMD_VIPER_7411)
170 t &= 0x0f;
171 else
172 t |= 0xf0;
173 pci_write_config_byte(dev, AMD_IDE_CONFIG + offset, t);
174
175 return dev->irq;
176}
177
178static u8 amd_cable_detect(ide_hwif_t *hwif)
179{
180 if ((amd_80w >> hwif->channel) & 1)
181 return ATA_CBL_PATA80;
182 else
183 return ATA_CBL_PATA40;
184}
185
186static void __devinit init_hwif_amd74xx(ide_hwif_t *hwif)
187{
188 struct pci_dev *dev = to_pci_dev(hwif->dev);
189
190 if (hwif->irq == 0) /* 0 is bogus but will do for now */
191 hwif->irq = pci_get_legacy_ide_irq(dev, hwif->channel);
192}
193
194static const struct ide_port_ops amd_port_ops = {
195 .set_pio_mode = amd_set_pio_mode,
196 .set_dma_mode = amd_set_drive,
197 .cable_detect = amd_cable_detect,
198};
199
200#define IDE_HFLAGS_AMD \
201 (IDE_HFLAG_PIO_NO_BLACKLIST | \
202 IDE_HFLAG_POST_SET_MODE | \
203 IDE_HFLAG_IO_32BIT | \
204 IDE_HFLAG_UNMASK_IRQS)
205
206#define DECLARE_AMD_DEV(swdma, udma) \
207 { \
208 .name = DRV_NAME, \
209 .init_chipset = init_chipset_amd74xx, \
210 .init_hwif = init_hwif_amd74xx, \
211 .enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, \
212 .port_ops = &amd_port_ops, \
213 .host_flags = IDE_HFLAGS_AMD, \
214 .pio_mask = ATA_PIO5, \
215 .swdma_mask = swdma, \
216 .mwdma_mask = ATA_MWDMA2, \
217 .udma_mask = udma, \
218 }
219
220#define DECLARE_NV_DEV(udma) \
221 { \
222 .name = DRV_NAME, \
223 .init_chipset = init_chipset_amd74xx, \
224 .init_hwif = init_hwif_amd74xx, \
225 .enablebits = {{0x50,0x02,0x02}, {0x50,0x01,0x01}}, \
226 .port_ops = &amd_port_ops, \
227 .host_flags = IDE_HFLAGS_AMD, \
228 .pio_mask = ATA_PIO5, \
229 .swdma_mask = ATA_SWDMA2, \
230 .mwdma_mask = ATA_MWDMA2, \
231 .udma_mask = udma, \
232 }
233
234static const struct ide_port_info amd74xx_chipsets[] __devinitdata = {
235 /* 0: AMD7401 */ DECLARE_AMD_DEV(0x00, ATA_UDMA2),
236 /* 1: AMD7409 */ DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA4),
237 /* 2: AMD7411/7441 */ DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA5),
238 /* 3: AMD8111 */ DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA6),
239
240 /* 4: NFORCE */ DECLARE_NV_DEV(ATA_UDMA5),
241 /* 5: >= NFORCE2 */ DECLARE_NV_DEV(ATA_UDMA6),
242
243 /* 6: AMD5536 */ DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA5),
244};
245
246static int __devinit amd74xx_probe(struct pci_dev *dev, const struct pci_device_id *id)
247{
248 struct ide_port_info d;
249 u8 idx = id->driver_data;
250
251 d = amd74xx_chipsets[idx];
252
253 /*
254 * Check for bad SWDMA and incorrectly wired Serenade mainboards.
255 */
256 if (idx == 1) {
257 if (dev->revision <= 7)
258 d.swdma_mask = 0;
259 d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX;
260 } else if (idx == 3) {
261 if (dev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
262 dev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
263 d.udma_mask = ATA_UDMA5;
264 }
265
266 printk(KERN_INFO "%s %s: UDMA%s controller\n",
267 d.name, pci_name(dev), amd_dma[fls(d.udma_mask) - 1]);
268
269 /*
270 * Determine the system bus clock.
271 */
272 amd_clock = (ide_pci_clk ? ide_pci_clk : 33) * 1000;
273
274 switch (amd_clock) {
275 case 33000: amd_clock = 33333; break;
276 case 37000: amd_clock = 37500; break;
277 case 41000: amd_clock = 41666; break;
278 }
279
280 if (amd_clock < 20000 || amd_clock > 50000) {
281 printk(KERN_WARNING "%s: User given PCI clock speed impossible"
282 " (%d), using 33 MHz instead.\n",
283 d.name, amd_clock);
284 amd_clock = 33333;
285 }
286
287 return ide_pci_init_one(dev, &d, NULL);
288}
289
290static const struct pci_device_id amd74xx_pci_tbl[] = {
291 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 },
292 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 },
293 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 2 },
294 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 2 },
295 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 3 },
296 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 4 },
297 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 5 },
298 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 5 },
299#ifdef CONFIG_BLK_DEV_IDE_SATA
300 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), 5 },
301#endif
302 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 5 },
303 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 5 },
304#ifdef CONFIG_BLK_DEV_IDE_SATA
305 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), 5 },
306 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), 5 },
307#endif
308 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 5 },
309 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 5 },
310 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 5 },
311 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 5 },
312 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 5 },
313 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 5 },
314 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 5 },
315 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE), 5 },
316 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE), 5 },
317 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 6 },
318 { 0, },
319};
320MODULE_DEVICE_TABLE(pci, amd74xx_pci_tbl);
321
322static struct pci_driver amd74xx_pci_driver = {
323 .name = "AMD_IDE",
324 .id_table = amd74xx_pci_tbl,
325 .probe = amd74xx_probe,
326 .remove = ide_pci_remove,
327 .suspend = ide_pci_suspend,
328 .resume = ide_pci_resume,
329};
330
331static int __init amd74xx_ide_init(void)
332{
333 return ide_pci_register_driver(&amd74xx_pci_driver);
334}
335
336static void __exit amd74xx_ide_exit(void)
337{
338 pci_unregister_driver(&amd74xx_pci_driver);
339}
340
341module_init(amd74xx_ide_init);
342module_exit(amd74xx_ide_exit);
343
344MODULE_AUTHOR("Vojtech Pavlik");
345MODULE_DESCRIPTION("AMD PCI IDE driver");
346MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/atiixp.c b/drivers/ide/pci/atiixp.c
deleted file mode 100644
index b2735d28f5cc..000000000000
--- a/drivers/ide/pci/atiixp.c
+++ /dev/null
@@ -1,209 +0,0 @@
1/*
2 * Copyright (C) 2003 ATI Inc. <hyu@ati.com>
3 * Copyright (C) 2004,2007 Bartlomiej Zolnierkiewicz
4 */
5
6#include <linux/types.h>
7#include <linux/module.h>
8#include <linux/kernel.h>
9#include <linux/pci.h>
10#include <linux/ide.h>
11#include <linux/init.h>
12
13#define DRV_NAME "atiixp"
14
15#define ATIIXP_IDE_PIO_TIMING 0x40
16#define ATIIXP_IDE_MDMA_TIMING 0x44
17#define ATIIXP_IDE_PIO_CONTROL 0x48
18#define ATIIXP_IDE_PIO_MODE 0x4a
19#define ATIIXP_IDE_UDMA_CONTROL 0x54
20#define ATIIXP_IDE_UDMA_MODE 0x56
21
22typedef struct {
23 u8 command_width;
24 u8 recover_width;
25} atiixp_ide_timing;
26
27static atiixp_ide_timing pio_timing[] = {
28 { 0x05, 0x0d },
29 { 0x04, 0x07 },
30 { 0x03, 0x04 },
31 { 0x02, 0x02 },
32 { 0x02, 0x00 },
33};
34
35static atiixp_ide_timing mdma_timing[] = {
36 { 0x07, 0x07 },
37 { 0x02, 0x01 },
38 { 0x02, 0x00 },
39};
40
41static DEFINE_SPINLOCK(atiixp_lock);
42
43/**
44 * atiixp_set_pio_mode - set host controller for PIO mode
45 * @drive: drive
46 * @pio: PIO mode number
47 *
48 * Set the interface PIO mode.
49 */
50
51static void atiixp_set_pio_mode(ide_drive_t *drive, const u8 pio)
52{
53 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
54 unsigned long flags;
55 int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8;
56 u32 pio_timing_data;
57 u16 pio_mode_data;
58
59 spin_lock_irqsave(&atiixp_lock, flags);
60
61 pci_read_config_word(dev, ATIIXP_IDE_PIO_MODE, &pio_mode_data);
62 pio_mode_data &= ~(0x07 << (drive->dn * 4));
63 pio_mode_data |= (pio << (drive->dn * 4));
64 pci_write_config_word(dev, ATIIXP_IDE_PIO_MODE, pio_mode_data);
65
66 pci_read_config_dword(dev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data);
67 pio_timing_data &= ~(0xff << timing_shift);
68 pio_timing_data |= (pio_timing[pio].recover_width << timing_shift) |
69 (pio_timing[pio].command_width << (timing_shift + 4));
70 pci_write_config_dword(dev, ATIIXP_IDE_PIO_TIMING, pio_timing_data);
71
72 spin_unlock_irqrestore(&atiixp_lock, flags);
73}
74
75/**
76 * atiixp_set_dma_mode - set host controller for DMA mode
77 * @drive: drive
78 * @speed: DMA mode
79 *
80 * Set a ATIIXP host controller to the desired DMA mode. This involves
81 * programming the right timing data into the PCI configuration space.
82 */
83
84static void atiixp_set_dma_mode(ide_drive_t *drive, const u8 speed)
85{
86 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
87 unsigned long flags;
88 int timing_shift = (drive->dn & 2) ? 16 : 0 + (drive->dn & 1) ? 0 : 8;
89 u32 tmp32;
90 u16 tmp16;
91 u16 udma_ctl = 0;
92
93 spin_lock_irqsave(&atiixp_lock, flags);
94
95 pci_read_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, &udma_ctl);
96
97 if (speed >= XFER_UDMA_0) {
98 pci_read_config_word(dev, ATIIXP_IDE_UDMA_MODE, &tmp16);
99 tmp16 &= ~(0x07 << (drive->dn * 4));
100 tmp16 |= ((speed & 0x07) << (drive->dn * 4));
101 pci_write_config_word(dev, ATIIXP_IDE_UDMA_MODE, tmp16);
102
103 udma_ctl |= (1 << drive->dn);
104 } else if (speed >= XFER_MW_DMA_0) {
105 u8 i = speed & 0x03;
106
107 pci_read_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, &tmp32);
108 tmp32 &= ~(0xff << timing_shift);
109 tmp32 |= (mdma_timing[i].recover_width << timing_shift) |
110 (mdma_timing[i].command_width << (timing_shift + 4));
111 pci_write_config_dword(dev, ATIIXP_IDE_MDMA_TIMING, tmp32);
112
113 udma_ctl &= ~(1 << drive->dn);
114 }
115
116 pci_write_config_word(dev, ATIIXP_IDE_UDMA_CONTROL, udma_ctl);
117
118 spin_unlock_irqrestore(&atiixp_lock, flags);
119}
120
121static u8 atiixp_cable_detect(ide_hwif_t *hwif)
122{
123 struct pci_dev *pdev = to_pci_dev(hwif->dev);
124 u8 udma_mode = 0, ch = hwif->channel;
125
126 pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ch, &udma_mode);
127
128 if ((udma_mode & 0x07) >= 0x04 || (udma_mode & 0x70) >= 0x40)
129 return ATA_CBL_PATA80;
130 else
131 return ATA_CBL_PATA40;
132}
133
134static const struct ide_port_ops atiixp_port_ops = {
135 .set_pio_mode = atiixp_set_pio_mode,
136 .set_dma_mode = atiixp_set_dma_mode,
137 .cable_detect = atiixp_cable_detect,
138};
139
140static const struct ide_port_info atiixp_pci_info[] __devinitdata = {
141 { /* 0: IXP200/300/400/700 */
142 .name = DRV_NAME,
143 .enablebits = {{0x48,0x01,0x00}, {0x48,0x08,0x00}},
144 .port_ops = &atiixp_port_ops,
145 .host_flags = IDE_HFLAG_LEGACY_IRQS,
146 .pio_mask = ATA_PIO4,
147 .mwdma_mask = ATA_MWDMA2,
148 .udma_mask = ATA_UDMA5,
149 },
150 { /* 1: IXP600 */
151 .name = DRV_NAME,
152 .enablebits = {{0x48,0x01,0x00}, {0x00,0x00,0x00}},
153 .port_ops = &atiixp_port_ops,
154 .host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_LEGACY_IRQS,
155 .pio_mask = ATA_PIO4,
156 .mwdma_mask = ATA_MWDMA2,
157 .udma_mask = ATA_UDMA5,
158 },
159};
160
161/**
162 * atiixp_init_one - called when a ATIIXP is found
163 * @dev: the atiixp device
164 * @id: the matching pci id
165 *
166 * Called when the PCI registration layer (or the IDE initialization)
167 * finds a device matching our IDE device tables.
168 */
169
170static int __devinit atiixp_init_one(struct pci_dev *dev, const struct pci_device_id *id)
171{
172 return ide_pci_init_one(dev, &atiixp_pci_info[id->driver_data], NULL);
173}
174
175static const struct pci_device_id atiixp_pci_tbl[] = {
176 { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP200_IDE), 0 },
177 { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP300_IDE), 0 },
178 { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP400_IDE), 0 },
179 { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP600_IDE), 1 },
180 { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP700_IDE), 0 },
181 { 0, },
182};
183MODULE_DEVICE_TABLE(pci, atiixp_pci_tbl);
184
185static struct pci_driver atiixp_pci_driver = {
186 .name = "ATIIXP_IDE",
187 .id_table = atiixp_pci_tbl,
188 .probe = atiixp_init_one,
189 .remove = ide_pci_remove,
190 .suspend = ide_pci_suspend,
191 .resume = ide_pci_resume,
192};
193
194static int __init atiixp_ide_init(void)
195{
196 return ide_pci_register_driver(&atiixp_pci_driver);
197}
198
199static void __exit atiixp_ide_exit(void)
200{
201 pci_unregister_driver(&atiixp_pci_driver);
202}
203
204module_init(atiixp_ide_init);
205module_exit(atiixp_ide_exit);
206
207MODULE_AUTHOR("HUI YU");
208MODULE_DESCRIPTION("PCI driver module for ATI IXP IDE");
209MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/cmd640.c b/drivers/ide/pci/cmd640.c
deleted file mode 100644
index e4306647d00d..000000000000
--- a/drivers/ide/pci/cmd640.c
+++ /dev/null
@@ -1,836 +0,0 @@
1/*
2 * Copyright (C) 1995-1996 Linus Torvalds & authors (see below)
3 */
4
5/*
6 * Original authors: abramov@cecmow.enet.dec.com (Igor Abramov)
7 * mlord@pobox.com (Mark Lord)
8 *
9 * See linux/MAINTAINERS for address of current maintainer.
10 *
11 * This file provides support for the advanced features and bugs
12 * of IDE interfaces using the CMD Technologies 0640 IDE interface chip.
13 *
14 * These chips are basically fucked by design, and getting this driver
15 * to work on every motherboard design that uses this screwed chip seems
16 * bloody well impossible. However, we're still trying.
17 *
18 * Version 0.97 worked for everybody.
19 *
20 * User feedback is essential. Many thanks to the beta test team:
21 *
22 * A.Hartgers@stud.tue.nl, JZDQC@CUNYVM.CUNY.edu, abramov@cecmow.enet.dec.com,
23 * bardj@utopia.ppp.sn.no, bart@gaga.tue.nl, bbol001@cs.auckland.ac.nz,
24 * chrisc@dbass.demon.co.uk, dalecki@namu26.Num.Math.Uni-Goettingen.de,
25 * derekn@vw.ece.cmu.edu, florian@btp2x3.phy.uni-bayreuth.de,
26 * flynn@dei.unipd.it, gadio@netvision.net.il, godzilla@futuris.net,
27 * j@pobox.com, jkemp1@mises.uni-paderborn.de, jtoppe@hiwaay.net,
28 * kerouac@ssnet.com, meskes@informatik.rwth-aachen.de, hzoli@cs.elte.hu,
29 * peter@udgaard.isgtec.com, phil@tazenda.demon.co.uk, roadcapw@cfw.com,
30 * s0033las@sun10.vsz.bme.hu, schaffer@tam.cornell.edu, sjd@slip.net,
31 * steve@ei.org, ulrpeg@bigcomm.gun.de, ism@tardis.ed.ac.uk, mack@cray.com
32 * liug@mama.indstate.edu, and others.
33 *
34 * Version 0.01 Initial version, hacked out of ide.c,
35 * and #include'd rather than compiled separately.
36 * This will get cleaned up in a subsequent release.
37 *
38 * Version 0.02 Fixes for vlb initialization code, enable prefetch
39 * for versions 'B' and 'C' of chip by default,
40 * some code cleanup.
41 *
42 * Version 0.03 Added reset of secondary interface,
43 * and black list for devices which are not compatible
44 * with prefetch mode. Separate function for setting
45 * prefetch is added, possibly it will be called some
46 * day from ioctl processing code.
47 *
48 * Version 0.04 Now configs/compiles separate from ide.c
49 *
50 * Version 0.05 Major rewrite of interface timing code.
51 * Added new function cmd640_set_mode to set PIO mode
52 * from ioctl call. New drives added to black list.
53 *
54 * Version 0.06 More code cleanup. Prefetch is enabled only for
55 * detected hard drives, not included in prefetch
56 * black list.
57 *
58 * Version 0.07 Changed to more conservative drive tuning policy.
59 * Unknown drives, which report PIO < 4 are set to
60 * (reported_PIO - 1) if it is supported, or to PIO0.
61 * List of known drives extended by info provided by
62 * CMD at their ftp site.
63 *
64 * Version 0.08 Added autotune/noautotune support.
65 *
66 * Version 0.09 Try to be smarter about 2nd port enabling.
67 * Version 0.10 Be nice and don't reset 2nd port.
68 * Version 0.11 Try to handle more weird situations.
69 *
70 * Version 0.12 Lots of bug fixes from Laszlo Peter
71 * irq unmasking disabled for reliability.
72 * try to be even smarter about the second port.
73 * tidy up source code formatting.
74 * Version 0.13 permit irq unmasking again.
75 * Version 0.90 massive code cleanup, some bugs fixed.
76 * defaults all drives to PIO mode0, prefetch off.
77 * autotune is OFF by default, with compile time flag.
78 * prefetch can be turned OFF/ON using "hdparm -p8/-p9"
79 * (requires hdparm-3.1 or newer)
80 * Version 0.91 first release to linux-kernel list.
81 * Version 0.92 move initial reg dump to separate callable function
82 * change "readahead" to "prefetch" to avoid confusion
83 * Version 0.95 respect original BIOS timings unless autotuning.
84 * tons of code cleanup and rearrangement.
85 * added CONFIG_BLK_DEV_CMD640_ENHANCED option
86 * prevent use of unmask when prefetch is on
87 * Version 0.96 prevent use of io_32bit when prefetch is off
88 * Version 0.97 fix VLB secondary interface for sjd@slip.net
89 * other minor tune-ups: 0.96 was very good.
90 * Version 0.98 ignore PCI version when disabled by BIOS
91 * Version 0.99 display setup/active/recovery clocks with PIO mode
92 * Version 1.00 Mmm.. cannot depend on PCMD_ENA in all systems
93 * Version 1.01 slow/fast devsel can be selected with "hdparm -p6/-p7"
94 * ("fast" is necessary for 32bit I/O in some systems)
95 * Version 1.02 fix bug that resulted in slow "setup times"
96 * (patch courtesy of Zoltan Hidvegi)
97 */
98
99#define CMD640_PREFETCH_MASKS 1
100
101/*#define CMD640_DUMP_REGS */
102
103#include <linux/types.h>
104#include <linux/kernel.h>
105#include <linux/delay.h>
106#include <linux/ide.h>
107#include <linux/init.h>
108
109#include <asm/io.h>
110
111#define DRV_NAME "cmd640"
112
113static int cmd640_vlb;
114
115/*
116 * CMD640 specific registers definition.
117 */
118
119#define VID 0x00
120#define DID 0x02
121#define PCMD 0x04
122#define PCMD_ENA 0x01
123#define PSTTS 0x06
124#define REVID 0x08
125#define PROGIF 0x09
126#define SUBCL 0x0a
127#define BASCL 0x0b
128#define BaseA0 0x10
129#define BaseA1 0x14
130#define BaseA2 0x18
131#define BaseA3 0x1c
132#define INTLINE 0x3c
133#define INPINE 0x3d
134
135#define CFR 0x50
136#define CFR_DEVREV 0x03
137#define CFR_IDE01INTR 0x04
138#define CFR_DEVID 0x18
139#define CFR_AT_VESA_078h 0x20
140#define CFR_DSA1 0x40
141#define CFR_DSA0 0x80
142
143#define CNTRL 0x51
144#define CNTRL_DIS_RA0 0x40
145#define CNTRL_DIS_RA1 0x80
146#define CNTRL_ENA_2ND 0x08
147
148#define CMDTIM 0x52
149#define ARTTIM0 0x53
150#define DRWTIM0 0x54
151#define ARTTIM1 0x55
152#define DRWTIM1 0x56
153#define ARTTIM23 0x57
154#define ARTTIM23_DIS_RA2 0x04
155#define ARTTIM23_DIS_RA3 0x08
156#define DRWTIM23 0x58
157#define BRST 0x59
158
159/*
160 * Registers and masks for easy access by drive index:
161 */
162static u8 prefetch_regs[4] = {CNTRL, CNTRL, ARTTIM23, ARTTIM23};
163static u8 prefetch_masks[4] = {CNTRL_DIS_RA0, CNTRL_DIS_RA1, ARTTIM23_DIS_RA2, ARTTIM23_DIS_RA3};
164
165#ifdef CONFIG_BLK_DEV_CMD640_ENHANCED
166
167static u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
168static u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM23, DRWTIM23};
169
170/*
171 * Current cmd640 timing values for each drive.
172 * The defaults for each are the slowest possible timings.
173 */
174static u8 setup_counts[4] = {4, 4, 4, 4}; /* Address setup count (in clocks) */
175static u8 active_counts[4] = {16, 16, 16, 16}; /* Active count (encoded) */
176static u8 recovery_counts[4] = {16, 16, 16, 16}; /* Recovery count (encoded) */
177
178#endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */
179
180static DEFINE_SPINLOCK(cmd640_lock);
181
182/*
183 * Interface to access cmd640x registers
184 */
185static unsigned int cmd640_key;
186static void (*__put_cmd640_reg)(u16 reg, u8 val);
187static u8 (*__get_cmd640_reg)(u16 reg);
188
189/*
190 * This is read from the CFR reg, and is used in several places.
191 */
192static unsigned int cmd640_chip_version;
193
194/*
195 * The CMD640x chip does not support DWORD config write cycles, but some
196 * of the BIOSes use them to implement the config services.
197 * Therefore, we must use direct IO instead.
198 */
199
200/* PCI method 1 access */
201
202static void put_cmd640_reg_pci1(u16 reg, u8 val)
203{
204 outl_p((reg & 0xfc) | cmd640_key, 0xcf8);
205 outb_p(val, (reg & 3) | 0xcfc);
206}
207
208static u8 get_cmd640_reg_pci1(u16 reg)
209{
210 outl_p((reg & 0xfc) | cmd640_key, 0xcf8);
211 return inb_p((reg & 3) | 0xcfc);
212}
213
214/* PCI method 2 access (from CMD datasheet) */
215
216static void put_cmd640_reg_pci2(u16 reg, u8 val)
217{
218 outb_p(0x10, 0xcf8);
219 outb_p(val, cmd640_key + reg);
220 outb_p(0, 0xcf8);
221}
222
223static u8 get_cmd640_reg_pci2(u16 reg)
224{
225 u8 b;
226
227 outb_p(0x10, 0xcf8);
228 b = inb_p(cmd640_key + reg);
229 outb_p(0, 0xcf8);
230 return b;
231}
232
233/* VLB access */
234
235static void put_cmd640_reg_vlb(u16 reg, u8 val)
236{
237 outb_p(reg, cmd640_key);
238 outb_p(val, cmd640_key + 4);
239}
240
241static u8 get_cmd640_reg_vlb(u16 reg)
242{
243 outb_p(reg, cmd640_key);
244 return inb_p(cmd640_key + 4);
245}
246
247static u8 get_cmd640_reg(u16 reg)
248{
249 unsigned long flags;
250 u8 b;
251
252 spin_lock_irqsave(&cmd640_lock, flags);
253 b = __get_cmd640_reg(reg);
254 spin_unlock_irqrestore(&cmd640_lock, flags);
255 return b;
256}
257
258static void put_cmd640_reg(u16 reg, u8 val)
259{
260 unsigned long flags;
261
262 spin_lock_irqsave(&cmd640_lock, flags);
263 __put_cmd640_reg(reg, val);
264 spin_unlock_irqrestore(&cmd640_lock, flags);
265}
266
267static int __init match_pci_cmd640_device(void)
268{
269 const u8 ven_dev[4] = {0x95, 0x10, 0x40, 0x06};
270 unsigned int i;
271 for (i = 0; i < 4; i++) {
272 if (get_cmd640_reg(i) != ven_dev[i])
273 return 0;
274 }
275#ifdef STUPIDLY_TRUST_BROKEN_PCMD_ENA_BIT
276 if ((get_cmd640_reg(PCMD) & PCMD_ENA) == 0) {
277 printk("ide: cmd640 on PCI disabled by BIOS\n");
278 return 0;
279 }
280#endif /* STUPIDLY_TRUST_BROKEN_PCMD_ENA_BIT */
281 return 1; /* success */
282}
283
284/*
285 * Probe for CMD640x -- pci method 1
286 */
287static int __init probe_for_cmd640_pci1(void)
288{
289 __get_cmd640_reg = get_cmd640_reg_pci1;
290 __put_cmd640_reg = put_cmd640_reg_pci1;
291 for (cmd640_key = 0x80000000;
292 cmd640_key <= 0x8000f800;
293 cmd640_key += 0x800) {
294 if (match_pci_cmd640_device())
295 return 1; /* success */
296 }
297 return 0;
298}
299
300/*
301 * Probe for CMD640x -- pci method 2
302 */
303static int __init probe_for_cmd640_pci2(void)
304{
305 __get_cmd640_reg = get_cmd640_reg_pci2;
306 __put_cmd640_reg = put_cmd640_reg_pci2;
307 for (cmd640_key = 0xc000; cmd640_key <= 0xcf00; cmd640_key += 0x100) {
308 if (match_pci_cmd640_device())
309 return 1; /* success */
310 }
311 return 0;
312}
313
314/*
315 * Probe for CMD640x -- vlb
316 */
317static int __init probe_for_cmd640_vlb(void)
318{
319 u8 b;
320
321 __get_cmd640_reg = get_cmd640_reg_vlb;
322 __put_cmd640_reg = put_cmd640_reg_vlb;
323 cmd640_key = 0x178;
324 b = get_cmd640_reg(CFR);
325 if (b == 0xff || b == 0x00 || (b & CFR_AT_VESA_078h)) {
326 cmd640_key = 0x78;
327 b = get_cmd640_reg(CFR);
328 if (b == 0xff || b == 0x00 || !(b & CFR_AT_VESA_078h))
329 return 0;
330 }
331 return 1; /* success */
332}
333
334/*
335 * Returns 1 if an IDE interface/drive exists at 0x170,
336 * Returns 0 otherwise.
337 */
338static int __init secondary_port_responding(void)
339{
340 unsigned long flags;
341
342 spin_lock_irqsave(&cmd640_lock, flags);
343
344 outb_p(0x0a, 0x176); /* select drive0 */
345 udelay(100);
346 if ((inb_p(0x176) & 0x1f) != 0x0a) {
347 outb_p(0x1a, 0x176); /* select drive1 */
348 udelay(100);
349 if ((inb_p(0x176) & 0x1f) != 0x1a) {
350 spin_unlock_irqrestore(&cmd640_lock, flags);
351 return 0; /* nothing responded */
352 }
353 }
354 spin_unlock_irqrestore(&cmd640_lock, flags);
355 return 1; /* success */
356}
357
358#ifdef CMD640_DUMP_REGS
359/*
360 * Dump out all cmd640 registers. May be called from ide.c
361 */
362static void cmd640_dump_regs(void)
363{
364 unsigned int reg = cmd640_vlb ? 0x50 : 0x00;
365
366 /* Dump current state of chip registers */
367 printk("ide: cmd640 internal register dump:");
368 for (; reg <= 0x59; reg++) {
369 if (!(reg & 0x0f))
370 printk("\n%04x:", reg);
371 printk(" %02x", get_cmd640_reg(reg));
372 }
373 printk("\n");
374}
375#endif
376
377static void __set_prefetch_mode(ide_drive_t *drive, int mode)
378{
379 if (mode) { /* want prefetch on? */
380#if CMD640_PREFETCH_MASKS
381 drive->dev_flags |= IDE_DFLAG_NO_UNMASK;
382 drive->dev_flags &= ~IDE_DFLAG_UNMASK;
383#endif
384 drive->dev_flags &= ~IDE_DFLAG_NO_IO_32BIT;
385 } else {
386 drive->dev_flags &= ~IDE_DFLAG_NO_UNMASK;
387 drive->dev_flags |= IDE_DFLAG_NO_IO_32BIT;
388 drive->io_32bit = 0;
389 }
390}
391
392#ifndef CONFIG_BLK_DEV_CMD640_ENHANCED
393/*
394 * Check whether prefetch is on for a drive,
395 * and initialize the unmask flags for safe operation.
396 */
397static void __init check_prefetch(ide_drive_t *drive, unsigned int index)
398{
399 u8 b = get_cmd640_reg(prefetch_regs[index]);
400
401 __set_prefetch_mode(drive, (b & prefetch_masks[index]) ? 0 : 1);
402}
403#else
404
405/*
406 * Sets prefetch mode for a drive.
407 */
408static void set_prefetch_mode(ide_drive_t *drive, unsigned int index, int mode)
409{
410 unsigned long flags;
411 int reg = prefetch_regs[index];
412 u8 b;
413
414 spin_lock_irqsave(&cmd640_lock, flags);
415 b = __get_cmd640_reg(reg);
416 __set_prefetch_mode(drive, mode);
417 if (mode)
418 b &= ~prefetch_masks[index]; /* enable prefetch */
419 else
420 b |= prefetch_masks[index]; /* disable prefetch */
421 __put_cmd640_reg(reg, b);
422 spin_unlock_irqrestore(&cmd640_lock, flags);
423}
424
425/*
426 * Dump out current drive clocks settings
427 */
428static void display_clocks(unsigned int index)
429{
430 u8 active_count, recovery_count;
431
432 active_count = active_counts[index];
433 if (active_count == 1)
434 ++active_count;
435 recovery_count = recovery_counts[index];
436 if (active_count > 3 && recovery_count == 1)
437 ++recovery_count;
438 if (cmd640_chip_version > 1)
439 recovery_count += 1; /* cmd640b uses (count + 1)*/
440 printk(", clocks=%d/%d/%d\n", setup_counts[index], active_count, recovery_count);
441}
442
443/*
444 * Pack active and recovery counts into single byte representation
445 * used by controller
446 */
447static inline u8 pack_nibbles(u8 upper, u8 lower)
448{
449 return ((upper & 0x0f) << 4) | (lower & 0x0f);
450}
451
452/*
453 * This routine writes the prepared setup/active/recovery counts
454 * for a drive into the cmd640 chipset registers to active them.
455 */
456static void program_drive_counts(ide_drive_t *drive, unsigned int index)
457{
458 unsigned long flags;
459 u8 setup_count = setup_counts[index];
460 u8 active_count = active_counts[index];
461 u8 recovery_count = recovery_counts[index];
462
463 /*
464 * Set up address setup count and drive read/write timing registers.
465 * Primary interface has individual count/timing registers for
466 * each drive. Secondary interface has one common set of registers,
467 * so we merge the timings, using the slowest value for each timing.
468 */
469 if (index > 1) {
470 ide_hwif_t *hwif = drive->hwif;
471 ide_drive_t *peer = &hwif->drives[!(drive->dn & 1)];
472 unsigned int mate = index ^ 1;
473
474 if (peer->dev_flags & IDE_DFLAG_PRESENT) {
475 if (setup_count < setup_counts[mate])
476 setup_count = setup_counts[mate];
477 if (active_count < active_counts[mate])
478 active_count = active_counts[mate];
479 if (recovery_count < recovery_counts[mate])
480 recovery_count = recovery_counts[mate];
481 }
482 }
483
484 /*
485 * Convert setup_count to internal chipset representation
486 */
487 switch (setup_count) {
488 case 4: setup_count = 0x00; break;
489 case 3: setup_count = 0x80; break;
490 case 1:
491 case 2: setup_count = 0x40; break;
492 default: setup_count = 0xc0; /* case 5 */
493 }
494
495 /*
496 * Now that everything is ready, program the new timings
497 */
498 spin_lock_irqsave(&cmd640_lock, flags);
499 /*
500 * Program the address_setup clocks into ARTTIM reg,
501 * and then the active/recovery counts into the DRWTIM reg
502 * (this converts counts of 16 into counts of zero -- okay).
503 */
504 setup_count |= __get_cmd640_reg(arttim_regs[index]) & 0x3f;
505 __put_cmd640_reg(arttim_regs[index], setup_count);
506 __put_cmd640_reg(drwtim_regs[index], pack_nibbles(active_count, recovery_count));
507 spin_unlock_irqrestore(&cmd640_lock, flags);
508}
509
510/*
511 * Set a specific pio_mode for a drive
512 */
513static void cmd640_set_mode(ide_drive_t *drive, unsigned int index,
514 u8 pio_mode, unsigned int cycle_time)
515{
516 struct ide_timing *t;
517 int setup_time, active_time, recovery_time, clock_time;
518 u8 setup_count, active_count, recovery_count, recovery_count2, cycle_count;
519 int bus_speed;
520
521 if (cmd640_vlb)
522 bus_speed = ide_vlb_clk ? ide_vlb_clk : 50;
523 else
524 bus_speed = ide_pci_clk ? ide_pci_clk : 33;
525
526 if (pio_mode > 5)
527 pio_mode = 5;
528
529 t = ide_timing_find_mode(XFER_PIO_0 + pio_mode);
530 setup_time = t->setup;
531 active_time = t->active;
532
533 recovery_time = cycle_time - (setup_time + active_time);
534 clock_time = 1000 / bus_speed;
535 cycle_count = DIV_ROUND_UP(cycle_time, clock_time);
536
537 setup_count = DIV_ROUND_UP(setup_time, clock_time);
538
539 active_count = DIV_ROUND_UP(active_time, clock_time);
540 if (active_count < 2)
541 active_count = 2; /* minimum allowed by cmd640 */
542
543 recovery_count = DIV_ROUND_UP(recovery_time, clock_time);
544 recovery_count2 = cycle_count - (setup_count + active_count);
545 if (recovery_count2 > recovery_count)
546 recovery_count = recovery_count2;
547 if (recovery_count < 2)
548 recovery_count = 2; /* minimum allowed by cmd640 */
549 if (recovery_count > 17) {
550 active_count += recovery_count - 17;
551 recovery_count = 17;
552 }
553 if (active_count > 16)
554 active_count = 16; /* maximum allowed by cmd640 */
555 if (cmd640_chip_version > 1)
556 recovery_count -= 1; /* cmd640b uses (count + 1)*/
557 if (recovery_count > 16)
558 recovery_count = 16; /* maximum allowed by cmd640 */
559
560 setup_counts[index] = setup_count;
561 active_counts[index] = active_count;
562 recovery_counts[index] = recovery_count;
563
564 /*
565 * In a perfect world, we might set the drive pio mode here
566 * (using WIN_SETFEATURE) before continuing.
567 *
568 * But we do not, because:
569 * 1) this is the wrong place to do it (proper is do_special() in ide.c)
570 * 2) in practice this is rarely, if ever, necessary
571 */
572 program_drive_counts(drive, index);
573}
574
575static void cmd640_set_pio_mode(ide_drive_t *drive, const u8 pio)
576{
577 unsigned int index = 0, cycle_time;
578 u8 b;
579
580 switch (pio) {
581 case 6: /* set fast-devsel off */
582 case 7: /* set fast-devsel on */
583 b = get_cmd640_reg(CNTRL) & ~0x27;
584 if (pio & 1)
585 b |= 0x27;
586 put_cmd640_reg(CNTRL, b);
587 printk("%s: %sabled cmd640 fast host timing (devsel)\n",
588 drive->name, (pio & 1) ? "en" : "dis");
589 return;
590 case 8: /* set prefetch off */
591 case 9: /* set prefetch on */
592 set_prefetch_mode(drive, index, pio & 1);
593 printk("%s: %sabled cmd640 prefetch\n",
594 drive->name, (pio & 1) ? "en" : "dis");
595 return;
596 }
597
598 cycle_time = ide_pio_cycle_time(drive, pio);
599 cmd640_set_mode(drive, index, pio, cycle_time);
600
601 printk("%s: selected cmd640 PIO mode%d (%dns)",
602 drive->name, pio, cycle_time);
603
604 display_clocks(index);
605}
606#endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */
607
608static void cmd640_init_dev(ide_drive_t *drive)
609{
610 unsigned int i = drive->hwif->channel * 2 + (drive->dn & 1);
611
612#ifdef CONFIG_BLK_DEV_CMD640_ENHANCED
613 /*
614 * Reset timing to the slowest speed and turn off prefetch.
615 * This way, the drive identify code has a better chance.
616 */
617 setup_counts[i] = 4; /* max possible */
618 active_counts[i] = 16; /* max possible */
619 recovery_counts[i] = 16; /* max possible */
620 program_drive_counts(drive, i);
621 set_prefetch_mode(drive, i, 0);
622 printk(KERN_INFO DRV_NAME ": drive%d timings/prefetch cleared\n", i);
623#else
624 /*
625 * Set the drive unmask flags to match the prefetch setting.
626 */
627 check_prefetch(drive, i);
628 printk(KERN_INFO DRV_NAME ": drive%d timings/prefetch(%s) preserved\n",
629 i, (drive->dev_flags & IDE_DFLAG_NO_IO_32BIT) ? "off" : "on");
630#endif /* CONFIG_BLK_DEV_CMD640_ENHANCED */
631}
632
633
634static const struct ide_port_ops cmd640_port_ops = {
635 .init_dev = cmd640_init_dev,
636#ifdef CONFIG_BLK_DEV_CMD640_ENHANCED
637 .set_pio_mode = cmd640_set_pio_mode,
638#endif
639};
640
641static int pci_conf1(void)
642{
643 unsigned long flags;
644 u32 tmp;
645
646 spin_lock_irqsave(&cmd640_lock, flags);
647 outb(0x01, 0xCFB);
648 tmp = inl(0xCF8);
649 outl(0x80000000, 0xCF8);
650 if (inl(0xCF8) == 0x80000000) {
651 outl(tmp, 0xCF8);
652 spin_unlock_irqrestore(&cmd640_lock, flags);
653 return 1;
654 }
655 outl(tmp, 0xCF8);
656 spin_unlock_irqrestore(&cmd640_lock, flags);
657 return 0;
658}
659
660static int pci_conf2(void)
661{
662 unsigned long flags;
663
664 spin_lock_irqsave(&cmd640_lock, flags);
665 outb(0x00, 0xCFB);
666 outb(0x00, 0xCF8);
667 outb(0x00, 0xCFA);
668 if (inb(0xCF8) == 0x00 && inb(0xCF8) == 0x00) {
669 spin_unlock_irqrestore(&cmd640_lock, flags);
670 return 1;
671 }
672 spin_unlock_irqrestore(&cmd640_lock, flags);
673 return 0;
674}
675
676static const struct ide_port_info cmd640_port_info __initdata = {
677 .chipset = ide_cmd640,
678 .host_flags = IDE_HFLAG_SERIALIZE |
679 IDE_HFLAG_NO_DMA |
680 IDE_HFLAG_ABUSE_PREFETCH |
681 IDE_HFLAG_ABUSE_FAST_DEVSEL,
682 .port_ops = &cmd640_port_ops,
683 .pio_mask = ATA_PIO5,
684};
685
686static int cmd640x_init_one(unsigned long base, unsigned long ctl)
687{
688 if (!request_region(base, 8, DRV_NAME)) {
689 printk(KERN_ERR "%s: I/O resource 0x%lX-0x%lX not free.\n",
690 DRV_NAME, base, base + 7);
691 return -EBUSY;
692 }
693
694 if (!request_region(ctl, 1, DRV_NAME)) {
695 printk(KERN_ERR "%s: I/O resource 0x%lX not free.\n",
696 DRV_NAME, ctl);
697 release_region(base, 8);
698 return -EBUSY;
699 }
700
701 return 0;
702}
703
704/*
705 * Probe for a cmd640 chipset, and initialize it if found.
706 */
707static int __init cmd640x_init(void)
708{
709 int second_port_cmd640 = 0, rc;
710 const char *bus_type, *port2;
711 u8 b, cfr;
712 hw_regs_t hw[2], *hws[] = { NULL, NULL, NULL, NULL };
713
714 if (cmd640_vlb && probe_for_cmd640_vlb()) {
715 bus_type = "VLB";
716 } else {
717 cmd640_vlb = 0;
718 /* Find out what kind of PCI probing is supported otherwise
719 Justin Gibbs will sulk.. */
720 if (pci_conf1() && probe_for_cmd640_pci1())
721 bus_type = "PCI (type1)";
722 else if (pci_conf2() && probe_for_cmd640_pci2())
723 bus_type = "PCI (type2)";
724 else
725 return 0;
726 }
727 /*
728 * Undocumented magic (there is no 0x5b reg in specs)
729 */
730 put_cmd640_reg(0x5b, 0xbd);
731 if (get_cmd640_reg(0x5b) != 0xbd) {
732 printk(KERN_ERR "ide: cmd640 init failed: wrong value in reg 0x5b\n");
733 return 0;
734 }
735 put_cmd640_reg(0x5b, 0);
736
737#ifdef CMD640_DUMP_REGS
738 cmd640_dump_regs();
739#endif
740
741 /*
742 * Documented magic begins here
743 */
744 cfr = get_cmd640_reg(CFR);
745 cmd640_chip_version = cfr & CFR_DEVREV;
746 if (cmd640_chip_version == 0) {
747 printk("ide: bad cmd640 revision: %d\n", cmd640_chip_version);
748 return 0;
749 }
750
751 rc = cmd640x_init_one(0x1f0, 0x3f6);
752 if (rc)
753 return rc;
754
755 rc = cmd640x_init_one(0x170, 0x376);
756 if (rc) {
757 release_region(0x3f6, 1);
758 release_region(0x1f0, 8);
759 return rc;
760 }
761
762 memset(&hw, 0, sizeof(hw));
763
764 ide_std_init_ports(&hw[0], 0x1f0, 0x3f6);
765 hw[0].irq = 14;
766 hw[0].chipset = ide_cmd640;
767
768 ide_std_init_ports(&hw[1], 0x170, 0x376);
769 hw[1].irq = 15;
770 hw[1].chipset = ide_cmd640;
771
772 printk(KERN_INFO "cmd640: buggy cmd640%c interface on %s, config=0x%02x"
773 "\n", 'a' + cmd640_chip_version - 1, bus_type, cfr);
774
775 /*
776 * Initialize data for primary port
777 */
778 hws[0] = &hw[0];
779
780 /*
781 * Ensure compatibility by always using the slowest timings
782 * for access to the drive's command register block,
783 * and reset the prefetch burstsize to default (512 bytes).
784 *
785 * Maybe we need a way to NOT do these on *some* systems?
786 */
787 put_cmd640_reg(CMDTIM, 0);
788 put_cmd640_reg(BRST, 0x40);
789
790 b = get_cmd640_reg(CNTRL);
791
792 /*
793 * Try to enable the secondary interface, if not already enabled
794 */
795 if (secondary_port_responding()) {
796 if ((b & CNTRL_ENA_2ND)) {
797 second_port_cmd640 = 1;
798 port2 = "okay";
799 } else if (cmd640_vlb) {
800 second_port_cmd640 = 1;
801 port2 = "alive";
802 } else
803 port2 = "not cmd640";
804 } else {
805 put_cmd640_reg(CNTRL, b ^ CNTRL_ENA_2ND); /* toggle the bit */
806 if (secondary_port_responding()) {
807 second_port_cmd640 = 1;
808 port2 = "enabled";
809 } else {
810 put_cmd640_reg(CNTRL, b); /* restore original setting */
811 port2 = "not responding";
812 }
813 }
814
815 /*
816 * Initialize data for secondary cmd640 port, if enabled
817 */
818 if (second_port_cmd640)
819 hws[1] = &hw[1];
820
821 printk(KERN_INFO "cmd640: %sserialized, secondary interface %s\n",
822 second_port_cmd640 ? "" : "not ", port2);
823
824#ifdef CMD640_DUMP_REGS
825 cmd640_dump_regs();
826#endif
827
828 return ide_host_add(&cmd640_port_info, hws, NULL);
829}
830
831module_param_named(probe_vlb, cmd640_vlb, bool, 0);
832MODULE_PARM_DESC(probe_vlb, "probe for VLB version of CMD640 chipset");
833
834module_init(cmd640x_init);
835
836MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/cmd64x.c b/drivers/ide/pci/cmd64x.c
deleted file mode 100644
index 935385c77e06..000000000000
--- a/drivers/ide/pci/cmd64x.c
+++ /dev/null
@@ -1,532 +0,0 @@
1/*
2 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
3 * Due to massive hardware bugs, UltraDMA is only supported
4 * on the 646U2 and not on the 646U.
5 *
6 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
7 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
8 *
9 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
10 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
11 */
12
13#include <linux/module.h>
14#include <linux/types.h>
15#include <linux/pci.h>
16#include <linux/ide.h>
17#include <linux/init.h>
18
19#include <asm/io.h>
20
21#define DRV_NAME "cmd64x"
22
23#define CMD_DEBUG 0
24
25#if CMD_DEBUG
26#define cmdprintk(x...) printk(x)
27#else
28#define cmdprintk(x...)
29#endif
30
31/*
32 * CMD64x specific registers definition.
33 */
34#define CFR 0x50
35#define CFR_INTR_CH0 0x04
36
37#define CMDTIM 0x52
38#define ARTTIM0 0x53
39#define DRWTIM0 0x54
40#define ARTTIM1 0x55
41#define DRWTIM1 0x56
42#define ARTTIM23 0x57
43#define ARTTIM23_DIS_RA2 0x04
44#define ARTTIM23_DIS_RA3 0x08
45#define ARTTIM23_INTR_CH1 0x10
46#define DRWTIM2 0x58
47#define BRST 0x59
48#define DRWTIM3 0x5b
49
50#define BMIDECR0 0x70
51#define MRDMODE 0x71
52#define MRDMODE_INTR_CH0 0x04
53#define MRDMODE_INTR_CH1 0x08
54#define UDIDETCR0 0x73
55#define DTPR0 0x74
56#define BMIDECR1 0x78
57#define BMIDECSR 0x79
58#define UDIDETCR1 0x7B
59#define DTPR1 0x7C
60
61static u8 quantize_timing(int timing, int quant)
62{
63 return (timing + quant - 1) / quant;
64}
65
66/*
67 * This routine calculates active/recovery counts and then writes them into
68 * the chipset registers.
69 */
70static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time)
71{
72 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
73 int clock_time = 1000 / (ide_pci_clk ? ide_pci_clk : 33);
74 u8 cycle_count, active_count, recovery_count, drwtim;
75 static const u8 recovery_values[] =
76 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
77 static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
78
79 cmdprintk("program_cycle_times parameters: total=%d, active=%d\n",
80 cycle_time, active_time);
81
82 cycle_count = quantize_timing( cycle_time, clock_time);
83 active_count = quantize_timing(active_time, clock_time);
84 recovery_count = cycle_count - active_count;
85
86 /*
87 * In case we've got too long recovery phase, try to lengthen
88 * the active phase
89 */
90 if (recovery_count > 16) {
91 active_count += recovery_count - 16;
92 recovery_count = 16;
93 }
94 if (active_count > 16) /* shouldn't actually happen... */
95 active_count = 16;
96
97 cmdprintk("Final counts: total=%d, active=%d, recovery=%d\n",
98 cycle_count, active_count, recovery_count);
99
100 /*
101 * Convert values to internal chipset representation
102 */
103 recovery_count = recovery_values[recovery_count];
104 active_count &= 0x0f;
105
106 /* Program the active/recovery counts into the DRWTIM register */
107 drwtim = (active_count << 4) | recovery_count;
108 (void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim);
109 cmdprintk("Write 0x%02x to reg 0x%x\n", drwtim, drwtim_regs[drive->dn]);
110}
111
112/*
113 * This routine writes into the chipset registers
114 * PIO setup/active/recovery timings.
115 */
116static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio)
117{
118 ide_hwif_t *hwif = HWIF(drive);
119 struct pci_dev *dev = to_pci_dev(hwif->dev);
120 struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
121 unsigned int cycle_time;
122 u8 setup_count, arttim = 0;
123
124 static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
125 static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
126
127 cycle_time = ide_pio_cycle_time(drive, pio);
128
129 program_cycle_times(drive, cycle_time, t->active);
130
131 setup_count = quantize_timing(t->setup,
132 1000 / (ide_pci_clk ? ide_pci_clk : 33));
133
134 /*
135 * The primary channel has individual address setup timing registers
136 * for each drive and the hardware selects the slowest timing itself.
137 * The secondary channel has one common register and we have to select
138 * the slowest address setup timing ourselves.
139 */
140 if (hwif->channel) {
141 ide_drive_t *drives = hwif->drives;
142
143 drive->drive_data = setup_count;
144 setup_count = max(drives[0].drive_data, drives[1].drive_data);
145 }
146
147 if (setup_count > 5) /* shouldn't actually happen... */
148 setup_count = 5;
149 cmdprintk("Final address setup count: %d\n", setup_count);
150
151 /*
152 * Program the address setup clocks into the ARTTIM registers.
153 * Avoid clearing the secondary channel's interrupt bit.
154 */
155 (void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
156 if (hwif->channel)
157 arttim &= ~ARTTIM23_INTR_CH1;
158 arttim &= ~0xc0;
159 arttim |= setup_values[setup_count];
160 (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
161 cmdprintk("Write 0x%02x to reg 0x%x\n", arttim, arttim_regs[drive->dn]);
162}
163
164/*
165 * Attempts to set drive's PIO mode.
166 * Special cases are 8: prefetch off, 9: prefetch on (both never worked)
167 */
168
169static void cmd64x_set_pio_mode(ide_drive_t *drive, const u8 pio)
170{
171 /*
172 * Filter out the prefetch control values
173 * to prevent PIO5 from being programmed
174 */
175 if (pio == 8 || pio == 9)
176 return;
177
178 cmd64x_tune_pio(drive, pio);
179}
180
181static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed)
182{
183 ide_hwif_t *hwif = HWIF(drive);
184 struct pci_dev *dev = to_pci_dev(hwif->dev);
185 u8 unit = drive->dn & 0x01;
186 u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0;
187
188 if (speed >= XFER_SW_DMA_0) {
189 (void) pci_read_config_byte(dev, pciU, &regU);
190 regU &= ~(unit ? 0xCA : 0x35);
191 }
192
193 switch(speed) {
194 case XFER_UDMA_5:
195 regU |= unit ? 0x0A : 0x05;
196 break;
197 case XFER_UDMA_4:
198 regU |= unit ? 0x4A : 0x15;
199 break;
200 case XFER_UDMA_3:
201 regU |= unit ? 0x8A : 0x25;
202 break;
203 case XFER_UDMA_2:
204 regU |= unit ? 0x42 : 0x11;
205 break;
206 case XFER_UDMA_1:
207 regU |= unit ? 0x82 : 0x21;
208 break;
209 case XFER_UDMA_0:
210 regU |= unit ? 0xC2 : 0x31;
211 break;
212 case XFER_MW_DMA_2:
213 program_cycle_times(drive, 120, 70);
214 break;
215 case XFER_MW_DMA_1:
216 program_cycle_times(drive, 150, 80);
217 break;
218 case XFER_MW_DMA_0:
219 program_cycle_times(drive, 480, 215);
220 break;
221 }
222
223 if (speed >= XFER_SW_DMA_0)
224 (void) pci_write_config_byte(dev, pciU, regU);
225}
226
227static int cmd648_dma_end(ide_drive_t *drive)
228{
229 ide_hwif_t *hwif = HWIF(drive);
230 unsigned long base = hwif->dma_base - (hwif->channel * 8);
231 int err = ide_dma_end(drive);
232 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
233 MRDMODE_INTR_CH0;
234 u8 mrdmode = inb(base + 1);
235
236 /* clear the interrupt bit */
237 outb((mrdmode & ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1)) | irq_mask,
238 base + 1);
239
240 return err;
241}
242
243static int cmd64x_dma_end(ide_drive_t *drive)
244{
245 ide_hwif_t *hwif = HWIF(drive);
246 struct pci_dev *dev = to_pci_dev(hwif->dev);
247 int irq_reg = hwif->channel ? ARTTIM23 : CFR;
248 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
249 CFR_INTR_CH0;
250 u8 irq_stat = 0;
251 int err = ide_dma_end(drive);
252
253 (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
254 /* clear the interrupt bit */
255 (void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask);
256
257 return err;
258}
259
260static int cmd648_dma_test_irq(ide_drive_t *drive)
261{
262 ide_hwif_t *hwif = HWIF(drive);
263 unsigned long base = hwif->dma_base - (hwif->channel * 8);
264 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
265 MRDMODE_INTR_CH0;
266 u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
267 u8 mrdmode = inb(base + 1);
268
269#ifdef DEBUG
270 printk("%s: dma_stat: 0x%02x mrdmode: 0x%02x irq_mask: 0x%02x\n",
271 drive->name, dma_stat, mrdmode, irq_mask);
272#endif
273 if (!(mrdmode & irq_mask))
274 return 0;
275
276 /* return 1 if INTR asserted */
277 if (dma_stat & 4)
278 return 1;
279
280 return 0;
281}
282
283static int cmd64x_dma_test_irq(ide_drive_t *drive)
284{
285 ide_hwif_t *hwif = HWIF(drive);
286 struct pci_dev *dev = to_pci_dev(hwif->dev);
287 int irq_reg = hwif->channel ? ARTTIM23 : CFR;
288 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
289 CFR_INTR_CH0;
290 u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
291 u8 irq_stat = 0;
292
293 (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
294
295#ifdef DEBUG
296 printk("%s: dma_stat: 0x%02x irq_stat: 0x%02x irq_mask: 0x%02x\n",
297 drive->name, dma_stat, irq_stat, irq_mask);
298#endif
299 if (!(irq_stat & irq_mask))
300 return 0;
301
302 /* return 1 if INTR asserted */
303 if (dma_stat & 4)
304 return 1;
305
306 return 0;
307}
308
309/*
310 * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
311 * event order for DMA transfers.
312 */
313
314static int cmd646_1_dma_end(ide_drive_t *drive)
315{
316 ide_hwif_t *hwif = HWIF(drive);
317 u8 dma_stat = 0, dma_cmd = 0;
318
319 drive->waiting_for_dma = 0;
320 /* get DMA status */
321 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
322 /* read DMA command state */
323 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
324 /* stop DMA */
325 outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
326 /* clear the INTR & ERROR bits */
327 outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS);
328 /* and free any DMA resources */
329 ide_destroy_dmatable(drive);
330 /* verify good DMA status */
331 return (dma_stat & 7) != 4;
332}
333
334static unsigned int init_chipset_cmd64x(struct pci_dev *dev)
335{
336 u8 mrdmode = 0;
337
338 /* Set a good latency timer and cache line size value. */
339 (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
340 /* FIXME: pci_set_master() to ensure a good latency timer value */
341
342 /*
343 * Enable interrupts, select MEMORY READ LINE for reads.
344 *
345 * NOTE: although not mentioned in the PCI0646U specs,
346 * bits 0-1 are write only and won't be read back as
347 * set or not -- PCI0646U2 specs clarify this point.
348 */
349 (void) pci_read_config_byte (dev, MRDMODE, &mrdmode);
350 mrdmode &= ~0x30;
351 (void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02));
352
353 return 0;
354}
355
356static u8 cmd64x_cable_detect(ide_hwif_t *hwif)
357{
358 struct pci_dev *dev = to_pci_dev(hwif->dev);
359 u8 bmidecsr = 0, mask = hwif->channel ? 0x02 : 0x01;
360
361 switch (dev->device) {
362 case PCI_DEVICE_ID_CMD_648:
363 case PCI_DEVICE_ID_CMD_649:
364 pci_read_config_byte(dev, BMIDECSR, &bmidecsr);
365 return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
366 default:
367 return ATA_CBL_PATA40;
368 }
369}
370
371static const struct ide_port_ops cmd64x_port_ops = {
372 .set_pio_mode = cmd64x_set_pio_mode,
373 .set_dma_mode = cmd64x_set_dma_mode,
374 .cable_detect = cmd64x_cable_detect,
375};
376
377static const struct ide_dma_ops cmd64x_dma_ops = {
378 .dma_host_set = ide_dma_host_set,
379 .dma_setup = ide_dma_setup,
380 .dma_exec_cmd = ide_dma_exec_cmd,
381 .dma_start = ide_dma_start,
382 .dma_end = cmd64x_dma_end,
383 .dma_test_irq = cmd64x_dma_test_irq,
384 .dma_lost_irq = ide_dma_lost_irq,
385 .dma_timeout = ide_dma_timeout,
386};
387
388static const struct ide_dma_ops cmd646_rev1_dma_ops = {
389 .dma_host_set = ide_dma_host_set,
390 .dma_setup = ide_dma_setup,
391 .dma_exec_cmd = ide_dma_exec_cmd,
392 .dma_start = ide_dma_start,
393 .dma_end = cmd646_1_dma_end,
394 .dma_test_irq = ide_dma_test_irq,
395 .dma_lost_irq = ide_dma_lost_irq,
396 .dma_timeout = ide_dma_timeout,
397};
398
399static const struct ide_dma_ops cmd648_dma_ops = {
400 .dma_host_set = ide_dma_host_set,
401 .dma_setup = ide_dma_setup,
402 .dma_exec_cmd = ide_dma_exec_cmd,
403 .dma_start = ide_dma_start,
404 .dma_end = cmd648_dma_end,
405 .dma_test_irq = cmd648_dma_test_irq,
406 .dma_lost_irq = ide_dma_lost_irq,
407 .dma_timeout = ide_dma_timeout,
408};
409
410static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
411 { /* 0: CMD643 */
412 .name = DRV_NAME,
413 .init_chipset = init_chipset_cmd64x,
414 .enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
415 .port_ops = &cmd64x_port_ops,
416 .dma_ops = &cmd64x_dma_ops,
417 .host_flags = IDE_HFLAG_CLEAR_SIMPLEX |
418 IDE_HFLAG_ABUSE_PREFETCH,
419 .pio_mask = ATA_PIO5,
420 .mwdma_mask = ATA_MWDMA2,
421 .udma_mask = 0x00, /* no udma */
422 },
423 { /* 1: CMD646 */
424 .name = DRV_NAME,
425 .init_chipset = init_chipset_cmd64x,
426 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
427 .chipset = ide_cmd646,
428 .port_ops = &cmd64x_port_ops,
429 .dma_ops = &cmd648_dma_ops,
430 .host_flags = IDE_HFLAG_ABUSE_PREFETCH,
431 .pio_mask = ATA_PIO5,
432 .mwdma_mask = ATA_MWDMA2,
433 .udma_mask = ATA_UDMA2,
434 },
435 { /* 2: CMD648 */
436 .name = DRV_NAME,
437 .init_chipset = init_chipset_cmd64x,
438 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
439 .port_ops = &cmd64x_port_ops,
440 .dma_ops = &cmd648_dma_ops,
441 .host_flags = IDE_HFLAG_ABUSE_PREFETCH,
442 .pio_mask = ATA_PIO5,
443 .mwdma_mask = ATA_MWDMA2,
444 .udma_mask = ATA_UDMA4,
445 },
446 { /* 3: CMD649 */
447 .name = DRV_NAME,
448 .init_chipset = init_chipset_cmd64x,
449 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
450 .port_ops = &cmd64x_port_ops,
451 .dma_ops = &cmd648_dma_ops,
452 .host_flags = IDE_HFLAG_ABUSE_PREFETCH,
453 .pio_mask = ATA_PIO5,
454 .mwdma_mask = ATA_MWDMA2,
455 .udma_mask = ATA_UDMA5,
456 }
457};
458
459static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
460{
461 struct ide_port_info d;
462 u8 idx = id->driver_data;
463
464 d = cmd64x_chipsets[idx];
465
466 if (idx == 1) {
467 /*
468 * UltraDMA only supported on PCI646U and PCI646U2, which
469 * correspond to revisions 0x03, 0x05 and 0x07 respectively.
470 * Actually, although the CMD tech support people won't
471 * tell me the details, the 0x03 revision cannot support
472 * UDMA correctly without hardware modifications, and even
473 * then it only works with Quantum disks due to some
474 * hold time assumptions in the 646U part which are fixed
475 * in the 646U2.
476 *
477 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
478 */
479 if (dev->revision < 5) {
480 d.udma_mask = 0x00;
481 /*
482 * The original PCI0646 didn't have the primary
483 * channel enable bit, it appeared starting with
484 * PCI0646U (i.e. revision ID 3).
485 */
486 if (dev->revision < 3) {
487 d.enablebits[0].reg = 0;
488 if (dev->revision == 1)
489 d.dma_ops = &cmd646_rev1_dma_ops;
490 else
491 d.dma_ops = &cmd64x_dma_ops;
492 }
493 }
494 }
495
496 return ide_pci_init_one(dev, &d, NULL);
497}
498
499static const struct pci_device_id cmd64x_pci_tbl[] = {
500 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
501 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
502 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 2 },
503 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 3 },
504 { 0, },
505};
506MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);
507
508static struct pci_driver cmd64x_pci_driver = {
509 .name = "CMD64x_IDE",
510 .id_table = cmd64x_pci_tbl,
511 .probe = cmd64x_init_one,
512 .remove = ide_pci_remove,
513 .suspend = ide_pci_suspend,
514 .resume = ide_pci_resume,
515};
516
517static int __init cmd64x_ide_init(void)
518{
519 return ide_pci_register_driver(&cmd64x_pci_driver);
520}
521
522static void __exit cmd64x_ide_exit(void)
523{
524 pci_unregister_driver(&cmd64x_pci_driver);
525}
526
527module_init(cmd64x_ide_init);
528module_exit(cmd64x_ide_exit);
529
530MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick");
531MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
532MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/cs5520.c b/drivers/ide/pci/cs5520.c
deleted file mode 100644
index 5efb467f8fa0..000000000000
--- a/drivers/ide/pci/cs5520.c
+++ /dev/null
@@ -1,165 +0,0 @@
1/*
2 * IDE tuning and bus mastering support for the CS5510/CS5520
3 * chipsets
4 *
5 * The CS5510/CS5520 are slightly unusual devices. Unlike the
6 * typical IDE controllers they do bus mastering with the drive in
7 * PIO mode and smarter silicon.
8 *
9 * The practical upshot of this is that we must always tune the
10 * drive for the right PIO mode. We must also ignore all the blacklists
11 * and the drive bus mastering DMA information.
12 *
13 * *** This driver is strictly experimental ***
14 *
15 * (c) Copyright Red Hat Inc 2002
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the
19 * Free Software Foundation; either version 2, or (at your option) any
20 * later version.
21 *
22 * This program is distributed in the hope that it will be useful, but
23 * WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
25 * General Public License for more details.
26 *
27 * For the avoidance of doubt the "preferred form" of this code is one which
28 * is in an open non patent encumbered format. Where cryptographic key signing
29 * forms part of the process of creating an executable the information
30 * including keys needed to generate an equivalently functional executable
31 * are deemed to be part of the source code.
32 *
33 */
34
35#include <linux/module.h>
36#include <linux/types.h>
37#include <linux/kernel.h>
38#include <linux/init.h>
39#include <linux/pci.h>
40#include <linux/ide.h>
41#include <linux/dma-mapping.h>
42
43#define DRV_NAME "cs5520"
44
45struct pio_clocks
46{
47 int address;
48 int assert;
49 int recovery;
50};
51
52static struct pio_clocks cs5520_pio_clocks[]={
53 {3, 6, 11},
54 {2, 5, 6},
55 {1, 4, 3},
56 {1, 3, 2},
57 {1, 2, 1}
58};
59
60static void cs5520_set_pio_mode(ide_drive_t *drive, const u8 pio)
61{
62 ide_hwif_t *hwif = HWIF(drive);
63 struct pci_dev *pdev = to_pci_dev(hwif->dev);
64 int controller = drive->dn > 1 ? 1 : 0;
65
66 /* 8bit CAT/CRT - 8bit command timing for channel */
67 pci_write_config_byte(pdev, 0x62 + controller,
68 (cs5520_pio_clocks[pio].recovery << 4) |
69 (cs5520_pio_clocks[pio].assert));
70
71 /* 0x64 - 16bit Primary, 0x68 - 16bit Secondary */
72
73 /* FIXME: should these use address ? */
74 /* Data read timing */
75 pci_write_config_byte(pdev, 0x64 + 4*controller + (drive->dn&1),
76 (cs5520_pio_clocks[pio].recovery << 4) |
77 (cs5520_pio_clocks[pio].assert));
78 /* Write command timing */
79 pci_write_config_byte(pdev, 0x66 + 4*controller + (drive->dn&1),
80 (cs5520_pio_clocks[pio].recovery << 4) |
81 (cs5520_pio_clocks[pio].assert));
82}
83
84static void cs5520_set_dma_mode(ide_drive_t *drive, const u8 speed)
85{
86 printk(KERN_ERR "cs55x0: bad ide timing.\n");
87
88 cs5520_set_pio_mode(drive, 0);
89}
90
91static const struct ide_port_ops cs5520_port_ops = {
92 .set_pio_mode = cs5520_set_pio_mode,
93 .set_dma_mode = cs5520_set_dma_mode,
94};
95
96static const struct ide_port_info cyrix_chipset __devinitdata = {
97 .name = DRV_NAME,
98 .enablebits = { { 0x60, 0x01, 0x01 }, { 0x60, 0x02, 0x02 } },
99 .port_ops = &cs5520_port_ops,
100 .host_flags = IDE_HFLAG_ISA_PORTS | IDE_HFLAG_CS5520,
101 .pio_mask = ATA_PIO4,
102};
103
104/*
105 * The 5510/5520 are a bit weird. They don't quite set up the way
106 * the PCI helper layer expects so we must do much of the set up
107 * work longhand.
108 */
109
110static int __devinit cs5520_init_one(struct pci_dev *dev, const struct pci_device_id *id)
111{
112 const struct ide_port_info *d = &cyrix_chipset;
113 hw_regs_t hw[4], *hws[] = { NULL, NULL, NULL, NULL };
114
115 ide_setup_pci_noise(dev, d);
116
117 /* We must not grab the entire device, it has 'ISA' space in its
118 * BARS too and we will freak out other bits of the kernel
119 */
120 if (pci_enable_device_io(dev)) {
121 printk(KERN_WARNING "%s: Unable to enable 55x0.\n", d->name);
122 return -ENODEV;
123 }
124 pci_set_master(dev);
125 if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) {
126 printk(KERN_WARNING "%s: No suitable DMA available.\n",
127 d->name);
128 return -ENODEV;
129 }
130
131 /*
132 * Now the chipset is configured we can let the core
133 * do all the device setup for us
134 */
135
136 ide_pci_setup_ports(dev, d, 14, &hw[0], &hws[0]);
137
138 return ide_host_add(d, hws, NULL);
139}
140
141static const struct pci_device_id cs5520_pci_tbl[] = {
142 { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5510), 0 },
143 { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5520), 1 },
144 { 0, },
145};
146MODULE_DEVICE_TABLE(pci, cs5520_pci_tbl);
147
148static struct pci_driver cs5520_pci_driver = {
149 .name = "Cyrix_IDE",
150 .id_table = cs5520_pci_tbl,
151 .probe = cs5520_init_one,
152 .suspend = ide_pci_suspend,
153 .resume = ide_pci_resume,
154};
155
156static int __init cs5520_ide_init(void)
157{
158 return ide_pci_register_driver(&cs5520_pci_driver);
159}
160
161module_init(cs5520_ide_init);
162
163MODULE_AUTHOR("Alan Cox");
164MODULE_DESCRIPTION("PCI driver module for Cyrix 5510/5520 IDE");
165MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/cs5530.c b/drivers/ide/pci/cs5530.c
deleted file mode 100644
index 53f079cc00af..000000000000
--- a/drivers/ide/pci/cs5530.c
+++ /dev/null
@@ -1,294 +0,0 @@
1/*
2 * Copyright (C) 2000 Andre Hedrick <andre@linux-ide.org>
3 * Copyright (C) 2000 Mark Lord <mlord@pobox.com>
4 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
5 *
6 * May be copied or modified under the terms of the GNU General Public License
7 *
8 * Development of this chipset driver was funded
9 * by the nice folks at National Semiconductor.
10 *
11 * Documentation:
12 * CS5530 documentation available from National Semiconductor.
13 */
14
15#include <linux/module.h>
16#include <linux/types.h>
17#include <linux/kernel.h>
18#include <linux/pci.h>
19#include <linux/init.h>
20#include <linux/ide.h>
21
22#include <asm/io.h>
23
24#define DRV_NAME "cs5530"
25
26/*
27 * Here are the standard PIO mode 0-4 timings for each "format".
28 * Format-0 uses fast data reg timings, with slower command reg timings.
29 * Format-1 uses fast timings for all registers, but won't work with all drives.
30 */
31static unsigned int cs5530_pio_timings[2][5] = {
32 {0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010},
33 {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}
34};
35
36/*
37 * After chip reset, the PIO timings are set to 0x0000e132, which is not valid.
38 */
39#define CS5530_BAD_PIO(timings) (((timings)&~0x80000000)==0x0000e132)
40#define CS5530_BASEREG(hwif) (((hwif)->dma_base & ~0xf) + ((hwif)->channel ? 0x30 : 0x20))
41
42/**
43 * cs5530_set_pio_mode - set host controller for PIO mode
44 * @drive: drive
45 * @pio: PIO mode number
46 *
47 * Handles setting of PIO mode for the chipset.
48 *
49 * The init_hwif_cs5530() routine guarantees that all drives
50 * will have valid default PIO timings set up before we get here.
51 */
52
53static void cs5530_set_pio_mode(ide_drive_t *drive, const u8 pio)
54{
55 unsigned long basereg = CS5530_BASEREG(drive->hwif);
56 unsigned int format = (inl(basereg + 4) >> 31) & 1;
57
58 outl(cs5530_pio_timings[format][pio], basereg + ((drive->dn & 1)<<3));
59}
60
61/**
62 * cs5530_udma_filter - UDMA filter
63 * @drive: drive
64 *
65 * cs5530_udma_filter() does UDMA mask filtering for the given drive
66 * taking into the consideration capabilities of the mate device.
67 *
68 * The CS5530 specifies that two drives sharing a cable cannot mix
69 * UDMA/MDMA. It has to be one or the other, for the pair, though
70 * different timings can still be chosen for each drive. We could
71 * set the appropriate timing bits on the fly, but that might be
72 * a bit confusing. So, for now we statically handle this requirement
73 * by looking at our mate drive to see what it is capable of, before
74 * choosing a mode for our own drive.
75 *
76 * Note: This relies on the fact we never fail from UDMA to MWDMA2
77 * but instead drop to PIO.
78 */
79
80static u8 cs5530_udma_filter(ide_drive_t *drive)
81{
82 ide_hwif_t *hwif = drive->hwif;
83 ide_drive_t *mate = ide_get_pair_dev(drive);
84 u16 *mateid = mate->id;
85 u8 mask = hwif->ultra_mask;
86
87 if (mate == NULL)
88 goto out;
89
90 if (ata_id_has_dma(mateid) && __ide_dma_bad_drive(mate) == 0) {
91 if ((mateid[ATA_ID_FIELD_VALID] & 4) &&
92 (mateid[ATA_ID_UDMA_MODES] & 7))
93 goto out;
94 if ((mateid[ATA_ID_FIELD_VALID] & 2) &&
95 (mateid[ATA_ID_MWDMA_MODES] & 7))
96 mask = 0;
97 }
98out:
99 return mask;
100}
101
102static void cs5530_set_dma_mode(ide_drive_t *drive, const u8 mode)
103{
104 unsigned long basereg;
105 unsigned int reg, timings = 0;
106
107 switch (mode) {
108 case XFER_UDMA_0: timings = 0x00921250; break;
109 case XFER_UDMA_1: timings = 0x00911140; break;
110 case XFER_UDMA_2: timings = 0x00911030; break;
111 case XFER_MW_DMA_0: timings = 0x00077771; break;
112 case XFER_MW_DMA_1: timings = 0x00012121; break;
113 case XFER_MW_DMA_2: timings = 0x00002020; break;
114 }
115 basereg = CS5530_BASEREG(drive->hwif);
116 reg = inl(basereg + 4); /* get drive0 config register */
117 timings |= reg & 0x80000000; /* preserve PIO format bit */
118 if ((drive-> dn & 1) == 0) { /* are we configuring drive0? */
119 outl(timings, basereg + 4); /* write drive0 config register */
120 } else {
121 if (timings & 0x00100000)
122 reg |= 0x00100000; /* enable UDMA timings for both drives */
123 else
124 reg &= ~0x00100000; /* disable UDMA timings for both drives */
125 outl(reg, basereg + 4); /* write drive0 config register */
126 outl(timings, basereg + 12); /* write drive1 config register */
127 }
128}
129
130/**
131 * init_chipset_5530 - set up 5530 bridge
132 * @dev: PCI device
133 *
134 * Initialize the cs5530 bridge for reliable IDE DMA operation.
135 */
136
137static unsigned int init_chipset_cs5530(struct pci_dev *dev)
138{
139 struct pci_dev *master_0 = NULL, *cs5530_0 = NULL;
140
141 if (pci_resource_start(dev, 4) == 0)
142 return -EFAULT;
143
144 dev = NULL;
145 while ((dev = pci_get_device(PCI_VENDOR_ID_CYRIX, PCI_ANY_ID, dev)) != NULL) {
146 switch (dev->device) {
147 case PCI_DEVICE_ID_CYRIX_PCI_MASTER:
148 master_0 = pci_dev_get(dev);
149 break;
150 case PCI_DEVICE_ID_CYRIX_5530_LEGACY:
151 cs5530_0 = pci_dev_get(dev);
152 break;
153 }
154 }
155 if (!master_0) {
156 printk(KERN_ERR DRV_NAME ": unable to locate PCI MASTER function\n");
157 goto out;
158 }
159 if (!cs5530_0) {
160 printk(KERN_ERR DRV_NAME ": unable to locate CS5530 LEGACY function\n");
161 goto out;
162 }
163
164 /*
165 * Enable BusMaster and MemoryWriteAndInvalidate for the cs5530:
166 * --> OR 0x14 into 16-bit PCI COMMAND reg of function 0 of the cs5530
167 */
168
169 pci_set_master(cs5530_0);
170 pci_try_set_mwi(cs5530_0);
171
172 /*
173 * Set PCI CacheLineSize to 16-bytes:
174 * --> Write 0x04 into 8-bit PCI CACHELINESIZE reg of function 0 of the cs5530
175 */
176
177 pci_write_config_byte(cs5530_0, PCI_CACHE_LINE_SIZE, 0x04);
178
179 /*
180 * Disable trapping of UDMA register accesses (Win98 hack):
181 * --> Write 0x5006 into 16-bit reg at offset 0xd0 of function 0 of the cs5530
182 */
183
184 pci_write_config_word(cs5530_0, 0xd0, 0x5006);
185
186 /*
187 * Bit-1 at 0x40 enables MemoryWriteAndInvalidate on internal X-bus:
188 * The other settings are what is necessary to get the register
189 * into a sane state for IDE DMA operation.
190 */
191
192 pci_write_config_byte(master_0, 0x40, 0x1e);
193
194 /*
195 * Set max PCI burst size (16-bytes seems to work best):
196 * 16bytes: set bit-1 at 0x41 (reg value of 0x16)
197 * all others: clear bit-1 at 0x41, and do:
198 * 128bytes: OR 0x00 at 0x41
199 * 256bytes: OR 0x04 at 0x41
200 * 512bytes: OR 0x08 at 0x41
201 * 1024bytes: OR 0x0c at 0x41
202 */
203
204 pci_write_config_byte(master_0, 0x41, 0x14);
205
206 /*
207 * These settings are necessary to get the chip
208 * into a sane state for IDE DMA operation.
209 */
210
211 pci_write_config_byte(master_0, 0x42, 0x00);
212 pci_write_config_byte(master_0, 0x43, 0xc1);
213
214out:
215 pci_dev_put(master_0);
216 pci_dev_put(cs5530_0);
217 return 0;
218}
219
220/**
221 * init_hwif_cs5530 - initialise an IDE channel
222 * @hwif: IDE to initialize
223 *
224 * This gets invoked by the IDE driver once for each channel. It
225 * performs channel-specific pre-initialization before drive probing.
226 */
227
228static void __devinit init_hwif_cs5530 (ide_hwif_t *hwif)
229{
230 unsigned long basereg;
231 u32 d0_timings;
232
233 basereg = CS5530_BASEREG(hwif);
234 d0_timings = inl(basereg + 0);
235 if (CS5530_BAD_PIO(d0_timings))
236 outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 0);
237 if (CS5530_BAD_PIO(inl(basereg + 8)))
238 outl(cs5530_pio_timings[(d0_timings >> 31) & 1][0], basereg + 8);
239}
240
241static const struct ide_port_ops cs5530_port_ops = {
242 .set_pio_mode = cs5530_set_pio_mode,
243 .set_dma_mode = cs5530_set_dma_mode,
244 .udma_filter = cs5530_udma_filter,
245};
246
247static const struct ide_port_info cs5530_chipset __devinitdata = {
248 .name = DRV_NAME,
249 .init_chipset = init_chipset_cs5530,
250 .init_hwif = init_hwif_cs5530,
251 .port_ops = &cs5530_port_ops,
252 .host_flags = IDE_HFLAG_SERIALIZE |
253 IDE_HFLAG_POST_SET_MODE,
254 .pio_mask = ATA_PIO4,
255 .mwdma_mask = ATA_MWDMA2,
256 .udma_mask = ATA_UDMA2,
257};
258
259static int __devinit cs5530_init_one(struct pci_dev *dev, const struct pci_device_id *id)
260{
261 return ide_pci_init_one(dev, &cs5530_chipset, NULL);
262}
263
264static const struct pci_device_id cs5530_pci_tbl[] = {
265 { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE), 0 },
266 { 0, },
267};
268MODULE_DEVICE_TABLE(pci, cs5530_pci_tbl);
269
270static struct pci_driver cs5530_pci_driver = {
271 .name = "CS5530 IDE",
272 .id_table = cs5530_pci_tbl,
273 .probe = cs5530_init_one,
274 .remove = ide_pci_remove,
275 .suspend = ide_pci_suspend,
276 .resume = ide_pci_resume,
277};
278
279static int __init cs5530_ide_init(void)
280{
281 return ide_pci_register_driver(&cs5530_pci_driver);
282}
283
284static void __exit cs5530_ide_exit(void)
285{
286 pci_unregister_driver(&cs5530_pci_driver);
287}
288
289module_init(cs5530_ide_init);
290module_exit(cs5530_ide_exit);
291
292MODULE_AUTHOR("Mark Lord");
293MODULE_DESCRIPTION("PCI driver module for Cyrix/NS 5530 IDE");
294MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/cs5535.c b/drivers/ide/pci/cs5535.c
deleted file mode 100644
index 983d957a0189..000000000000
--- a/drivers/ide/pci/cs5535.c
+++ /dev/null
@@ -1,219 +0,0 @@
1/*
2 * Copyright (C) 2004-2005 Advanced Micro Devices, Inc.
3 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
4 *
5 * History:
6 * 09/20/2005 - Jaya Kumar <jayakumar.ide@gmail.com>
7 * - Reworked tuneproc, set_drive, misc mods to prep for mainline
8 * - Work was sponsored by CIS (M) Sdn Bhd.
9 * Ported to Kernel 2.6.11 on June 26, 2005 by
10 * Wolfgang Zuleger <wolfgang.zuleger@gmx.de>
11 * Alexander Kiausch <alex.kiausch@t-online.de>
12 * Originally developed by AMD for 2.4/2.6
13 *
14 * Development of this chipset driver was funded
15 * by the nice folks at National Semiconductor/AMD.
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License version 2 as published by
19 * the Free Software Foundation.
20 *
21 * Documentation:
22 * CS5535 documentation available from AMD
23 */
24
25#include <linux/module.h>
26#include <linux/pci.h>
27#include <linux/ide.h>
28
29#define DRV_NAME "cs5535"
30
31#define MSR_ATAC_BASE 0x51300000
32#define ATAC_GLD_MSR_CAP (MSR_ATAC_BASE+0)
33#define ATAC_GLD_MSR_CONFIG (MSR_ATAC_BASE+0x01)
34#define ATAC_GLD_MSR_SMI (MSR_ATAC_BASE+0x02)
35#define ATAC_GLD_MSR_ERROR (MSR_ATAC_BASE+0x03)
36#define ATAC_GLD_MSR_PM (MSR_ATAC_BASE+0x04)
37#define ATAC_GLD_MSR_DIAG (MSR_ATAC_BASE+0x05)
38#define ATAC_IO_BAR (MSR_ATAC_BASE+0x08)
39#define ATAC_RESET (MSR_ATAC_BASE+0x10)
40#define ATAC_CH0D0_PIO (MSR_ATAC_BASE+0x20)
41#define ATAC_CH0D0_DMA (MSR_ATAC_BASE+0x21)
42#define ATAC_CH0D1_PIO (MSR_ATAC_BASE+0x22)
43#define ATAC_CH0D1_DMA (MSR_ATAC_BASE+0x23)
44#define ATAC_PCI_ABRTERR (MSR_ATAC_BASE+0x24)
45#define ATAC_BM0_CMD_PRIM 0x00
46#define ATAC_BM0_STS_PRIM 0x02
47#define ATAC_BM0_PRD 0x04
48#define CS5535_CABLE_DETECT 0x48
49
50/* Format I PIO settings. We separate out cmd and data for safer timings */
51
52static unsigned int cs5535_pio_cmd_timings[5] =
53{ 0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131 };
54static unsigned int cs5535_pio_dta_timings[5] =
55{ 0xF7F4, 0xF173, 0x8141, 0x5131, 0x1131 };
56
57static unsigned int cs5535_mwdma_timings[3] =
58{ 0x7F0FFFF3, 0x7F035352, 0x7f024241 };
59
60static unsigned int cs5535_udma_timings[5] =
61{ 0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061 };
62
63/* Macros to check if the register is the reset value - reset value is an
64 invalid timing and indicates the register has not been set previously */
65
66#define CS5535_BAD_PIO(timings) ( (timings&~0x80000000UL) == 0x00009172 )
67#define CS5535_BAD_DMA(timings) ( (timings & 0x000FFFFF) == 0x00077771 )
68
69/****
70 * cs5535_set_speed - Configure the chipset to the new speed
71 * @drive: Drive to set up
72 * @speed: desired speed
73 *
74 * cs5535_set_speed() configures the chipset to a new speed.
75 */
76static void cs5535_set_speed(ide_drive_t *drive, const u8 speed)
77{
78 u32 reg = 0, dummy;
79 u8 unit = drive->dn & 1;
80
81 /* Set the PIO timings */
82 if (speed < XFER_SW_DMA_0) {
83 ide_drive_t *pair = ide_get_pair_dev(drive);
84 u8 cmd, pioa;
85
86 cmd = pioa = speed - XFER_PIO_0;
87
88 if (pair) {
89 u8 piob = ide_get_best_pio_mode(pair, 255, 4);
90
91 if (piob < cmd)
92 cmd = piob;
93 }
94
95 /* Write the speed of the current drive */
96 reg = (cs5535_pio_cmd_timings[cmd] << 16) |
97 cs5535_pio_dta_timings[pioa];
98 wrmsr(unit ? ATAC_CH0D1_PIO : ATAC_CH0D0_PIO, reg, 0);
99
100 /* And if nessesary - change the speed of the other drive */
101 rdmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, dummy);
102
103 if (((reg >> 16) & cs5535_pio_cmd_timings[cmd]) !=
104 cs5535_pio_cmd_timings[cmd]) {
105 reg &= 0x0000FFFF;
106 reg |= cs5535_pio_cmd_timings[cmd] << 16;
107 wrmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, 0);
108 }
109
110 /* Set bit 31 of the DMA register for PIO format 1 timings */
111 rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);
112 wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA,
113 reg | 0x80000000UL, 0);
114 } else {
115 rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);
116
117 reg &= 0x80000000UL; /* Preserve the PIO format bit */
118
119 if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_4)
120 reg |= cs5535_udma_timings[speed - XFER_UDMA_0];
121 else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
122 reg |= cs5535_mwdma_timings[speed - XFER_MW_DMA_0];
123 else
124 return;
125
126 wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, 0);
127 }
128}
129
130/**
131 * cs5535_set_dma_mode - set host controller for DMA mode
132 * @drive: drive
133 * @speed: DMA mode
134 *
135 * Programs the chipset for DMA mode.
136 */
137
138static void cs5535_set_dma_mode(ide_drive_t *drive, const u8 speed)
139{
140 cs5535_set_speed(drive, speed);
141}
142
143/**
144 * cs5535_set_pio_mode - set host controller for PIO mode
145 * @drive: drive
146 * @pio: PIO mode number
147 *
148 * A callback from the upper layers for PIO-only tuning.
149 */
150
151static void cs5535_set_pio_mode(ide_drive_t *drive, const u8 pio)
152{
153 cs5535_set_speed(drive, XFER_PIO_0 + pio);
154}
155
156static u8 cs5535_cable_detect(ide_hwif_t *hwif)
157{
158 struct pci_dev *dev = to_pci_dev(hwif->dev);
159 u8 bit;
160
161 /* if a 80 wire cable was detected */
162 pci_read_config_byte(dev, CS5535_CABLE_DETECT, &bit);
163
164 return (bit & 1) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
165}
166
167static const struct ide_port_ops cs5535_port_ops = {
168 .set_pio_mode = cs5535_set_pio_mode,
169 .set_dma_mode = cs5535_set_dma_mode,
170 .cable_detect = cs5535_cable_detect,
171};
172
173static const struct ide_port_info cs5535_chipset __devinitdata = {
174 .name = DRV_NAME,
175 .port_ops = &cs5535_port_ops,
176 .host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_POST_SET_MODE,
177 .pio_mask = ATA_PIO4,
178 .mwdma_mask = ATA_MWDMA2,
179 .udma_mask = ATA_UDMA4,
180};
181
182static int __devinit cs5535_init_one(struct pci_dev *dev,
183 const struct pci_device_id *id)
184{
185 return ide_pci_init_one(dev, &cs5535_chipset, NULL);
186}
187
188static const struct pci_device_id cs5535_pci_tbl[] = {
189 { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_CS5535_IDE), 0 },
190 { 0, },
191};
192
193MODULE_DEVICE_TABLE(pci, cs5535_pci_tbl);
194
195static struct pci_driver cs5535_pci_driver = {
196 .name = "CS5535_IDE",
197 .id_table = cs5535_pci_tbl,
198 .probe = cs5535_init_one,
199 .remove = ide_pci_remove,
200 .suspend = ide_pci_suspend,
201 .resume = ide_pci_resume,
202};
203
204static int __init cs5535_ide_init(void)
205{
206 return ide_pci_register_driver(&cs5535_pci_driver);
207}
208
209static void __exit cs5535_ide_exit(void)
210{
211 pci_unregister_driver(&cs5535_pci_driver);
212}
213
214module_init(cs5535_ide_init);
215module_exit(cs5535_ide_exit);
216
217MODULE_AUTHOR("AMD");
218MODULE_DESCRIPTION("PCI driver module for AMD/NS CS5535 IDE");
219MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/cy82c693.c b/drivers/ide/pci/cy82c693.c
deleted file mode 100644
index 5297f07d2933..000000000000
--- a/drivers/ide/pci/cy82c693.c
+++ /dev/null
@@ -1,358 +0,0 @@
1/*
2 * Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer
3 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator
4 *
5 * CYPRESS CY82C693 chipset IDE controller
6 *
7 * The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards.
8 * Writing the driver was quite simple, since most of the job is
9 * done by the generic pci-ide support.
10 * The hard part was finding the CY82C693's datasheet on Cypress's
11 * web page :-(. But Altavista solved this problem :-).
12 *
13 *
14 * Notes:
15 * - I recently got a 16.8G IBM DTTA, so I was able to test it with
16 * a large and fast disk - the results look great, so I'd say the
17 * driver is working fine :-)
18 * hdparm -t reports 8.17 MB/sec at about 6% CPU usage for the DTTA
19 * - this is my first linux driver, so there's probably a lot of room
20 * for optimizations and bug fixing, so feel free to do it.
21 * - if using PIO mode it's a good idea to set the PIO mode and
22 * 32-bit I/O support (if possible), e.g. hdparm -p2 -c1 /dev/hda
23 * - I had some problems with my IBM DHEA with PIO modes < 2
24 * (lost interrupts) ?????
25 * - first tests with DMA look okay, they seem to work, but there is a
26 * problem with sound - the BusMaster IDE TimeOut should fixed this
27 *
28 * Ancient History:
29 * AMH@1999-08-24: v0.34 init_cy82c693_chip moved to pci_init_cy82c693
30 * ASK@1999-01-23: v0.33 made a few minor code clean ups
31 * removed DMA clock speed setting by default
32 * added boot message
33 * ASK@1998-11-01: v0.32 added support to set BusMaster IDE TimeOut
34 * added support to set DMA Controller Clock Speed
35 * ASK@1998-10-31: v0.31 fixed problem with setting to high DMA modes
36 * on some drives.
37 * ASK@1998-10-29: v0.3 added support to set DMA modes
38 * ASK@1998-10-28: v0.2 added support to set PIO modes
39 * ASK@1998-10-27: v0.1 first version - chipset detection
40 *
41 */
42
43#include <linux/module.h>
44#include <linux/types.h>
45#include <linux/pci.h>
46#include <linux/ide.h>
47#include <linux/init.h>
48
49#include <asm/io.h>
50
51#define DRV_NAME "cy82c693"
52
53/*
54 * The following are used to debug the driver.
55 */
56#define CY82C693_DEBUG_INFO 0
57
58/*
59 * NOTE: the value for busmaster timeout is tricky and I got it by
60 * trial and error! By using a to low value will cause DMA timeouts
61 * and drop IDE performance, and by using a to high value will cause
62 * audio playback to scatter.
63 * If you know a better value or how to calc it, please let me know.
64 */
65
66/* twice the value written in cy82c693ub datasheet */
67#define BUSMASTER_TIMEOUT 0x50
68/*
69 * the value above was tested on my machine and it seems to work okay
70 */
71
72/* here are the offset definitions for the registers */
73#define CY82_IDE_CMDREG 0x04
74#define CY82_IDE_ADDRSETUP 0x48
75#define CY82_IDE_MASTER_IOR 0x4C
76#define CY82_IDE_MASTER_IOW 0x4D
77#define CY82_IDE_SLAVE_IOR 0x4E
78#define CY82_IDE_SLAVE_IOW 0x4F
79#define CY82_IDE_MASTER_8BIT 0x50
80#define CY82_IDE_SLAVE_8BIT 0x51
81
82#define CY82_INDEX_PORT 0x22
83#define CY82_DATA_PORT 0x23
84
85#define CY82_INDEX_CHANNEL0 0x30
86#define CY82_INDEX_CHANNEL1 0x31
87#define CY82_INDEX_TIMEOUT 0x32
88
89/* the min and max PCI bus speed in MHz - from datasheet */
90#define CY82C963_MIN_BUS_SPEED 25
91#define CY82C963_MAX_BUS_SPEED 33
92
93/* the struct for the PIO mode timings */
94typedef struct pio_clocks_s {
95 u8 address_time; /* Address setup (clocks) */
96 u8 time_16r; /* clocks for 16bit IOR (0xF0=Active/data, 0x0F=Recovery) */
97 u8 time_16w; /* clocks for 16bit IOW (0xF0=Active/data, 0x0F=Recovery) */
98 u8 time_8; /* clocks for 8bit (0xF0=Active/data, 0x0F=Recovery) */
99} pio_clocks_t;
100
101/*
102 * calc clocks using bus_speed
103 * returns (rounded up) time in bus clocks for time in ns
104 */
105static int calc_clk(int time, int bus_speed)
106{
107 int clocks;
108
109 clocks = (time*bus_speed+999)/1000 - 1;
110
111 if (clocks < 0)
112 clocks = 0;
113
114 if (clocks > 0x0F)
115 clocks = 0x0F;
116
117 return clocks;
118}
119
120/*
121 * compute the values for the clock registers for PIO
122 * mode and pci_clk [MHz] speed
123 *
124 * NOTE: for mode 0,1 and 2 drives 8-bit IDE command control registers are used
125 * for mode 3 and 4 drives 8 and 16-bit timings are the same
126 *
127 */
128static void compute_clocks(u8 pio, pio_clocks_t *p_pclk)
129{
130 struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
131 int clk1, clk2;
132 int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
133
134 /* we don't check against CY82C693's min and max speed,
135 * so you can play with the idebus=xx parameter
136 */
137
138 /* let's calc the address setup time clocks */
139 p_pclk->address_time = (u8)calc_clk(t->setup, bus_speed);
140
141 /* let's calc the active and recovery time clocks */
142 clk1 = calc_clk(t->active, bus_speed);
143
144 /* calc recovery timing */
145 clk2 = t->cycle - t->active - t->setup;
146
147 clk2 = calc_clk(clk2, bus_speed);
148
149 clk1 = (clk1<<4)|clk2; /* combine active and recovery clocks */
150
151 /* note: we use the same values for 16bit IOR and IOW
152 * those are all the same, since I don't have other
153 * timings than those from ide-lib.c
154 */
155
156 p_pclk->time_16r = (u8)clk1;
157 p_pclk->time_16w = (u8)clk1;
158
159 /* what are good values for 8bit ?? */
160 p_pclk->time_8 = (u8)clk1;
161}
162
163/*
164 * set DMA mode a specific channel for CY82C693
165 */
166
167static void cy82c693_set_dma_mode(ide_drive_t *drive, const u8 mode)
168{
169 ide_hwif_t *hwif = drive->hwif;
170 u8 single = (mode & 0x10) >> 4, index = 0, data = 0;
171
172 index = hwif->channel ? CY82_INDEX_CHANNEL1 : CY82_INDEX_CHANNEL0;
173
174 data = (mode & 3) | (single << 2);
175
176 outb(index, CY82_INDEX_PORT);
177 outb(data, CY82_DATA_PORT);
178
179#if CY82C693_DEBUG_INFO
180 printk(KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n",
181 drive->name, hwif->channel, drive->dn & 1, mode & 3, single);
182#endif /* CY82C693_DEBUG_INFO */
183
184 /*
185 * note: below we set the value for Bus Master IDE TimeOut Register
186 * I'm not absolutly sure what this does, but it solved my problem
187 * with IDE DMA and sound, so I now can play sound and work with
188 * my IDE driver at the same time :-)
189 *
190 * If you know the correct (best) value for this register please
191 * let me know - ASK
192 */
193
194 data = BUSMASTER_TIMEOUT;
195 outb(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
196 outb(data, CY82_DATA_PORT);
197
198#if CY82C693_DEBUG_INFO
199 printk(KERN_INFO "%s: Set IDE Bus Master TimeOut Register to 0x%X\n",
200 drive->name, data);
201#endif /* CY82C693_DEBUG_INFO */
202}
203
204static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio)
205{
206 ide_hwif_t *hwif = HWIF(drive);
207 struct pci_dev *dev = to_pci_dev(hwif->dev);
208 pio_clocks_t pclk;
209 unsigned int addrCtrl;
210
211 /* select primary or secondary channel */
212 if (hwif->index > 0) { /* drive is on the secondary channel */
213 dev = pci_get_slot(dev->bus, dev->devfn+1);
214 if (!dev) {
215 printk(KERN_ERR "%s: tune_drive: "
216 "Cannot find secondary interface!\n",
217 drive->name);
218 return;
219 }
220 }
221
222 /* let's calc the values for this PIO mode */
223 compute_clocks(pio, &pclk);
224
225 /* now let's write the clocks registers */
226 if ((drive->dn & 1) == 0) {
227 /*
228 * set master drive
229 * address setup control register
230 * is 32 bit !!!
231 */
232 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
233
234 addrCtrl &= (~0xF);
235 addrCtrl |= (unsigned int)pclk.address_time;
236 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
237
238 /* now let's set the remaining registers */
239 pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, pclk.time_16r);
240 pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, pclk.time_16w);
241 pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, pclk.time_8);
242
243 addrCtrl &= 0xF;
244 } else {
245 /*
246 * set slave drive
247 * address setup control register
248 * is 32 bit !!!
249 */
250 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
251
252 addrCtrl &= (~0xF0);
253 addrCtrl |= ((unsigned int)pclk.address_time<<4);
254 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
255
256 /* now let's set the remaining registers */
257 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, pclk.time_16r);
258 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, pclk.time_16w);
259 pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, pclk.time_8);
260
261 addrCtrl >>= 4;
262 addrCtrl &= 0xF;
263 }
264
265#if CY82C693_DEBUG_INFO
266 printk(KERN_INFO "%s (ch=%d, dev=%d): set PIO timing to "
267 "(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
268 drive->name, hwif->channel, drive->dn & 1,
269 addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
270#endif /* CY82C693_DEBUG_INFO */
271}
272
273static void __devinit init_iops_cy82c693(ide_hwif_t *hwif)
274{
275 static ide_hwif_t *primary;
276 struct pci_dev *dev = to_pci_dev(hwif->dev);
277
278 if (PCI_FUNC(dev->devfn) == 1)
279 primary = hwif;
280 else {
281 hwif->mate = primary;
282 hwif->channel = 1;
283 }
284}
285
286static const struct ide_port_ops cy82c693_port_ops = {
287 .set_pio_mode = cy82c693_set_pio_mode,
288 .set_dma_mode = cy82c693_set_dma_mode,
289};
290
291static const struct ide_port_info cy82c693_chipset __devinitdata = {
292 .name = DRV_NAME,
293 .init_iops = init_iops_cy82c693,
294 .port_ops = &cy82c693_port_ops,
295 .chipset = ide_cy82c693,
296 .host_flags = IDE_HFLAG_SINGLE,
297 .pio_mask = ATA_PIO4,
298 .swdma_mask = ATA_SWDMA2,
299 .mwdma_mask = ATA_MWDMA2,
300};
301
302static int __devinit cy82c693_init_one(struct pci_dev *dev, const struct pci_device_id *id)
303{
304 struct pci_dev *dev2;
305 int ret = -ENODEV;
306
307 /* CY82C693 is more than only a IDE controller.
308 Function 1 is primary IDE channel, function 2 - secondary. */
309 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE &&
310 PCI_FUNC(dev->devfn) == 1) {
311 dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
312 ret = ide_pci_init_two(dev, dev2, &cy82c693_chipset, NULL);
313 if (ret)
314 pci_dev_put(dev2);
315 }
316 return ret;
317}
318
319static void __devexit cy82c693_remove(struct pci_dev *dev)
320{
321 struct ide_host *host = pci_get_drvdata(dev);
322 struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;
323
324 ide_pci_remove(dev);
325 pci_dev_put(dev2);
326}
327
328static const struct pci_device_id cy82c693_pci_tbl[] = {
329 { PCI_VDEVICE(CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693), 0 },
330 { 0, },
331};
332MODULE_DEVICE_TABLE(pci, cy82c693_pci_tbl);
333
334static struct pci_driver cy82c693_pci_driver = {
335 .name = "Cypress_IDE",
336 .id_table = cy82c693_pci_tbl,
337 .probe = cy82c693_init_one,
338 .remove = __devexit_p(cy82c693_remove),
339 .suspend = ide_pci_suspend,
340 .resume = ide_pci_resume,
341};
342
343static int __init cy82c693_ide_init(void)
344{
345 return ide_pci_register_driver(&cy82c693_pci_driver);
346}
347
348static void __exit cy82c693_ide_exit(void)
349{
350 pci_unregister_driver(&cy82c693_pci_driver);
351}
352
353module_init(cy82c693_ide_init);
354module_exit(cy82c693_ide_exit);
355
356MODULE_AUTHOR("Andreas Krebs, Andre Hedrick");
357MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE");
358MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/delkin_cb.c b/drivers/ide/pci/delkin_cb.c
deleted file mode 100644
index 8f1b2d9f0513..000000000000
--- a/drivers/ide/pci/delkin_cb.c
+++ /dev/null
@@ -1,192 +0,0 @@
1/*
2 * Created 20 Oct 2004 by Mark Lord
3 *
4 * Basic support for Delkin/ASKA/Workbit Cardbus CompactFlash adapter
5 *
6 * Modeled after the 16-bit PCMCIA driver: ide-cs.c
7 *
8 * This is slightly peculiar, in that it is a PCI driver,
9 * but is NOT an IDE PCI driver -- the IDE layer does not directly
10 * support hot insertion/removal of PCI interfaces, so this driver
11 * is unable to use the IDE PCI interfaces. Instead, it uses the
12 * same interfaces as the ide-cs (PCMCIA) driver uses.
13 * On the plus side, the driver is also smaller/simpler this way.
14 *
15 * This file is subject to the terms and conditions of the GNU General Public
16 * License. See the file COPYING in the main directory of this archive for
17 * more details.
18 */
19
20#include <linux/types.h>
21#include <linux/module.h>
22#include <linux/ide.h>
23#include <linux/init.h>
24#include <linux/pci.h>
25
26#include <asm/io.h>
27
28/*
29 * No chip documentation has yet been found,
30 * so these configuration values were pulled from
31 * a running Win98 system using "debug".
32 * This gives around 3MByte/second read performance,
33 * which is about 2/3 of what the chip is capable of.
34 *
35 * There is also a 4KByte mmio region on the card,
36 * but its purpose has yet to be reverse-engineered.
37 */
38static const u8 setup[] = {
39 0x00, 0x05, 0xbe, 0x01, 0x20, 0x8f, 0x00, 0x00,
40 0xa4, 0x1f, 0xb3, 0x1b, 0x00, 0x00, 0x00, 0x80,
41 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
42 0x00, 0x00, 0x00, 0x00, 0xa4, 0x83, 0x02, 0x13,
43};
44
45static const struct ide_port_ops delkin_cb_port_ops = {
46 .quirkproc = ide_undecoded_slave,
47};
48
49static unsigned int delkin_cb_init_chipset(struct pci_dev *dev)
50{
51 unsigned long base = pci_resource_start(dev, 0);
52 int i;
53
54 outb(0x02, base + 0x1e); /* set nIEN to block interrupts */
55 inb(base + 0x17); /* read status to clear interrupts */
56
57 for (i = 0; i < sizeof(setup); ++i) {
58 if (setup[i])
59 outb(setup[i], base + i);
60 }
61
62 return 0;
63}
64
65static const struct ide_port_info delkin_cb_port_info = {
66 .port_ops = &delkin_cb_port_ops,
67 .host_flags = IDE_HFLAG_IO_32BIT | IDE_HFLAG_UNMASK_IRQS |
68 IDE_HFLAG_NO_DMA,
69 .init_chipset = delkin_cb_init_chipset,
70};
71
72static int __devinit
73delkin_cb_probe (struct pci_dev *dev, const struct pci_device_id *id)
74{
75 struct ide_host *host;
76 unsigned long base;
77 int rc;
78 hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
79
80 rc = pci_enable_device(dev);
81 if (rc) {
82 printk(KERN_ERR "delkin_cb: pci_enable_device failed (%d)\n", rc);
83 return rc;
84 }
85 rc = pci_request_regions(dev, "delkin_cb");
86 if (rc) {
87 printk(KERN_ERR "delkin_cb: pci_request_regions failed (%d)\n", rc);
88 pci_disable_device(dev);
89 return rc;
90 }
91 base = pci_resource_start(dev, 0);
92
93 delkin_cb_init_chipset(dev);
94
95 memset(&hw, 0, sizeof(hw));
96 ide_std_init_ports(&hw, base + 0x10, base + 0x1e);
97 hw.irq = dev->irq;
98 hw.dev = &dev->dev;
99 hw.chipset = ide_pci; /* this enables IRQ sharing */
100
101 rc = ide_host_add(&delkin_cb_port_info, hws, &host);
102 if (rc)
103 goto out_disable;
104
105 pci_set_drvdata(dev, host);
106
107 return 0;
108
109out_disable:
110 pci_release_regions(dev);
111 pci_disable_device(dev);
112 return rc;
113}
114
115static void
116delkin_cb_remove (struct pci_dev *dev)
117{
118 struct ide_host *host = pci_get_drvdata(dev);
119
120 ide_host_remove(host);
121
122 pci_release_regions(dev);
123 pci_disable_device(dev);
124}
125
126#ifdef CONFIG_PM
127static int delkin_cb_suspend(struct pci_dev *dev, pm_message_t state)
128{
129 pci_save_state(dev);
130 pci_disable_device(dev);
131 pci_set_power_state(dev, pci_choose_state(dev, state));
132
133 return 0;
134}
135
136static int delkin_cb_resume(struct pci_dev *dev)
137{
138 struct ide_host *host = pci_get_drvdata(dev);
139 int rc;
140
141 pci_set_power_state(dev, PCI_D0);
142
143 rc = pci_enable_device(dev);
144 if (rc)
145 return rc;
146
147 pci_restore_state(dev);
148 pci_set_master(dev);
149
150 if (host->init_chipset)
151 host->init_chipset(dev);
152
153 return 0;
154}
155#else
156#define delkin_cb_suspend NULL
157#define delkin_cb_resume NULL
158#endif
159
160static struct pci_device_id delkin_cb_pci_tbl[] __devinitdata = {
161 { 0x1145, 0xf021, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
162 { 0x1145, 0xf024, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
163 { 0, },
164};
165MODULE_DEVICE_TABLE(pci, delkin_cb_pci_tbl);
166
167static struct pci_driver delkin_cb_pci_driver = {
168 .name = "Delkin-ASKA-Workbit Cardbus IDE",
169 .id_table = delkin_cb_pci_tbl,
170 .probe = delkin_cb_probe,
171 .remove = delkin_cb_remove,
172 .suspend = delkin_cb_suspend,
173 .resume = delkin_cb_resume,
174};
175
176static int __init delkin_cb_init(void)
177{
178 return pci_register_driver(&delkin_cb_pci_driver);
179}
180
181static void __exit delkin_cb_exit(void)
182{
183 pci_unregister_driver(&delkin_cb_pci_driver);
184}
185
186module_init(delkin_cb_init);
187module_exit(delkin_cb_exit);
188
189MODULE_AUTHOR("Mark Lord");
190MODULE_DESCRIPTION("Basic support for Delkin/ASKA/Workbit Cardbus IDE");
191MODULE_LICENSE("GPL");
192
diff --git a/drivers/ide/pci/generic.c b/drivers/ide/pci/generic.c
deleted file mode 100644
index 474f96a7c076..000000000000
--- a/drivers/ide/pci/generic.c
+++ /dev/null
@@ -1,193 +0,0 @@
1/*
2 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
3 * Portions (C) Copyright 2002 Red Hat Inc <alan@redhat.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * For the avoidance of doubt the "preferred form" of this code is one which
16 * is in an open non patent encumbered format. Where cryptographic key signing
17 * forms part of the process of creating an executable the information
18 * including keys needed to generate an equivalently functional executable
19 * are deemed to be part of the source code.
20 */
21
22#include <linux/types.h>
23#include <linux/module.h>
24#include <linux/kernel.h>
25#include <linux/pci.h>
26#include <linux/ide.h>
27#include <linux/init.h>
28
29#define DRV_NAME "ide_pci_generic"
30
31static int ide_generic_all; /* Set to claim all devices */
32
33module_param_named(all_generic_ide, ide_generic_all, bool, 0444);
34MODULE_PARM_DESC(all_generic_ide, "IDE generic will claim all unknown PCI IDE storage controllers.");
35
36#define IDE_HFLAGS_UMC (IDE_HFLAG_NO_DMA | IDE_HFLAG_FORCE_LEGACY_IRQS)
37
38#define DECLARE_GENERIC_PCI_DEV(extra_flags) \
39 { \
40 .name = DRV_NAME, \
41 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA | \
42 extra_flags, \
43 .swdma_mask = ATA_SWDMA2, \
44 .mwdma_mask = ATA_MWDMA2, \
45 .udma_mask = ATA_UDMA6, \
46 }
47
48static const struct ide_port_info generic_chipsets[] __devinitdata = {
49 /* 0: Unknown */
50 DECLARE_GENERIC_PCI_DEV(0),
51
52 { /* 1: NS87410 */
53 .name = DRV_NAME,
54 .enablebits = { {0x43, 0x08, 0x08}, {0x47, 0x08, 0x08} },
55 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA,
56 .swdma_mask = ATA_SWDMA2,
57 .mwdma_mask = ATA_MWDMA2,
58 .udma_mask = ATA_UDMA6,
59 },
60
61 /* 2: SAMURAI / HT6565 / HINT_IDE */
62 DECLARE_GENERIC_PCI_DEV(0),
63 /* 3: UM8673F / UM8886A / UM8886BF */
64 DECLARE_GENERIC_PCI_DEV(IDE_HFLAGS_UMC),
65 /* 4: VIA_IDE / OPTI621V / Piccolo010{2,3,5} */
66 DECLARE_GENERIC_PCI_DEV(IDE_HFLAG_NO_AUTODMA),
67
68 { /* 5: VIA8237SATA */
69 .name = DRV_NAME,
70 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA |
71 IDE_HFLAG_OFF_BOARD,
72 .swdma_mask = ATA_SWDMA2,
73 .mwdma_mask = ATA_MWDMA2,
74 .udma_mask = ATA_UDMA6,
75 },
76
77 { /* 6: Revolution */
78 .name = DRV_NAME,
79 .host_flags = IDE_HFLAG_CLEAR_SIMPLEX |
80 IDE_HFLAG_TRUST_BIOS_FOR_DMA |
81 IDE_HFLAG_OFF_BOARD,
82 .swdma_mask = ATA_SWDMA2,
83 .mwdma_mask = ATA_MWDMA2,
84 .udma_mask = ATA_UDMA6,
85 }
86};
87
88/**
89 * generic_init_one - called when a PIIX is found
90 * @dev: the generic device
91 * @id: the matching pci id
92 *
93 * Called when the PCI registration layer (or the IDE initialization)
94 * finds a device matching our IDE device tables.
95 */
96
97static int __devinit generic_init_one(struct pci_dev *dev, const struct pci_device_id *id)
98{
99 const struct ide_port_info *d = &generic_chipsets[id->driver_data];
100 int ret = -ENODEV;
101
102 /* Don't use the generic entry unless instructed to do so */
103 if (id->driver_data == 0 && ide_generic_all == 0)
104 goto out;
105
106 switch (dev->vendor) {
107 case PCI_VENDOR_ID_UMC:
108 if (dev->device == PCI_DEVICE_ID_UMC_UM8886A &&
109 !(PCI_FUNC(dev->devfn) & 1))
110 goto out; /* UM8886A/BF pair */
111 break;
112 case PCI_VENDOR_ID_OPTI:
113 if (dev->device == PCI_DEVICE_ID_OPTI_82C558 &&
114 !(PCI_FUNC(dev->devfn) & 1))
115 goto out;
116 break;
117 case PCI_VENDOR_ID_JMICRON:
118 if (dev->device != PCI_DEVICE_ID_JMICRON_JMB368 &&
119 PCI_FUNC(dev->devfn) != 1)
120 goto out;
121 break;
122 case PCI_VENDOR_ID_NS:
123 if (dev->device == PCI_DEVICE_ID_NS_87410 &&
124 (dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
125 goto out;
126 break;
127 }
128
129 if (dev->vendor != PCI_VENDOR_ID_JMICRON) {
130 u16 command;
131 pci_read_config_word(dev, PCI_COMMAND, &command);
132 if (!(command & PCI_COMMAND_IO)) {
133 printk(KERN_INFO "%s %s: skipping disabled "
134 "controller\n", d->name, pci_name(dev));
135 goto out;
136 }
137 }
138 ret = ide_pci_init_one(dev, d, NULL);
139out:
140 return ret;
141}
142
143static const struct pci_device_id generic_pci_tbl[] = {
144 { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87410), 1 },
145 { PCI_VDEVICE(PCTECH, PCI_DEVICE_ID_PCTECH_SAMURAI_IDE), 2 },
146 { PCI_VDEVICE(HOLTEK, PCI_DEVICE_ID_HOLTEK_6565), 2 },
147 { PCI_VDEVICE(UMC, PCI_DEVICE_ID_UMC_UM8673F), 3 },
148 { PCI_VDEVICE(UMC, PCI_DEVICE_ID_UMC_UM8886A), 3 },
149 { PCI_VDEVICE(UMC, PCI_DEVICE_ID_UMC_UM8886BF), 3 },
150 { PCI_VDEVICE(HINT, PCI_DEVICE_ID_HINT_VXPROII_IDE), 2 },
151 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C561), 4 },
152 { PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C558), 4 },
153#ifdef CONFIG_BLK_DEV_IDE_SATA
154 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_8237_SATA), 5 },
155#endif
156 { PCI_VDEVICE(TOSHIBA, PCI_DEVICE_ID_TOSHIBA_PICCOLO), 4 },
157 { PCI_VDEVICE(TOSHIBA, PCI_DEVICE_ID_TOSHIBA_PICCOLO_1), 4 },
158 { PCI_VDEVICE(TOSHIBA, PCI_DEVICE_ID_TOSHIBA_PICCOLO_2), 4 },
159 { PCI_VDEVICE(NETCELL, PCI_DEVICE_ID_REVOLUTION), 6 },
160 /*
161 * Must come last. If you add entries adjust
162 * this table and generic_chipsets[] appropriately.
163 */
164 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE << 8, 0xFFFFFF00UL, 0 },
165 { 0, },
166};
167MODULE_DEVICE_TABLE(pci, generic_pci_tbl);
168
169static struct pci_driver generic_pci_driver = {
170 .name = "PCI_IDE",
171 .id_table = generic_pci_tbl,
172 .probe = generic_init_one,
173 .remove = ide_pci_remove,
174 .suspend = ide_pci_suspend,
175 .resume = ide_pci_resume,
176};
177
178static int __init generic_ide_init(void)
179{
180 return ide_pci_register_driver(&generic_pci_driver);
181}
182
183static void __exit generic_ide_exit(void)
184{
185 pci_unregister_driver(&generic_pci_driver);
186}
187
188module_init(generic_ide_init);
189module_exit(generic_ide_exit);
190
191MODULE_AUTHOR("Andre Hedrick");
192MODULE_DESCRIPTION("PCI driver module for generic PCI IDE");
193MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/hpt366.c b/drivers/ide/pci/hpt366.c
deleted file mode 100644
index a7909e9c720e..000000000000
--- a/drivers/ide/pci/hpt366.c
+++ /dev/null
@@ -1,1643 +0,0 @@
1/*
2 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
3 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
4 * Portions Copyright (C) 2003 Red Hat Inc
5 * Portions Copyright (C) 2007 Bartlomiej Zolnierkiewicz
6 * Portions Copyright (C) 2005-2008 MontaVista Software, Inc.
7 *
8 * Thanks to HighPoint Technologies for their assistance, and hardware.
9 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
10 * donation of an ABit BP6 mainboard, processor, and memory acellerated
11 * development and support.
12 *
13 *
14 * HighPoint has its own drivers (open source except for the RAID part)
15 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
16 * This may be useful to anyone wanting to work on this driver, however do not
17 * trust them too much since the code tends to become less and less meaningful
18 * as the time passes... :-/
19 *
20 * Note that final HPT370 support was done by force extraction of GPL.
21 *
22 * - add function for getting/setting power status of drive
23 * - the HPT370's state machine can get confused. reset it before each dma
24 * xfer to prevent that from happening.
25 * - reset state engine whenever we get an error.
26 * - check for busmaster state at end of dma.
27 * - use new highpoint timings.
28 * - detect bus speed using highpoint register.
29 * - use pll if we don't have a clock table. added a 66MHz table that's
30 * just 2x the 33MHz table.
31 * - removed turnaround. NOTE: we never want to switch between pll and
32 * pci clocks as the chip can glitch in those cases. the highpoint
33 * approved workaround slows everything down too much to be useful. in
34 * addition, we would have to serialize access to each chip.
35 * Adrian Sun <a.sun@sun.com>
36 *
37 * add drive timings for 66MHz PCI bus,
38 * fix ATA Cable signal detection, fix incorrect /proc info
39 * add /proc display for per-drive PIO/DMA/UDMA mode and
40 * per-channel ATA-33/66 Cable detect.
41 * Duncan Laurie <void@sun.com>
42 *
43 * fixup /proc output for multiple controllers
44 * Tim Hockin <thockin@sun.com>
45 *
46 * On hpt366:
47 * Reset the hpt366 on error, reset on dma
48 * Fix disabling Fast Interrupt hpt366.
49 * Mike Waychison <crlf@sun.com>
50 *
51 * Added support for 372N clocking and clock switching. The 372N needs
52 * different clocks on read/write. This requires overloading rw_disk and
53 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
54 * keeping me sane.
55 * Alan Cox <alan@redhat.com>
56 *
57 * - fix the clock turnaround code: it was writing to the wrong ports when
58 * called for the secondary channel, caching the current clock mode per-
59 * channel caused the cached register value to get out of sync with the
60 * actual one, the channels weren't serialized, the turnaround shouldn't
61 * be done on 66 MHz PCI bus
62 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
63 * does not allow for this speed anyway
64 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
65 * their primary channel is kind of virtual, it isn't tied to any pins)
66 * - fix/remove bad/unused timing tables and use one set of tables for the whole
67 * HPT37x chip family; save space by introducing the separate transfer mode
68 * table in which the mode lookup is done
69 * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives
70 * the wrong PCI frequency since DPLL has already been calibrated by BIOS;
71 * read it only from the function 0 of HPT374 chips
72 * - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
73 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
74 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
75 * they tamper with its fields
76 * - pass to the init_setup handlers a copy of the ide_pci_device_t structure
77 * since they may tamper with its fields
78 * - prefix the driver startup messages with the real chip name
79 * - claim the extra 240 bytes of I/O space for all chips
80 * - optimize the UltraDMA filtering and the drive list lookup code
81 * - use pci_get_slot() to get to the function 1 of HPT36x/374
82 * - cache offset of the channel's misc. control registers (MCRs) being used
83 * throughout the driver
84 * - only touch the relevant MCR when detecting the cable type on HPT374's
85 * function 1
86 * - rename all the register related variables consistently
87 * - move all the interrupt twiddling code from the speedproc handlers into
88 * init_hwif_hpt366(), also grouping all the DMA related code together there
89 * - merge HPT36x/HPT37x speedproc handlers, fix PIO timing register mask and
90 * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
91 * when setting an UltraDMA mode
92 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
93 * the best possible one
94 * - clean up DMA timeout handling for HPT370
95 * - switch to using the enumeration type to differ between the numerous chip
96 * variants, matching PCI device/revision ID with the chip type early, at the
97 * init_setup stage
98 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
99 * stop duplicating it for each channel by storing the pointer in the pci_dev
100 * structure: first, at the init_setup stage, point it to a static "template"
101 * with only the chip type and its specific base DPLL frequency, the highest
102 * UltraDMA mode, and the chip settings table pointer filled, then, at the
103 * init_chipset stage, allocate per-chip instance and fill it with the rest
104 * of the necessary information
105 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
106 * switch to calculating PCI clock frequency based on the chip's base DPLL
107 * frequency
108 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
109 * anything newer than HPT370/A (except HPT374 that is not capable of this
110 * mode according to the manual)
111 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
112 * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
113 * unify HPT36x/37x timing setup code and the speedproc handlers by joining
114 * the register setting lists into the table indexed by the clock selected
115 * - set the correct hwif->ultra_mask for each individual chip
116 * - add Ultra and MW DMA mode filtering for the HPT37[24] based SATA cards
117 * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
118 */
119
120#include <linux/types.h>
121#include <linux/module.h>
122#include <linux/kernel.h>
123#include <linux/delay.h>
124#include <linux/blkdev.h>
125#include <linux/interrupt.h>
126#include <linux/pci.h>
127#include <linux/init.h>
128#include <linux/ide.h>
129
130#include <asm/uaccess.h>
131#include <asm/io.h>
132
133#define DRV_NAME "hpt366"
134
135/* various tuning parameters */
136#define HPT_RESET_STATE_ENGINE
137#undef HPT_DELAY_INTERRUPT
138#define HPT_SERIALIZE_IO 0
139
140static const char *quirk_drives[] = {
141 "QUANTUM FIREBALLlct08 08",
142 "QUANTUM FIREBALLP KA6.4",
143 "QUANTUM FIREBALLP LM20.4",
144 "QUANTUM FIREBALLP LM20.5",
145 NULL
146};
147
148static const char *bad_ata100_5[] = {
149 "IBM-DTLA-307075",
150 "IBM-DTLA-307060",
151 "IBM-DTLA-307045",
152 "IBM-DTLA-307030",
153 "IBM-DTLA-307020",
154 "IBM-DTLA-307015",
155 "IBM-DTLA-305040",
156 "IBM-DTLA-305030",
157 "IBM-DTLA-305020",
158 "IC35L010AVER07-0",
159 "IC35L020AVER07-0",
160 "IC35L030AVER07-0",
161 "IC35L040AVER07-0",
162 "IC35L060AVER07-0",
163 "WDC AC310200R",
164 NULL
165};
166
167static const char *bad_ata66_4[] = {
168 "IBM-DTLA-307075",
169 "IBM-DTLA-307060",
170 "IBM-DTLA-307045",
171 "IBM-DTLA-307030",
172 "IBM-DTLA-307020",
173 "IBM-DTLA-307015",
174 "IBM-DTLA-305040",
175 "IBM-DTLA-305030",
176 "IBM-DTLA-305020",
177 "IC35L010AVER07-0",
178 "IC35L020AVER07-0",
179 "IC35L030AVER07-0",
180 "IC35L040AVER07-0",
181 "IC35L060AVER07-0",
182 "WDC AC310200R",
183 "MAXTOR STM3320620A",
184 NULL
185};
186
187static const char *bad_ata66_3[] = {
188 "WDC AC310200R",
189 NULL
190};
191
192static const char *bad_ata33[] = {
193 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
194 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
195 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
196 "Maxtor 90510D4",
197 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
198 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
199 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
200 NULL
201};
202
203static u8 xfer_speeds[] = {
204 XFER_UDMA_6,
205 XFER_UDMA_5,
206 XFER_UDMA_4,
207 XFER_UDMA_3,
208 XFER_UDMA_2,
209 XFER_UDMA_1,
210 XFER_UDMA_0,
211
212 XFER_MW_DMA_2,
213 XFER_MW_DMA_1,
214 XFER_MW_DMA_0,
215
216 XFER_PIO_4,
217 XFER_PIO_3,
218 XFER_PIO_2,
219 XFER_PIO_1,
220 XFER_PIO_0
221};
222
223/* Key for bus clock timings
224 * 36x 37x
225 * bits bits
226 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
227 * cycles = value + 1
228 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
229 * cycles = value + 1
230 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
231 * register access.
232 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
233 * register access.
234 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
235 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
236 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
237 * MW DMA xfer.
238 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
239 * task file register access.
240 * 28 28 UDMA enable.
241 * 29 29 DMA enable.
242 * 30 30 PIO MST enable. If set, the chip is in bus master mode during
243 * PIO xfer.
244 * 31 31 FIFO enable.
245 */
246
247static u32 forty_base_hpt36x[] = {
248 /* XFER_UDMA_6 */ 0x900fd943,
249 /* XFER_UDMA_5 */ 0x900fd943,
250 /* XFER_UDMA_4 */ 0x900fd943,
251 /* XFER_UDMA_3 */ 0x900ad943,
252 /* XFER_UDMA_2 */ 0x900bd943,
253 /* XFER_UDMA_1 */ 0x9008d943,
254 /* XFER_UDMA_0 */ 0x9008d943,
255
256 /* XFER_MW_DMA_2 */ 0xa008d943,
257 /* XFER_MW_DMA_1 */ 0xa010d955,
258 /* XFER_MW_DMA_0 */ 0xa010d9fc,
259
260 /* XFER_PIO_4 */ 0xc008d963,
261 /* XFER_PIO_3 */ 0xc010d974,
262 /* XFER_PIO_2 */ 0xc010d997,
263 /* XFER_PIO_1 */ 0xc010d9c7,
264 /* XFER_PIO_0 */ 0xc018d9d9
265};
266
267static u32 thirty_three_base_hpt36x[] = {
268 /* XFER_UDMA_6 */ 0x90c9a731,
269 /* XFER_UDMA_5 */ 0x90c9a731,
270 /* XFER_UDMA_4 */ 0x90c9a731,
271 /* XFER_UDMA_3 */ 0x90cfa731,
272 /* XFER_UDMA_2 */ 0x90caa731,
273 /* XFER_UDMA_1 */ 0x90cba731,
274 /* XFER_UDMA_0 */ 0x90c8a731,
275
276 /* XFER_MW_DMA_2 */ 0xa0c8a731,
277 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
278 /* XFER_MW_DMA_0 */ 0xa0c8a797,
279
280 /* XFER_PIO_4 */ 0xc0c8a731,
281 /* XFER_PIO_3 */ 0xc0c8a742,
282 /* XFER_PIO_2 */ 0xc0d0a753,
283 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
284 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
285};
286
287static u32 twenty_five_base_hpt36x[] = {
288 /* XFER_UDMA_6 */ 0x90c98521,
289 /* XFER_UDMA_5 */ 0x90c98521,
290 /* XFER_UDMA_4 */ 0x90c98521,
291 /* XFER_UDMA_3 */ 0x90cf8521,
292 /* XFER_UDMA_2 */ 0x90cf8521,
293 /* XFER_UDMA_1 */ 0x90cb8521,
294 /* XFER_UDMA_0 */ 0x90cb8521,
295
296 /* XFER_MW_DMA_2 */ 0xa0ca8521,
297 /* XFER_MW_DMA_1 */ 0xa0ca8532,
298 /* XFER_MW_DMA_0 */ 0xa0ca8575,
299
300 /* XFER_PIO_4 */ 0xc0ca8521,
301 /* XFER_PIO_3 */ 0xc0ca8532,
302 /* XFER_PIO_2 */ 0xc0ca8542,
303 /* XFER_PIO_1 */ 0xc0d08572,
304 /* XFER_PIO_0 */ 0xc0d08585
305};
306
307#if 0
308/* These are the timing tables from the HighPoint open source drivers... */
309static u32 thirty_three_base_hpt37x[] = {
310 /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */
311 /* XFER_UDMA_5 */ 0x12446231,
312 /* XFER_UDMA_4 */ 0x12446231,
313 /* XFER_UDMA_3 */ 0x126c6231,
314 /* XFER_UDMA_2 */ 0x12486231,
315 /* XFER_UDMA_1 */ 0x124c6233,
316 /* XFER_UDMA_0 */ 0x12506297,
317
318 /* XFER_MW_DMA_2 */ 0x22406c31,
319 /* XFER_MW_DMA_1 */ 0x22406c33,
320 /* XFER_MW_DMA_0 */ 0x22406c97,
321
322 /* XFER_PIO_4 */ 0x06414e31,
323 /* XFER_PIO_3 */ 0x06414e42,
324 /* XFER_PIO_2 */ 0x06414e53,
325 /* XFER_PIO_1 */ 0x06814e93,
326 /* XFER_PIO_0 */ 0x06814ea7
327};
328
329static u32 fifty_base_hpt37x[] = {
330 /* XFER_UDMA_6 */ 0x12848242,
331 /* XFER_UDMA_5 */ 0x12848242,
332 /* XFER_UDMA_4 */ 0x12ac8242,
333 /* XFER_UDMA_3 */ 0x128c8242,
334 /* XFER_UDMA_2 */ 0x120c8242,
335 /* XFER_UDMA_1 */ 0x12148254,
336 /* XFER_UDMA_0 */ 0x121882ea,
337
338 /* XFER_MW_DMA_2 */ 0x22808242,
339 /* XFER_MW_DMA_1 */ 0x22808254,
340 /* XFER_MW_DMA_0 */ 0x228082ea,
341
342 /* XFER_PIO_4 */ 0x0a81f442,
343 /* XFER_PIO_3 */ 0x0a81f443,
344 /* XFER_PIO_2 */ 0x0a81f454,
345 /* XFER_PIO_1 */ 0x0ac1f465,
346 /* XFER_PIO_0 */ 0x0ac1f48a
347};
348
349static u32 sixty_six_base_hpt37x[] = {
350 /* XFER_UDMA_6 */ 0x1c869c62,
351 /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */
352 /* XFER_UDMA_4 */ 0x1c8a9c62,
353 /* XFER_UDMA_3 */ 0x1c8e9c62,
354 /* XFER_UDMA_2 */ 0x1c929c62,
355 /* XFER_UDMA_1 */ 0x1c9a9c62,
356 /* XFER_UDMA_0 */ 0x1c829c62,
357
358 /* XFER_MW_DMA_2 */ 0x2c829c62,
359 /* XFER_MW_DMA_1 */ 0x2c829c66,
360 /* XFER_MW_DMA_0 */ 0x2c829d2e,
361
362 /* XFER_PIO_4 */ 0x0c829c62,
363 /* XFER_PIO_3 */ 0x0c829c84,
364 /* XFER_PIO_2 */ 0x0c829ca6,
365 /* XFER_PIO_1 */ 0x0d029d26,
366 /* XFER_PIO_0 */ 0x0d029d5e
367};
368#else
369/*
370 * The following are the new timing tables with PIO mode data/taskfile transfer
371 * overclocking fixed...
372 */
373
374/* This table is taken from the HPT370 data manual rev. 1.02 */
375static u32 thirty_three_base_hpt37x[] = {
376 /* XFER_UDMA_6 */ 0x16455031, /* 0x16655031 ?? */
377 /* XFER_UDMA_5 */ 0x16455031,
378 /* XFER_UDMA_4 */ 0x16455031,
379 /* XFER_UDMA_3 */ 0x166d5031,
380 /* XFER_UDMA_2 */ 0x16495031,
381 /* XFER_UDMA_1 */ 0x164d5033,
382 /* XFER_UDMA_0 */ 0x16515097,
383
384 /* XFER_MW_DMA_2 */ 0x26515031,
385 /* XFER_MW_DMA_1 */ 0x26515033,
386 /* XFER_MW_DMA_0 */ 0x26515097,
387
388 /* XFER_PIO_4 */ 0x06515021,
389 /* XFER_PIO_3 */ 0x06515022,
390 /* XFER_PIO_2 */ 0x06515033,
391 /* XFER_PIO_1 */ 0x06915065,
392 /* XFER_PIO_0 */ 0x06d1508a
393};
394
395static u32 fifty_base_hpt37x[] = {
396 /* XFER_UDMA_6 */ 0x1a861842,
397 /* XFER_UDMA_5 */ 0x1a861842,
398 /* XFER_UDMA_4 */ 0x1aae1842,
399 /* XFER_UDMA_3 */ 0x1a8e1842,
400 /* XFER_UDMA_2 */ 0x1a0e1842,
401 /* XFER_UDMA_1 */ 0x1a161854,
402 /* XFER_UDMA_0 */ 0x1a1a18ea,
403
404 /* XFER_MW_DMA_2 */ 0x2a821842,
405 /* XFER_MW_DMA_1 */ 0x2a821854,
406 /* XFER_MW_DMA_0 */ 0x2a8218ea,
407
408 /* XFER_PIO_4 */ 0x0a821842,
409 /* XFER_PIO_3 */ 0x0a821843,
410 /* XFER_PIO_2 */ 0x0a821855,
411 /* XFER_PIO_1 */ 0x0ac218a8,
412 /* XFER_PIO_0 */ 0x0b02190c
413};
414
415static u32 sixty_six_base_hpt37x[] = {
416 /* XFER_UDMA_6 */ 0x1c86fe62,
417 /* XFER_UDMA_5 */ 0x1caefe62, /* 0x1c8afe62 */
418 /* XFER_UDMA_4 */ 0x1c8afe62,
419 /* XFER_UDMA_3 */ 0x1c8efe62,
420 /* XFER_UDMA_2 */ 0x1c92fe62,
421 /* XFER_UDMA_1 */ 0x1c9afe62,
422 /* XFER_UDMA_0 */ 0x1c82fe62,
423
424 /* XFER_MW_DMA_2 */ 0x2c82fe62,
425 /* XFER_MW_DMA_1 */ 0x2c82fe66,
426 /* XFER_MW_DMA_0 */ 0x2c82ff2e,
427
428 /* XFER_PIO_4 */ 0x0c82fe62,
429 /* XFER_PIO_3 */ 0x0c82fe84,
430 /* XFER_PIO_2 */ 0x0c82fea6,
431 /* XFER_PIO_1 */ 0x0d02ff26,
432 /* XFER_PIO_0 */ 0x0d42ff7f
433};
434#endif
435
436#define HPT366_DEBUG_DRIVE_INFO 0
437#define HPT371_ALLOW_ATA133_6 1
438#define HPT302_ALLOW_ATA133_6 1
439#define HPT372_ALLOW_ATA133_6 1
440#define HPT370_ALLOW_ATA100_5 0
441#define HPT366_ALLOW_ATA66_4 1
442#define HPT366_ALLOW_ATA66_3 1
443#define HPT366_MAX_DEVS 8
444
445/* Supported ATA clock frequencies */
446enum ata_clock {
447 ATA_CLOCK_25MHZ,
448 ATA_CLOCK_33MHZ,
449 ATA_CLOCK_40MHZ,
450 ATA_CLOCK_50MHZ,
451 ATA_CLOCK_66MHZ,
452 NUM_ATA_CLOCKS
453};
454
455struct hpt_timings {
456 u32 pio_mask;
457 u32 dma_mask;
458 u32 ultra_mask;
459 u32 *clock_table[NUM_ATA_CLOCKS];
460};
461
462/*
463 * Hold all the HighPoint chip information in one place.
464 */
465
466struct hpt_info {
467 char *chip_name; /* Chip name */
468 u8 chip_type; /* Chip type */
469 u8 udma_mask; /* Allowed UltraDMA modes mask. */
470 u8 dpll_clk; /* DPLL clock in MHz */
471 u8 pci_clk; /* PCI clock in MHz */
472 struct hpt_timings *timings; /* Chipset timing data */
473 u8 clock; /* ATA clock selected */
474};
475
476/* Supported HighPoint chips */
477enum {
478 HPT36x,
479 HPT370,
480 HPT370A,
481 HPT374,
482 HPT372,
483 HPT372A,
484 HPT302,
485 HPT371,
486 HPT372N,
487 HPT302N,
488 HPT371N
489};
490
491static struct hpt_timings hpt36x_timings = {
492 .pio_mask = 0xc1f8ffff,
493 .dma_mask = 0x303800ff,
494 .ultra_mask = 0x30070000,
495 .clock_table = {
496 [ATA_CLOCK_25MHZ] = twenty_five_base_hpt36x,
497 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt36x,
498 [ATA_CLOCK_40MHZ] = forty_base_hpt36x,
499 [ATA_CLOCK_50MHZ] = NULL,
500 [ATA_CLOCK_66MHZ] = NULL
501 }
502};
503
504static struct hpt_timings hpt37x_timings = {
505 .pio_mask = 0xcfc3ffff,
506 .dma_mask = 0x31c001ff,
507 .ultra_mask = 0x303c0000,
508 .clock_table = {
509 [ATA_CLOCK_25MHZ] = NULL,
510 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt37x,
511 [ATA_CLOCK_40MHZ] = NULL,
512 [ATA_CLOCK_50MHZ] = fifty_base_hpt37x,
513 [ATA_CLOCK_66MHZ] = sixty_six_base_hpt37x
514 }
515};
516
517static const struct hpt_info hpt36x __devinitdata = {
518 .chip_name = "HPT36x",
519 .chip_type = HPT36x,
520 .udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2,
521 .dpll_clk = 0, /* no DPLL */
522 .timings = &hpt36x_timings
523};
524
525static const struct hpt_info hpt370 __devinitdata = {
526 .chip_name = "HPT370",
527 .chip_type = HPT370,
528 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
529 .dpll_clk = 48,
530 .timings = &hpt37x_timings
531};
532
533static const struct hpt_info hpt370a __devinitdata = {
534 .chip_name = "HPT370A",
535 .chip_type = HPT370A,
536 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
537 .dpll_clk = 48,
538 .timings = &hpt37x_timings
539};
540
541static const struct hpt_info hpt374 __devinitdata = {
542 .chip_name = "HPT374",
543 .chip_type = HPT374,
544 .udma_mask = ATA_UDMA5,
545 .dpll_clk = 48,
546 .timings = &hpt37x_timings
547};
548
549static const struct hpt_info hpt372 __devinitdata = {
550 .chip_name = "HPT372",
551 .chip_type = HPT372,
552 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
553 .dpll_clk = 55,
554 .timings = &hpt37x_timings
555};
556
557static const struct hpt_info hpt372a __devinitdata = {
558 .chip_name = "HPT372A",
559 .chip_type = HPT372A,
560 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
561 .dpll_clk = 66,
562 .timings = &hpt37x_timings
563};
564
565static const struct hpt_info hpt302 __devinitdata = {
566 .chip_name = "HPT302",
567 .chip_type = HPT302,
568 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
569 .dpll_clk = 66,
570 .timings = &hpt37x_timings
571};
572
573static const struct hpt_info hpt371 __devinitdata = {
574 .chip_name = "HPT371",
575 .chip_type = HPT371,
576 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
577 .dpll_clk = 66,
578 .timings = &hpt37x_timings
579};
580
581static const struct hpt_info hpt372n __devinitdata = {
582 .chip_name = "HPT372N",
583 .chip_type = HPT372N,
584 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
585 .dpll_clk = 77,
586 .timings = &hpt37x_timings
587};
588
589static const struct hpt_info hpt302n __devinitdata = {
590 .chip_name = "HPT302N",
591 .chip_type = HPT302N,
592 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
593 .dpll_clk = 77,
594 .timings = &hpt37x_timings
595};
596
597static const struct hpt_info hpt371n __devinitdata = {
598 .chip_name = "HPT371N",
599 .chip_type = HPT371N,
600 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
601 .dpll_clk = 77,
602 .timings = &hpt37x_timings
603};
604
605static int check_in_drive_list(ide_drive_t *drive, const char **list)
606{
607 char *m = (char *)&drive->id[ATA_ID_PROD];
608
609 while (*list)
610 if (!strcmp(*list++, m))
611 return 1;
612 return 0;
613}
614
615static struct hpt_info *hpt3xx_get_info(struct device *dev)
616{
617 struct ide_host *host = dev_get_drvdata(dev);
618 struct hpt_info *info = (struct hpt_info *)host->host_priv;
619
620 return dev == host->dev[1] ? info + 1 : info;
621}
622
623/*
624 * The Marvell bridge chips used on the HighPoint SATA cards do not seem
625 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
626 */
627
628static u8 hpt3xx_udma_filter(ide_drive_t *drive)
629{
630 ide_hwif_t *hwif = HWIF(drive);
631 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
632 u8 mask = hwif->ultra_mask;
633
634 switch (info->chip_type) {
635 case HPT36x:
636 if (!HPT366_ALLOW_ATA66_4 ||
637 check_in_drive_list(drive, bad_ata66_4))
638 mask = ATA_UDMA3;
639
640 if (!HPT366_ALLOW_ATA66_3 ||
641 check_in_drive_list(drive, bad_ata66_3))
642 mask = ATA_UDMA2;
643 break;
644 case HPT370:
645 if (!HPT370_ALLOW_ATA100_5 ||
646 check_in_drive_list(drive, bad_ata100_5))
647 mask = ATA_UDMA4;
648 break;
649 case HPT370A:
650 if (!HPT370_ALLOW_ATA100_5 ||
651 check_in_drive_list(drive, bad_ata100_5))
652 return ATA_UDMA4;
653 case HPT372 :
654 case HPT372A:
655 case HPT372N:
656 case HPT374 :
657 if (ata_id_is_sata(drive->id))
658 mask &= ~0x0e;
659 /* Fall thru */
660 default:
661 return mask;
662 }
663
664 return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask;
665}
666
667static u8 hpt3xx_mdma_filter(ide_drive_t *drive)
668{
669 ide_hwif_t *hwif = HWIF(drive);
670 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
671
672 switch (info->chip_type) {
673 case HPT372 :
674 case HPT372A:
675 case HPT372N:
676 case HPT374 :
677 if (ata_id_is_sata(drive->id))
678 return 0x00;
679 /* Fall thru */
680 default:
681 return 0x07;
682 }
683}
684
685static u32 get_speed_setting(u8 speed, struct hpt_info *info)
686{
687 int i;
688
689 /*
690 * Lookup the transfer mode table to get the index into
691 * the timing table.
692 *
693 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
694 */
695 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
696 if (xfer_speeds[i] == speed)
697 break;
698
699 return info->timings->clock_table[info->clock][i];
700}
701
702static void hpt3xx_set_mode(ide_drive_t *drive, const u8 speed)
703{
704 ide_hwif_t *hwif = drive->hwif;
705 struct pci_dev *dev = to_pci_dev(hwif->dev);
706 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
707 struct hpt_timings *t = info->timings;
708 u8 itr_addr = 0x40 + (drive->dn * 4);
709 u32 old_itr = 0;
710 u32 new_itr = get_speed_setting(speed, info);
711 u32 itr_mask = speed < XFER_MW_DMA_0 ? t->pio_mask :
712 (speed < XFER_UDMA_0 ? t->dma_mask :
713 t->ultra_mask);
714
715 pci_read_config_dword(dev, itr_addr, &old_itr);
716 new_itr = (old_itr & ~itr_mask) | (new_itr & itr_mask);
717 /*
718 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
719 * to avoid problems handling I/O errors later
720 */
721 new_itr &= ~0xc0000000;
722
723 pci_write_config_dword(dev, itr_addr, new_itr);
724}
725
726static void hpt3xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
727{
728 hpt3xx_set_mode(drive, XFER_PIO_0 + pio);
729}
730
731static void hpt3xx_quirkproc(ide_drive_t *drive)
732{
733 char *m = (char *)&drive->id[ATA_ID_PROD];
734 const char **list = quirk_drives;
735
736 while (*list)
737 if (strstr(m, *list++)) {
738 drive->quirk_list = 1;
739 return;
740 }
741
742 drive->quirk_list = 0;
743}
744
745static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
746{
747 ide_hwif_t *hwif = HWIF(drive);
748 struct pci_dev *dev = to_pci_dev(hwif->dev);
749 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
750
751 if (drive->quirk_list == 0)
752 return;
753
754 if (info->chip_type >= HPT370) {
755 u8 scr1 = 0;
756
757 pci_read_config_byte(dev, 0x5a, &scr1);
758 if (((scr1 & 0x10) >> 4) != mask) {
759 if (mask)
760 scr1 |= 0x10;
761 else
762 scr1 &= ~0x10;
763 pci_write_config_byte(dev, 0x5a, scr1);
764 }
765 } else if (mask)
766 disable_irq(hwif->irq);
767 else
768 enable_irq(hwif->irq);
769}
770
771/*
772 * This is specific to the HPT366 UDMA chipset
773 * by HighPoint|Triones Technologies, Inc.
774 */
775static void hpt366_dma_lost_irq(ide_drive_t *drive)
776{
777 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
778 u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
779
780 pci_read_config_byte(dev, 0x50, &mcr1);
781 pci_read_config_byte(dev, 0x52, &mcr3);
782 pci_read_config_byte(dev, 0x5a, &scr1);
783 printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
784 drive->name, __func__, mcr1, mcr3, scr1);
785 if (scr1 & 0x10)
786 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
787 ide_dma_lost_irq(drive);
788}
789
790static void hpt370_clear_engine(ide_drive_t *drive)
791{
792 ide_hwif_t *hwif = HWIF(drive);
793 struct pci_dev *dev = to_pci_dev(hwif->dev);
794
795 pci_write_config_byte(dev, hwif->select_data, 0x37);
796 udelay(10);
797}
798
799static void hpt370_irq_timeout(ide_drive_t *drive)
800{
801 ide_hwif_t *hwif = HWIF(drive);
802 struct pci_dev *dev = to_pci_dev(hwif->dev);
803 u16 bfifo = 0;
804 u8 dma_cmd;
805
806 pci_read_config_word(dev, hwif->select_data + 2, &bfifo);
807 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);
808
809 /* get DMA command mode */
810 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
811 /* stop DMA */
812 outb(dma_cmd & ~0x1, hwif->dma_base + ATA_DMA_CMD);
813 hpt370_clear_engine(drive);
814}
815
816static void hpt370_dma_start(ide_drive_t *drive)
817{
818#ifdef HPT_RESET_STATE_ENGINE
819 hpt370_clear_engine(drive);
820#endif
821 ide_dma_start(drive);
822}
823
824static int hpt370_dma_end(ide_drive_t *drive)
825{
826 ide_hwif_t *hwif = HWIF(drive);
827 u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
828
829 if (dma_stat & 0x01) {
830 /* wait a little */
831 udelay(20);
832 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
833 if (dma_stat & 0x01)
834 hpt370_irq_timeout(drive);
835 }
836 return ide_dma_end(drive);
837}
838
839static void hpt370_dma_timeout(ide_drive_t *drive)
840{
841 hpt370_irq_timeout(drive);
842 ide_dma_timeout(drive);
843}
844
845/* returns 1 if DMA IRQ issued, 0 otherwise */
846static int hpt374_dma_test_irq(ide_drive_t *drive)
847{
848 ide_hwif_t *hwif = HWIF(drive);
849 struct pci_dev *dev = to_pci_dev(hwif->dev);
850 u16 bfifo = 0;
851 u8 dma_stat;
852
853 pci_read_config_word(dev, hwif->select_data + 2, &bfifo);
854 if (bfifo & 0x1FF) {
855// printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
856 return 0;
857 }
858
859 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
860 /* return 1 if INTR asserted */
861 if (dma_stat & 4)
862 return 1;
863
864 return 0;
865}
866
867static int hpt374_dma_end(ide_drive_t *drive)
868{
869 ide_hwif_t *hwif = HWIF(drive);
870 struct pci_dev *dev = to_pci_dev(hwif->dev);
871 u8 mcr = 0, mcr_addr = hwif->select_data;
872 u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01;
873
874 pci_read_config_byte(dev, 0x6a, &bwsr);
875 pci_read_config_byte(dev, mcr_addr, &mcr);
876 if (bwsr & mask)
877 pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
878 return ide_dma_end(drive);
879}
880
881/**
882 * hpt3xxn_set_clock - perform clock switching dance
883 * @hwif: hwif to switch
884 * @mode: clocking mode (0x21 for write, 0x23 otherwise)
885 *
886 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
887 */
888
889static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
890{
891 unsigned long base = hwif->extra_base;
892 u8 scr2 = inb(base + 0x6b);
893
894 if ((scr2 & 0x7f) == mode)
895 return;
896
897 /* Tristate the bus */
898 outb(0x80, base + 0x63);
899 outb(0x80, base + 0x67);
900
901 /* Switch clock and reset channels */
902 outb(mode, base + 0x6b);
903 outb(0xc0, base + 0x69);
904
905 /*
906 * Reset the state machines.
907 * NOTE: avoid accidentally enabling the disabled channels.
908 */
909 outb(inb(base + 0x60) | 0x32, base + 0x60);
910 outb(inb(base + 0x64) | 0x32, base + 0x64);
911
912 /* Complete reset */
913 outb(0x00, base + 0x69);
914
915 /* Reconnect channels to bus */
916 outb(0x00, base + 0x63);
917 outb(0x00, base + 0x67);
918}
919
920/**
921 * hpt3xxn_rw_disk - prepare for I/O
922 * @drive: drive for command
923 * @rq: block request structure
924 *
925 * This is called when a disk I/O is issued to HPT3xxN.
926 * We need it because of the clock switching.
927 */
928
929static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
930{
931 hpt3xxn_set_clock(HWIF(drive), rq_data_dir(rq) ? 0x23 : 0x21);
932}
933
934/**
935 * hpt37x_calibrate_dpll - calibrate the DPLL
936 * @dev: PCI device
937 *
938 * Perform a calibration cycle on the DPLL.
939 * Returns 1 if this succeeds
940 */
941static int hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high)
942{
943 u32 dpll = (f_high << 16) | f_low | 0x100;
944 u8 scr2;
945 int i;
946
947 pci_write_config_dword(dev, 0x5c, dpll);
948
949 /* Wait for oscillator ready */
950 for(i = 0; i < 0x5000; ++i) {
951 udelay(50);
952 pci_read_config_byte(dev, 0x5b, &scr2);
953 if (scr2 & 0x80)
954 break;
955 }
956 /* See if it stays ready (we'll just bail out if it's not yet) */
957 for(i = 0; i < 0x1000; ++i) {
958 pci_read_config_byte(dev, 0x5b, &scr2);
959 /* DPLL destabilized? */
960 if(!(scr2 & 0x80))
961 return 0;
962 }
963 /* Turn off tuning, we have the DPLL set */
964 pci_read_config_dword (dev, 0x5c, &dpll);
965 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
966 return 1;
967}
968
969static void hpt3xx_disable_fast_irq(struct pci_dev *dev, u8 mcr_addr)
970{
971 struct ide_host *host = pci_get_drvdata(dev);
972 struct hpt_info *info = host->host_priv + (&dev->dev == host->dev[1]);
973 u8 chip_type = info->chip_type;
974 u8 new_mcr, old_mcr = 0;
975
976 /*
977 * Disable the "fast interrupt" prediction. Don't hold off
978 * on interrupts. (== 0x01 despite what the docs say)
979 */
980 pci_read_config_byte(dev, mcr_addr + 1, &old_mcr);
981
982 if (chip_type >= HPT374)
983 new_mcr = old_mcr & ~0x07;
984 else if (chip_type >= HPT370) {
985 new_mcr = old_mcr;
986 new_mcr &= ~0x02;
987#ifdef HPT_DELAY_INTERRUPT
988 new_mcr &= ~0x01;
989#else
990 new_mcr |= 0x01;
991#endif
992 } else /* HPT366 and HPT368 */
993 new_mcr = old_mcr & ~0x80;
994
995 if (new_mcr != old_mcr)
996 pci_write_config_byte(dev, mcr_addr + 1, new_mcr);
997}
998
999static unsigned int init_chipset_hpt366(struct pci_dev *dev)
1000{
1001 unsigned long io_base = pci_resource_start(dev, 4);
1002 struct hpt_info *info = hpt3xx_get_info(&dev->dev);
1003 const char *name = DRV_NAME;
1004 u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */
1005 u8 chip_type;
1006 enum ata_clock clock;
1007
1008 chip_type = info->chip_type;
1009
1010 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1011 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1012 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1013 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1014
1015 /*
1016 * First, try to estimate the PCI clock frequency...
1017 */
1018 if (chip_type >= HPT370) {
1019 u8 scr1 = 0;
1020 u16 f_cnt = 0;
1021 u32 temp = 0;
1022
1023 /* Interrupt force enable. */
1024 pci_read_config_byte(dev, 0x5a, &scr1);
1025 if (scr1 & 0x10)
1026 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
1027
1028 /*
1029 * HighPoint does this for HPT372A.
1030 * NOTE: This register is only writeable via I/O space.
1031 */
1032 if (chip_type == HPT372A)
1033 outb(0x0e, io_base + 0x9c);
1034
1035 /*
1036 * Default to PCI clock. Make sure MA15/16 are set to output
1037 * to prevent drives having problems with 40-pin cables.
1038 */
1039 pci_write_config_byte(dev, 0x5b, 0x23);
1040
1041 /*
1042 * We'll have to read f_CNT value in order to determine
1043 * the PCI clock frequency according to the following ratio:
1044 *
1045 * f_CNT = Fpci * 192 / Fdpll
1046 *
1047 * First try reading the register in which the HighPoint BIOS
1048 * saves f_CNT value before reprogramming the DPLL from its
1049 * default setting (which differs for the various chips).
1050 *
1051 * NOTE: This register is only accessible via I/O space;
1052 * HPT374 BIOS only saves it for the function 0, so we have to
1053 * always read it from there -- no need to check the result of
1054 * pci_get_slot() for the function 0 as the whole device has
1055 * been already "pinned" (via function 1) in init_setup_hpt374()
1056 */
1057 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1058 struct pci_dev *dev1 = pci_get_slot(dev->bus,
1059 dev->devfn - 1);
1060 unsigned long io_base = pci_resource_start(dev1, 4);
1061
1062 temp = inl(io_base + 0x90);
1063 pci_dev_put(dev1);
1064 } else
1065 temp = inl(io_base + 0x90);
1066
1067 /*
1068 * In case the signature check fails, we'll have to
1069 * resort to reading the f_CNT register itself in hopes
1070 * that nobody has touched the DPLL yet...
1071 */
1072 if ((temp & 0xFFFFF000) != 0xABCDE000) {
1073 int i;
1074
1075 printk(KERN_WARNING "%s %s: no clock data saved by "
1076 "BIOS\n", name, pci_name(dev));
1077
1078 /* Calculate the average value of f_CNT. */
1079 for (temp = i = 0; i < 128; i++) {
1080 pci_read_config_word(dev, 0x78, &f_cnt);
1081 temp += f_cnt & 0x1ff;
1082 mdelay(1);
1083 }
1084 f_cnt = temp / 128;
1085 } else
1086 f_cnt = temp & 0x1ff;
1087
1088 dpll_clk = info->dpll_clk;
1089 pci_clk = (f_cnt * dpll_clk) / 192;
1090
1091 /* Clamp PCI clock to bands. */
1092 if (pci_clk < 40)
1093 pci_clk = 33;
1094 else if(pci_clk < 45)
1095 pci_clk = 40;
1096 else if(pci_clk < 55)
1097 pci_clk = 50;
1098 else
1099 pci_clk = 66;
1100
1101 printk(KERN_INFO "%s %s: DPLL base: %d MHz, f_CNT: %d, "
1102 "assuming %d MHz PCI\n", name, pci_name(dev),
1103 dpll_clk, f_cnt, pci_clk);
1104 } else {
1105 u32 itr1 = 0;
1106
1107 pci_read_config_dword(dev, 0x40, &itr1);
1108
1109 /* Detect PCI clock by looking at cmd_high_time. */
1110 switch((itr1 >> 8) & 0x07) {
1111 case 0x09:
1112 pci_clk = 40;
1113 break;
1114 case 0x05:
1115 pci_clk = 25;
1116 break;
1117 case 0x07:
1118 default:
1119 pci_clk = 33;
1120 break;
1121 }
1122 }
1123
1124 /* Let's assume we'll use PCI clock for the ATA clock... */
1125 switch (pci_clk) {
1126 case 25:
1127 clock = ATA_CLOCK_25MHZ;
1128 break;
1129 case 33:
1130 default:
1131 clock = ATA_CLOCK_33MHZ;
1132 break;
1133 case 40:
1134 clock = ATA_CLOCK_40MHZ;
1135 break;
1136 case 50:
1137 clock = ATA_CLOCK_50MHZ;
1138 break;
1139 case 66:
1140 clock = ATA_CLOCK_66MHZ;
1141 break;
1142 }
1143
1144 /*
1145 * Only try the DPLL if we don't have a table for the PCI clock that
1146 * we are running at for HPT370/A, always use it for anything newer...
1147 *
1148 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
1149 * We also don't like using the DPLL because this causes glitches
1150 * on PRST-/SRST- when the state engine gets reset...
1151 */
1152 if (chip_type >= HPT374 || info->timings->clock_table[clock] == NULL) {
1153 u16 f_low, delta = pci_clk < 50 ? 2 : 4;
1154 int adjust;
1155
1156 /*
1157 * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1158 * supported/enabled, use 50 MHz DPLL clock otherwise...
1159 */
1160 if (info->udma_mask == ATA_UDMA6) {
1161 dpll_clk = 66;
1162 clock = ATA_CLOCK_66MHZ;
1163 } else if (dpll_clk) { /* HPT36x chips don't have DPLL */
1164 dpll_clk = 50;
1165 clock = ATA_CLOCK_50MHZ;
1166 }
1167
1168 if (info->timings->clock_table[clock] == NULL) {
1169 printk(KERN_ERR "%s %s: unknown bus timing!\n",
1170 name, pci_name(dev));
1171 return -EIO;
1172 }
1173
1174 /* Select the DPLL clock. */
1175 pci_write_config_byte(dev, 0x5b, 0x21);
1176
1177 /*
1178 * Adjust the DPLL based upon PCI clock, enable it,
1179 * and wait for stabilization...
1180 */
1181 f_low = (pci_clk * 48) / dpll_clk;
1182
1183 for (adjust = 0; adjust < 8; adjust++) {
1184 if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta))
1185 break;
1186
1187 /*
1188 * See if it'll settle at a fractionally different clock
1189 */
1190 if (adjust & 1)
1191 f_low -= adjust >> 1;
1192 else
1193 f_low += adjust >> 1;
1194 }
1195 if (adjust == 8) {
1196 printk(KERN_ERR "%s %s: DPLL did not stabilize!\n",
1197 name, pci_name(dev));
1198 return -EIO;
1199 }
1200
1201 printk(KERN_INFO "%s %s: using %d MHz DPLL clock\n",
1202 name, pci_name(dev), dpll_clk);
1203 } else {
1204 /* Mark the fact that we're not using the DPLL. */
1205 dpll_clk = 0;
1206
1207 printk(KERN_INFO "%s %s: using %d MHz PCI clock\n",
1208 name, pci_name(dev), pci_clk);
1209 }
1210
1211 /* Store the clock frequencies. */
1212 info->dpll_clk = dpll_clk;
1213 info->pci_clk = pci_clk;
1214 info->clock = clock;
1215
1216 if (chip_type >= HPT370) {
1217 u8 mcr1, mcr4;
1218
1219 /*
1220 * Reset the state engines.
1221 * NOTE: Avoid accidentally enabling the disabled channels.
1222 */
1223 pci_read_config_byte (dev, 0x50, &mcr1);
1224 pci_read_config_byte (dev, 0x54, &mcr4);
1225 pci_write_config_byte(dev, 0x50, (mcr1 | 0x32));
1226 pci_write_config_byte(dev, 0x54, (mcr4 | 0x32));
1227 udelay(100);
1228 }
1229
1230 /*
1231 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
1232 * the MISC. register to stretch the UltraDMA Tss timing.
1233 * NOTE: This register is only writeable via I/O space.
1234 */
1235 if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
1236 outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
1237
1238 hpt3xx_disable_fast_irq(dev, 0x50);
1239 hpt3xx_disable_fast_irq(dev, 0x54);
1240
1241 return dev->irq;
1242}
1243
1244static u8 hpt3xx_cable_detect(ide_hwif_t *hwif)
1245{
1246 struct pci_dev *dev = to_pci_dev(hwif->dev);
1247 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
1248 u8 chip_type = info->chip_type;
1249 u8 scr1 = 0, ata66 = hwif->channel ? 0x01 : 0x02;
1250
1251 /*
1252 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1253 * address lines to access an external EEPROM. To read valid
1254 * cable detect state the pins must be enabled as inputs.
1255 */
1256 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1257 /*
1258 * HPT374 PCI function 1
1259 * - set bit 15 of reg 0x52 to enable TCBLID as input
1260 * - set bit 15 of reg 0x56 to enable FCBLID as input
1261 */
1262 u8 mcr_addr = hwif->select_data + 2;
1263 u16 mcr;
1264
1265 pci_read_config_word(dev, mcr_addr, &mcr);
1266 pci_write_config_word(dev, mcr_addr, (mcr | 0x8000));
1267 /* now read cable id register */
1268 pci_read_config_byte(dev, 0x5a, &scr1);
1269 pci_write_config_word(dev, mcr_addr, mcr);
1270 } else if (chip_type >= HPT370) {
1271 /*
1272 * HPT370/372 and 374 pcifn 0
1273 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
1274 */
1275 u8 scr2 = 0;
1276
1277 pci_read_config_byte(dev, 0x5b, &scr2);
1278 pci_write_config_byte(dev, 0x5b, (scr2 & ~1));
1279 /* now read cable id register */
1280 pci_read_config_byte(dev, 0x5a, &scr1);
1281 pci_write_config_byte(dev, 0x5b, scr2);
1282 } else
1283 pci_read_config_byte(dev, 0x5a, &scr1);
1284
1285 return (scr1 & ata66) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
1286}
1287
1288static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1289{
1290 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
1291 int serialize = HPT_SERIALIZE_IO;
1292 u8 chip_type = info->chip_type;
1293
1294 /* Cache the channel's MISC. control registers' offset */
1295 hwif->select_data = hwif->channel ? 0x54 : 0x50;
1296
1297 /*
1298 * HPT3xxN chips have some complications:
1299 *
1300 * - on 33 MHz PCI we must clock switch
1301 * - on 66 MHz PCI we must NOT use the PCI clock
1302 */
1303 if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) {
1304 /*
1305 * Clock is shared between the channels,
1306 * so we'll have to serialize them... :-(
1307 */
1308 serialize = 1;
1309 hwif->rw_disk = &hpt3xxn_rw_disk;
1310 }
1311
1312 /* Serialize access to this device if needed */
1313 if (serialize && hwif->mate)
1314 hwif->serialized = hwif->mate->serialized = 1;
1315}
1316
1317static int __devinit init_dma_hpt366(ide_hwif_t *hwif,
1318 const struct ide_port_info *d)
1319{
1320 struct pci_dev *dev = to_pci_dev(hwif->dev);
1321 unsigned long flags, base = ide_pci_dma_base(hwif, d);
1322 u8 dma_old, dma_new, masterdma = 0, slavedma = 0;
1323
1324 if (base == 0)
1325 return -1;
1326
1327 hwif->dma_base = base;
1328
1329 if (ide_pci_check_simplex(hwif, d) < 0)
1330 return -1;
1331
1332 if (ide_pci_set_master(dev, d->name) < 0)
1333 return -1;
1334
1335 dma_old = inb(base + 2);
1336
1337 local_irq_save(flags);
1338
1339 dma_new = dma_old;
1340 pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
1341 pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma);
1342
1343 if (masterdma & 0x30) dma_new |= 0x20;
1344 if ( slavedma & 0x30) dma_new |= 0x40;
1345 if (dma_new != dma_old)
1346 outb(dma_new, base + 2);
1347
1348 local_irq_restore(flags);
1349
1350 printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n",
1351 hwif->name, base, base + 7);
1352
1353 hwif->extra_base = base + (hwif->channel ? 8 : 16);
1354
1355 if (ide_allocate_dma_engine(hwif))
1356 return -1;
1357
1358 hwif->dma_ops = &sff_dma_ops;
1359
1360 return 0;
1361}
1362
1363static void __devinit hpt374_init(struct pci_dev *dev, struct pci_dev *dev2)
1364{
1365 if (dev2->irq != dev->irq) {
1366 /* FIXME: we need a core pci_set_interrupt() */
1367 dev2->irq = dev->irq;
1368 printk(KERN_INFO DRV_NAME " %s: PCI config space interrupt "
1369 "fixed\n", pci_name(dev2));
1370 }
1371}
1372
1373static void __devinit hpt371_init(struct pci_dev *dev)
1374{
1375 u8 mcr1 = 0;
1376
1377 /*
1378 * HPT371 chips physically have only one channel, the secondary one,
1379 * but the primary channel registers do exist! Go figure...
1380 * So, we manually disable the non-existing channel here
1381 * (if the BIOS hasn't done this already).
1382 */
1383 pci_read_config_byte(dev, 0x50, &mcr1);
1384 if (mcr1 & 0x04)
1385 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
1386}
1387
1388static int __devinit hpt36x_init(struct pci_dev *dev, struct pci_dev *dev2)
1389{
1390 u8 mcr1 = 0, pin1 = 0, pin2 = 0;
1391
1392 /*
1393 * Now we'll have to force both channels enabled if
1394 * at least one of them has been enabled by BIOS...
1395 */
1396 pci_read_config_byte(dev, 0x50, &mcr1);
1397 if (mcr1 & 0x30)
1398 pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
1399
1400 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1401 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
1402
1403 if (pin1 != pin2 && dev->irq == dev2->irq) {
1404 printk(KERN_INFO DRV_NAME " %s: onboard version of chipset, "
1405 "pin1=%d pin2=%d\n", pci_name(dev), pin1, pin2);
1406 return 1;
1407 }
1408
1409 return 0;
1410}
1411
1412#define IDE_HFLAGS_HPT3XX \
1413 (IDE_HFLAG_NO_ATAPI_DMA | \
1414 IDE_HFLAG_OFF_BOARD)
1415
1416static const struct ide_port_ops hpt3xx_port_ops = {
1417 .set_pio_mode = hpt3xx_set_pio_mode,
1418 .set_dma_mode = hpt3xx_set_mode,
1419 .quirkproc = hpt3xx_quirkproc,
1420 .maskproc = hpt3xx_maskproc,
1421 .mdma_filter = hpt3xx_mdma_filter,
1422 .udma_filter = hpt3xx_udma_filter,
1423 .cable_detect = hpt3xx_cable_detect,
1424};
1425
1426static const struct ide_dma_ops hpt37x_dma_ops = {
1427 .dma_host_set = ide_dma_host_set,
1428 .dma_setup = ide_dma_setup,
1429 .dma_exec_cmd = ide_dma_exec_cmd,
1430 .dma_start = ide_dma_start,
1431 .dma_end = hpt374_dma_end,
1432 .dma_test_irq = hpt374_dma_test_irq,
1433 .dma_lost_irq = ide_dma_lost_irq,
1434 .dma_timeout = ide_dma_timeout,
1435};
1436
1437static const struct ide_dma_ops hpt370_dma_ops = {
1438 .dma_host_set = ide_dma_host_set,
1439 .dma_setup = ide_dma_setup,
1440 .dma_exec_cmd = ide_dma_exec_cmd,
1441 .dma_start = hpt370_dma_start,
1442 .dma_end = hpt370_dma_end,
1443 .dma_test_irq = ide_dma_test_irq,
1444 .dma_lost_irq = ide_dma_lost_irq,
1445 .dma_timeout = hpt370_dma_timeout,
1446};
1447
1448static const struct ide_dma_ops hpt36x_dma_ops = {
1449 .dma_host_set = ide_dma_host_set,
1450 .dma_setup = ide_dma_setup,
1451 .dma_exec_cmd = ide_dma_exec_cmd,
1452 .dma_start = ide_dma_start,
1453 .dma_end = ide_dma_end,
1454 .dma_test_irq = ide_dma_test_irq,
1455 .dma_lost_irq = hpt366_dma_lost_irq,
1456 .dma_timeout = ide_dma_timeout,
1457};
1458
1459static const struct ide_port_info hpt366_chipsets[] __devinitdata = {
1460 { /* 0: HPT36x */
1461 .name = DRV_NAME,
1462 .init_chipset = init_chipset_hpt366,
1463 .init_hwif = init_hwif_hpt366,
1464 .init_dma = init_dma_hpt366,
1465 /*
1466 * HPT36x chips have one channel per function and have
1467 * both channel enable bits located differently and visible
1468 * to both functions -- really stupid design decision... :-(
1469 * Bit 4 is for the primary channel, bit 5 for the secondary.
1470 */
1471 .enablebits = {{0x50,0x10,0x10}, {0x54,0x04,0x04}},
1472 .port_ops = &hpt3xx_port_ops,
1473 .dma_ops = &hpt36x_dma_ops,
1474 .host_flags = IDE_HFLAGS_HPT3XX | IDE_HFLAG_SINGLE,
1475 .pio_mask = ATA_PIO4,
1476 .mwdma_mask = ATA_MWDMA2,
1477 },
1478 { /* 1: HPT3xx */
1479 .name = DRV_NAME,
1480 .init_chipset = init_chipset_hpt366,
1481 .init_hwif = init_hwif_hpt366,
1482 .init_dma = init_dma_hpt366,
1483 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1484 .port_ops = &hpt3xx_port_ops,
1485 .dma_ops = &hpt37x_dma_ops,
1486 .host_flags = IDE_HFLAGS_HPT3XX,
1487 .pio_mask = ATA_PIO4,
1488 .mwdma_mask = ATA_MWDMA2,
1489 }
1490};
1491
1492/**
1493 * hpt366_init_one - called when an HPT366 is found
1494 * @dev: the hpt366 device
1495 * @id: the matching pci id
1496 *
1497 * Called when the PCI registration layer (or the IDE initialization)
1498 * finds a device matching our IDE device tables.
1499 */
1500static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1501{
1502 const struct hpt_info *info = NULL;
1503 struct hpt_info *dyn_info;
1504 struct pci_dev *dev2 = NULL;
1505 struct ide_port_info d;
1506 u8 idx = id->driver_data;
1507 u8 rev = dev->revision;
1508 int ret;
1509
1510 if ((idx == 0 || idx == 4) && (PCI_FUNC(dev->devfn) & 1))
1511 return -ENODEV;
1512
1513 switch (idx) {
1514 case 0:
1515 if (rev < 3)
1516 info = &hpt36x;
1517 else {
1518 switch (min_t(u8, rev, 6)) {
1519 case 3: info = &hpt370; break;
1520 case 4: info = &hpt370a; break;
1521 case 5: info = &hpt372; break;
1522 case 6: info = &hpt372n; break;
1523 }
1524 idx++;
1525 }
1526 break;
1527 case 1:
1528 info = (rev > 1) ? &hpt372n : &hpt372a;
1529 break;
1530 case 2:
1531 info = (rev > 1) ? &hpt302n : &hpt302;
1532 break;
1533 case 3:
1534 hpt371_init(dev);
1535 info = (rev > 1) ? &hpt371n : &hpt371;
1536 break;
1537 case 4:
1538 info = &hpt374;
1539 break;
1540 case 5:
1541 info = &hpt372n;
1542 break;
1543 }
1544
1545 printk(KERN_INFO DRV_NAME ": %s chipset detected\n", info->chip_name);
1546
1547 d = hpt366_chipsets[min_t(u8, idx, 1)];
1548
1549 d.udma_mask = info->udma_mask;
1550
1551 /* fixup ->dma_ops for HPT370/HPT370A */
1552 if (info == &hpt370 || info == &hpt370a)
1553 d.dma_ops = &hpt370_dma_ops;
1554
1555 if (info == &hpt36x || info == &hpt374)
1556 dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
1557
1558 dyn_info = kzalloc(sizeof(*dyn_info) * (dev2 ? 2 : 1), GFP_KERNEL);
1559 if (dyn_info == NULL) {
1560 printk(KERN_ERR "%s %s: out of memory!\n",
1561 d.name, pci_name(dev));
1562 pci_dev_put(dev2);
1563 return -ENOMEM;
1564 }
1565
1566 /*
1567 * Copy everything from a static "template" structure
1568 * to just allocated per-chip hpt_info structure.
1569 */
1570 memcpy(dyn_info, info, sizeof(*dyn_info));
1571
1572 if (dev2) {
1573 memcpy(dyn_info + 1, info, sizeof(*dyn_info));
1574
1575 if (info == &hpt374)
1576 hpt374_init(dev, dev2);
1577 else {
1578 if (hpt36x_init(dev, dev2))
1579 d.host_flags &= ~IDE_HFLAG_NON_BOOTABLE;
1580 }
1581
1582 ret = ide_pci_init_two(dev, dev2, &d, dyn_info);
1583 if (ret < 0) {
1584 pci_dev_put(dev2);
1585 kfree(dyn_info);
1586 }
1587 return ret;
1588 }
1589
1590 ret = ide_pci_init_one(dev, &d, dyn_info);
1591 if (ret < 0)
1592 kfree(dyn_info);
1593
1594 return ret;
1595}
1596
1597static void __devexit hpt366_remove(struct pci_dev *dev)
1598{
1599 struct ide_host *host = pci_get_drvdata(dev);
1600 struct ide_info *info = host->host_priv;
1601 struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;
1602
1603 ide_pci_remove(dev);
1604 pci_dev_put(dev2);
1605 kfree(info);
1606}
1607
1608static const struct pci_device_id hpt366_pci_tbl[] __devinitconst = {
1609 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), 0 },
1610 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), 1 },
1611 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), 2 },
1612 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), 3 },
1613 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), 4 },
1614 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), 5 },
1615 { 0, },
1616};
1617MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1618
1619static struct pci_driver hpt366_pci_driver = {
1620 .name = "HPT366_IDE",
1621 .id_table = hpt366_pci_tbl,
1622 .probe = hpt366_init_one,
1623 .remove = __devexit_p(hpt366_remove),
1624 .suspend = ide_pci_suspend,
1625 .resume = ide_pci_resume,
1626};
1627
1628static int __init hpt366_ide_init(void)
1629{
1630 return ide_pci_register_driver(&hpt366_pci_driver);
1631}
1632
1633static void __exit hpt366_ide_exit(void)
1634{
1635 pci_unregister_driver(&hpt366_pci_driver);
1636}
1637
1638module_init(hpt366_ide_init);
1639module_exit(hpt366_ide_exit);
1640
1641MODULE_AUTHOR("Andre Hedrick");
1642MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1643MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/it8213.c b/drivers/ide/pci/it8213.c
deleted file mode 100644
index 7c2feeb3c5ec..000000000000
--- a/drivers/ide/pci/it8213.c
+++ /dev/null
@@ -1,216 +0,0 @@
1/*
2 * ITE 8213 IDE driver
3 *
4 * Copyright (C) 2006 Jack Lee
5 * Copyright (C) 2006 Alan Cox
6 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
7 */
8
9#include <linux/kernel.h>
10#include <linux/types.h>
11#include <linux/module.h>
12#include <linux/pci.h>
13#include <linux/ide.h>
14#include <linux/init.h>
15
16#define DRV_NAME "it8213"
17
18/**
19 * it8213_set_pio_mode - set host controller for PIO mode
20 * @drive: drive
21 * @pio: PIO mode number
22 *
23 * Set the interface PIO mode.
24 */
25
26static void it8213_set_pio_mode(ide_drive_t *drive, const u8 pio)
27{
28 ide_hwif_t *hwif = HWIF(drive);
29 struct pci_dev *dev = to_pci_dev(hwif->dev);
30 int is_slave = drive->dn & 1;
31 int master_port = 0x40;
32 int slave_port = 0x44;
33 unsigned long flags;
34 u16 master_data;
35 u8 slave_data;
36 static DEFINE_SPINLOCK(tune_lock);
37 int control = 0;
38
39 static const u8 timings[][2] = {
40 { 0, 0 },
41 { 0, 0 },
42 { 1, 0 },
43 { 2, 1 },
44 { 2, 3 }, };
45
46 spin_lock_irqsave(&tune_lock, flags);
47 pci_read_config_word(dev, master_port, &master_data);
48
49 if (pio > 1)
50 control |= 1; /* Programmable timing on */
51 if (drive->media != ide_disk)
52 control |= 4; /* ATAPI */
53 if (pio > 2)
54 control |= 2; /* IORDY */
55 if (is_slave) {
56 master_data |= 0x4000;
57 master_data &= ~0x0070;
58 if (pio > 1)
59 master_data = master_data | (control << 4);
60 pci_read_config_byte(dev, slave_port, &slave_data);
61 slave_data = slave_data & 0xf0;
62 slave_data = slave_data | (timings[pio][0] << 2) | timings[pio][1];
63 } else {
64 master_data &= ~0x3307;
65 if (pio > 1)
66 master_data = master_data | control;
67 master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
68 }
69 pci_write_config_word(dev, master_port, master_data);
70 if (is_slave)
71 pci_write_config_byte(dev, slave_port, slave_data);
72 spin_unlock_irqrestore(&tune_lock, flags);
73}
74
75/**
76 * it8213_set_dma_mode - set host controller for DMA mode
77 * @drive: drive
78 * @speed: DMA mode
79 *
80 * Tune the ITE chipset for the DMA mode.
81 */
82
83static void it8213_set_dma_mode(ide_drive_t *drive, const u8 speed)
84{
85 ide_hwif_t *hwif = HWIF(drive);
86 struct pci_dev *dev = to_pci_dev(hwif->dev);
87 u8 maslave = 0x40;
88 int a_speed = 3 << (drive->dn * 4);
89 int u_flag = 1 << drive->dn;
90 int v_flag = 0x01 << drive->dn;
91 int w_flag = 0x10 << drive->dn;
92 int u_speed = 0;
93 u16 reg4042, reg4a;
94 u8 reg48, reg54, reg55;
95
96 pci_read_config_word(dev, maslave, &reg4042);
97 pci_read_config_byte(dev, 0x48, &reg48);
98 pci_read_config_word(dev, 0x4a, &reg4a);
99 pci_read_config_byte(dev, 0x54, &reg54);
100 pci_read_config_byte(dev, 0x55, &reg55);
101
102 if (speed >= XFER_UDMA_0) {
103 u8 udma = speed - XFER_UDMA_0;
104
105 u_speed = min_t(u8, 2 - (udma & 1), udma) << (drive->dn * 4);
106
107 if (!(reg48 & u_flag))
108 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
109 if (speed >= XFER_UDMA_5)
110 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
111 else
112 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
113
114 if ((reg4a & a_speed) != u_speed)
115 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
116 if (speed > XFER_UDMA_2) {
117 if (!(reg54 & v_flag))
118 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
119 } else
120 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
121 } else {
122 const u8 mwdma_to_pio[] = { 0, 3, 4 };
123 u8 pio;
124
125 if (reg48 & u_flag)
126 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
127 if (reg4a & a_speed)
128 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
129 if (reg54 & v_flag)
130 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
131 if (reg55 & w_flag)
132 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
133
134 if (speed >= XFER_MW_DMA_0)
135 pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
136 else
137 pio = 2; /* only SWDMA2 is allowed */
138
139 it8213_set_pio_mode(drive, pio);
140 }
141}
142
143static u8 it8213_cable_detect(ide_hwif_t *hwif)
144{
145 struct pci_dev *dev = to_pci_dev(hwif->dev);
146 u8 reg42h = 0;
147
148 pci_read_config_byte(dev, 0x42, &reg42h);
149
150 return (reg42h & 0x02) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
151}
152
153static const struct ide_port_ops it8213_port_ops = {
154 .set_pio_mode = it8213_set_pio_mode,
155 .set_dma_mode = it8213_set_dma_mode,
156 .cable_detect = it8213_cable_detect,
157};
158
159static const struct ide_port_info it8213_chipset __devinitdata = {
160 .name = DRV_NAME,
161 .enablebits = { {0x41, 0x80, 0x80} },
162 .port_ops = &it8213_port_ops,
163 .host_flags = IDE_HFLAG_SINGLE,
164 .pio_mask = ATA_PIO4,
165 .swdma_mask = ATA_SWDMA2_ONLY,
166 .mwdma_mask = ATA_MWDMA12_ONLY,
167 .udma_mask = ATA_UDMA6,
168};
169
170/**
171 * it8213_init_one - pci layer discovery entry
172 * @dev: PCI device
173 * @id: ident table entry
174 *
175 * Called by the PCI code when it finds an ITE8213 controller. As
176 * this device follows the standard interfaces we can use the
177 * standard helper functions to do almost all the work for us.
178 */
179
180static int __devinit it8213_init_one(struct pci_dev *dev, const struct pci_device_id *id)
181{
182 return ide_pci_init_one(dev, &it8213_chipset, NULL);
183}
184
185static const struct pci_device_id it8213_pci_tbl[] = {
186 { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8213), 0 },
187 { 0, },
188};
189
190MODULE_DEVICE_TABLE(pci, it8213_pci_tbl);
191
192static struct pci_driver it8213_pci_driver = {
193 .name = "ITE8213_IDE",
194 .id_table = it8213_pci_tbl,
195 .probe = it8213_init_one,
196 .remove = ide_pci_remove,
197 .suspend = ide_pci_suspend,
198 .resume = ide_pci_resume,
199};
200
201static int __init it8213_ide_init(void)
202{
203 return ide_pci_register_driver(&it8213_pci_driver);
204}
205
206static void __exit it8213_ide_exit(void)
207{
208 pci_unregister_driver(&it8213_pci_driver);
209}
210
211module_init(it8213_ide_init);
212module_exit(it8213_ide_exit);
213
214MODULE_AUTHOR("Jack Lee, Alan Cox");
215MODULE_DESCRIPTION("PCI driver module for the ITE 8213");
216MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/it821x.c b/drivers/ide/pci/it821x.c
deleted file mode 100644
index 995e18bb3139..000000000000
--- a/drivers/ide/pci/it821x.c
+++ /dev/null
@@ -1,706 +0,0 @@
1/*
2 * Copyright (C) 2004 Red Hat <alan@redhat.com>
3 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
4 *
5 * May be copied or modified under the terms of the GNU General Public License
6 * Based in part on the ITE vendor provided SCSI driver.
7 *
8 * Documentation available from
9 * http://www.ite.com.tw/pc/IT8212F_V04.pdf
10 * Some other documents are NDA.
11 *
12 * The ITE8212 isn't exactly a standard IDE controller. It has two
13 * modes. In pass through mode then it is an IDE controller. In its smart
14 * mode its actually quite a capable hardware raid controller disguised
15 * as an IDE controller. Smart mode only understands DMA read/write and
16 * identify, none of the fancier commands apply. The IT8211 is identical
17 * in other respects but lacks the raid mode.
18 *
19 * Errata:
20 * o Rev 0x10 also requires master/slave hold the same DMA timings and
21 * cannot do ATAPI MWDMA.
22 * o The identify data for raid volumes lacks CHS info (technically ok)
23 * but also fails to set the LBA28 and other bits. We fix these in
24 * the IDE probe quirk code.
25 * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode
26 * raid then the controller firmware dies
27 * o Smart mode without RAID doesn't clear all the necessary identify
28 * bits to reduce the command set to the one used
29 *
30 * This has a few impacts on the driver
31 * - In pass through mode we do all the work you would expect
32 * - In smart mode the clocking set up is done by the controller generally
33 * but we must watch the other limits and filter.
34 * - There are a few extra vendor commands that actually talk to the
35 * controller but only work PIO with no IRQ.
36 *
37 * Vendor areas of the identify block in smart mode are used for the
38 * timing and policy set up. Each HDD in raid mode also has a serial
39 * block on the disk. The hardware extra commands are get/set chip status,
40 * rebuild, get rebuild status.
41 *
42 * In Linux the driver supports pass through mode as if the device was
43 * just another IDE controller. If the smart mode is running then
44 * volumes are managed by the controller firmware and each IDE "disk"
45 * is a raid volume. Even more cute - the controller can do automated
46 * hotplug and rebuild.
47 *
48 * The pass through controller itself is a little demented. It has a
49 * flaw that it has a single set of PIO/MWDMA timings per channel so
50 * non UDMA devices restrict each others performance. It also has a
51 * single clock source per channel so mixed UDMA100/133 performance
52 * isn't perfect and we have to pick a clock. Thankfully none of this
53 * matters in smart mode. ATAPI DMA is not currently supported.
54 *
55 * It seems the smart mode is a win for RAID1/RAID10 but otherwise not.
56 *
57 * TODO
58 * - ATAPI UDMA is ok but not MWDMA it seems
59 * - RAID configuration ioctls
60 * - Move to libata once it grows up
61 */
62
63#include <linux/types.h>
64#include <linux/module.h>
65#include <linux/pci.h>
66#include <linux/ide.h>
67#include <linux/init.h>
68
69#define DRV_NAME "it821x"
70
71struct it821x_dev
72{
73 unsigned int smart:1, /* Are we in smart raid mode */
74 timing10:1; /* Rev 0x10 */
75 u8 clock_mode; /* 0, ATA_50 or ATA_66 */
76 u8 want[2][2]; /* Mode/Pri log for master slave */
77 /* We need these for switching the clock when DMA goes on/off
78 The high byte is the 66Mhz timing */
79 u16 pio[2]; /* Cached PIO values */
80 u16 mwdma[2]; /* Cached MWDMA values */
81 u16 udma[2]; /* Cached UDMA values (per drive) */
82};
83
84#define ATA_66 0
85#define ATA_50 1
86#define ATA_ANY 2
87
88#define UDMA_OFF 0
89#define MWDMA_OFF 0
90
91/*
92 * We allow users to force the card into non raid mode without
93 * flashing the alternative BIOS. This is also necessary right now
94 * for embedded platforms that cannot run a PC BIOS but are using this
95 * device.
96 */
97
98static int it8212_noraid;
99
100/**
101 * it821x_program - program the PIO/MWDMA registers
102 * @drive: drive to tune
103 * @timing: timing info
104 *
105 * Program the PIO/MWDMA timing for this channel according to the
106 * current clock.
107 */
108
109static void it821x_program(ide_drive_t *drive, u16 timing)
110{
111 ide_hwif_t *hwif = drive->hwif;
112 struct pci_dev *dev = to_pci_dev(hwif->dev);
113 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
114 int channel = hwif->channel;
115 u8 conf;
116
117 /* Program PIO/MWDMA timing bits */
118 if(itdev->clock_mode == ATA_66)
119 conf = timing >> 8;
120 else
121 conf = timing & 0xFF;
122
123 pci_write_config_byte(dev, 0x54 + 4 * channel, conf);
124}
125
126/**
127 * it821x_program_udma - program the UDMA registers
128 * @drive: drive to tune
129 * @timing: timing info
130 *
131 * Program the UDMA timing for this drive according to the
132 * current clock.
133 */
134
135static void it821x_program_udma(ide_drive_t *drive, u16 timing)
136{
137 ide_hwif_t *hwif = drive->hwif;
138 struct pci_dev *dev = to_pci_dev(hwif->dev);
139 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
140 int channel = hwif->channel;
141 u8 unit = drive->dn & 1, conf;
142
143 /* Program UDMA timing bits */
144 if(itdev->clock_mode == ATA_66)
145 conf = timing >> 8;
146 else
147 conf = timing & 0xFF;
148
149 if (itdev->timing10 == 0)
150 pci_write_config_byte(dev, 0x56 + 4 * channel + unit, conf);
151 else {
152 pci_write_config_byte(dev, 0x56 + 4 * channel, conf);
153 pci_write_config_byte(dev, 0x56 + 4 * channel + 1, conf);
154 }
155}
156
157/**
158 * it821x_clock_strategy
159 * @drive: drive to set up
160 *
161 * Select between the 50 and 66Mhz base clocks to get the best
162 * results for this interface.
163 */
164
165static void it821x_clock_strategy(ide_drive_t *drive)
166{
167 ide_hwif_t *hwif = drive->hwif;
168 struct pci_dev *dev = to_pci_dev(hwif->dev);
169 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
170 ide_drive_t *pair;
171 int clock, altclock, sel = 0;
172 u8 unit = drive->dn & 1, v;
173
174 pair = &hwif->drives[1 - unit];
175
176 if(itdev->want[0][0] > itdev->want[1][0]) {
177 clock = itdev->want[0][1];
178 altclock = itdev->want[1][1];
179 } else {
180 clock = itdev->want[1][1];
181 altclock = itdev->want[0][1];
182 }
183
184 /*
185 * if both clocks can be used for the mode with the higher priority
186 * use the clock needed by the mode with the lower priority
187 */
188 if (clock == ATA_ANY)
189 clock = altclock;
190
191 /* Nobody cares - keep the same clock */
192 if(clock == ATA_ANY)
193 return;
194 /* No change */
195 if(clock == itdev->clock_mode)
196 return;
197
198 /* Load this into the controller ? */
199 if(clock == ATA_66)
200 itdev->clock_mode = ATA_66;
201 else {
202 itdev->clock_mode = ATA_50;
203 sel = 1;
204 }
205
206 pci_read_config_byte(dev, 0x50, &v);
207 v &= ~(1 << (1 + hwif->channel));
208 v |= sel << (1 + hwif->channel);
209 pci_write_config_byte(dev, 0x50, v);
210
211 /*
212 * Reprogram the UDMA/PIO of the pair drive for the switch
213 * MWDMA will be dealt with by the dma switcher
214 */
215 if(pair && itdev->udma[1-unit] != UDMA_OFF) {
216 it821x_program_udma(pair, itdev->udma[1-unit]);
217 it821x_program(pair, itdev->pio[1-unit]);
218 }
219 /*
220 * Reprogram the UDMA/PIO of our drive for the switch.
221 * MWDMA will be dealt with by the dma switcher
222 */
223 if(itdev->udma[unit] != UDMA_OFF) {
224 it821x_program_udma(drive, itdev->udma[unit]);
225 it821x_program(drive, itdev->pio[unit]);
226 }
227}
228
229/**
230 * it821x_set_pio_mode - set host controller for PIO mode
231 * @drive: drive
232 * @pio: PIO mode number
233 *
234 * Tune the host to the desired PIO mode taking into the consideration
235 * the maximum PIO mode supported by the other device on the cable.
236 */
237
238static void it821x_set_pio_mode(ide_drive_t *drive, const u8 pio)
239{
240 ide_hwif_t *hwif = drive->hwif;
241 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
242 ide_drive_t *pair;
243 u8 unit = drive->dn & 1, set_pio = pio;
244
245 /* Spec says 89 ref driver uses 88 */
246 static u16 pio_timings[]= { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 };
247 static u8 pio_want[] = { ATA_66, ATA_66, ATA_66, ATA_66, ATA_ANY };
248
249 pair = &hwif->drives[1 - unit];
250
251 /*
252 * Compute the best PIO mode we can for a given device. We must
253 * pick a speed that does not cause problems with the other device
254 * on the cable.
255 */
256 if (pair) {
257 u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4);
258 /* trim PIO to the slowest of the master/slave */
259 if (pair_pio < set_pio)
260 set_pio = pair_pio;
261 }
262
263 /* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */
264 itdev->want[unit][1] = pio_want[set_pio];
265 itdev->want[unit][0] = 1; /* PIO is lowest priority */
266 itdev->pio[unit] = pio_timings[set_pio];
267 it821x_clock_strategy(drive);
268 it821x_program(drive, itdev->pio[unit]);
269}
270
271/**
272 * it821x_tune_mwdma - tune a channel for MWDMA
273 * @drive: drive to set up
274 * @mode_wanted: the target operating mode
275 *
276 * Load the timing settings for this device mode into the
277 * controller when doing MWDMA in pass through mode. The caller
278 * must manage the whole lack of per device MWDMA/PIO timings and
279 * the shared MWDMA/PIO timing register.
280 */
281
282static void it821x_tune_mwdma (ide_drive_t *drive, byte mode_wanted)
283{
284 ide_hwif_t *hwif = drive->hwif;
285 struct pci_dev *dev = to_pci_dev(hwif->dev);
286 struct it821x_dev *itdev = (void *)ide_get_hwifdata(hwif);
287 u8 unit = drive->dn & 1, channel = hwif->channel, conf;
288
289 static u16 dma[] = { 0x8866, 0x3222, 0x3121 };
290 static u8 mwdma_want[] = { ATA_ANY, ATA_66, ATA_ANY };
291
292 itdev->want[unit][1] = mwdma_want[mode_wanted];
293 itdev->want[unit][0] = 2; /* MWDMA is low priority */
294 itdev->mwdma[unit] = dma[mode_wanted];
295 itdev->udma[unit] = UDMA_OFF;
296
297 /* UDMA bits off - Revision 0x10 do them in pairs */
298 pci_read_config_byte(dev, 0x50, &conf);
299 if (itdev->timing10)
300 conf |= channel ? 0x60: 0x18;
301 else
302 conf |= 1 << (3 + 2 * channel + unit);
303 pci_write_config_byte(dev, 0x50, conf);
304
305 it821x_clock_strategy(drive);
306 /* FIXME: do we need to program this ? */
307 /* it821x_program(drive, itdev->mwdma[unit]); */
308}
309
310/**
311 * it821x_tune_udma - tune a channel for UDMA
312 * @drive: drive to set up
313 * @mode_wanted: the target operating mode
314 *
315 * Load the timing settings for this device mode into the
316 * controller when doing UDMA modes in pass through.
317 */
318
319static void it821x_tune_udma (ide_drive_t *drive, byte mode_wanted)
320{
321 ide_hwif_t *hwif = drive->hwif;
322 struct pci_dev *dev = to_pci_dev(hwif->dev);
323 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
324 u8 unit = drive->dn & 1, channel = hwif->channel, conf;
325
326 static u16 udma[] = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 };
327 static u8 udma_want[] = { ATA_ANY, ATA_50, ATA_ANY, ATA_66, ATA_66, ATA_50, ATA_66 };
328
329 itdev->want[unit][1] = udma_want[mode_wanted];
330 itdev->want[unit][0] = 3; /* UDMA is high priority */
331 itdev->mwdma[unit] = MWDMA_OFF;
332 itdev->udma[unit] = udma[mode_wanted];
333 if(mode_wanted >= 5)
334 itdev->udma[unit] |= 0x8080; /* UDMA 5/6 select on */
335
336 /* UDMA on. Again revision 0x10 must do the pair */
337 pci_read_config_byte(dev, 0x50, &conf);
338 if (itdev->timing10)
339 conf &= channel ? 0x9F: 0xE7;
340 else
341 conf &= ~ (1 << (3 + 2 * channel + unit));
342 pci_write_config_byte(dev, 0x50, conf);
343
344 it821x_clock_strategy(drive);
345 it821x_program_udma(drive, itdev->udma[unit]);
346
347}
348
349/**
350 * it821x_dma_read - DMA hook
351 * @drive: drive for DMA
352 *
353 * The IT821x has a single timing register for MWDMA and for PIO
354 * operations. As we flip back and forth we have to reload the
355 * clock. In addition the rev 0x10 device only works if the same
356 * timing value is loaded into the master and slave UDMA clock
357 * so we must also reload that.
358 *
359 * FIXME: we could figure out in advance if we need to do reloads
360 */
361
362static void it821x_dma_start(ide_drive_t *drive)
363{
364 ide_hwif_t *hwif = drive->hwif;
365 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
366 u8 unit = drive->dn & 1;
367
368 if(itdev->mwdma[unit] != MWDMA_OFF)
369 it821x_program(drive, itdev->mwdma[unit]);
370 else if(itdev->udma[unit] != UDMA_OFF && itdev->timing10)
371 it821x_program_udma(drive, itdev->udma[unit]);
372 ide_dma_start(drive);
373}
374
375/**
376 * it821x_dma_write - DMA hook
377 * @drive: drive for DMA stop
378 *
379 * The IT821x has a single timing register for MWDMA and for PIO
380 * operations. As we flip back and forth we have to reload the
381 * clock.
382 */
383
384static int it821x_dma_end(ide_drive_t *drive)
385{
386 ide_hwif_t *hwif = drive->hwif;
387 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
388 int ret = ide_dma_end(drive);
389 u8 unit = drive->dn & 1;
390
391 if(itdev->mwdma[unit] != MWDMA_OFF)
392 it821x_program(drive, itdev->pio[unit]);
393 return ret;
394}
395
396/**
397 * it821x_set_dma_mode - set host controller for DMA mode
398 * @drive: drive
399 * @speed: DMA mode
400 *
401 * Tune the ITE chipset for the desired DMA mode.
402 */
403
404static void it821x_set_dma_mode(ide_drive_t *drive, const u8 speed)
405{
406 /*
407 * MWDMA tuning is really hard because our MWDMA and PIO
408 * timings are kept in the same place. We can switch in the
409 * host dma on/off callbacks.
410 */
411 if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_6)
412 it821x_tune_udma(drive, speed - XFER_UDMA_0);
413 else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
414 it821x_tune_mwdma(drive, speed - XFER_MW_DMA_0);
415}
416
417/**
418 * it821x_cable_detect - cable detection
419 * @hwif: interface to check
420 *
421 * Check for the presence of an ATA66 capable cable on the
422 * interface. Problematic as it seems some cards don't have
423 * the needed logic onboard.
424 */
425
426static u8 it821x_cable_detect(ide_hwif_t *hwif)
427{
428 /* The reference driver also only does disk side */
429 return ATA_CBL_PATA80;
430}
431
432/**
433 * it821x_quirkproc - post init callback
434 * @drive: drive
435 *
436 * This callback is run after the drive has been probed but
437 * before anything gets attached. It allows drivers to do any
438 * final tuning that is needed, or fixups to work around bugs.
439 */
440
441static void it821x_quirkproc(ide_drive_t *drive)
442{
443 struct it821x_dev *itdev = ide_get_hwifdata(drive->hwif);
444 u16 *id = drive->id;
445
446 if (!itdev->smart) {
447 /*
448 * If we are in pass through mode then not much
449 * needs to be done, but we do bother to clear the
450 * IRQ mask as we may well be in PIO (eg rev 0x10)
451 * for now and we know unmasking is safe on this chipset.
452 */
453 drive->dev_flags |= IDE_DFLAG_UNMASK;
454 } else {
455 /*
456 * Perform fixups on smart mode. We need to "lose" some
457 * capabilities the firmware lacks but does not filter, and
458 * also patch up some capability bits that it forgets to set
459 * in RAID mode.
460 */
461
462 /* Check for RAID v native */
463 if (strstr((char *)&id[ATA_ID_PROD],
464 "Integrated Technology Express")) {
465 /* In raid mode the ident block is slightly buggy
466 We need to set the bits so that the IDE layer knows
467 LBA28. LBA48 and DMA ar valid */
468 id[ATA_ID_CAPABILITY] |= (3 << 8); /* LBA28, DMA */
469 id[ATA_ID_COMMAND_SET_2] |= 0x0400; /* LBA48 valid */
470 id[ATA_ID_CFS_ENABLE_2] |= 0x0400; /* LBA48 on */
471 /* Reporting logic */
472 printk(KERN_INFO "%s: IT8212 %sRAID %d volume",
473 drive->name, id[147] ? "Bootable " : "",
474 id[ATA_ID_CSFO]);
475 if (id[ATA_ID_CSFO] != 1)
476 printk(KERN_CONT "(%dK stripe)", id[146]);
477 printk(KERN_CONT ".\n");
478 } else {
479 /* Non RAID volume. Fixups to stop the core code
480 doing unsupported things */
481 id[ATA_ID_FIELD_VALID] &= 3;
482 id[ATA_ID_QUEUE_DEPTH] = 0;
483 id[ATA_ID_COMMAND_SET_1] = 0;
484 id[ATA_ID_COMMAND_SET_2] &= 0xC400;
485 id[ATA_ID_CFSSE] &= 0xC000;
486 id[ATA_ID_CFS_ENABLE_1] = 0;
487 id[ATA_ID_CFS_ENABLE_2] &= 0xC400;
488 id[ATA_ID_CSF_DEFAULT] &= 0xC000;
489 id[127] = 0;
490 id[ATA_ID_DLF] = 0;
491 id[ATA_ID_CSFO] = 0;
492 id[ATA_ID_CFA_POWER] = 0;
493 printk(KERN_INFO "%s: Performing identify fixups.\n",
494 drive->name);
495 }
496
497 /*
498 * Set MWDMA0 mode as enabled/support - just to tell
499 * IDE core that DMA is supported (it821x hardware
500 * takes care of DMA mode programming).
501 */
502 if (ata_id_has_dma(id)) {
503 id[ATA_ID_MWDMA_MODES] |= 0x0101;
504 drive->current_speed = XFER_MW_DMA_0;
505 }
506 }
507
508}
509
510static struct ide_dma_ops it821x_pass_through_dma_ops = {
511 .dma_host_set = ide_dma_host_set,
512 .dma_setup = ide_dma_setup,
513 .dma_exec_cmd = ide_dma_exec_cmd,
514 .dma_start = it821x_dma_start,
515 .dma_end = it821x_dma_end,
516 .dma_test_irq = ide_dma_test_irq,
517 .dma_timeout = ide_dma_timeout,
518 .dma_lost_irq = ide_dma_lost_irq,
519};
520
521/**
522 * init_hwif_it821x - set up hwif structs
523 * @hwif: interface to set up
524 *
525 * We do the basic set up of the interface structure. The IT8212
526 * requires several custom handlers so we override the default
527 * ide DMA handlers appropriately
528 */
529
530static void __devinit init_hwif_it821x(ide_hwif_t *hwif)
531{
532 struct pci_dev *dev = to_pci_dev(hwif->dev);
533 struct ide_host *host = pci_get_drvdata(dev);
534 struct it821x_dev *itdevs = host->host_priv;
535 struct it821x_dev *idev = itdevs + hwif->channel;
536 u8 conf;
537
538 ide_set_hwifdata(hwif, idev);
539
540 pci_read_config_byte(dev, 0x50, &conf);
541 if (conf & 1) {
542 idev->smart = 1;
543 hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
544 /* Long I/O's although allowed in LBA48 space cause the
545 onboard firmware to enter the twighlight zone */
546 hwif->rqsize = 256;
547 }
548
549 /* Pull the current clocks from 0x50 also */
550 if (conf & (1 << (1 + hwif->channel)))
551 idev->clock_mode = ATA_50;
552 else
553 idev->clock_mode = ATA_66;
554
555 idev->want[0][1] = ATA_ANY;
556 idev->want[1][1] = ATA_ANY;
557
558 /*
559 * Not in the docs but according to the reference driver
560 * this is necessary.
561 */
562
563 pci_read_config_byte(dev, 0x08, &conf);
564 if (conf == 0x10) {
565 idev->timing10 = 1;
566 hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
567 if (idev->smart == 0)
568 printk(KERN_WARNING DRV_NAME " %s: revision 0x10, "
569 "workarounds activated\n", pci_name(dev));
570 }
571
572 if (idev->smart == 0) {
573 /* MWDMA/PIO clock switching for pass through mode */
574 hwif->dma_ops = &it821x_pass_through_dma_ops;
575 } else
576 hwif->host_flags |= IDE_HFLAG_NO_SET_MODE;
577
578 if (hwif->dma_base == 0)
579 return;
580
581 hwif->ultra_mask = ATA_UDMA6;
582 hwif->mwdma_mask = ATA_MWDMA2;
583}
584
585static void it8212_disable_raid(struct pci_dev *dev)
586{
587 /* Reset local CPU, and set BIOS not ready */
588 pci_write_config_byte(dev, 0x5E, 0x01);
589
590 /* Set to bypass mode, and reset PCI bus */
591 pci_write_config_byte(dev, 0x50, 0x00);
592 pci_write_config_word(dev, PCI_COMMAND,
593 PCI_COMMAND_PARITY | PCI_COMMAND_IO |
594 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
595 pci_write_config_word(dev, 0x40, 0xA0F3);
596
597 pci_write_config_dword(dev,0x4C, 0x02040204);
598 pci_write_config_byte(dev, 0x42, 0x36);
599 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
600}
601
602static unsigned int init_chipset_it821x(struct pci_dev *dev)
603{
604 u8 conf;
605 static char *mode[2] = { "pass through", "smart" };
606
607 /* Force the card into bypass mode if so requested */
608 if (it8212_noraid) {
609 printk(KERN_INFO DRV_NAME " %s: forcing bypass mode\n",
610 pci_name(dev));
611 it8212_disable_raid(dev);
612 }
613 pci_read_config_byte(dev, 0x50, &conf);
614 printk(KERN_INFO DRV_NAME " %s: controller in %s mode\n",
615 pci_name(dev), mode[conf & 1]);
616 return 0;
617}
618
619static const struct ide_port_ops it821x_port_ops = {
620 /* it821x_set_{pio,dma}_mode() are only used in pass-through mode */
621 .set_pio_mode = it821x_set_pio_mode,
622 .set_dma_mode = it821x_set_dma_mode,
623 .quirkproc = it821x_quirkproc,
624 .cable_detect = it821x_cable_detect,
625};
626
627static const struct ide_port_info it821x_chipset __devinitdata = {
628 .name = DRV_NAME,
629 .init_chipset = init_chipset_it821x,
630 .init_hwif = init_hwif_it821x,
631 .port_ops = &it821x_port_ops,
632 .pio_mask = ATA_PIO4,
633};
634
635/**
636 * it821x_init_one - pci layer discovery entry
637 * @dev: PCI device
638 * @id: ident table entry
639 *
640 * Called by the PCI code when it finds an ITE821x controller.
641 * We then use the IDE PCI generic helper to do most of the work.
642 */
643
644static int __devinit it821x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
645{
646 struct it821x_dev *itdevs;
647 int rc;
648
649 itdevs = kzalloc(2 * sizeof(*itdevs), GFP_KERNEL);
650 if (itdevs == NULL) {
651 printk(KERN_ERR DRV_NAME " %s: out of memory\n", pci_name(dev));
652 return -ENOMEM;
653 }
654
655 rc = ide_pci_init_one(dev, &it821x_chipset, itdevs);
656 if (rc)
657 kfree(itdevs);
658
659 return rc;
660}
661
662static void __devexit it821x_remove(struct pci_dev *dev)
663{
664 struct ide_host *host = pci_get_drvdata(dev);
665 struct it821x_dev *itdevs = host->host_priv;
666
667 ide_pci_remove(dev);
668 kfree(itdevs);
669}
670
671static const struct pci_device_id it821x_pci_tbl[] = {
672 { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8211), 0 },
673 { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8212), 0 },
674 { 0, },
675};
676
677MODULE_DEVICE_TABLE(pci, it821x_pci_tbl);
678
679static struct pci_driver it821x_pci_driver = {
680 .name = "ITE821x IDE",
681 .id_table = it821x_pci_tbl,
682 .probe = it821x_init_one,
683 .remove = __devexit_p(it821x_remove),
684 .suspend = ide_pci_suspend,
685 .resume = ide_pci_resume,
686};
687
688static int __init it821x_ide_init(void)
689{
690 return ide_pci_register_driver(&it821x_pci_driver);
691}
692
693static void __exit it821x_ide_exit(void)
694{
695 pci_unregister_driver(&it821x_pci_driver);
696}
697
698module_init(it821x_ide_init);
699module_exit(it821x_ide_exit);
700
701module_param_named(noraid, it8212_noraid, int, S_IRUGO);
702MODULE_PARM_DESC(noraid, "Force card into bypass mode");
703
704MODULE_AUTHOR("Alan Cox");
705MODULE_DESCRIPTION("PCI driver module for the ITE 821x");
706MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/jmicron.c b/drivers/ide/pci/jmicron.c
deleted file mode 100644
index 9a68433cf46d..000000000000
--- a/drivers/ide/pci/jmicron.c
+++ /dev/null
@@ -1,176 +0,0 @@
1
2/*
3 * Copyright (C) 2006 Red Hat <alan@redhat.com>
4 *
5 * May be copied or modified under the terms of the GNU General Public License
6 */
7
8#include <linux/types.h>
9#include <linux/module.h>
10#include <linux/pci.h>
11#include <linux/ide.h>
12#include <linux/init.h>
13
14#define DRV_NAME "jmicron"
15
16typedef enum {
17 PORT_PATA0 = 0,
18 PORT_PATA1 = 1,
19 PORT_SATA = 2,
20} port_type;
21
22/**
23 * jmicron_cable_detect - cable detection
24 * @hwif: IDE port
25 *
26 * Returns the cable type.
27 */
28
29static u8 jmicron_cable_detect(ide_hwif_t *hwif)
30{
31 struct pci_dev *pdev = to_pci_dev(hwif->dev);
32
33 u32 control;
34 u32 control5;
35
36 int port = hwif->channel;
37 port_type port_map[2];
38
39 pci_read_config_dword(pdev, 0x40, &control);
40
41 /* There are two basic mappings. One has the two SATA ports merged
42 as master/slave and the secondary as PATA, the other has only the
43 SATA port mapped */
44 if (control & (1 << 23)) {
45 port_map[0] = PORT_SATA;
46 port_map[1] = PORT_PATA0;
47 } else {
48 port_map[0] = PORT_SATA;
49 port_map[1] = PORT_SATA;
50 }
51
52 /* The 365/366 may have this bit set to map the second PATA port
53 as the internal primary channel */
54 pci_read_config_dword(pdev, 0x80, &control5);
55 if (control5 & (1<<24))
56 port_map[0] = PORT_PATA1;
57
58 /* The two ports may then be logically swapped by the firmware */
59 if (control & (1 << 22))
60 port = port ^ 1;
61
62 /*
63 * Now we know which physical port we are talking about we can
64 * actually do our cable checking etc. Thankfully we don't need
65 * to do the plumbing for other cases.
66 */
67 switch (port_map[port]) {
68 case PORT_PATA0:
69 if (control & (1 << 3)) /* 40/80 pin primary */
70 return ATA_CBL_PATA40;
71 return ATA_CBL_PATA80;
72 case PORT_PATA1:
73 if (control5 & (1 << 19)) /* 40/80 pin secondary */
74 return ATA_CBL_PATA40;
75 return ATA_CBL_PATA80;
76 case PORT_SATA:
77 break;
78 }
79 /* Avoid bogus "control reaches end of non-void function" */
80 return ATA_CBL_PATA80;
81}
82
83static void jmicron_set_pio_mode(ide_drive_t *drive, const u8 pio)
84{
85}
86
87/**
88 * jmicron_set_dma_mode - set host controller for DMA mode
89 * @drive: drive
90 * @mode: DMA mode
91 *
92 * As the JMicron snoops for timings we don't need to do anything here.
93 */
94
95static void jmicron_set_dma_mode(ide_drive_t *drive, const u8 mode)
96{
97}
98
99static const struct ide_port_ops jmicron_port_ops = {
100 .set_pio_mode = jmicron_set_pio_mode,
101 .set_dma_mode = jmicron_set_dma_mode,
102 .cable_detect = jmicron_cable_detect,
103};
104
105static const struct ide_port_info jmicron_chipset __devinitdata = {
106 .name = DRV_NAME,
107 .enablebits = { { 0x40, 0x01, 0x01 }, { 0x40, 0x10, 0x10 } },
108 .port_ops = &jmicron_port_ops,
109 .pio_mask = ATA_PIO5,
110 .mwdma_mask = ATA_MWDMA2,
111 .udma_mask = ATA_UDMA6,
112};
113
114/**
115 * jmicron_init_one - pci layer discovery entry
116 * @dev: PCI device
117 * @id: ident table entry
118 *
119 * Called by the PCI code when it finds a Jmicron controller.
120 * We then use the IDE PCI generic helper to do most of the work.
121 */
122
123static int __devinit jmicron_init_one(struct pci_dev *dev, const struct pci_device_id *id)
124{
125 return ide_pci_init_one(dev, &jmicron_chipset, NULL);
126}
127
128/* All JMB PATA controllers have and will continue to have the same
129 * interface. Matching vendor and device class is enough for all
130 * current and future controllers if the controller is programmed
131 * properly.
132 *
133 * If libata is configured, jmicron PCI quirk programs the controller
134 * into the correct mode. If libata isn't configured, match known
135 * device IDs too to maintain backward compatibility.
136 */
137static struct pci_device_id jmicron_pci_tbl[] = {
138#if !defined(CONFIG_ATA) && !defined(CONFIG_ATA_MODULE)
139 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMB361) },
140 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMB363) },
141 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMB365) },
142 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMB366) },
143 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMB368) },
144#endif
145 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
146 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, 0 },
147 { 0, },
148};
149
150MODULE_DEVICE_TABLE(pci, jmicron_pci_tbl);
151
152static struct pci_driver jmicron_pci_driver = {
153 .name = "JMicron IDE",
154 .id_table = jmicron_pci_tbl,
155 .probe = jmicron_init_one,
156 .remove = ide_pci_remove,
157 .suspend = ide_pci_suspend,
158 .resume = ide_pci_resume,
159};
160
161static int __init jmicron_ide_init(void)
162{
163 return ide_pci_register_driver(&jmicron_pci_driver);
164}
165
166static void __exit jmicron_ide_exit(void)
167{
168 pci_unregister_driver(&jmicron_pci_driver);
169}
170
171module_init(jmicron_ide_init);
172module_exit(jmicron_ide_exit);
173
174MODULE_AUTHOR("Alan Cox");
175MODULE_DESCRIPTION("PCI driver module for the JMicron in legacy modes");
176MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/ns87415.c b/drivers/ide/pci/ns87415.c
deleted file mode 100644
index 13789060f407..000000000000
--- a/drivers/ide/pci/ns87415.c
+++ /dev/null
@@ -1,366 +0,0 @@
1/*
2 * Copyright (C) 1997-1998 Mark Lord <mlord@pobox.com>
3 * Copyright (C) 1998 Eddie C. Dost <ecd@skynet.be>
4 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2004 Grant Grundler <grundler at parisc-linux.org>
6 *
7 * Inspired by an earlier effort from David S. Miller <davem@redhat.com>
8 */
9
10#include <linux/module.h>
11#include <linux/types.h>
12#include <linux/kernel.h>
13#include <linux/interrupt.h>
14#include <linux/pci.h>
15#include <linux/delay.h>
16#include <linux/ide.h>
17#include <linux/init.h>
18
19#include <asm/io.h>
20
21#define DRV_NAME "ns87415"
22
23#ifdef CONFIG_SUPERIO
24/* SUPERIO 87560 is a PoS chip that NatSem denies exists.
25 * Unfortunately, it's built-in on all Astro-based PA-RISC workstations
26 * which use the integrated NS87514 cell for CD-ROM support.
27 * i.e we have to support for CD-ROM installs.
28 * See drivers/parisc/superio.c for more gory details.
29 */
30#include <asm/superio.h>
31
32#define SUPERIO_IDE_MAX_RETRIES 25
33
34/* Because of a defect in Super I/O, all reads of the PCI DMA status
35 * registers, IDE status register and the IDE select register need to be
36 * retried
37 */
38static u8 superio_ide_inb (unsigned long port)
39{
40 u8 tmp;
41 int retries = SUPERIO_IDE_MAX_RETRIES;
42
43 /* printk(" [ reading port 0x%x with retry ] ", port); */
44
45 do {
46 tmp = inb(port);
47 if (tmp == 0)
48 udelay(50);
49 } while (tmp == 0 && retries-- > 0);
50
51 return tmp;
52}
53
54static u8 superio_read_status(ide_hwif_t *hwif)
55{
56 return superio_ide_inb(hwif->io_ports.status_addr);
57}
58
59static u8 superio_read_sff_dma_status(ide_hwif_t *hwif)
60{
61 return superio_ide_inb(hwif->dma_base + ATA_DMA_STATUS);
62}
63
64static void superio_tf_read(ide_drive_t *drive, ide_task_t *task)
65{
66 struct ide_io_ports *io_ports = &drive->hwif->io_ports;
67 struct ide_taskfile *tf = &task->tf;
68
69 if (task->tf_flags & IDE_TFLAG_IN_DATA) {
70 u16 data = inw(io_ports->data_addr);
71
72 tf->data = data & 0xff;
73 tf->hob_data = (data >> 8) & 0xff;
74 }
75
76 /* be sure we're looking at the low order bits */
77 outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr);
78
79 if (task->tf_flags & IDE_TFLAG_IN_FEATURE)
80 tf->feature = inb(io_ports->feature_addr);
81 if (task->tf_flags & IDE_TFLAG_IN_NSECT)
82 tf->nsect = inb(io_ports->nsect_addr);
83 if (task->tf_flags & IDE_TFLAG_IN_LBAL)
84 tf->lbal = inb(io_ports->lbal_addr);
85 if (task->tf_flags & IDE_TFLAG_IN_LBAM)
86 tf->lbam = inb(io_ports->lbam_addr);
87 if (task->tf_flags & IDE_TFLAG_IN_LBAH)
88 tf->lbah = inb(io_ports->lbah_addr);
89 if (task->tf_flags & IDE_TFLAG_IN_DEVICE)
90 tf->device = superio_ide_inb(io_ports->device_addr);
91
92 if (task->tf_flags & IDE_TFLAG_LBA48) {
93 outb(ATA_DEVCTL_OBS | 0x80, io_ports->ctl_addr);
94
95 if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
96 tf->hob_feature = inb(io_ports->feature_addr);
97 if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
98 tf->hob_nsect = inb(io_ports->nsect_addr);
99 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
100 tf->hob_lbal = inb(io_ports->lbal_addr);
101 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
102 tf->hob_lbam = inb(io_ports->lbam_addr);
103 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
104 tf->hob_lbah = inb(io_ports->lbah_addr);
105 }
106}
107
108static const struct ide_tp_ops superio_tp_ops = {
109 .exec_command = ide_exec_command,
110 .read_status = superio_read_status,
111 .read_altstatus = ide_read_altstatus,
112 .read_sff_dma_status = superio_read_sff_dma_status,
113
114 .set_irq = ide_set_irq,
115
116 .tf_load = ide_tf_load,
117 .tf_read = superio_tf_read,
118
119 .input_data = ide_input_data,
120 .output_data = ide_output_data,
121};
122
123static void __devinit superio_init_iops(struct hwif_s *hwif)
124{
125 struct pci_dev *pdev = to_pci_dev(hwif->dev);
126 u32 dma_stat;
127 u8 port = hwif->channel, tmp;
128
129 dma_stat = (pci_resource_start(pdev, 4) & ~3) + (!port ? 2 : 0xa);
130
131 /* Clear error/interrupt, enable dma */
132 tmp = superio_ide_inb(dma_stat);
133 outb(tmp | 0x66, dma_stat);
134}
135#endif
136
137static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 };
138
139/*
140 * This routine either enables/disables (according to IDE_DFLAG_PRESENT)
141 * the IRQ associated with the port (HWIF(drive)),
142 * and selects either PIO or DMA handshaking for the next I/O operation.
143 */
144static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
145{
146 ide_hwif_t *hwif = HWIF(drive);
147 struct pci_dev *dev = to_pci_dev(hwif->dev);
148 unsigned int bit, other, new, *old = (unsigned int *) hwif->select_data;
149 unsigned long flags;
150
151 local_irq_save(flags);
152 new = *old;
153
154 /* Adjust IRQ enable bit */
155 bit = 1 << (8 + hwif->channel);
156
157 if (drive->dev_flags & IDE_DFLAG_PRESENT)
158 new &= ~bit;
159 else
160 new |= bit;
161
162 /* Select PIO or DMA, DMA may only be selected for one drive/channel. */
163 bit = 1 << (20 + (drive->dn & 1) + (hwif->channel << 1));
164 other = 1 << (20 + (1 - (drive->dn & 1)) + (hwif->channel << 1));
165 new = use_dma ? ((new & ~other) | bit) : (new & ~bit);
166
167 if (new != *old) {
168 unsigned char stat;
169
170 /*
171 * Don't change DMA engine settings while Write Buffers
172 * are busy.
173 */
174 (void) pci_read_config_byte(dev, 0x43, &stat);
175 while (stat & 0x03) {
176 udelay(1);
177 (void) pci_read_config_byte(dev, 0x43, &stat);
178 }
179
180 *old = new;
181 (void) pci_write_config_dword(dev, 0x40, new);
182
183 /*
184 * And let things settle...
185 */
186 udelay(10);
187 }
188
189 local_irq_restore(flags);
190}
191
192static void ns87415_selectproc (ide_drive_t *drive)
193{
194 ns87415_prepare_drive(drive,
195 !!(drive->dev_flags & IDE_DFLAG_USING_DMA));
196}
197
198static int ns87415_dma_end(ide_drive_t *drive)
199{
200 ide_hwif_t *hwif = HWIF(drive);
201 u8 dma_stat = 0, dma_cmd = 0;
202
203 drive->waiting_for_dma = 0;
204 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
205 /* get DMA command mode */
206 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
207 /* stop DMA */
208 outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
209 /* from ERRATA: clear the INTR & ERROR bits */
210 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
211 outb(dma_cmd | 6, hwif->dma_base + ATA_DMA_CMD);
212 /* and free any DMA resources */
213 ide_destroy_dmatable(drive);
214 /* verify good DMA status */
215 return (dma_stat & 7) != 4;
216}
217
218static int ns87415_dma_setup(ide_drive_t *drive)
219{
220 /* select DMA xfer */
221 ns87415_prepare_drive(drive, 1);
222 if (!ide_dma_setup(drive))
223 return 0;
224 /* DMA failed: select PIO xfer */
225 ns87415_prepare_drive(drive, 0);
226 return 1;
227}
228
229static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif)
230{
231 struct pci_dev *dev = to_pci_dev(hwif->dev);
232 unsigned int ctrl, using_inta;
233 u8 progif;
234#ifdef __sparc_v9__
235 int timeout;
236 u8 stat;
237#endif
238
239 /*
240 * We cannot probe for IRQ: both ports share common IRQ on INTA.
241 * Also, leave IRQ masked during drive probing, to prevent infinite
242 * interrupts from a potentially floating INTA..
243 *
244 * IRQs get unmasked in selectproc when drive is first used.
245 */
246 (void) pci_read_config_dword(dev, 0x40, &ctrl);
247 (void) pci_read_config_byte(dev, 0x09, &progif);
248 /* is irq in "native" mode? */
249 using_inta = progif & (1 << (hwif->channel << 1));
250 if (!using_inta)
251 using_inta = ctrl & (1 << (4 + hwif->channel));
252 if (hwif->mate) {
253 hwif->select_data = hwif->mate->select_data;
254 } else {
255 hwif->select_data = (unsigned long)
256 &ns87415_control[ns87415_count++];
257 ctrl |= (1 << 8) | (1 << 9); /* mask both IRQs */
258 if (using_inta)
259 ctrl &= ~(1 << 6); /* unmask INTA */
260 *((unsigned int *)hwif->select_data) = ctrl;
261 (void) pci_write_config_dword(dev, 0x40, ctrl);
262
263 /*
264 * Set prefetch size to 512 bytes for both ports,
265 * but don't turn on/off prefetching here.
266 */
267 pci_write_config_byte(dev, 0x55, 0xee);
268
269#ifdef __sparc_v9__
270 /*
271 * XXX: Reset the device, if we don't it will not respond to
272 * SELECT_DRIVE() properly during first ide_probe_port().
273 */
274 timeout = 10000;
275 outb(12, hwif->io_ports.ctl_addr);
276 udelay(10);
277 outb(8, hwif->io_ports.ctl_addr);
278 do {
279 udelay(50);
280 stat = hwif->tp_ops->read_status(hwif);
281 if (stat == 0xff)
282 break;
283 } while ((stat & ATA_BUSY) && --timeout);
284#endif
285 }
286
287 if (!using_inta)
288 hwif->irq = __ide_default_irq(hwif->io_ports.data_addr);
289 else if (!hwif->irq && hwif->mate && hwif->mate->irq)
290 hwif->irq = hwif->mate->irq; /* share IRQ with mate */
291
292 if (!hwif->dma_base)
293 return;
294
295 outb(0x60, hwif->dma_base + ATA_DMA_STATUS);
296}
297
298static const struct ide_port_ops ns87415_port_ops = {
299 .selectproc = ns87415_selectproc,
300};
301
302static const struct ide_dma_ops ns87415_dma_ops = {
303 .dma_host_set = ide_dma_host_set,
304 .dma_setup = ns87415_dma_setup,
305 .dma_exec_cmd = ide_dma_exec_cmd,
306 .dma_start = ide_dma_start,
307 .dma_end = ns87415_dma_end,
308 .dma_test_irq = ide_dma_test_irq,
309 .dma_lost_irq = ide_dma_lost_irq,
310 .dma_timeout = ide_dma_timeout,
311};
312
313static const struct ide_port_info ns87415_chipset __devinitdata = {
314 .name = DRV_NAME,
315 .init_hwif = init_hwif_ns87415,
316 .port_ops = &ns87415_port_ops,
317 .dma_ops = &ns87415_dma_ops,
318 .host_flags = IDE_HFLAG_TRUST_BIOS_FOR_DMA |
319 IDE_HFLAG_NO_ATAPI_DMA,
320};
321
322static int __devinit ns87415_init_one(struct pci_dev *dev, const struct pci_device_id *id)
323{
324 struct ide_port_info d = ns87415_chipset;
325
326#ifdef CONFIG_SUPERIO
327 if (PCI_SLOT(dev->devfn) == 0xE) {
328 /* Built-in - assume it's under superio. */
329 d.init_iops = superio_init_iops;
330 d.tp_ops = &superio_tp_ops;
331 }
332#endif
333 return ide_pci_init_one(dev, &d, NULL);
334}
335
336static const struct pci_device_id ns87415_pci_tbl[] = {
337 { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_87415), 0 },
338 { 0, },
339};
340MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl);
341
342static struct pci_driver ns87415_pci_driver = {
343 .name = "NS87415_IDE",
344 .id_table = ns87415_pci_tbl,
345 .probe = ns87415_init_one,
346 .remove = ide_pci_remove,
347 .suspend = ide_pci_suspend,
348 .resume = ide_pci_resume,
349};
350
351static int __init ns87415_ide_init(void)
352{
353 return ide_pci_register_driver(&ns87415_pci_driver);
354}
355
356static void __exit ns87415_ide_exit(void)
357{
358 pci_unregister_driver(&ns87415_pci_driver);
359}
360
361module_init(ns87415_ide_init);
362module_exit(ns87415_ide_exit);
363
364MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick");
365MODULE_DESCRIPTION("PCI driver module for NS87415 IDE");
366MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/opti621.c b/drivers/ide/pci/opti621.c
deleted file mode 100644
index 6048eda3cd61..000000000000
--- a/drivers/ide/pci/opti621.c
+++ /dev/null
@@ -1,247 +0,0 @@
1/*
2 * Copyright (C) 1996-1998 Linus Torvalds & authors (see below)
3 */
4
5/*
6 * Authors:
7 * Jaromir Koutek <miri@punknet.cz>,
8 * Jan Harkes <jaharkes@cwi.nl>,
9 * Mark Lord <mlord@pobox.com>
10 * Some parts of code are from ali14xx.c and from rz1000.c.
11 *
12 * OPTi is trademark of OPTi, Octek is trademark of Octek.
13 *
14 * I used docs from OPTi databook, from ftp.opti.com, file 9123-0002.ps
15 * and disassembled/traced setupvic.exe (DOS program).
16 * It increases kernel code about 2 kB.
17 * I don't have this card no more, but I hope I can get some in case
18 * of needed development.
19 * My card is Octek PIDE 1.01 (on card) or OPTiViC (program).
20 * It has a place for a secondary connector in circuit, but nothing
21 * is there. Also BIOS says no address for
22 * secondary controller (see bellow in ide_init_opti621).
23 * I've only tested this on my system, which only has one disk.
24 * It's Western Digital WDAC2850, with PIO mode 3. The PCI bus
25 * is at 20 MHz (I have DX2/80, I tried PCI at 40, but I got random
26 * lockups). I tried the OCTEK double speed CD-ROM and
27 * it does not work! But I can't boot DOS also, so it's probably
28 * hardware fault. I have connected Conner 80MB, the Seagate 850MB (no
29 * problems) and Seagate 1GB (as slave, WD as master). My experiences
30 * with the third, 1GB drive: I got 3MB/s (hdparm), but sometimes
31 * it slows to about 100kB/s! I don't know why and I have
32 * not this drive now, so I can't try it again.
33 * I write this driver because I lost the paper ("manual") with
34 * settings of jumpers on the card and I have to boot Linux with
35 * Loadlin except LILO, cause I have to run the setupvic.exe program
36 * already or I get disk errors (my test: rpm -Vf
37 * /usr/X11R6/bin/XF86_SVGA - or any big file).
38 * Some numbers from hdparm -t /dev/hda:
39 * Timing buffer-cache reads: 32 MB in 3.02 seconds =10.60 MB/sec
40 * Timing buffered disk reads: 16 MB in 5.52 seconds = 2.90 MB/sec
41 * I have 4 Megs/s before, but I don't know why (maybe changes
42 * in hdparm test).
43 * After release of 0.1, I got some successful reports, so it might work.
44 *
45 * The main problem with OPTi is that some timings for master
46 * and slave must be the same. For example, if you have master
47 * PIO 3 and slave PIO 0, driver have to set some timings of
48 * master for PIO 0. Second problem is that opti621_set_pio_mode
49 * got only one drive to set, but have to set both drives.
50 * This is solved in compute_pios. If you don't set
51 * the second drive, compute_pios use ide_get_best_pio_mode
52 * for autoselect mode (you can change it to PIO 0, if you want).
53 * If you then set the second drive to another PIO, the old value
54 * (automatically selected) will be overrided by yours.
55 * There is a 25/33MHz switch in configuration
56 * register, but driver is written for use at any frequency.
57 *
58 * Version 0.1, Nov 8, 1996
59 * by Jaromir Koutek, for 2.1.8.
60 * Initial version of driver.
61 *
62 * Version 0.2
63 * Number 0.2 skipped.
64 *
65 * Version 0.3, Nov 29, 1997
66 * by Mark Lord (probably), for 2.1.68
67 * Updates for use with new IDE block driver.
68 *
69 * Version 0.4, Dec 14, 1997
70 * by Jan Harkes
71 * Fixed some errors and cleaned the code.
72 *
73 * Version 0.5, Jan 2, 1998
74 * by Jaromir Koutek
75 * Updates for use with (again) new IDE block driver.
76 * Update of documentation.
77 *
78 * Version 0.6, Jan 2, 1999
79 * by Jaromir Koutek
80 * Reversed to version 0.3 of the driver, because
81 * 0.5 doesn't work.
82 */
83
84#include <linux/types.h>
85#include <linux/module.h>
86#include <linux/kernel.h>
87#include <linux/pci.h>
88#include <linux/ide.h>
89
90#include <asm/io.h>
91
92#define DRV_NAME "opti621"
93
94#define READ_REG 0 /* index of Read cycle timing register */
95#define WRITE_REG 1 /* index of Write cycle timing register */
96#define CNTRL_REG 3 /* index of Control register */
97#define STRAP_REG 5 /* index of Strap register */
98#define MISC_REG 6 /* index of Miscellaneous register */
99
100static int reg_base;
101
102static DEFINE_SPINLOCK(opti621_lock);
103
104/* Write value to register reg, base of register
105 * is at reg_base (0x1f0 primary, 0x170 secondary,
106 * if not changed by PCI configuration).
107 * This is from setupvic.exe program.
108 */
109static void write_reg(u8 value, int reg)
110{
111 inw(reg_base + 1);
112 inw(reg_base + 1);
113 outb(3, reg_base + 2);
114 outb(value, reg_base + reg);
115 outb(0x83, reg_base + 2);
116}
117
118/* Read value from register reg, base of register
119 * is at reg_base (0x1f0 primary, 0x170 secondary,
120 * if not changed by PCI configuration).
121 * This is from setupvic.exe program.
122 */
123static u8 read_reg(int reg)
124{
125 u8 ret = 0;
126
127 inw(reg_base + 1);
128 inw(reg_base + 1);
129 outb(3, reg_base + 2);
130 ret = inb(reg_base + reg);
131 outb(0x83, reg_base + 2);
132
133 return ret;
134}
135
136static void opti621_set_pio_mode(ide_drive_t *drive, const u8 pio)
137{
138 ide_hwif_t *hwif = drive->hwif;
139 ide_drive_t *pair = ide_get_pair_dev(drive);
140 unsigned long flags;
141 u8 tim, misc, addr_pio = pio, clk;
142
143 /* DRDY is default 2 (by OPTi Databook) */
144 static const u8 addr_timings[2][5] = {
145 { 0x20, 0x10, 0x00, 0x00, 0x00 }, /* 33 MHz */
146 { 0x10, 0x10, 0x00, 0x00, 0x00 }, /* 25 MHz */
147 };
148 static const u8 data_rec_timings[2][5] = {
149 { 0x5b, 0x45, 0x32, 0x21, 0x20 }, /* 33 MHz */
150 { 0x48, 0x34, 0x21, 0x10, 0x10 } /* 25 MHz */
151 };
152
153 drive->drive_data = XFER_PIO_0 + pio;
154
155 if (pair) {
156 if (pair->drive_data && pair->drive_data < drive->drive_data)
157 addr_pio = pair->drive_data - XFER_PIO_0;
158 }
159
160 spin_lock_irqsave(&opti621_lock, flags);
161
162 reg_base = hwif->io_ports.data_addr;
163
164 /* allow Register-B */
165 outb(0xc0, reg_base + CNTRL_REG);
166 /* hmm, setupvic.exe does this ;-) */
167 outb(0xff, reg_base + 5);
168 /* if reads 0xff, adapter not exist? */
169 (void)inb(reg_base + CNTRL_REG);
170 /* if reads 0xc0, no interface exist? */
171 read_reg(CNTRL_REG);
172
173 /* check CLK speed */
174 clk = read_reg(STRAP_REG) & 1;
175
176 printk(KERN_INFO "%s: CLK = %d MHz\n", hwif->name, clk ? 25 : 33);
177
178 tim = data_rec_timings[clk][pio];
179 misc = addr_timings[clk][addr_pio];
180
181 /* select Index-0/1 for Register-A/B */
182 write_reg(drive->dn & 1, MISC_REG);
183 /* set read cycle timings */
184 write_reg(tim, READ_REG);
185 /* set write cycle timings */
186 write_reg(tim, WRITE_REG);
187
188 /* use Register-A for drive 0 */
189 /* use Register-B for drive 1 */
190 write_reg(0x85, CNTRL_REG);
191
192 /* set address setup, DRDY timings, */
193 /* and read prefetch for both drives */
194 write_reg(misc, MISC_REG);
195
196 spin_unlock_irqrestore(&opti621_lock, flags);
197}
198
199static const struct ide_port_ops opti621_port_ops = {
200 .set_pio_mode = opti621_set_pio_mode,
201};
202
203static const struct ide_port_info opti621_chipset __devinitdata = {
204 .name = DRV_NAME,
205 .enablebits = { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} },
206 .port_ops = &opti621_port_ops,
207 .host_flags = IDE_HFLAG_NO_DMA,
208 .pio_mask = ATA_PIO4,
209};
210
211static int __devinit opti621_init_one(struct pci_dev *dev, const struct pci_device_id *id)
212{
213 return ide_pci_init_one(dev, &opti621_chipset, NULL);
214}
215
216static const struct pci_device_id opti621_pci_tbl[] = {
217 { PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C621), 0 },
218 { PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C825), 0 },
219 { 0, },
220};
221MODULE_DEVICE_TABLE(pci, opti621_pci_tbl);
222
223static struct pci_driver opti621_pci_driver = {
224 .name = "Opti621_IDE",
225 .id_table = opti621_pci_tbl,
226 .probe = opti621_init_one,
227 .remove = ide_pci_remove,
228 .suspend = ide_pci_suspend,
229 .resume = ide_pci_resume,
230};
231
232static int __init opti621_ide_init(void)
233{
234 return ide_pci_register_driver(&opti621_pci_driver);
235}
236
237static void __exit opti621_ide_exit(void)
238{
239 pci_unregister_driver(&opti621_pci_driver);
240}
241
242module_init(opti621_ide_init);
243module_exit(opti621_ide_exit);
244
245MODULE_AUTHOR("Jaromir Koutek, Jan Harkes, Mark Lord");
246MODULE_DESCRIPTION("PCI driver module for Opti621 IDE");
247MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/pdc202xx_new.c b/drivers/ide/pci/pdc202xx_new.c
deleted file mode 100644
index 211ae46e3e0c..000000000000
--- a/drivers/ide/pci/pdc202xx_new.c
+++ /dev/null
@@ -1,588 +0,0 @@
1/*
2 * Promise TX2/TX4/TX2000/133 IDE driver
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * Split from:
10 * linux/drivers/ide/pdc202xx.c Version 0.35 Mar. 30, 2002
11 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
12 * Copyright (C) 2005-2007 MontaVista Software, Inc.
13 * Portions Copyright (C) 1999 Promise Technology, Inc.
14 * Author: Frank Tiernan (frankt@promise.com)
15 * Released under terms of General Public License
16 */
17
18#include <linux/module.h>
19#include <linux/types.h>
20#include <linux/kernel.h>
21#include <linux/delay.h>
22#include <linux/pci.h>
23#include <linux/init.h>
24#include <linux/ide.h>
25
26#include <asm/io.h>
27
28#ifdef CONFIG_PPC_PMAC
29#include <asm/prom.h>
30#include <asm/pci-bridge.h>
31#endif
32
33#define DRV_NAME "pdc202xx_new"
34
35#undef DEBUG
36
37#ifdef DEBUG
38#define DBG(fmt, args...) printk("%s: " fmt, __func__, ## args)
39#else
40#define DBG(fmt, args...)
41#endif
42
43static const char *pdc_quirk_drives[] = {
44 "QUANTUM FIREBALLlct08 08",
45 "QUANTUM FIREBALLP KA6.4",
46 "QUANTUM FIREBALLP KA9.1",
47 "QUANTUM FIREBALLP LM20.4",
48 "QUANTUM FIREBALLP KX13.6",
49 "QUANTUM FIREBALLP KX20.5",
50 "QUANTUM FIREBALLP KX27.3",
51 "QUANTUM FIREBALLP LM20.5",
52 NULL
53};
54
55static u8 max_dma_rate(struct pci_dev *pdev)
56{
57 u8 mode;
58
59 switch(pdev->device) {
60 case PCI_DEVICE_ID_PROMISE_20277:
61 case PCI_DEVICE_ID_PROMISE_20276:
62 case PCI_DEVICE_ID_PROMISE_20275:
63 case PCI_DEVICE_ID_PROMISE_20271:
64 case PCI_DEVICE_ID_PROMISE_20269:
65 mode = 4;
66 break;
67 case PCI_DEVICE_ID_PROMISE_20270:
68 case PCI_DEVICE_ID_PROMISE_20268:
69 mode = 3;
70 break;
71 default:
72 return 0;
73 }
74
75 return mode;
76}
77
78/**
79 * get_indexed_reg - Get indexed register
80 * @hwif: for the port address
81 * @index: index of the indexed register
82 */
83static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
84{
85 u8 value;
86
87 outb(index, hwif->dma_base + 1);
88 value = inb(hwif->dma_base + 3);
89
90 DBG("index[%02X] value[%02X]\n", index, value);
91 return value;
92}
93
94/**
95 * set_indexed_reg - Set indexed register
96 * @hwif: for the port address
97 * @index: index of the indexed register
98 */
99static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
100{
101 outb(index, hwif->dma_base + 1);
102 outb(value, hwif->dma_base + 3);
103 DBG("index[%02X] value[%02X]\n", index, value);
104}
105
106/*
107 * ATA Timing Tables based on 133 MHz PLL output clock.
108 *
109 * If the PLL outputs 100 MHz clock, the ASIC hardware will set
110 * the timing registers automatically when "set features" command is
111 * issued to the device. However, if the PLL output clock is 133 MHz,
112 * the following tables must be used.
113 */
114static struct pio_timing {
115 u8 reg0c, reg0d, reg13;
116} pio_timings [] = {
117 { 0xfb, 0x2b, 0xac }, /* PIO mode 0, IORDY off, Prefetch off */
118 { 0x46, 0x29, 0xa4 }, /* PIO mode 1, IORDY off, Prefetch off */
119 { 0x23, 0x26, 0x64 }, /* PIO mode 2, IORDY off, Prefetch off */
120 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
121 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
122};
123
124static struct mwdma_timing {
125 u8 reg0e, reg0f;
126} mwdma_timings [] = {
127 { 0xdf, 0x5f }, /* MWDMA mode 0 */
128 { 0x6b, 0x27 }, /* MWDMA mode 1 */
129 { 0x69, 0x25 }, /* MWDMA mode 2 */
130};
131
132static struct udma_timing {
133 u8 reg10, reg11, reg12;
134} udma_timings [] = {
135 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
136 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
137 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
138 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
139 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
140 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
141 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
142};
143
144static void pdcnew_set_dma_mode(ide_drive_t *drive, const u8 speed)
145{
146 ide_hwif_t *hwif = HWIF(drive);
147 struct pci_dev *dev = to_pci_dev(hwif->dev);
148 u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
149
150 /*
151 * IDE core issues SETFEATURES_XFER to the drive first (thanks to
152 * IDE_HFLAG_POST_SET_MODE in ->host_flags). PDC202xx hardware will
153 * automatically set the timing registers based on 100 MHz PLL output.
154 *
155 * As we set up the PLL to output 133 MHz for UltraDMA/133 capable
156 * chips, we must override the default register settings...
157 */
158 if (max_dma_rate(dev) == 4) {
159 u8 mode = speed & 0x07;
160
161 if (speed >= XFER_UDMA_0) {
162 set_indexed_reg(hwif, 0x10 + adj,
163 udma_timings[mode].reg10);
164 set_indexed_reg(hwif, 0x11 + adj,
165 udma_timings[mode].reg11);
166 set_indexed_reg(hwif, 0x12 + adj,
167 udma_timings[mode].reg12);
168 } else {
169 set_indexed_reg(hwif, 0x0e + adj,
170 mwdma_timings[mode].reg0e);
171 set_indexed_reg(hwif, 0x0f + adj,
172 mwdma_timings[mode].reg0f);
173 }
174 } else if (speed == XFER_UDMA_2) {
175 /* Set tHOLD bit to 0 if using UDMA mode 2 */
176 u8 tmp = get_indexed_reg(hwif, 0x10 + adj);
177
178 set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
179 }
180}
181
182static void pdcnew_set_pio_mode(ide_drive_t *drive, const u8 pio)
183{
184 ide_hwif_t *hwif = drive->hwif;
185 struct pci_dev *dev = to_pci_dev(hwif->dev);
186 u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
187
188 if (max_dma_rate(dev) == 4) {
189 set_indexed_reg(hwif, 0x0c + adj, pio_timings[pio].reg0c);
190 set_indexed_reg(hwif, 0x0d + adj, pio_timings[pio].reg0d);
191 set_indexed_reg(hwif, 0x13 + adj, pio_timings[pio].reg13);
192 }
193}
194
195static u8 pdcnew_cable_detect(ide_hwif_t *hwif)
196{
197 if (get_indexed_reg(hwif, 0x0b) & 0x04)
198 return ATA_CBL_PATA40;
199 else
200 return ATA_CBL_PATA80;
201}
202
203static void pdcnew_quirkproc(ide_drive_t *drive)
204{
205 const char **list, *m = (char *)&drive->id[ATA_ID_PROD];
206
207 for (list = pdc_quirk_drives; *list != NULL; list++)
208 if (strstr(m, *list) != NULL) {
209 drive->quirk_list = 2;
210 return;
211 }
212
213 drive->quirk_list = 0;
214}
215
216static void pdcnew_reset(ide_drive_t *drive)
217{
218 /*
219 * Deleted this because it is redundant from the caller.
220 */
221 printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n",
222 HWIF(drive)->channel ? "Secondary" : "Primary");
223}
224
225/**
226 * read_counter - Read the byte count registers
227 * @dma_base: for the port address
228 */
229static long read_counter(u32 dma_base)
230{
231 u32 pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08;
232 u8 cnt0, cnt1, cnt2, cnt3;
233 long count = 0, last;
234 int retry = 3;
235
236 do {
237 last = count;
238
239 /* Read the current count */
240 outb(0x20, pri_dma_base + 0x01);
241 cnt0 = inb(pri_dma_base + 0x03);
242 outb(0x21, pri_dma_base + 0x01);
243 cnt1 = inb(pri_dma_base + 0x03);
244 outb(0x20, sec_dma_base + 0x01);
245 cnt2 = inb(sec_dma_base + 0x03);
246 outb(0x21, sec_dma_base + 0x01);
247 cnt3 = inb(sec_dma_base + 0x03);
248
249 count = (cnt3 << 23) | (cnt2 << 15) | (cnt1 << 8) | cnt0;
250
251 /*
252 * The 30-bit decrementing counter is read in 4 pieces.
253 * Incorrect value may be read when the most significant bytes
254 * are changing...
255 */
256 } while (retry-- && (((last ^ count) & 0x3fff8000) || last < count));
257
258 DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n",
259 cnt0, cnt1, cnt2, cnt3);
260
261 return count;
262}
263
264/**
265 * detect_pll_input_clock - Detect the PLL input clock in Hz.
266 * @dma_base: for the port address
267 * E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
268 */
269static long detect_pll_input_clock(unsigned long dma_base)
270{
271 struct timeval start_time, end_time;
272 long start_count, end_count;
273 long pll_input, usec_elapsed;
274 u8 scr1;
275
276 start_count = read_counter(dma_base);
277 do_gettimeofday(&start_time);
278
279 /* Start the test mode */
280 outb(0x01, dma_base + 0x01);
281 scr1 = inb(dma_base + 0x03);
282 DBG("scr1[%02X]\n", scr1);
283 outb(scr1 | 0x40, dma_base + 0x03);
284
285 /* Let the counter run for 10 ms. */
286 mdelay(10);
287
288 end_count = read_counter(dma_base);
289 do_gettimeofday(&end_time);
290
291 /* Stop the test mode */
292 outb(0x01, dma_base + 0x01);
293 scr1 = inb(dma_base + 0x03);
294 DBG("scr1[%02X]\n", scr1);
295 outb(scr1 & ~0x40, dma_base + 0x03);
296
297 /*
298 * Calculate the input clock in Hz
299 * (the clock counter is 30 bit wide and counts down)
300 */
301 usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
302 (end_time.tv_usec - start_time.tv_usec);
303 pll_input = ((start_count - end_count) & 0x3fffffff) / 10 *
304 (10000000 / usec_elapsed);
305
306 DBG("start[%ld] end[%ld]\n", start_count, end_count);
307
308 return pll_input;
309}
310
311#ifdef CONFIG_PPC_PMAC
312static void apple_kiwi_init(struct pci_dev *pdev)
313{
314 struct device_node *np = pci_device_to_OF_node(pdev);
315 u8 conf;
316
317 if (np == NULL || !of_device_is_compatible(np, "kiwi-root"))
318 return;
319
320 if (pdev->revision >= 0x03) {
321 /* Setup chip magic config stuff (from darwin) */
322 pci_read_config_byte (pdev, 0x40, &conf);
323 pci_write_config_byte(pdev, 0x40, (conf | 0x01));
324 }
325}
326#endif /* CONFIG_PPC_PMAC */
327
328static unsigned int init_chipset_pdcnew(struct pci_dev *dev)
329{
330 const char *name = DRV_NAME;
331 unsigned long dma_base = pci_resource_start(dev, 4);
332 unsigned long sec_dma_base = dma_base + 0x08;
333 long pll_input, pll_output, ratio;
334 int f, r;
335 u8 pll_ctl0, pll_ctl1;
336
337 if (dma_base == 0)
338 return -EFAULT;
339
340#ifdef CONFIG_PPC_PMAC
341 apple_kiwi_init(dev);
342#endif
343
344 /* Calculate the required PLL output frequency */
345 switch(max_dma_rate(dev)) {
346 case 4: /* it's 133 MHz for Ultra133 chips */
347 pll_output = 133333333;
348 break;
349 case 3: /* and 100 MHz for Ultra100 chips */
350 default:
351 pll_output = 100000000;
352 break;
353 }
354
355 /*
356 * Detect PLL input clock.
357 * On some systems, where PCI bus is running at non-standard clock rate
358 * (e.g. 25 or 40 MHz), we have to adjust the cycle time.
359 * PDC20268 and newer chips employ PLL circuit to help correct timing
360 * registers setting.
361 */
362 pll_input = detect_pll_input_clock(dma_base);
363 printk(KERN_INFO "%s %s: PLL input clock is %ld kHz\n",
364 name, pci_name(dev), pll_input / 1000);
365
366 /* Sanity check */
367 if (unlikely(pll_input < 5000000L || pll_input > 70000000L)) {
368 printk(KERN_ERR "%s %s: Bad PLL input clock %ld Hz, giving up!"
369 "\n", name, pci_name(dev), pll_input);
370 goto out;
371 }
372
373#ifdef DEBUG
374 DBG("pll_output is %ld Hz\n", pll_output);
375
376 /* Show the current clock value of PLL control register
377 * (maybe already configured by the BIOS)
378 */
379 outb(0x02, sec_dma_base + 0x01);
380 pll_ctl0 = inb(sec_dma_base + 0x03);
381 outb(0x03, sec_dma_base + 0x01);
382 pll_ctl1 = inb(sec_dma_base + 0x03);
383
384 DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
385#endif
386
387 /*
388 * Calculate the ratio of F, R and NO
389 * POUT = (F + 2) / (( R + 2) * NO)
390 */
391 ratio = pll_output / (pll_input / 1000);
392 if (ratio < 8600L) { /* 8.6x */
393 /* Using NO = 0x01, R = 0x0d */
394 r = 0x0d;
395 } else if (ratio < 12900L) { /* 12.9x */
396 /* Using NO = 0x01, R = 0x08 */
397 r = 0x08;
398 } else if (ratio < 16100L) { /* 16.1x */
399 /* Using NO = 0x01, R = 0x06 */
400 r = 0x06;
401 } else if (ratio < 64000L) { /* 64x */
402 r = 0x00;
403 } else {
404 /* Invalid ratio */
405 printk(KERN_ERR "%s %s: Bad ratio %ld, giving up!\n",
406 name, pci_name(dev), ratio);
407 goto out;
408 }
409
410 f = (ratio * (r + 2)) / 1000 - 2;
411
412 DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio);
413
414 if (unlikely(f < 0 || f > 127)) {
415 /* Invalid F */
416 printk(KERN_ERR "%s %s: F[%d] invalid!\n",
417 name, pci_name(dev), f);
418 goto out;
419 }
420
421 pll_ctl0 = (u8) f;
422 pll_ctl1 = (u8) r;
423
424 DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
425
426 outb(0x02, sec_dma_base + 0x01);
427 outb(pll_ctl0, sec_dma_base + 0x03);
428 outb(0x03, sec_dma_base + 0x01);
429 outb(pll_ctl1, sec_dma_base + 0x03);
430
431 /* Wait the PLL circuit to be stable */
432 mdelay(30);
433
434#ifdef DEBUG
435 /*
436 * Show the current clock value of PLL control register
437 */
438 outb(0x02, sec_dma_base + 0x01);
439 pll_ctl0 = inb(sec_dma_base + 0x03);
440 outb(0x03, sec_dma_base + 0x01);
441 pll_ctl1 = inb(sec_dma_base + 0x03);
442
443 DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
444#endif
445
446 out:
447 return dev->irq;
448}
449
450static struct pci_dev * __devinit pdc20270_get_dev2(struct pci_dev *dev)
451{
452 struct pci_dev *dev2;
453
454 dev2 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn) + 1,
455 PCI_FUNC(dev->devfn)));
456
457 if (dev2 &&
458 dev2->vendor == dev->vendor &&
459 dev2->device == dev->device) {
460
461 if (dev2->irq != dev->irq) {
462 dev2->irq = dev->irq;
463 printk(KERN_INFO DRV_NAME " %s: PCI config space "
464 "interrupt fixed\n", pci_name(dev));
465 }
466
467 return dev2;
468 }
469
470 return NULL;
471}
472
473static const struct ide_port_ops pdcnew_port_ops = {
474 .set_pio_mode = pdcnew_set_pio_mode,
475 .set_dma_mode = pdcnew_set_dma_mode,
476 .quirkproc = pdcnew_quirkproc,
477 .resetproc = pdcnew_reset,
478 .cable_detect = pdcnew_cable_detect,
479};
480
481#define DECLARE_PDCNEW_DEV(udma) \
482 { \
483 .name = DRV_NAME, \
484 .init_chipset = init_chipset_pdcnew, \
485 .port_ops = &pdcnew_port_ops, \
486 .host_flags = IDE_HFLAG_POST_SET_MODE | \
487 IDE_HFLAG_ERROR_STOPS_FIFO | \
488 IDE_HFLAG_OFF_BOARD, \
489 .pio_mask = ATA_PIO4, \
490 .mwdma_mask = ATA_MWDMA2, \
491 .udma_mask = udma, \
492 }
493
494static const struct ide_port_info pdcnew_chipsets[] __devinitdata = {
495 /* 0: PDC202{68,70} */ DECLARE_PDCNEW_DEV(ATA_UDMA5),
496 /* 1: PDC202{69,71,75,76,77} */ DECLARE_PDCNEW_DEV(ATA_UDMA6),
497};
498
499/**
500 * pdc202new_init_one - called when a pdc202xx is found
501 * @dev: the pdc202new device
502 * @id: the matching pci id
503 *
504 * Called when the PCI registration layer (or the IDE initialization)
505 * finds a device matching our IDE device tables.
506 */
507
508static int __devinit pdc202new_init_one(struct pci_dev *dev, const struct pci_device_id *id)
509{
510 const struct ide_port_info *d = &pdcnew_chipsets[id->driver_data];
511 struct pci_dev *bridge = dev->bus->self;
512
513 if (dev->device == PCI_DEVICE_ID_PROMISE_20270 && bridge &&
514 bridge->vendor == PCI_VENDOR_ID_DEC &&
515 bridge->device == PCI_DEVICE_ID_DEC_21150) {
516 struct pci_dev *dev2;
517
518 if (PCI_SLOT(dev->devfn) & 2)
519 return -ENODEV;
520
521 dev2 = pdc20270_get_dev2(dev);
522
523 if (dev2) {
524 int ret = ide_pci_init_two(dev, dev2, d, NULL);
525 if (ret < 0)
526 pci_dev_put(dev2);
527 return ret;
528 }
529 }
530
531 if (dev->device == PCI_DEVICE_ID_PROMISE_20276 && bridge &&
532 bridge->vendor == PCI_VENDOR_ID_INTEL &&
533 (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
534 bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
535 printk(KERN_INFO DRV_NAME " %s: attached to I2O RAID controller,"
536 " skipping\n", pci_name(dev));
537 return -ENODEV;
538 }
539
540 return ide_pci_init_one(dev, d, NULL);
541}
542
543static void __devexit pdc202new_remove(struct pci_dev *dev)
544{
545 struct ide_host *host = pci_get_drvdata(dev);
546 struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;
547
548 ide_pci_remove(dev);
549 pci_dev_put(dev2);
550}
551
552static const struct pci_device_id pdc202new_pci_tbl[] = {
553 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), 0 },
554 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), 1 },
555 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), 0 },
556 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), 1 },
557 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), 1 },
558 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), 1 },
559 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), 1 },
560 { 0, },
561};
562MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);
563
564static struct pci_driver pdc202new_pci_driver = {
565 .name = "Promise_IDE",
566 .id_table = pdc202new_pci_tbl,
567 .probe = pdc202new_init_one,
568 .remove = __devexit_p(pdc202new_remove),
569 .suspend = ide_pci_suspend,
570 .resume = ide_pci_resume,
571};
572
573static int __init pdc202new_ide_init(void)
574{
575 return ide_pci_register_driver(&pdc202new_pci_driver);
576}
577
578static void __exit pdc202new_ide_exit(void)
579{
580 pci_unregister_driver(&pdc202new_pci_driver);
581}
582
583module_init(pdc202new_ide_init);
584module_exit(pdc202new_ide_exit);
585
586MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
587MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
588MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/pdc202xx_old.c b/drivers/ide/pci/pdc202xx_old.c
deleted file mode 100644
index 799557c25eef..000000000000
--- a/drivers/ide/pci/pdc202xx_old.c
+++ /dev/null
@@ -1,453 +0,0 @@
1/*
2 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
3 * Copyright (C) 2006-2007 MontaVista Software, Inc.
4 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
5 *
6 * Portions Copyright (C) 1999 Promise Technology, Inc.
7 * Author: Frank Tiernan (frankt@promise.com)
8 * Released under terms of General Public License
9 */
10
11#include <linux/types.h>
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/delay.h>
15#include <linux/blkdev.h>
16#include <linux/pci.h>
17#include <linux/init.h>
18#include <linux/ide.h>
19
20#include <asm/io.h>
21
22#define DRV_NAME "pdc202xx_old"
23
24#define PDC202XX_DEBUG_DRIVE_INFO 0
25
26static const char *pdc_quirk_drives[] = {
27 "QUANTUM FIREBALLlct08 08",
28 "QUANTUM FIREBALLP KA6.4",
29 "QUANTUM FIREBALLP KA9.1",
30 "QUANTUM FIREBALLP LM20.4",
31 "QUANTUM FIREBALLP KX13.6",
32 "QUANTUM FIREBALLP KX20.5",
33 "QUANTUM FIREBALLP KX27.3",
34 "QUANTUM FIREBALLP LM20.5",
35 NULL
36};
37
38static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
39
40static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
41{
42 ide_hwif_t *hwif = HWIF(drive);
43 struct pci_dev *dev = to_pci_dev(hwif->dev);
44 u8 drive_pci = 0x60 + (drive->dn << 2);
45
46 u8 AP = 0, BP = 0, CP = 0;
47 u8 TA = 0, TB = 0, TC = 0;
48
49#if PDC202XX_DEBUG_DRIVE_INFO
50 u32 drive_conf = 0;
51 pci_read_config_dword(dev, drive_pci, &drive_conf);
52#endif
53
54 /*
55 * TODO: do this once per channel
56 */
57 if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
58 pdc_old_disable_66MHz_clock(hwif);
59
60 pci_read_config_byte(dev, drive_pci, &AP);
61 pci_read_config_byte(dev, drive_pci + 1, &BP);
62 pci_read_config_byte(dev, drive_pci + 2, &CP);
63
64 switch(speed) {
65 case XFER_UDMA_5:
66 case XFER_UDMA_4: TB = 0x20; TC = 0x01; break;
67 case XFER_UDMA_2: TB = 0x20; TC = 0x01; break;
68 case XFER_UDMA_3:
69 case XFER_UDMA_1: TB = 0x40; TC = 0x02; break;
70 case XFER_UDMA_0:
71 case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
72 case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
73 case XFER_MW_DMA_0: TB = 0xE0; TC = 0x0F; break;
74 case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
75 case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
76 case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
77 case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
78 case XFER_PIO_0:
79 default: TA = 0x09; TB = 0x13; break;
80 }
81
82 if (speed < XFER_SW_DMA_0) {
83 /*
84 * preserve SYNC_INT / ERDDY_EN bits while clearing
85 * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
86 */
87 AP &= ~0x3f;
88 if (ata_id_iordy_disable(drive->id))
89 AP |= 0x20; /* set IORDY_EN bit */
90 if (drive->media == ide_disk)
91 AP |= 0x10; /* set Prefetch_EN bit */
92 /* clear PB[4:0] bits of register B */
93 BP &= ~0x1f;
94 pci_write_config_byte(dev, drive_pci, AP | TA);
95 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
96 } else {
97 /* clear MB[2:0] bits of register B */
98 BP &= ~0xe0;
99 /* clear MC[3:0] bits of register C */
100 CP &= ~0x0f;
101 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
102 pci_write_config_byte(dev, drive_pci + 2, CP | TC);
103 }
104
105#if PDC202XX_DEBUG_DRIVE_INFO
106 printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
107 drive->name, ide_xfer_verbose(speed),
108 drive->dn, drive_conf);
109 pci_read_config_dword(dev, drive_pci, &drive_conf);
110 printk("0x%08x\n", drive_conf);
111#endif
112}
113
114static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
115{
116 pdc202xx_set_mode(drive, XFER_PIO_0 + pio);
117}
118
119static u8 pdc2026x_cable_detect(ide_hwif_t *hwif)
120{
121 struct pci_dev *dev = to_pci_dev(hwif->dev);
122 u16 CIS, mask = hwif->channel ? (1 << 11) : (1 << 10);
123
124 pci_read_config_word(dev, 0x50, &CIS);
125
126 return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
127}
128
129/*
130 * Set the control register to use the 66MHz system
131 * clock for UDMA 3/4/5 mode operation when necessary.
132 *
133 * FIXME: this register is shared by both channels, some locking is needed
134 *
135 * It may also be possible to leave the 66MHz clock on
136 * and readjust the timing parameters.
137 */
138static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
139{
140 unsigned long clock_reg = hwif->extra_base + 0x01;
141 u8 clock = inb(clock_reg);
142
143 outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
144}
145
146static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
147{
148 unsigned long clock_reg = hwif->extra_base + 0x01;
149 u8 clock = inb(clock_reg);
150
151 outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
152}
153
154static void pdc202xx_quirkproc(ide_drive_t *drive)
155{
156 const char **list, *m = (char *)&drive->id[ATA_ID_PROD];
157
158 for (list = pdc_quirk_drives; *list != NULL; list++)
159 if (strstr(m, *list) != NULL) {
160 drive->quirk_list = 2;
161 return;
162 }
163
164 drive->quirk_list = 0;
165}
166
167static void pdc202xx_dma_start(ide_drive_t *drive)
168{
169 if (drive->current_speed > XFER_UDMA_2)
170 pdc_old_enable_66MHz_clock(drive->hwif);
171 if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) {
172 struct request *rq = HWGROUP(drive)->rq;
173 ide_hwif_t *hwif = HWIF(drive);
174 unsigned long high_16 = hwif->extra_base - 16;
175 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
176 u32 word_count = 0;
177 u8 clock = inb(high_16 + 0x11);
178
179 outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
180 word_count = (rq->nr_sectors << 8);
181 word_count = (rq_data_dir(rq) == READ) ?
182 word_count | 0x05000000 :
183 word_count | 0x06000000;
184 outl(word_count, atapi_reg);
185 }
186 ide_dma_start(drive);
187}
188
189static int pdc202xx_dma_end(ide_drive_t *drive)
190{
191 if (drive->media != ide_disk || (drive->dev_flags & IDE_DFLAG_LBA48)) {
192 ide_hwif_t *hwif = HWIF(drive);
193 unsigned long high_16 = hwif->extra_base - 16;
194 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
195 u8 clock = 0;
196
197 outl(0, atapi_reg); /* zero out extra */
198 clock = inb(high_16 + 0x11);
199 outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
200 }
201 if (drive->current_speed > XFER_UDMA_2)
202 pdc_old_disable_66MHz_clock(drive->hwif);
203 return ide_dma_end(drive);
204}
205
206static int pdc202xx_dma_test_irq(ide_drive_t *drive)
207{
208 ide_hwif_t *hwif = HWIF(drive);
209 unsigned long high_16 = hwif->extra_base - 16;
210 u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
211 u8 sc1d = inb(high_16 + 0x001d);
212
213 if (hwif->channel) {
214 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
215 if ((sc1d & 0x50) == 0x50)
216 goto somebody_else;
217 else if ((sc1d & 0x40) == 0x40)
218 return (dma_stat & 4) == 4;
219 } else {
220 /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
221 if ((sc1d & 0x05) == 0x05)
222 goto somebody_else;
223 else if ((sc1d & 0x04) == 0x04)
224 return (dma_stat & 4) == 4;
225 }
226somebody_else:
227 return (dma_stat & 4) == 4; /* return 1 if INTR asserted */
228}
229
230static void pdc202xx_reset_host (ide_hwif_t *hwif)
231{
232 unsigned long high_16 = hwif->extra_base - 16;
233 u8 udma_speed_flag = inb(high_16 | 0x001f);
234
235 outb(udma_speed_flag | 0x10, high_16 | 0x001f);
236 mdelay(100);
237 outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
238 mdelay(2000); /* 2 seconds ?! */
239
240 printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
241 hwif->channel ? "Secondary" : "Primary");
242}
243
244static void pdc202xx_reset (ide_drive_t *drive)
245{
246 ide_hwif_t *hwif = HWIF(drive);
247 ide_hwif_t *mate = hwif->mate;
248
249 pdc202xx_reset_host(hwif);
250 pdc202xx_reset_host(mate);
251
252 ide_set_max_pio(drive);
253}
254
255static void pdc202xx_dma_lost_irq(ide_drive_t *drive)
256{
257 pdc202xx_reset(drive);
258 ide_dma_lost_irq(drive);
259}
260
261static void pdc202xx_dma_timeout(ide_drive_t *drive)
262{
263 pdc202xx_reset(drive);
264 ide_dma_timeout(drive);
265}
266
267static unsigned int init_chipset_pdc202xx(struct pci_dev *dev)
268{
269 unsigned long dmabase = pci_resource_start(dev, 4);
270 u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
271
272 if (dmabase == 0)
273 goto out;
274
275 udma_speed_flag = inb(dmabase | 0x1f);
276 primary_mode = inb(dmabase | 0x1a);
277 secondary_mode = inb(dmabase | 0x1b);
278 printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
279 "Primary %s Mode " \
280 "Secondary %s Mode.\n", pci_name(dev),
281 (udma_speed_flag & 1) ? "EN" : "DIS",
282 (primary_mode & 1) ? "MASTER" : "PCI",
283 (secondary_mode & 1) ? "MASTER" : "PCI" );
284
285 if (!(udma_speed_flag & 1)) {
286 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
287 pci_name(dev), udma_speed_flag,
288 (udma_speed_flag|1));
289 outb(udma_speed_flag | 1, dmabase | 0x1f);
290 printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
291 }
292out:
293 return dev->irq;
294}
295
296static void __devinit pdc202ata4_fixup_irq(struct pci_dev *dev,
297 const char *name)
298{
299 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
300 u8 irq = 0, irq2 = 0;
301 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
302 /* 0xbc */
303 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
304 if (irq != irq2) {
305 pci_write_config_byte(dev,
306 (PCI_INTERRUPT_LINE)|0x80, irq); /* 0xbc */
307 printk(KERN_INFO "%s %s: PCI config space interrupt "
308 "mirror fixed\n", name, pci_name(dev));
309 }
310 }
311}
312
313#define IDE_HFLAGS_PDC202XX \
314 (IDE_HFLAG_ERROR_STOPS_FIFO | \
315 IDE_HFLAG_OFF_BOARD)
316
317static const struct ide_port_ops pdc20246_port_ops = {
318 .set_pio_mode = pdc202xx_set_pio_mode,
319 .set_dma_mode = pdc202xx_set_mode,
320 .quirkproc = pdc202xx_quirkproc,
321};
322
323static const struct ide_port_ops pdc2026x_port_ops = {
324 .set_pio_mode = pdc202xx_set_pio_mode,
325 .set_dma_mode = pdc202xx_set_mode,
326 .quirkproc = pdc202xx_quirkproc,
327 .resetproc = pdc202xx_reset,
328 .cable_detect = pdc2026x_cable_detect,
329};
330
331static const struct ide_dma_ops pdc20246_dma_ops = {
332 .dma_host_set = ide_dma_host_set,
333 .dma_setup = ide_dma_setup,
334 .dma_exec_cmd = ide_dma_exec_cmd,
335 .dma_start = ide_dma_start,
336 .dma_end = ide_dma_end,
337 .dma_test_irq = pdc202xx_dma_test_irq,
338 .dma_lost_irq = pdc202xx_dma_lost_irq,
339 .dma_timeout = pdc202xx_dma_timeout,
340};
341
342static const struct ide_dma_ops pdc2026x_dma_ops = {
343 .dma_host_set = ide_dma_host_set,
344 .dma_setup = ide_dma_setup,
345 .dma_exec_cmd = ide_dma_exec_cmd,
346 .dma_start = pdc202xx_dma_start,
347 .dma_end = pdc202xx_dma_end,
348 .dma_test_irq = pdc202xx_dma_test_irq,
349 .dma_lost_irq = pdc202xx_dma_lost_irq,
350 .dma_timeout = pdc202xx_dma_timeout,
351};
352
353#define DECLARE_PDC2026X_DEV(udma, extra_flags) \
354 { \
355 .name = DRV_NAME, \
356 .init_chipset = init_chipset_pdc202xx, \
357 .port_ops = &pdc2026x_port_ops, \
358 .dma_ops = &pdc2026x_dma_ops, \
359 .host_flags = IDE_HFLAGS_PDC202XX | extra_flags, \
360 .pio_mask = ATA_PIO4, \
361 .mwdma_mask = ATA_MWDMA2, \
362 .udma_mask = udma, \
363 }
364
365static const struct ide_port_info pdc202xx_chipsets[] __devinitdata = {
366 { /* 0: PDC20246 */
367 .name = DRV_NAME,
368 .init_chipset = init_chipset_pdc202xx,
369 .port_ops = &pdc20246_port_ops,
370 .dma_ops = &pdc20246_dma_ops,
371 .host_flags = IDE_HFLAGS_PDC202XX,
372 .pio_mask = ATA_PIO4,
373 .mwdma_mask = ATA_MWDMA2,
374 .udma_mask = ATA_UDMA2,
375 },
376
377 /* 1: PDC2026{2,3} */
378 DECLARE_PDC2026X_DEV(ATA_UDMA4, 0),
379 /* 2: PDC2026{5,7} */
380 DECLARE_PDC2026X_DEV(ATA_UDMA5, IDE_HFLAG_RQSIZE_256),
381};
382
383/**
384 * pdc202xx_init_one - called when a PDC202xx is found
385 * @dev: the pdc202xx device
386 * @id: the matching pci id
387 *
388 * Called when the PCI registration layer (or the IDE initialization)
389 * finds a device matching our IDE device tables.
390 */
391
392static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
393{
394 const struct ide_port_info *d;
395 u8 idx = id->driver_data;
396
397 d = &pdc202xx_chipsets[idx];
398
399 if (idx < 2)
400 pdc202ata4_fixup_irq(dev, d->name);
401
402 if (dev->vendor == PCI_DEVICE_ID_PROMISE_20265) {
403 struct pci_dev *bridge = dev->bus->self;
404
405 if (bridge &&
406 bridge->vendor == PCI_VENDOR_ID_INTEL &&
407 (bridge->device == PCI_DEVICE_ID_INTEL_I960 ||
408 bridge->device == PCI_DEVICE_ID_INTEL_I960RM)) {
409 printk(KERN_INFO DRV_NAME " %s: skipping Promise "
410 "PDC20265 attached to I2O RAID controller\n",
411 pci_name(dev));
412 return -ENODEV;
413 }
414 }
415
416 return ide_pci_init_one(dev, d, NULL);
417}
418
419static const struct pci_device_id pdc202xx_pci_tbl[] = {
420 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
421 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
422 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
423 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
424 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
425 { 0, },
426};
427MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
428
429static struct pci_driver pdc202xx_pci_driver = {
430 .name = "Promise_Old_IDE",
431 .id_table = pdc202xx_pci_tbl,
432 .probe = pdc202xx_init_one,
433 .remove = ide_pci_remove,
434 .suspend = ide_pci_suspend,
435 .resume = ide_pci_resume,
436};
437
438static int __init pdc202xx_ide_init(void)
439{
440 return ide_pci_register_driver(&pdc202xx_pci_driver);
441}
442
443static void __exit pdc202xx_ide_exit(void)
444{
445 pci_unregister_driver(&pdc202xx_pci_driver);
446}
447
448module_init(pdc202xx_ide_init);
449module_exit(pdc202xx_ide_exit);
450
451MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
452MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
453MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/piix.c b/drivers/ide/pci/piix.c
deleted file mode 100644
index d63f9fdca76b..000000000000
--- a/drivers/ide/pci/piix.c
+++ /dev/null
@@ -1,480 +0,0 @@
1/*
2 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
3 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
4 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
5 * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
6 *
7 * May be copied or modified under the terms of the GNU General Public License
8 *
9 * Documentation:
10 *
11 * Publically available from Intel web site. Errata documentation
12 * is also publically available. As an aide to anyone hacking on this
13 * driver the list of errata that are relevant is below.going back to
14 * PIIX4. Older device documentation is now a bit tricky to find.
15 *
16 * Errata of note:
17 *
18 * Unfixable
19 * PIIX4 errata #9 - Only on ultra obscure hw
20 * ICH3 errata #13 - Not observed to affect real hw
21 * by Intel
22 *
23 * Things we must deal with
24 * PIIX4 errata #10 - BM IDE hang with non UDMA
25 * (must stop/start dma to recover)
26 * 440MX errata #15 - As PIIX4 errata #10
27 * PIIX4 errata #15 - Must not read control registers
28 * during a PIO transfer
29 * 440MX errata #13 - As PIIX4 errata #15
30 * ICH2 errata #21 - DMA mode 0 doesn't work right
31 * ICH0/1 errata #55 - As ICH2 errata #21
32 * ICH2 spec c #9 - Extra operations needed to handle
33 * drive hotswap [NOT YET SUPPORTED]
34 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
35 * and must be dword aligned
36 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
37 *
38 * Should have been BIOS fixed:
39 * 450NX: errata #19 - DMA hangs on old 450NX
40 * 450NX: errata #20 - DMA hangs on old 450NX
41 * 450NX: errata #25 - Corruption with DMA on old 450NX
42 * ICH3 errata #15 - IDE deadlock under high load
43 * (BIOS must set dev 31 fn 0 bit 23)
44 * ICH3 errata #18 - Don't use native mode
45 */
46
47#include <linux/types.h>
48#include <linux/module.h>
49#include <linux/kernel.h>
50#include <linux/pci.h>
51#include <linux/ide.h>
52#include <linux/init.h>
53
54#include <asm/io.h>
55
56#define DRV_NAME "piix"
57
58static int no_piix_dma;
59
60/**
61 * piix_set_pio_mode - set host controller for PIO mode
62 * @drive: drive
63 * @pio: PIO mode number
64 *
65 * Set the interface PIO mode based upon the settings done by AMI BIOS.
66 */
67
68static void piix_set_pio_mode(ide_drive_t *drive, const u8 pio)
69{
70 ide_hwif_t *hwif = HWIF(drive);
71 struct pci_dev *dev = to_pci_dev(hwif->dev);
72 int is_slave = drive->dn & 1;
73 int master_port = hwif->channel ? 0x42 : 0x40;
74 int slave_port = 0x44;
75 unsigned long flags;
76 u16 master_data;
77 u8 slave_data;
78 static DEFINE_SPINLOCK(tune_lock);
79 int control = 0;
80
81 /* ISP RTC */
82 static const u8 timings[][2]= {
83 { 0, 0 },
84 { 0, 0 },
85 { 1, 0 },
86 { 2, 1 },
87 { 2, 3 }, };
88
89 /*
90 * Master vs slave is synchronized above us but the slave register is
91 * shared by the two hwifs so the corner case of two slave timeouts in
92 * parallel must be locked.
93 */
94 spin_lock_irqsave(&tune_lock, flags);
95 pci_read_config_word(dev, master_port, &master_data);
96
97 if (pio > 1)
98 control |= 1; /* Programmable timing on */
99 if (drive->media == ide_disk)
100 control |= 4; /* Prefetch, post write */
101 if (pio > 2)
102 control |= 2; /* IORDY */
103 if (is_slave) {
104 master_data |= 0x4000;
105 master_data &= ~0x0070;
106 if (pio > 1) {
107 /* Set PPE, IE and TIME */
108 master_data |= control << 4;
109 }
110 pci_read_config_byte(dev, slave_port, &slave_data);
111 slave_data &= hwif->channel ? 0x0f : 0xf0;
112 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
113 (hwif->channel ? 4 : 0);
114 } else {
115 master_data &= ~0x3307;
116 if (pio > 1) {
117 /* enable PPE, IE and TIME */
118 master_data |= control;
119 }
120 master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
121 }
122 pci_write_config_word(dev, master_port, master_data);
123 if (is_slave)
124 pci_write_config_byte(dev, slave_port, slave_data);
125 spin_unlock_irqrestore(&tune_lock, flags);
126}
127
128/**
129 * piix_set_dma_mode - set host controller for DMA mode
130 * @drive: drive
131 * @speed: DMA mode
132 *
133 * Set a PIIX host controller to the desired DMA mode. This involves
134 * programming the right timing data into the PCI configuration space.
135 */
136
137static void piix_set_dma_mode(ide_drive_t *drive, const u8 speed)
138{
139 ide_hwif_t *hwif = HWIF(drive);
140 struct pci_dev *dev = to_pci_dev(hwif->dev);
141 u8 maslave = hwif->channel ? 0x42 : 0x40;
142 int a_speed = 3 << (drive->dn * 4);
143 int u_flag = 1 << drive->dn;
144 int v_flag = 0x01 << drive->dn;
145 int w_flag = 0x10 << drive->dn;
146 int u_speed = 0;
147 int sitre;
148 u16 reg4042, reg4a;
149 u8 reg48, reg54, reg55;
150
151 pci_read_config_word(dev, maslave, &reg4042);
152 sitre = (reg4042 & 0x4000) ? 1 : 0;
153 pci_read_config_byte(dev, 0x48, &reg48);
154 pci_read_config_word(dev, 0x4a, &reg4a);
155 pci_read_config_byte(dev, 0x54, &reg54);
156 pci_read_config_byte(dev, 0x55, &reg55);
157
158 if (speed >= XFER_UDMA_0) {
159 u8 udma = speed - XFER_UDMA_0;
160
161 u_speed = min_t(u8, 2 - (udma & 1), udma) << (drive->dn * 4);
162
163 if (!(reg48 & u_flag))
164 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
165 if (speed == XFER_UDMA_5) {
166 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
167 } else {
168 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
169 }
170 if ((reg4a & a_speed) != u_speed)
171 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
172 if (speed > XFER_UDMA_2) {
173 if (!(reg54 & v_flag))
174 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
175 } else
176 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
177 } else {
178 const u8 mwdma_to_pio[] = { 0, 3, 4 };
179 u8 pio;
180
181 if (reg48 & u_flag)
182 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
183 if (reg4a & a_speed)
184 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
185 if (reg54 & v_flag)
186 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
187 if (reg55 & w_flag)
188 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
189
190 if (speed >= XFER_MW_DMA_0)
191 pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
192 else
193 pio = 2; /* only SWDMA2 is allowed */
194
195 piix_set_pio_mode(drive, pio);
196 }
197}
198
199/**
200 * init_chipset_ich - set up the ICH chipset
201 * @dev: PCI device to set up
202 *
203 * Initialize the PCI device as required. For the ICH this turns
204 * out to be nice and simple.
205 */
206
207static unsigned int init_chipset_ich(struct pci_dev *dev)
208{
209 u32 extra = 0;
210
211 pci_read_config_dword(dev, 0x54, &extra);
212 pci_write_config_dword(dev, 0x54, extra | 0x400);
213
214 return 0;
215}
216
217/**
218 * ich_clear_irq - clear BMDMA status
219 * @drive: IDE drive
220 *
221 * ICHx contollers set DMA INTR no matter DMA or PIO.
222 * BMDMA status might need to be cleared even for
223 * PIO interrupts to prevent spurious/lost IRQ.
224 */
225static void ich_clear_irq(ide_drive_t *drive)
226{
227 ide_hwif_t *hwif = HWIF(drive);
228 u8 dma_stat;
229
230 /*
231 * ide_dma_end() needs BMDMA status for error checking.
232 * So, skip clearing BMDMA status here and leave it
233 * to ide_dma_end() if this is DMA interrupt.
234 */
235 if (drive->waiting_for_dma || hwif->dma_base == 0)
236 return;
237
238 /* clear the INTR & ERROR bits */
239 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
240 /* Should we force the bit as well ? */
241 outb(dma_stat, hwif->dma_base + ATA_DMA_STATUS);
242}
243
244struct ich_laptop {
245 u16 device;
246 u16 subvendor;
247 u16 subdevice;
248};
249
250/*
251 * List of laptops that use short cables rather than 80 wire
252 */
253
254static const struct ich_laptop ich_laptop[] = {
255 /* devid, subvendor, subdev */
256 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
257 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
258 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
259 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
260 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
261 { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */
262 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on Acer Aspire 2023WLMi */
263 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
264 /* end marker */
265 { 0, }
266};
267
268static u8 piix_cable_detect(ide_hwif_t *hwif)
269{
270 struct pci_dev *pdev = to_pci_dev(hwif->dev);
271 const struct ich_laptop *lap = &ich_laptop[0];
272 u8 reg54h = 0, mask = hwif->channel ? 0xc0 : 0x30;
273
274 /* check for specials */
275 while (lap->device) {
276 if (lap->device == pdev->device &&
277 lap->subvendor == pdev->subsystem_vendor &&
278 lap->subdevice == pdev->subsystem_device) {
279 return ATA_CBL_PATA40_SHORT;
280 }
281 lap++;
282 }
283
284 pci_read_config_byte(pdev, 0x54, &reg54h);
285
286 return (reg54h & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
287}
288
289/**
290 * init_hwif_piix - fill in the hwif for the PIIX
291 * @hwif: IDE interface
292 *
293 * Set up the ide_hwif_t for the PIIX interface according to the
294 * capabilities of the hardware.
295 */
296
297static void __devinit init_hwif_piix(ide_hwif_t *hwif)
298{
299 if (!hwif->dma_base)
300 return;
301
302 if (no_piix_dma)
303 hwif->ultra_mask = hwif->mwdma_mask = hwif->swdma_mask = 0;
304}
305
306static const struct ide_port_ops piix_port_ops = {
307 .set_pio_mode = piix_set_pio_mode,
308 .set_dma_mode = piix_set_dma_mode,
309 .cable_detect = piix_cable_detect,
310};
311
312static const struct ide_port_ops ich_port_ops = {
313 .set_pio_mode = piix_set_pio_mode,
314 .set_dma_mode = piix_set_dma_mode,
315 .clear_irq = ich_clear_irq,
316 .cable_detect = piix_cable_detect,
317};
318
319#ifndef CONFIG_IA64
320 #define IDE_HFLAGS_PIIX IDE_HFLAG_LEGACY_IRQS
321#else
322 #define IDE_HFLAGS_PIIX 0
323#endif
324
325#define DECLARE_PIIX_DEV(udma) \
326 { \
327 .name = DRV_NAME, \
328 .init_hwif = init_hwif_piix, \
329 .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
330 .port_ops = &piix_port_ops, \
331 .host_flags = IDE_HFLAGS_PIIX, \
332 .pio_mask = ATA_PIO4, \
333 .swdma_mask = ATA_SWDMA2_ONLY, \
334 .mwdma_mask = ATA_MWDMA12_ONLY, \
335 .udma_mask = udma, \
336 }
337
338#define DECLARE_ICH_DEV(udma) \
339 { \
340 .name = DRV_NAME, \
341 .init_chipset = init_chipset_ich, \
342 .init_hwif = init_hwif_piix, \
343 .enablebits = {{0x41,0x80,0x80}, {0x43,0x80,0x80}}, \
344 .port_ops = &ich_port_ops, \
345 .host_flags = IDE_HFLAGS_PIIX, \
346 .pio_mask = ATA_PIO4, \
347 .swdma_mask = ATA_SWDMA2_ONLY, \
348 .mwdma_mask = ATA_MWDMA12_ONLY, \
349 .udma_mask = udma, \
350 }
351
352static const struct ide_port_info piix_pci_info[] __devinitdata = {
353 /* 0: MPIIX */
354 { /*
355 * MPIIX actually has only a single IDE channel mapped to
356 * the primary or secondary ports depending on the value
357 * of the bit 14 of the IDETIM register at offset 0x6c
358 */
359 .name = DRV_NAME,
360 .enablebits = {{0x6d,0xc0,0x80}, {0x6d,0xc0,0xc0}},
361 .host_flags = IDE_HFLAG_ISA_PORTS | IDE_HFLAG_NO_DMA |
362 IDE_HFLAGS_PIIX,
363 .pio_mask = ATA_PIO4,
364 /* This is a painful system best to let it self tune for now */
365 },
366 /* 1: PIIXa/PIIXb/PIIX3 */
367 DECLARE_PIIX_DEV(0x00), /* no udma */
368 /* 2: PIIX4 */
369 DECLARE_PIIX_DEV(ATA_UDMA2),
370 /* 3: ICH0 */
371 DECLARE_ICH_DEV(ATA_UDMA2),
372 /* 4: ICH */
373 DECLARE_ICH_DEV(ATA_UDMA4),
374 /* 5: PIIX4 */
375 DECLARE_PIIX_DEV(ATA_UDMA4),
376 /* 6: ICH[2-7]/ICH[2-3]M/C-ICH/ICH5-SATA/ESB2/ICH8M */
377 DECLARE_ICH_DEV(ATA_UDMA5),
378};
379
380/**
381 * piix_init_one - called when a PIIX is found
382 * @dev: the piix device
383 * @id: the matching pci id
384 *
385 * Called when the PCI registration layer (or the IDE initialization)
386 * finds a device matching our IDE device tables.
387 */
388
389static int __devinit piix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
390{
391 return ide_pci_init_one(dev, &piix_pci_info[id->driver_data], NULL);
392}
393
394/**
395 * piix_check_450nx - Check for problem 450NX setup
396 *
397 * Check for the present of 450NX errata #19 and errata #25. If
398 * they are found, disable use of DMA IDE
399 */
400
401static void __devinit piix_check_450nx(void)
402{
403 struct pci_dev *pdev = NULL;
404 u16 cfg;
405 while((pdev=pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev))!=NULL)
406 {
407 /* Look for 450NX PXB. Check for problem configurations
408 A PCI quirk checks bit 6 already */
409 pci_read_config_word(pdev, 0x41, &cfg);
410 /* Only on the original revision: IDE DMA can hang */
411 if (pdev->revision == 0x00)
412 no_piix_dma = 1;
413 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
414 else if (cfg & (1<<14) && pdev->revision < 5)
415 no_piix_dma = 2;
416 }
417 if(no_piix_dma)
418 printk(KERN_WARNING DRV_NAME ": 450NX errata present, disabling IDE DMA.\n");
419 if(no_piix_dma == 2)
420 printk(KERN_WARNING DRV_NAME ": A BIOS update may resolve this.\n");
421}
422
423static const struct pci_device_id piix_pci_tbl[] = {
424 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_0), 1 },
425 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371FB_1), 1 },
426 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX), 0 },
427 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371SB_1), 1 },
428 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371AB), 2 },
429 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AB_1), 3 },
430 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82443MX_1), 2 },
431 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801AA_1), 4 },
432 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82372FB_1), 5 },
433 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82451NX), 2 },
434 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_9), 6 },
435 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801BA_8), 6 },
436 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_10), 6 },
437 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801CA_11), 6 },
438 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_11), 6 },
439 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_11), 6 },
440 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801E_11), 6 },
441 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_10), 6 },
442#ifdef CONFIG_BLK_DEV_IDE_SATA
443 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801EB_1), 6 },
444#endif
445 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB_2), 6 },
446 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH6_19), 6 },
447 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH7_21), 6 },
448 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82801DB_1), 6 },
449 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ESB2_18), 6 },
450 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICH8_6), 6 },
451 { 0, },
452};
453MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
454
455static struct pci_driver piix_pci_driver = {
456 .name = "PIIX_IDE",
457 .id_table = piix_pci_tbl,
458 .probe = piix_init_one,
459 .remove = ide_pci_remove,
460 .suspend = ide_pci_suspend,
461 .resume = ide_pci_resume,
462};
463
464static int __init piix_ide_init(void)
465{
466 piix_check_450nx();
467 return ide_pci_register_driver(&piix_pci_driver);
468}
469
470static void __exit piix_ide_exit(void)
471{
472 pci_unregister_driver(&piix_pci_driver);
473}
474
475module_init(piix_ide_init);
476module_exit(piix_ide_exit);
477
478MODULE_AUTHOR("Andre Hedrick, Andrzej Krzysztofowicz");
479MODULE_DESCRIPTION("PCI driver module for Intel PIIX IDE");
480MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/rz1000.c b/drivers/ide/pci/rz1000.c
deleted file mode 100644
index 7daf0135cbac..000000000000
--- a/drivers/ide/pci/rz1000.c
+++ /dev/null
@@ -1,85 +0,0 @@
1/*
2 * Copyright (C) 1995-1998 Linus Torvalds & author (see below)
3 */
4
5/*
6 * Principal Author: mlord@pobox.com (Mark Lord)
7 *
8 * See linux/MAINTAINERS for address of current maintainer.
9 *
10 * This file provides support for disabling the buggy read-ahead
11 * mode of the RZ1000 IDE chipset, commonly used on Intel motherboards.
12 *
13 * Dunno if this fixes both ports, or only the primary port (?).
14 */
15
16#include <linux/types.h>
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/pci.h>
20#include <linux/ide.h>
21#include <linux/init.h>
22
23#define DRV_NAME "rz1000"
24
25static void __devinit init_hwif_rz1000 (ide_hwif_t *hwif)
26{
27 struct pci_dev *dev = to_pci_dev(hwif->dev);
28 u16 reg;
29
30 if (!pci_read_config_word (dev, 0x40, &reg) &&
31 !pci_write_config_word(dev, 0x40, reg & 0xdfff)) {
32 printk(KERN_INFO "%s: disabled chipset read-ahead "
33 "(buggy RZ1000/RZ1001)\n", hwif->name);
34 } else {
35 if (hwif->mate)
36 hwif->mate->serialized = hwif->serialized = 1;
37 hwif->host_flags |= IDE_HFLAG_NO_UNMASK_IRQS;
38 printk(KERN_INFO "%s: serialized, disabled unmasking "
39 "(buggy RZ1000/RZ1001)\n", hwif->name);
40 }
41}
42
43static const struct ide_port_info rz1000_chipset __devinitdata = {
44 .name = DRV_NAME,
45 .init_hwif = init_hwif_rz1000,
46 .chipset = ide_rz1000,
47 .host_flags = IDE_HFLAG_NO_DMA,
48};
49
50static int __devinit rz1000_init_one(struct pci_dev *dev, const struct pci_device_id *id)
51{
52 return ide_pci_init_one(dev, &rz1000_chipset, NULL);
53}
54
55static const struct pci_device_id rz1000_pci_tbl[] = {
56 { PCI_VDEVICE(PCTECH, PCI_DEVICE_ID_PCTECH_RZ1000), 0 },
57 { PCI_VDEVICE(PCTECH, PCI_DEVICE_ID_PCTECH_RZ1001), 0 },
58 { 0, },
59};
60MODULE_DEVICE_TABLE(pci, rz1000_pci_tbl);
61
62static struct pci_driver rz1000_pci_driver = {
63 .name = "RZ1000_IDE",
64 .id_table = rz1000_pci_tbl,
65 .probe = rz1000_init_one,
66 .remove = ide_pci_remove,
67};
68
69static int __init rz1000_ide_init(void)
70{
71 return ide_pci_register_driver(&rz1000_pci_driver);
72}
73
74static void __exit rz1000_ide_exit(void)
75{
76 pci_unregister_driver(&rz1000_pci_driver);
77}
78
79module_init(rz1000_ide_init);
80module_exit(rz1000_ide_exit);
81
82MODULE_AUTHOR("Andre Hedrick");
83MODULE_DESCRIPTION("PCI driver module for RZ1000 IDE");
84MODULE_LICENSE("GPL");
85
diff --git a/drivers/ide/pci/sc1200.c b/drivers/ide/pci/sc1200.c
deleted file mode 100644
index f1a8758e3a99..000000000000
--- a/drivers/ide/pci/sc1200.c
+++ /dev/null
@@ -1,357 +0,0 @@
1/*
2 * Copyright (C) 2000-2002 Mark Lord <mlord@pobox.com>
3 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
4 *
5 * May be copied or modified under the terms of the GNU General Public License
6 *
7 * Development of this chipset driver was funded
8 * by the nice folks at National Semiconductor.
9 *
10 * Documentation:
11 * Available from National Semiconductor
12 */
13
14#include <linux/module.h>
15#include <linux/types.h>
16#include <linux/kernel.h>
17#include <linux/pci.h>
18#include <linux/init.h>
19#include <linux/ide.h>
20#include <linux/pm.h>
21
22#include <asm/io.h>
23
24#define DRV_NAME "sc1200"
25
26#define SC1200_REV_A 0x00
27#define SC1200_REV_B1 0x01
28#define SC1200_REV_B3 0x02
29#define SC1200_REV_C1 0x03
30#define SC1200_REV_D1 0x04
31
32#define PCI_CLK_33 0x00
33#define PCI_CLK_48 0x01
34#define PCI_CLK_66 0x02
35#define PCI_CLK_33A 0x03
36
37static unsigned short sc1200_get_pci_clock (void)
38{
39 unsigned char chip_id, silicon_revision;
40 unsigned int pci_clock;
41 /*
42 * Check the silicon revision, as not all versions of the chip
43 * have the register with the fast PCI bus timings.
44 */
45 chip_id = inb (0x903c);
46 silicon_revision = inb (0x903d);
47
48 // Read the fast pci clock frequency
49 if (chip_id == 0x04 && silicon_revision < SC1200_REV_B1) {
50 pci_clock = PCI_CLK_33;
51 } else {
52 // check clock generator configuration (cfcc)
53 // the clock is in bits 8 and 9 of this word
54
55 pci_clock = inw (0x901e);
56 pci_clock >>= 8;
57 pci_clock &= 0x03;
58 if (pci_clock == PCI_CLK_33A)
59 pci_clock = PCI_CLK_33;
60 }
61 return pci_clock;
62}
63
64/*
65 * Here are the standard PIO mode 0-4 timings for each "format".
66 * Format-0 uses fast data reg timings, with slower command reg timings.
67 * Format-1 uses fast timings for all registers, but won't work with all drives.
68 */
69static const unsigned int sc1200_pio_timings[4][5] =
70 {{0x00009172, 0x00012171, 0x00020080, 0x00032010, 0x00040010}, // format0 33Mhz
71 {0xd1329172, 0x71212171, 0x30200080, 0x20102010, 0x00100010}, // format1, 33Mhz
72 {0xfaa3f4f3, 0xc23232b2, 0x513101c1, 0x31213121, 0x10211021}, // format1, 48Mhz
73 {0xfff4fff4, 0xf35353d3, 0x814102f1, 0x42314231, 0x11311131}}; // format1, 66Mhz
74
75/*
76 * After chip reset, the PIO timings are set to 0x00009172, which is not valid.
77 */
78//#define SC1200_BAD_PIO(timings) (((timings)&~0x80000000)==0x00009172)
79
80static void sc1200_tunepio(ide_drive_t *drive, u8 pio)
81{
82 ide_hwif_t *hwif = drive->hwif;
83 struct pci_dev *pdev = to_pci_dev(hwif->dev);
84 unsigned int basereg = hwif->channel ? 0x50 : 0x40, format = 0;
85
86 pci_read_config_dword(pdev, basereg + 4, &format);
87 format = (format >> 31) & 1;
88 if (format)
89 format += sc1200_get_pci_clock();
90 pci_write_config_dword(pdev, basereg + ((drive->dn & 1) << 3),
91 sc1200_pio_timings[format][pio]);
92}
93
94/*
95 * The SC1200 specifies that two drives sharing a cable cannot mix
96 * UDMA/MDMA. It has to be one or the other, for the pair, though
97 * different timings can still be chosen for each drive. We could
98 * set the appropriate timing bits on the fly, but that might be
99 * a bit confusing. So, for now we statically handle this requirement
100 * by looking at our mate drive to see what it is capable of, before
101 * choosing a mode for our own drive.
102 */
103static u8 sc1200_udma_filter(ide_drive_t *drive)
104{
105 ide_hwif_t *hwif = drive->hwif;
106 ide_drive_t *mate = ide_get_pair_dev(drive);
107 u16 *mateid = mate->id;
108 u8 mask = hwif->ultra_mask;
109
110 if (mate == NULL)
111 goto out;
112
113 if (ata_id_has_dma(mateid) && __ide_dma_bad_drive(mate) == 0) {
114 if ((mateid[ATA_ID_FIELD_VALID] & 4) &&
115 (mateid[ATA_ID_UDMA_MODES] & 7))
116 goto out;
117 if ((mateid[ATA_ID_FIELD_VALID] & 2) &&
118 (mateid[ATA_ID_MWDMA_MODES] & 7))
119 mask = 0;
120 }
121out:
122 return mask;
123}
124
125static void sc1200_set_dma_mode(ide_drive_t *drive, const u8 mode)
126{
127 ide_hwif_t *hwif = HWIF(drive);
128 struct pci_dev *dev = to_pci_dev(hwif->dev);
129 unsigned int reg, timings;
130 unsigned short pci_clock;
131 unsigned int basereg = hwif->channel ? 0x50 : 0x40;
132
133 static const u32 udma_timing[3][3] = {
134 { 0x00921250, 0x00911140, 0x00911030 },
135 { 0x00932470, 0x00922260, 0x00922140 },
136 { 0x009436a1, 0x00933481, 0x00923261 },
137 };
138
139 static const u32 mwdma_timing[3][3] = {
140 { 0x00077771, 0x00012121, 0x00002020 },
141 { 0x000bbbb2, 0x00024241, 0x00013131 },
142 { 0x000ffff3, 0x00035352, 0x00015151 },
143 };
144
145 pci_clock = sc1200_get_pci_clock();
146
147 /*
148 * Note that each DMA mode has several timings associated with it.
149 * The correct timing depends on the fast PCI clock freq.
150 */
151
152 if (mode >= XFER_UDMA_0)
153 timings = udma_timing[pci_clock][mode - XFER_UDMA_0];
154 else
155 timings = mwdma_timing[pci_clock][mode - XFER_MW_DMA_0];
156
157 if ((drive->dn & 1) == 0) {
158 pci_read_config_dword(dev, basereg + 4, &reg);
159 timings |= reg & 0x80000000; /* preserve PIO format bit */
160 pci_write_config_dword(dev, basereg + 4, timings);
161 } else
162 pci_write_config_dword(dev, basereg + 12, timings);
163}
164
165/* Replacement for the standard ide_dma_end action in
166 * dma_proc.
167 *
168 * returns 1 on error, 0 otherwise
169 */
170static int sc1200_dma_end(ide_drive_t *drive)
171{
172 ide_hwif_t *hwif = HWIF(drive);
173 unsigned long dma_base = hwif->dma_base;
174 byte dma_stat;
175
176 dma_stat = inb(dma_base+2); /* get DMA status */
177
178 if (!(dma_stat & 4))
179 printk(" ide_dma_end dma_stat=%0x err=%x newerr=%x\n",
180 dma_stat, ((dma_stat&7)!=4), ((dma_stat&2)==2));
181
182 outb(dma_stat|0x1b, dma_base+2); /* clear the INTR & ERROR bits */
183 outb(inb(dma_base)&~1, dma_base); /* !! DO THIS HERE !! stop DMA */
184
185 drive->waiting_for_dma = 0;
186 ide_destroy_dmatable(drive); /* purge DMA mappings */
187
188 return (dma_stat & 7) != 4; /* verify good DMA status */
189}
190
191/*
192 * sc1200_set_pio_mode() handles setting of PIO modes
193 * for both the chipset and drive.
194 *
195 * All existing BIOSs for this chipset guarantee that all drives
196 * will have valid default PIO timings set up before we get here.
197 */
198
199static void sc1200_set_pio_mode(ide_drive_t *drive, const u8 pio)
200{
201 ide_hwif_t *hwif = HWIF(drive);
202 int mode = -1;
203
204 /*
205 * bad abuse of ->set_pio_mode interface
206 */
207 switch (pio) {
208 case 200: mode = XFER_UDMA_0; break;
209 case 201: mode = XFER_UDMA_1; break;
210 case 202: mode = XFER_UDMA_2; break;
211 case 100: mode = XFER_MW_DMA_0; break;
212 case 101: mode = XFER_MW_DMA_1; break;
213 case 102: mode = XFER_MW_DMA_2; break;
214 }
215 if (mode != -1) {
216 printk("SC1200: %s: changing (U)DMA mode\n", drive->name);
217 ide_dma_off_quietly(drive);
218 if (ide_set_dma_mode(drive, mode) == 0 &&
219 (drive->dev_flags & IDE_DFLAG_USING_DMA))
220 hwif->dma_ops->dma_host_set(drive, 1);
221 return;
222 }
223
224 sc1200_tunepio(drive, pio);
225}
226
227#ifdef CONFIG_PM
228struct sc1200_saved_state {
229 u32 regs[8];
230};
231
232static int sc1200_suspend (struct pci_dev *dev, pm_message_t state)
233{
234 printk("SC1200: suspend(%u)\n", state.event);
235
236 /*
237 * we only save state when going from full power to less
238 */
239 if (state.event == PM_EVENT_ON) {
240 struct ide_host *host = pci_get_drvdata(dev);
241 struct sc1200_saved_state *ss = host->host_priv;
242 unsigned int r;
243
244 /*
245 * save timing registers
246 * (this may be unnecessary if BIOS also does it)
247 */
248 for (r = 0; r < 8; r++)
249 pci_read_config_dword(dev, 0x40 + r * 4, &ss->regs[r]);
250 }
251
252 pci_disable_device(dev);
253 pci_set_power_state(dev, pci_choose_state(dev, state));
254 return 0;
255}
256
257static int sc1200_resume (struct pci_dev *dev)
258{
259 struct ide_host *host = pci_get_drvdata(dev);
260 struct sc1200_saved_state *ss = host->host_priv;
261 unsigned int r;
262 int i;
263
264 i = pci_enable_device(dev);
265 if (i)
266 return i;
267
268 /*
269 * restore timing registers
270 * (this may be unnecessary if BIOS also does it)
271 */
272 for (r = 0; r < 8; r++)
273 pci_write_config_dword(dev, 0x40 + r * 4, ss->regs[r]);
274
275 return 0;
276}
277#endif
278
279static const struct ide_port_ops sc1200_port_ops = {
280 .set_pio_mode = sc1200_set_pio_mode,
281 .set_dma_mode = sc1200_set_dma_mode,
282 .udma_filter = sc1200_udma_filter,
283};
284
285static const struct ide_dma_ops sc1200_dma_ops = {
286 .dma_host_set = ide_dma_host_set,
287 .dma_setup = ide_dma_setup,
288 .dma_exec_cmd = ide_dma_exec_cmd,
289 .dma_start = ide_dma_start,
290 .dma_end = sc1200_dma_end,
291 .dma_test_irq = ide_dma_test_irq,
292 .dma_lost_irq = ide_dma_lost_irq,
293 .dma_timeout = ide_dma_timeout,
294};
295
296static const struct ide_port_info sc1200_chipset __devinitdata = {
297 .name = DRV_NAME,
298 .port_ops = &sc1200_port_ops,
299 .dma_ops = &sc1200_dma_ops,
300 .host_flags = IDE_HFLAG_SERIALIZE |
301 IDE_HFLAG_POST_SET_MODE |
302 IDE_HFLAG_ABUSE_DMA_MODES,
303 .pio_mask = ATA_PIO4,
304 .mwdma_mask = ATA_MWDMA2,
305 .udma_mask = ATA_UDMA2,
306};
307
308static int __devinit sc1200_init_one(struct pci_dev *dev, const struct pci_device_id *id)
309{
310 struct sc1200_saved_state *ss = NULL;
311 int rc;
312
313#ifdef CONFIG_PM
314 ss = kmalloc(sizeof(*ss), GFP_KERNEL);
315 if (ss == NULL)
316 return -ENOMEM;
317#endif
318 rc = ide_pci_init_one(dev, &sc1200_chipset, ss);
319 if (rc)
320 kfree(ss);
321
322 return rc;
323}
324
325static const struct pci_device_id sc1200_pci_tbl[] = {
326 { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_SCx200_IDE), 0},
327 { 0, },
328};
329MODULE_DEVICE_TABLE(pci, sc1200_pci_tbl);
330
331static struct pci_driver sc1200_pci_driver = {
332 .name = "SC1200_IDE",
333 .id_table = sc1200_pci_tbl,
334 .probe = sc1200_init_one,
335 .remove = ide_pci_remove,
336#ifdef CONFIG_PM
337 .suspend = sc1200_suspend,
338 .resume = sc1200_resume,
339#endif
340};
341
342static int __init sc1200_ide_init(void)
343{
344 return ide_pci_register_driver(&sc1200_pci_driver);
345}
346
347static void __exit sc1200_ide_exit(void)
348{
349 pci_unregister_driver(&sc1200_pci_driver);
350}
351
352module_init(sc1200_ide_init);
353module_exit(sc1200_ide_exit);
354
355MODULE_AUTHOR("Mark Lord");
356MODULE_DESCRIPTION("PCI driver module for NS SC1200 IDE");
357MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/scc_pata.c b/drivers/ide/pci/scc_pata.c
deleted file mode 100644
index 49f163aa51e3..000000000000
--- a/drivers/ide/pci/scc_pata.c
+++ /dev/null
@@ -1,966 +0,0 @@
1/*
2 * Support for IDE interfaces on Celleb platform
3 *
4 * (C) Copyright 2006 TOSHIBA CORPORATION
5 *
6 * This code is based on drivers/ide/pci/siimage.c:
7 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
8 * Copyright (C) 2003 Red Hat <alan@redhat.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
23 */
24
25#include <linux/types.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28#include <linux/delay.h>
29#include <linux/ide.h>
30#include <linux/init.h>
31
32#define PCI_DEVICE_ID_TOSHIBA_SCC_ATA 0x01b4
33
34#define SCC_PATA_NAME "scc IDE"
35
36#define TDVHSEL_MASTER 0x00000001
37#define TDVHSEL_SLAVE 0x00000004
38
39#define MODE_JCUSFEN 0x00000080
40
41#define CCKCTRL_ATARESET 0x00040000
42#define CCKCTRL_BUFCNT 0x00020000
43#define CCKCTRL_CRST 0x00010000
44#define CCKCTRL_OCLKEN 0x00000100
45#define CCKCTRL_ATACLKOEN 0x00000002
46#define CCKCTRL_LCLKEN 0x00000001
47
48#define QCHCD_IOS_SS 0x00000001
49
50#define QCHSD_STPDIAG 0x00020000
51
52#define INTMASK_MSK 0xD1000012
53#define INTSTS_SERROR 0x80000000
54#define INTSTS_PRERR 0x40000000
55#define INTSTS_RERR 0x10000000
56#define INTSTS_ICERR 0x01000000
57#define INTSTS_BMSINT 0x00000010
58#define INTSTS_BMHE 0x00000008
59#define INTSTS_IOIRQS 0x00000004
60#define INTSTS_INTRQ 0x00000002
61#define INTSTS_ACTEINT 0x00000001
62
63#define ECMODE_VALUE 0x01
64
65static struct scc_ports {
66 unsigned long ctl, dma;
67 struct ide_host *host; /* for removing port from system */
68} scc_ports[MAX_HWIFS];
69
70/* PIO transfer mode table */
71/* JCHST */
72static unsigned long JCHSTtbl[2][7] = {
73 {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00}, /* 100MHz */
74 {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00} /* 133MHz */
75};
76
77/* JCHHT */
78static unsigned long JCHHTtbl[2][7] = {
79 {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00}, /* 100MHz */
80 {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00} /* 133MHz */
81};
82
83/* JCHCT */
84static unsigned long JCHCTtbl[2][7] = {
85 {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00}, /* 100MHz */
86 {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00} /* 133MHz */
87};
88
89
90/* DMA transfer mode table */
91/* JCHDCTM/JCHDCTS */
92static unsigned long JCHDCTxtbl[2][7] = {
93 {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00}, /* 100MHz */
94 {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00} /* 133MHz */
95};
96
97/* JCSTWTM/JCSTWTS */
98static unsigned long JCSTWTxtbl[2][7] = {
99 {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00}, /* 100MHz */
100 {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
101};
102
103/* JCTSS */
104static unsigned long JCTSStbl[2][7] = {
105 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00}, /* 100MHz */
106 {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05} /* 133MHz */
107};
108
109/* JCENVT */
110static unsigned long JCENVTtbl[2][7] = {
111 {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00}, /* 100MHz */
112 {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02} /* 133MHz */
113};
114
115/* JCACTSELS/JCACTSELM */
116static unsigned long JCACTSELtbl[2][7] = {
117 {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00}, /* 100MHz */
118 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01} /* 133MHz */
119};
120
121
122static u8 scc_ide_inb(unsigned long port)
123{
124 u32 data = in_be32((void*)port);
125 return (u8)data;
126}
127
128static void scc_exec_command(ide_hwif_t *hwif, u8 cmd)
129{
130 out_be32((void *)hwif->io_ports.command_addr, cmd);
131 eieio();
132 in_be32((void *)(hwif->dma_base + 0x01c));
133 eieio();
134}
135
136static u8 scc_read_status(ide_hwif_t *hwif)
137{
138 return (u8)in_be32((void *)hwif->io_ports.status_addr);
139}
140
141static u8 scc_read_altstatus(ide_hwif_t *hwif)
142{
143 return (u8)in_be32((void *)hwif->io_ports.ctl_addr);
144}
145
146static u8 scc_read_sff_dma_status(ide_hwif_t *hwif)
147{
148 return (u8)in_be32((void *)(hwif->dma_base + 4));
149}
150
151static void scc_set_irq(ide_hwif_t *hwif, int on)
152{
153 u8 ctl = ATA_DEVCTL_OBS;
154
155 if (on == 4) { /* hack for SRST */
156 ctl |= 4;
157 on &= ~4;
158 }
159
160 ctl |= on ? 0 : 2;
161
162 out_be32((void *)hwif->io_ports.ctl_addr, ctl);
163 eieio();
164 in_be32((void *)(hwif->dma_base + 0x01c));
165 eieio();
166}
167
168static void scc_ide_insw(unsigned long port, void *addr, u32 count)
169{
170 u16 *ptr = (u16 *)addr;
171 while (count--) {
172 *ptr++ = le16_to_cpu(in_be32((void*)port));
173 }
174}
175
176static void scc_ide_insl(unsigned long port, void *addr, u32 count)
177{
178 u16 *ptr = (u16 *)addr;
179 while (count--) {
180 *ptr++ = le16_to_cpu(in_be32((void*)port));
181 *ptr++ = le16_to_cpu(in_be32((void*)port));
182 }
183}
184
185static void scc_ide_outb(u8 addr, unsigned long port)
186{
187 out_be32((void*)port, addr);
188}
189
190static void
191scc_ide_outsw(unsigned long port, void *addr, u32 count)
192{
193 u16 *ptr = (u16 *)addr;
194 while (count--) {
195 out_be32((void*)port, cpu_to_le16(*ptr++));
196 }
197}
198
199static void
200scc_ide_outsl(unsigned long port, void *addr, u32 count)
201{
202 u16 *ptr = (u16 *)addr;
203 while (count--) {
204 out_be32((void*)port, cpu_to_le16(*ptr++));
205 out_be32((void*)port, cpu_to_le16(*ptr++));
206 }
207}
208
209/**
210 * scc_set_pio_mode - set host controller for PIO mode
211 * @drive: drive
212 * @pio: PIO mode number
213 *
214 * Load the timing settings for this device mode into the
215 * controller.
216 */
217
218static void scc_set_pio_mode(ide_drive_t *drive, const u8 pio)
219{
220 ide_hwif_t *hwif = HWIF(drive);
221 struct scc_ports *ports = ide_get_hwifdata(hwif);
222 unsigned long ctl_base = ports->ctl;
223 unsigned long cckctrl_port = ctl_base + 0xff0;
224 unsigned long piosht_port = ctl_base + 0x000;
225 unsigned long pioct_port = ctl_base + 0x004;
226 unsigned long reg;
227 int offset;
228
229 reg = in_be32((void __iomem *)cckctrl_port);
230 if (reg & CCKCTRL_ATACLKOEN) {
231 offset = 1; /* 133MHz */
232 } else {
233 offset = 0; /* 100MHz */
234 }
235 reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
236 out_be32((void __iomem *)piosht_port, reg);
237 reg = JCHCTtbl[offset][pio];
238 out_be32((void __iomem *)pioct_port, reg);
239}
240
241/**
242 * scc_set_dma_mode - set host controller for DMA mode
243 * @drive: drive
244 * @speed: DMA mode
245 *
246 * Load the timing settings for this device mode into the
247 * controller.
248 */
249
250static void scc_set_dma_mode(ide_drive_t *drive, const u8 speed)
251{
252 ide_hwif_t *hwif = HWIF(drive);
253 struct scc_ports *ports = ide_get_hwifdata(hwif);
254 unsigned long ctl_base = ports->ctl;
255 unsigned long cckctrl_port = ctl_base + 0xff0;
256 unsigned long mdmact_port = ctl_base + 0x008;
257 unsigned long mcrcst_port = ctl_base + 0x00c;
258 unsigned long sdmact_port = ctl_base + 0x010;
259 unsigned long scrcst_port = ctl_base + 0x014;
260 unsigned long udenvt_port = ctl_base + 0x018;
261 unsigned long tdvhsel_port = ctl_base + 0x020;
262 int is_slave = (&hwif->drives[1] == drive);
263 int offset, idx;
264 unsigned long reg;
265 unsigned long jcactsel;
266
267 reg = in_be32((void __iomem *)cckctrl_port);
268 if (reg & CCKCTRL_ATACLKOEN) {
269 offset = 1; /* 133MHz */
270 } else {
271 offset = 0; /* 100MHz */
272 }
273
274 idx = speed - XFER_UDMA_0;
275
276 jcactsel = JCACTSELtbl[offset][idx];
277 if (is_slave) {
278 out_be32((void __iomem *)sdmact_port, JCHDCTxtbl[offset][idx]);
279 out_be32((void __iomem *)scrcst_port, JCSTWTxtbl[offset][idx]);
280 jcactsel = jcactsel << 2;
281 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_SLAVE) | jcactsel);
282 } else {
283 out_be32((void __iomem *)mdmact_port, JCHDCTxtbl[offset][idx]);
284 out_be32((void __iomem *)mcrcst_port, JCSTWTxtbl[offset][idx]);
285 out_be32((void __iomem *)tdvhsel_port, (in_be32((void __iomem *)tdvhsel_port) & ~TDVHSEL_MASTER) | jcactsel);
286 }
287 reg = JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx];
288 out_be32((void __iomem *)udenvt_port, reg);
289}
290
291static void scc_dma_host_set(ide_drive_t *drive, int on)
292{
293 ide_hwif_t *hwif = drive->hwif;
294 u8 unit = drive->dn & 1;
295 u8 dma_stat = scc_ide_inb(hwif->dma_base + 4);
296
297 if (on)
298 dma_stat |= (1 << (5 + unit));
299 else
300 dma_stat &= ~(1 << (5 + unit));
301
302 scc_ide_outb(dma_stat, hwif->dma_base + 4);
303}
304
305/**
306 * scc_ide_dma_setup - begin a DMA phase
307 * @drive: target device
308 *
309 * Build an IDE DMA PRD (IDE speak for scatter gather table)
310 * and then set up the DMA transfer registers.
311 *
312 * Returns 0 on success. If a PIO fallback is required then 1
313 * is returned.
314 */
315
316static int scc_dma_setup(ide_drive_t *drive)
317{
318 ide_hwif_t *hwif = drive->hwif;
319 struct request *rq = HWGROUP(drive)->rq;
320 unsigned int reading;
321 u8 dma_stat;
322
323 if (rq_data_dir(rq))
324 reading = 0;
325 else
326 reading = 1 << 3;
327
328 /* fall back to pio! */
329 if (!ide_build_dmatable(drive, rq)) {
330 ide_map_sg(drive, rq);
331 return 1;
332 }
333
334 /* PRD table */
335 out_be32((void __iomem *)(hwif->dma_base + 8), hwif->dmatable_dma);
336
337 /* specify r/w */
338 out_be32((void __iomem *)hwif->dma_base, reading);
339
340 /* read DMA status for INTR & ERROR flags */
341 dma_stat = in_be32((void __iomem *)(hwif->dma_base + 4));
342
343 /* clear INTR & ERROR flags */
344 out_be32((void __iomem *)(hwif->dma_base + 4), dma_stat | 6);
345 drive->waiting_for_dma = 1;
346 return 0;
347}
348
349static void scc_dma_start(ide_drive_t *drive)
350{
351 ide_hwif_t *hwif = drive->hwif;
352 u8 dma_cmd = scc_ide_inb(hwif->dma_base);
353
354 /* start DMA */
355 scc_ide_outb(dma_cmd | 1, hwif->dma_base);
356 wmb();
357}
358
359static int __scc_dma_end(ide_drive_t *drive)
360{
361 ide_hwif_t *hwif = drive->hwif;
362 u8 dma_stat, dma_cmd;
363
364 drive->waiting_for_dma = 0;
365 /* get DMA command mode */
366 dma_cmd = scc_ide_inb(hwif->dma_base);
367 /* stop DMA */
368 scc_ide_outb(dma_cmd & ~1, hwif->dma_base);
369 /* get DMA status */
370 dma_stat = scc_ide_inb(hwif->dma_base + 4);
371 /* clear the INTR & ERROR bits */
372 scc_ide_outb(dma_stat | 6, hwif->dma_base + 4);
373 /* purge DMA mappings */
374 ide_destroy_dmatable(drive);
375 /* verify good DMA status */
376 wmb();
377 return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0;
378}
379
380/**
381 * scc_dma_end - Stop DMA
382 * @drive: IDE drive
383 *
384 * Check and clear INT Status register.
385 * Then call __scc_dma_end().
386 */
387
388static int scc_dma_end(ide_drive_t *drive)
389{
390 ide_hwif_t *hwif = HWIF(drive);
391 void __iomem *dma_base = (void __iomem *)hwif->dma_base;
392 unsigned long intsts_port = hwif->dma_base + 0x014;
393 u32 reg;
394 int dma_stat, data_loss = 0;
395 static int retry = 0;
396
397 /* errata A308 workaround: Step5 (check data loss) */
398 /* We don't check non ide_disk because it is limited to UDMA4 */
399 if (!(in_be32((void __iomem *)hwif->io_ports.ctl_addr)
400 & ATA_ERR) &&
401 drive->media == ide_disk && drive->current_speed > XFER_UDMA_4) {
402 reg = in_be32((void __iomem *)intsts_port);
403 if (!(reg & INTSTS_ACTEINT)) {
404 printk(KERN_WARNING "%s: operation failed (transfer data loss)\n",
405 drive->name);
406 data_loss = 1;
407 if (retry++) {
408 struct request *rq = HWGROUP(drive)->rq;
409 int unit;
410 /* ERROR_RESET and drive->crc_count are needed
411 * to reduce DMA transfer mode in retry process.
412 */
413 if (rq)
414 rq->errors |= ERROR_RESET;
415 for (unit = 0; unit < MAX_DRIVES; unit++) {
416 ide_drive_t *drive = &hwif->drives[unit];
417 drive->crc_count++;
418 }
419 }
420 }
421 }
422
423 while (1) {
424 reg = in_be32((void __iomem *)intsts_port);
425
426 if (reg & INTSTS_SERROR) {
427 printk(KERN_WARNING "%s: SERROR\n", SCC_PATA_NAME);
428 out_be32((void __iomem *)intsts_port, INTSTS_SERROR|INTSTS_BMSINT);
429
430 out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS);
431 continue;
432 }
433
434 if (reg & INTSTS_PRERR) {
435 u32 maea0, maec0;
436 unsigned long ctl_base = hwif->config_data;
437
438 maea0 = in_be32((void __iomem *)(ctl_base + 0xF50));
439 maec0 = in_be32((void __iomem *)(ctl_base + 0xF54));
440
441 printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", SCC_PATA_NAME, maea0, maec0);
442
443 out_be32((void __iomem *)intsts_port, INTSTS_PRERR|INTSTS_BMSINT);
444
445 out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS);
446 continue;
447 }
448
449 if (reg & INTSTS_RERR) {
450 printk(KERN_WARNING "%s: Response Error\n", SCC_PATA_NAME);
451 out_be32((void __iomem *)intsts_port, INTSTS_RERR|INTSTS_BMSINT);
452
453 out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS);
454 continue;
455 }
456
457 if (reg & INTSTS_ICERR) {
458 out_be32(dma_base, in_be32(dma_base) & ~QCHCD_IOS_SS);
459
460 printk(KERN_WARNING "%s: Illegal Configuration\n", SCC_PATA_NAME);
461 out_be32((void __iomem *)intsts_port, INTSTS_ICERR|INTSTS_BMSINT);
462 continue;
463 }
464
465 if (reg & INTSTS_BMSINT) {
466 printk(KERN_WARNING "%s: Internal Bus Error\n", SCC_PATA_NAME);
467 out_be32((void __iomem *)intsts_port, INTSTS_BMSINT);
468
469 ide_do_reset(drive);
470 continue;
471 }
472
473 if (reg & INTSTS_BMHE) {
474 out_be32((void __iomem *)intsts_port, INTSTS_BMHE);
475 continue;
476 }
477
478 if (reg & INTSTS_ACTEINT) {
479 out_be32((void __iomem *)intsts_port, INTSTS_ACTEINT);
480 continue;
481 }
482
483 if (reg & INTSTS_IOIRQS) {
484 out_be32((void __iomem *)intsts_port, INTSTS_IOIRQS);
485 continue;
486 }
487 break;
488 }
489
490 dma_stat = __scc_dma_end(drive);
491 if (data_loss)
492 dma_stat |= 2; /* emulate DMA error (to retry command) */
493 return dma_stat;
494}
495
496/* returns 1 if dma irq issued, 0 otherwise */
497static int scc_dma_test_irq(ide_drive_t *drive)
498{
499 ide_hwif_t *hwif = HWIF(drive);
500 u32 int_stat = in_be32((void __iomem *)hwif->dma_base + 0x014);
501
502 /* SCC errata A252,A308 workaround: Step4 */
503 if ((in_be32((void __iomem *)hwif->io_ports.ctl_addr)
504 & ATA_ERR) &&
505 (int_stat & INTSTS_INTRQ))
506 return 1;
507
508 /* SCC errata A308 workaround: Step5 (polling IOIRQS) */
509 if (int_stat & INTSTS_IOIRQS)
510 return 1;
511
512 return 0;
513}
514
515static u8 scc_udma_filter(ide_drive_t *drive)
516{
517 ide_hwif_t *hwif = drive->hwif;
518 u8 mask = hwif->ultra_mask;
519
520 /* errata A308 workaround: limit non ide_disk drive to UDMA4 */
521 if ((drive->media != ide_disk) && (mask & 0xE0)) {
522 printk(KERN_INFO "%s: limit %s to UDMA4\n",
523 SCC_PATA_NAME, drive->name);
524 mask = ATA_UDMA4;
525 }
526
527 return mask;
528}
529
530/**
531 * setup_mmio_scc - map CTRL/BMID region
532 * @dev: PCI device we are configuring
533 * @name: device name
534 *
535 */
536
537static int setup_mmio_scc (struct pci_dev *dev, const char *name)
538{
539 unsigned long ctl_base = pci_resource_start(dev, 0);
540 unsigned long dma_base = pci_resource_start(dev, 1);
541 unsigned long ctl_size = pci_resource_len(dev, 0);
542 unsigned long dma_size = pci_resource_len(dev, 1);
543 void __iomem *ctl_addr;
544 void __iomem *dma_addr;
545 int i, ret;
546
547 for (i = 0; i < MAX_HWIFS; i++) {
548 if (scc_ports[i].ctl == 0)
549 break;
550 }
551 if (i >= MAX_HWIFS)
552 return -ENOMEM;
553
554 ret = pci_request_selected_regions(dev, (1 << 2) - 1, name);
555 if (ret < 0) {
556 printk(KERN_ERR "%s: can't reserve resources\n", name);
557 return ret;
558 }
559
560 if ((ctl_addr = ioremap(ctl_base, ctl_size)) == NULL)
561 goto fail_0;
562
563 if ((dma_addr = ioremap(dma_base, dma_size)) == NULL)
564 goto fail_1;
565
566 pci_set_master(dev);
567 scc_ports[i].ctl = (unsigned long)ctl_addr;
568 scc_ports[i].dma = (unsigned long)dma_addr;
569 pci_set_drvdata(dev, (void *) &scc_ports[i]);
570
571 return 1;
572
573 fail_1:
574 iounmap(ctl_addr);
575 fail_0:
576 return -ENOMEM;
577}
578
579static int scc_ide_setup_pci_device(struct pci_dev *dev,
580 const struct ide_port_info *d)
581{
582 struct scc_ports *ports = pci_get_drvdata(dev);
583 struct ide_host *host;
584 hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
585 int i, rc;
586
587 memset(&hw, 0, sizeof(hw));
588 for (i = 0; i <= 8; i++)
589 hw.io_ports_array[i] = ports->dma + 0x20 + i * 4;
590 hw.irq = dev->irq;
591 hw.dev = &dev->dev;
592 hw.chipset = ide_pci;
593
594 rc = ide_host_add(d, hws, &host);
595 if (rc)
596 return rc;
597
598 ports->host = host;
599
600 return 0;
601}
602
603/**
604 * init_setup_scc - set up an SCC PATA Controller
605 * @dev: PCI device
606 * @d: IDE port info
607 *
608 * Perform the initial set up for this device.
609 */
610
611static int __devinit init_setup_scc(struct pci_dev *dev,
612 const struct ide_port_info *d)
613{
614 unsigned long ctl_base;
615 unsigned long dma_base;
616 unsigned long cckctrl_port;
617 unsigned long intmask_port;
618 unsigned long mode_port;
619 unsigned long ecmode_port;
620 u32 reg = 0;
621 struct scc_ports *ports;
622 int rc;
623
624 rc = pci_enable_device(dev);
625 if (rc)
626 goto end;
627
628 rc = setup_mmio_scc(dev, d->name);
629 if (rc < 0)
630 goto end;
631
632 ports = pci_get_drvdata(dev);
633 ctl_base = ports->ctl;
634 dma_base = ports->dma;
635 cckctrl_port = ctl_base + 0xff0;
636 intmask_port = dma_base + 0x010;
637 mode_port = ctl_base + 0x024;
638 ecmode_port = ctl_base + 0xf00;
639
640 /* controller initialization */
641 reg = 0;
642 out_be32((void*)cckctrl_port, reg);
643 reg |= CCKCTRL_ATACLKOEN;
644 out_be32((void*)cckctrl_port, reg);
645 reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
646 out_be32((void*)cckctrl_port, reg);
647 reg |= CCKCTRL_CRST;
648 out_be32((void*)cckctrl_port, reg);
649
650 for (;;) {
651 reg = in_be32((void*)cckctrl_port);
652 if (reg & CCKCTRL_CRST)
653 break;
654 udelay(5000);
655 }
656
657 reg |= CCKCTRL_ATARESET;
658 out_be32((void*)cckctrl_port, reg);
659
660 out_be32((void*)ecmode_port, ECMODE_VALUE);
661 out_be32((void*)mode_port, MODE_JCUSFEN);
662 out_be32((void*)intmask_port, INTMASK_MSK);
663
664 rc = scc_ide_setup_pci_device(dev, d);
665
666 end:
667 return rc;
668}
669
670static void scc_tf_load(ide_drive_t *drive, ide_task_t *task)
671{
672 struct ide_io_ports *io_ports = &drive->hwif->io_ports;
673 struct ide_taskfile *tf = &task->tf;
674 u8 HIHI = (task->tf_flags & IDE_TFLAG_LBA48) ? 0xE0 : 0xEF;
675
676 if (task->tf_flags & IDE_TFLAG_FLAGGED)
677 HIHI = 0xFF;
678
679 if (task->tf_flags & IDE_TFLAG_OUT_DATA)
680 out_be32((void *)io_ports->data_addr,
681 (tf->hob_data << 8) | tf->data);
682
683 if (task->tf_flags & IDE_TFLAG_OUT_HOB_FEATURE)
684 scc_ide_outb(tf->hob_feature, io_ports->feature_addr);
685 if (task->tf_flags & IDE_TFLAG_OUT_HOB_NSECT)
686 scc_ide_outb(tf->hob_nsect, io_ports->nsect_addr);
687 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAL)
688 scc_ide_outb(tf->hob_lbal, io_ports->lbal_addr);
689 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAM)
690 scc_ide_outb(tf->hob_lbam, io_ports->lbam_addr);
691 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAH)
692 scc_ide_outb(tf->hob_lbah, io_ports->lbah_addr);
693
694 if (task->tf_flags & IDE_TFLAG_OUT_FEATURE)
695 scc_ide_outb(tf->feature, io_ports->feature_addr);
696 if (task->tf_flags & IDE_TFLAG_OUT_NSECT)
697 scc_ide_outb(tf->nsect, io_ports->nsect_addr);
698 if (task->tf_flags & IDE_TFLAG_OUT_LBAL)
699 scc_ide_outb(tf->lbal, io_ports->lbal_addr);
700 if (task->tf_flags & IDE_TFLAG_OUT_LBAM)
701 scc_ide_outb(tf->lbam, io_ports->lbam_addr);
702 if (task->tf_flags & IDE_TFLAG_OUT_LBAH)
703 scc_ide_outb(tf->lbah, io_ports->lbah_addr);
704
705 if (task->tf_flags & IDE_TFLAG_OUT_DEVICE)
706 scc_ide_outb((tf->device & HIHI) | drive->select,
707 io_ports->device_addr);
708}
709
710static void scc_tf_read(ide_drive_t *drive, ide_task_t *task)
711{
712 struct ide_io_ports *io_ports = &drive->hwif->io_ports;
713 struct ide_taskfile *tf = &task->tf;
714
715 if (task->tf_flags & IDE_TFLAG_IN_DATA) {
716 u16 data = (u16)in_be32((void *)io_ports->data_addr);
717
718 tf->data = data & 0xff;
719 tf->hob_data = (data >> 8) & 0xff;
720 }
721
722 /* be sure we're looking at the low order bits */
723 scc_ide_outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr);
724
725 if (task->tf_flags & IDE_TFLAG_IN_FEATURE)
726 tf->feature = scc_ide_inb(io_ports->feature_addr);
727 if (task->tf_flags & IDE_TFLAG_IN_NSECT)
728 tf->nsect = scc_ide_inb(io_ports->nsect_addr);
729 if (task->tf_flags & IDE_TFLAG_IN_LBAL)
730 tf->lbal = scc_ide_inb(io_ports->lbal_addr);
731 if (task->tf_flags & IDE_TFLAG_IN_LBAM)
732 tf->lbam = scc_ide_inb(io_ports->lbam_addr);
733 if (task->tf_flags & IDE_TFLAG_IN_LBAH)
734 tf->lbah = scc_ide_inb(io_ports->lbah_addr);
735 if (task->tf_flags & IDE_TFLAG_IN_DEVICE)
736 tf->device = scc_ide_inb(io_ports->device_addr);
737
738 if (task->tf_flags & IDE_TFLAG_LBA48) {
739 scc_ide_outb(ATA_DEVCTL_OBS | 0x80, io_ports->ctl_addr);
740
741 if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
742 tf->hob_feature = scc_ide_inb(io_ports->feature_addr);
743 if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
744 tf->hob_nsect = scc_ide_inb(io_ports->nsect_addr);
745 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
746 tf->hob_lbal = scc_ide_inb(io_ports->lbal_addr);
747 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
748 tf->hob_lbam = scc_ide_inb(io_ports->lbam_addr);
749 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
750 tf->hob_lbah = scc_ide_inb(io_ports->lbah_addr);
751 }
752}
753
754static void scc_input_data(ide_drive_t *drive, struct request *rq,
755 void *buf, unsigned int len)
756{
757 unsigned long data_addr = drive->hwif->io_ports.data_addr;
758
759 len++;
760
761 if (drive->io_32bit) {
762 scc_ide_insl(data_addr, buf, len / 4);
763
764 if ((len & 3) >= 2)
765 scc_ide_insw(data_addr, (u8 *)buf + (len & ~3), 1);
766 } else
767 scc_ide_insw(data_addr, buf, len / 2);
768}
769
770static void scc_output_data(ide_drive_t *drive, struct request *rq,
771 void *buf, unsigned int len)
772{
773 unsigned long data_addr = drive->hwif->io_ports.data_addr;
774
775 len++;
776
777 if (drive->io_32bit) {
778 scc_ide_outsl(data_addr, buf, len / 4);
779
780 if ((len & 3) >= 2)
781 scc_ide_outsw(data_addr, (u8 *)buf + (len & ~3), 1);
782 } else
783 scc_ide_outsw(data_addr, buf, len / 2);
784}
785
786/**
787 * init_mmio_iops_scc - set up the iops for MMIO
788 * @hwif: interface to set up
789 *
790 */
791
792static void __devinit init_mmio_iops_scc(ide_hwif_t *hwif)
793{
794 struct pci_dev *dev = to_pci_dev(hwif->dev);
795 struct scc_ports *ports = pci_get_drvdata(dev);
796 unsigned long dma_base = ports->dma;
797
798 ide_set_hwifdata(hwif, ports);
799
800 hwif->dma_base = dma_base;
801 hwif->config_data = ports->ctl;
802}
803
804/**
805 * init_iops_scc - set up iops
806 * @hwif: interface to set up
807 *
808 * Do the basic setup for the SCC hardware interface
809 * and then do the MMIO setup.
810 */
811
812static void __devinit init_iops_scc(ide_hwif_t *hwif)
813{
814 struct pci_dev *dev = to_pci_dev(hwif->dev);
815
816 hwif->hwif_data = NULL;
817 if (pci_get_drvdata(dev) == NULL)
818 return;
819 init_mmio_iops_scc(hwif);
820}
821
822static int __devinit scc_init_dma(ide_hwif_t *hwif,
823 const struct ide_port_info *d)
824{
825 return ide_allocate_dma_engine(hwif);
826}
827
828static u8 scc_cable_detect(ide_hwif_t *hwif)
829{
830 return ATA_CBL_PATA80;
831}
832
833/**
834 * init_hwif_scc - set up hwif
835 * @hwif: interface to set up
836 *
837 * We do the basic set up of the interface structure. The SCC
838 * requires several custom handlers so we override the default
839 * ide DMA handlers appropriately.
840 */
841
842static void __devinit init_hwif_scc(ide_hwif_t *hwif)
843{
844 /* PTERADD */
845 out_be32((void __iomem *)(hwif->dma_base + 0x018), hwif->dmatable_dma);
846
847 if (in_be32((void __iomem *)(hwif->config_data + 0xff0)) & CCKCTRL_ATACLKOEN)
848 hwif->ultra_mask = ATA_UDMA6; /* 133MHz */
849 else
850 hwif->ultra_mask = ATA_UDMA5; /* 100MHz */
851}
852
853static const struct ide_tp_ops scc_tp_ops = {
854 .exec_command = scc_exec_command,
855 .read_status = scc_read_status,
856 .read_altstatus = scc_read_altstatus,
857 .read_sff_dma_status = scc_read_sff_dma_status,
858
859 .set_irq = scc_set_irq,
860
861 .tf_load = scc_tf_load,
862 .tf_read = scc_tf_read,
863
864 .input_data = scc_input_data,
865 .output_data = scc_output_data,
866};
867
868static const struct ide_port_ops scc_port_ops = {
869 .set_pio_mode = scc_set_pio_mode,
870 .set_dma_mode = scc_set_dma_mode,
871 .udma_filter = scc_udma_filter,
872 .cable_detect = scc_cable_detect,
873};
874
875static const struct ide_dma_ops scc_dma_ops = {
876 .dma_host_set = scc_dma_host_set,
877 .dma_setup = scc_dma_setup,
878 .dma_exec_cmd = ide_dma_exec_cmd,
879 .dma_start = scc_dma_start,
880 .dma_end = scc_dma_end,
881 .dma_test_irq = scc_dma_test_irq,
882 .dma_lost_irq = ide_dma_lost_irq,
883 .dma_timeout = ide_dma_timeout,
884};
885
886#define DECLARE_SCC_DEV(name_str) \
887 { \
888 .name = name_str, \
889 .init_iops = init_iops_scc, \
890 .init_dma = scc_init_dma, \
891 .init_hwif = init_hwif_scc, \
892 .tp_ops = &scc_tp_ops, \
893 .port_ops = &scc_port_ops, \
894 .dma_ops = &scc_dma_ops, \
895 .host_flags = IDE_HFLAG_SINGLE, \
896 .pio_mask = ATA_PIO4, \
897 }
898
899static const struct ide_port_info scc_chipsets[] __devinitdata = {
900 /* 0 */ DECLARE_SCC_DEV("sccIDE"),
901};
902
903/**
904 * scc_init_one - pci layer discovery entry
905 * @dev: PCI device
906 * @id: ident table entry
907 *
908 * Called by the PCI code when it finds an SCC PATA controller.
909 * We then use the IDE PCI generic helper to do most of the work.
910 */
911
912static int __devinit scc_init_one(struct pci_dev *dev, const struct pci_device_id *id)
913{
914 return init_setup_scc(dev, &scc_chipsets[id->driver_data]);
915}
916
917/**
918 * scc_remove - pci layer remove entry
919 * @dev: PCI device
920 *
921 * Called by the PCI code when it removes an SCC PATA controller.
922 */
923
924static void __devexit scc_remove(struct pci_dev *dev)
925{
926 struct scc_ports *ports = pci_get_drvdata(dev);
927 struct ide_host *host = ports->host;
928
929 ide_host_remove(host);
930
931 iounmap((void*)ports->dma);
932 iounmap((void*)ports->ctl);
933 pci_release_selected_regions(dev, (1 << 2) - 1);
934 memset(ports, 0, sizeof(*ports));
935}
936
937static const struct pci_device_id scc_pci_tbl[] = {
938 { PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA), 0 },
939 { 0, },
940};
941MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
942
943static struct pci_driver scc_pci_driver = {
944 .name = "SCC IDE",
945 .id_table = scc_pci_tbl,
946 .probe = scc_init_one,
947 .remove = __devexit_p(scc_remove),
948};
949
950static int scc_ide_init(void)
951{
952 return ide_pci_register_driver(&scc_pci_driver);
953}
954
955module_init(scc_ide_init);
956/* -- No exit code?
957static void scc_ide_exit(void)
958{
959 ide_pci_unregister_driver(&scc_pci_driver);
960}
961module_exit(scc_ide_exit);
962 */
963
964
965MODULE_DESCRIPTION("PCI driver module for Toshiba SCC IDE");
966MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/serverworks.c b/drivers/ide/pci/serverworks.c
deleted file mode 100644
index 437bc919dafd..000000000000
--- a/drivers/ide/pci/serverworks.c
+++ /dev/null
@@ -1,470 +0,0 @@
1/*
2 * Copyright (C) 1998-2000 Michel Aubry
3 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
4 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
6 * Portions copyright (c) 2001 Sun Microsystems
7 *
8 *
9 * RCC/ServerWorks IDE driver for Linux
10 *
11 * OSB4: `Open South Bridge' IDE Interface (fn 1)
12 * supports UDMA mode 2 (33 MB/s)
13 *
14 * CSB5: `Champion South Bridge' IDE Interface (fn 1)
15 * all revisions support UDMA mode 4 (66 MB/s)
16 * revision A2.0 and up support UDMA mode 5 (100 MB/s)
17 *
18 * *** The CSB5 does not provide ANY register ***
19 * *** to detect 80-conductor cable presence. ***
20 *
21 * CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
22 *
23 * HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
24 * controller same as the CSB6. Single channel ATA100 only.
25 *
26 * Documentation:
27 * Available under NDA only. Errata info very hard to get.
28 *
29 */
30
31#include <linux/types.h>
32#include <linux/module.h>
33#include <linux/kernel.h>
34#include <linux/pci.h>
35#include <linux/ide.h>
36#include <linux/init.h>
37
38#include <asm/io.h>
39
40#define DRV_NAME "serverworks"
41
42#define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
43#define SVWKS_CSB6_REVISION 0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
44
45/* Seagate Barracuda ATA IV Family drives in UDMA mode 5
46 * can overrun their FIFOs when used with the CSB5 */
47static const char *svwks_bad_ata100[] = {
48 "ST320011A",
49 "ST340016A",
50 "ST360021A",
51 "ST380021A",
52 NULL
53};
54
55static struct pci_dev *isa_dev;
56
57static int check_in_drive_lists (ide_drive_t *drive, const char **list)
58{
59 char *m = (char *)&drive->id[ATA_ID_PROD];
60
61 while (*list)
62 if (!strcmp(*list++, m))
63 return 1;
64 return 0;
65}
66
67static u8 svwks_udma_filter(ide_drive_t *drive)
68{
69 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
70 u8 mask = 0;
71
72 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
73 return 0x1f;
74 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
75 u32 reg = 0;
76 if (isa_dev)
77 pci_read_config_dword(isa_dev, 0x64, &reg);
78
79 /*
80 * Don't enable UDMA on disk devices for the moment
81 */
82 if(drive->media == ide_disk)
83 return 0;
84 /* Check the OSB4 DMA33 enable bit */
85 return ((reg & 0x00004000) == 0x00004000) ? 0x07 : 0;
86 } else if (dev->revision < SVWKS_CSB5_REVISION_NEW) {
87 return 0x07;
88 } else if (dev->revision >= SVWKS_CSB5_REVISION_NEW) {
89 u8 btr = 0, mode;
90 pci_read_config_byte(dev, 0x5A, &btr);
91 mode = btr & 0x3;
92
93 /* If someone decides to do UDMA133 on CSB5 the same
94 issue will bite so be inclusive */
95 if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
96 mode = 2;
97
98 switch(mode) {
99 case 3: mask = 0x3f; break;
100 case 2: mask = 0x1f; break;
101 case 1: mask = 0x07; break;
102 default: mask = 0x00; break;
103 }
104 }
105 if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
106 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
107 (!(PCI_FUNC(dev->devfn) & 1)))
108 mask = 0x1f;
109
110 return mask;
111}
112
113static u8 svwks_csb_check (struct pci_dev *dev)
114{
115 switch (dev->device) {
116 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
117 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
118 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
119 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
120 return 1;
121 default:
122 break;
123 }
124 return 0;
125}
126
127static void svwks_set_pio_mode(ide_drive_t *drive, const u8 pio)
128{
129 static const u8 pio_modes[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
130 static const u8 drive_pci[] = { 0x41, 0x40, 0x43, 0x42 };
131
132 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
133
134 pci_write_config_byte(dev, drive_pci[drive->dn], pio_modes[pio]);
135
136 if (svwks_csb_check(dev)) {
137 u16 csb_pio = 0;
138
139 pci_read_config_word(dev, 0x4a, &csb_pio);
140
141 csb_pio &= ~(0x0f << (4 * drive->dn));
142 csb_pio |= (pio << (4 * drive->dn));
143
144 pci_write_config_word(dev, 0x4a, csb_pio);
145 }
146}
147
148static void svwks_set_dma_mode(ide_drive_t *drive, const u8 speed)
149{
150 static const u8 udma_modes[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
151 static const u8 dma_modes[] = { 0x77, 0x21, 0x20 };
152 static const u8 drive_pci2[] = { 0x45, 0x44, 0x47, 0x46 };
153
154 ide_hwif_t *hwif = HWIF(drive);
155 struct pci_dev *dev = to_pci_dev(hwif->dev);
156 u8 unit = drive->dn & 1;
157
158 u8 ultra_enable = 0, ultra_timing = 0, dma_timing = 0;
159
160 pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
161 pci_read_config_byte(dev, 0x54, &ultra_enable);
162
163 ultra_timing &= ~(0x0F << (4*unit));
164 ultra_enable &= ~(0x01 << drive->dn);
165
166 if (speed >= XFER_UDMA_0) {
167 dma_timing |= dma_modes[2];
168 ultra_timing |= (udma_modes[speed - XFER_UDMA_0] << (4 * unit));
169 ultra_enable |= (0x01 << drive->dn);
170 } else if (speed >= XFER_MW_DMA_0)
171 dma_timing |= dma_modes[speed - XFER_MW_DMA_0];
172
173 pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
174 pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
175 pci_write_config_byte(dev, 0x54, ultra_enable);
176}
177
178static unsigned int init_chipset_svwks(struct pci_dev *dev)
179{
180 unsigned int reg;
181 u8 btr;
182
183 /* force Master Latency Timer value to 64 PCICLKs */
184 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
185
186 /* OSB4 : South Bridge and IDE */
187 if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
188 isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
189 PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
190 if (isa_dev) {
191 pci_read_config_dword(isa_dev, 0x64, &reg);
192 reg &= ~0x00002000; /* disable 600ns interrupt mask */
193 if(!(reg & 0x00004000))
194 printk(KERN_DEBUG DRV_NAME " %s: UDMA not BIOS "
195 "enabled.\n", pci_name(dev));
196 reg |= 0x00004000; /* enable UDMA/33 support */
197 pci_write_config_dword(isa_dev, 0x64, reg);
198 }
199 }
200
201 /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
202 else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
203 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
204 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
205
206 /* Third Channel Test */
207 if (!(PCI_FUNC(dev->devfn) & 1)) {
208 struct pci_dev * findev = NULL;
209 u32 reg4c = 0;
210 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
211 PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
212 if (findev) {
213 pci_read_config_dword(findev, 0x4C, &reg4c);
214 reg4c &= ~0x000007FF;
215 reg4c |= 0x00000040;
216 reg4c |= 0x00000020;
217 pci_write_config_dword(findev, 0x4C, reg4c);
218 pci_dev_put(findev);
219 }
220 outb_p(0x06, 0x0c00);
221 dev->irq = inb_p(0x0c01);
222 } else {
223 struct pci_dev * findev = NULL;
224 u8 reg41 = 0;
225
226 findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
227 PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
228 if (findev) {
229 pci_read_config_byte(findev, 0x41, &reg41);
230 reg41 &= ~0x40;
231 pci_write_config_byte(findev, 0x41, reg41);
232 pci_dev_put(findev);
233 }
234 /*
235 * This is a device pin issue on CSB6.
236 * Since there will be a future raid mode,
237 * early versions of the chipset require the
238 * interrupt pin to be set, and it is a compatibility
239 * mode issue.
240 */
241 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
242 dev->irq = 0;
243 }
244// pci_read_config_dword(dev, 0x40, &pioreg)
245// pci_write_config_dword(dev, 0x40, 0x99999999);
246// pci_read_config_dword(dev, 0x44, &dmareg);
247// pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
248 /* setup the UDMA Control register
249 *
250 * 1. clear bit 6 to enable DMA
251 * 2. enable DMA modes with bits 0-1
252 * 00 : legacy
253 * 01 : udma2
254 * 10 : udma2/udma4
255 * 11 : udma2/udma4/udma5
256 */
257 pci_read_config_byte(dev, 0x5A, &btr);
258 btr &= ~0x40;
259 if (!(PCI_FUNC(dev->devfn) & 1))
260 btr |= 0x2;
261 else
262 btr |= (dev->revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
263 pci_write_config_byte(dev, 0x5A, btr);
264 }
265 /* Setup HT1000 SouthBridge Controller - Single Channel Only */
266 else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
267 pci_read_config_byte(dev, 0x5A, &btr);
268 btr &= ~0x40;
269 btr |= 0x3;
270 pci_write_config_byte(dev, 0x5A, btr);
271 }
272
273 return dev->irq;
274}
275
276static u8 ata66_svwks_svwks(ide_hwif_t *hwif)
277{
278 return ATA_CBL_PATA80;
279}
280
281/* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
282 * of the subsystem device ID indicate presence of an 80-pin cable.
283 * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
284 * Bit 15 set = secondary IDE channel has 80-pin cable.
285 * Bit 14 clear = primary IDE channel does not have 80-pin cable.
286 * Bit 14 set = primary IDE channel has 80-pin cable.
287 */
288static u8 ata66_svwks_dell(ide_hwif_t *hwif)
289{
290 struct pci_dev *dev = to_pci_dev(hwif->dev);
291
292 if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
293 dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
294 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
295 dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
296 return ((1 << (hwif->channel + 14)) &
297 dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
298 return ATA_CBL_PATA40;
299}
300
301/* Sun Cobalt Alpine hardware avoids the 80-pin cable
302 * detect issue by attaching the drives directly to the board.
303 * This check follows the Dell precedent (how scary is that?!)
304 *
305 * WARNING: this only works on Alpine hardware!
306 */
307static u8 ata66_svwks_cobalt(ide_hwif_t *hwif)
308{
309 struct pci_dev *dev = to_pci_dev(hwif->dev);
310
311 if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
312 dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
313 dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
314 return ((1 << (hwif->channel + 14)) &
315 dev->subsystem_device) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
316 return ATA_CBL_PATA40;
317}
318
319static u8 svwks_cable_detect(ide_hwif_t *hwif)
320{
321 struct pci_dev *dev = to_pci_dev(hwif->dev);
322
323 /* Server Works */
324 if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
325 return ata66_svwks_svwks (hwif);
326
327 /* Dell PowerEdge */
328 if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
329 return ata66_svwks_dell (hwif);
330
331 /* Cobalt Alpine */
332 if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
333 return ata66_svwks_cobalt (hwif);
334
335 /* Per Specified Design by OEM, and ASIC Architect */
336 if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
337 (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
338 return ATA_CBL_PATA80;
339
340 return ATA_CBL_PATA40;
341}
342
343static const struct ide_port_ops osb4_port_ops = {
344 .set_pio_mode = svwks_set_pio_mode,
345 .set_dma_mode = svwks_set_dma_mode,
346 .udma_filter = svwks_udma_filter,
347};
348
349static const struct ide_port_ops svwks_port_ops = {
350 .set_pio_mode = svwks_set_pio_mode,
351 .set_dma_mode = svwks_set_dma_mode,
352 .udma_filter = svwks_udma_filter,
353 .cable_detect = svwks_cable_detect,
354};
355
356#define IDE_HFLAGS_SVWKS IDE_HFLAG_LEGACY_IRQS
357
358static const struct ide_port_info serverworks_chipsets[] __devinitdata = {
359 { /* 0: OSB4 */
360 .name = DRV_NAME,
361 .init_chipset = init_chipset_svwks,
362 .port_ops = &osb4_port_ops,
363 .host_flags = IDE_HFLAGS_SVWKS,
364 .pio_mask = ATA_PIO4,
365 .mwdma_mask = ATA_MWDMA2,
366 .udma_mask = 0x00, /* UDMA is problematic on OSB4 */
367 },
368 { /* 1: CSB5 */
369 .name = DRV_NAME,
370 .init_chipset = init_chipset_svwks,
371 .port_ops = &svwks_port_ops,
372 .host_flags = IDE_HFLAGS_SVWKS,
373 .pio_mask = ATA_PIO4,
374 .mwdma_mask = ATA_MWDMA2,
375 .udma_mask = ATA_UDMA5,
376 },
377 { /* 2: CSB6 */
378 .name = DRV_NAME,
379 .init_chipset = init_chipset_svwks,
380 .port_ops = &svwks_port_ops,
381 .host_flags = IDE_HFLAGS_SVWKS,
382 .pio_mask = ATA_PIO4,
383 .mwdma_mask = ATA_MWDMA2,
384 .udma_mask = ATA_UDMA5,
385 },
386 { /* 3: CSB6-2 */
387 .name = DRV_NAME,
388 .init_chipset = init_chipset_svwks,
389 .port_ops = &svwks_port_ops,
390 .host_flags = IDE_HFLAGS_SVWKS | IDE_HFLAG_SINGLE,
391 .pio_mask = ATA_PIO4,
392 .mwdma_mask = ATA_MWDMA2,
393 .udma_mask = ATA_UDMA5,
394 },
395 { /* 4: HT1000 */
396 .name = DRV_NAME,
397 .init_chipset = init_chipset_svwks,
398 .port_ops = &svwks_port_ops,
399 .host_flags = IDE_HFLAGS_SVWKS | IDE_HFLAG_SINGLE,
400 .pio_mask = ATA_PIO4,
401 .mwdma_mask = ATA_MWDMA2,
402 .udma_mask = ATA_UDMA5,
403 }
404};
405
406/**
407 * svwks_init_one - called when a OSB/CSB is found
408 * @dev: the svwks device
409 * @id: the matching pci id
410 *
411 * Called when the PCI registration layer (or the IDE initialization)
412 * finds a device matching our IDE device tables.
413 */
414
415static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
416{
417 struct ide_port_info d;
418 u8 idx = id->driver_data;
419
420 d = serverworks_chipsets[idx];
421
422 if (idx == 1)
423 d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX;
424 else if (idx == 2 || idx == 3) {
425 if ((PCI_FUNC(dev->devfn) & 1) == 0) {
426 if (pci_resource_start(dev, 0) != 0x01f1)
427 d.host_flags |= IDE_HFLAG_NON_BOOTABLE;
428 d.host_flags |= IDE_HFLAG_SINGLE;
429 } else
430 d.host_flags &= ~IDE_HFLAG_SINGLE;
431 }
432
433 return ide_pci_init_one(dev, &d, NULL);
434}
435
436static const struct pci_device_id svwks_pci_tbl[] = {
437 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE), 0 },
438 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE), 1 },
439 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE), 2 },
440 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2), 3 },
441 { PCI_VDEVICE(SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE), 4 },
442 { 0, },
443};
444MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);
445
446static struct pci_driver svwks_pci_driver = {
447 .name = "Serverworks_IDE",
448 .id_table = svwks_pci_tbl,
449 .probe = svwks_init_one,
450 .remove = ide_pci_remove,
451 .suspend = ide_pci_suspend,
452 .resume = ide_pci_resume,
453};
454
455static int __init svwks_ide_init(void)
456{
457 return ide_pci_register_driver(&svwks_pci_driver);
458}
459
460static void __exit svwks_ide_exit(void)
461{
462 pci_unregister_driver(&svwks_pci_driver);
463}
464
465module_init(svwks_ide_init);
466module_exit(svwks_ide_exit);
467
468MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick");
469MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
470MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/sgiioc4.c b/drivers/ide/pci/sgiioc4.c
deleted file mode 100644
index 8af9b23499fd..000000000000
--- a/drivers/ide/pci/sgiioc4.c
+++ /dev/null
@@ -1,674 +0,0 @@
1/*
2 * Copyright (c) 2003-2006 Silicon Graphics, Inc. All Rights Reserved.
3 * Copyright (C) 2008 MontaVista Software, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License
7 * as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it would be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
12 *
13 * You should have received a copy of the GNU General Public
14 * License along with this program; if not, write the Free Software
15 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 *
17 * For further information regarding this notice, see:
18 *
19 * http://oss.sgi.com/projects/GenInfo/NoticeExplan
20 */
21
22#include <linux/module.h>
23#include <linux/types.h>
24#include <linux/pci.h>
25#include <linux/delay.h>
26#include <linux/init.h>
27#include <linux/kernel.h>
28#include <linux/ioport.h>
29#include <linux/blkdev.h>
30#include <linux/scatterlist.h>
31#include <linux/ioc4.h>
32#include <asm/io.h>
33
34#include <linux/ide.h>
35
36#define DRV_NAME "SGIIOC4"
37
38/* IOC4 Specific Definitions */
39#define IOC4_CMD_OFFSET 0x100
40#define IOC4_CTRL_OFFSET 0x120
41#define IOC4_DMA_OFFSET 0x140
42#define IOC4_INTR_OFFSET 0x0
43
44#define IOC4_TIMING 0x00
45#define IOC4_DMA_PTR_L 0x01
46#define IOC4_DMA_PTR_H 0x02
47#define IOC4_DMA_ADDR_L 0x03
48#define IOC4_DMA_ADDR_H 0x04
49#define IOC4_BC_DEV 0x05
50#define IOC4_BC_MEM 0x06
51#define IOC4_DMA_CTRL 0x07
52#define IOC4_DMA_END_ADDR 0x08
53
54/* Bits in the IOC4 Control/Status Register */
55#define IOC4_S_DMA_START 0x01
56#define IOC4_S_DMA_STOP 0x02
57#define IOC4_S_DMA_DIR 0x04
58#define IOC4_S_DMA_ACTIVE 0x08
59#define IOC4_S_DMA_ERROR 0x10
60#define IOC4_ATA_MEMERR 0x02
61
62/* Read/Write Directions */
63#define IOC4_DMA_WRITE 0x04
64#define IOC4_DMA_READ 0x00
65
66/* Interrupt Register Offsets */
67#define IOC4_INTR_REG 0x03
68#define IOC4_INTR_SET 0x05
69#define IOC4_INTR_CLEAR 0x07
70
71#define IOC4_IDE_CACHELINE_SIZE 128
72#define IOC4_CMD_CTL_BLK_SIZE 0x20
73#define IOC4_SUPPORTED_FIRMWARE_REV 46
74
75typedef struct {
76 u32 timing_reg0;
77 u32 timing_reg1;
78 u32 low_mem_ptr;
79 u32 high_mem_ptr;
80 u32 low_mem_addr;
81 u32 high_mem_addr;
82 u32 dev_byte_count;
83 u32 mem_byte_count;
84 u32 status;
85} ioc4_dma_regs_t;
86
87/* Each Physical Region Descriptor Entry size is 16 bytes (2 * 64 bits) */
88/* IOC4 has only 1 IDE channel */
89#define IOC4_PRD_BYTES 16
90#define IOC4_PRD_ENTRIES (PAGE_SIZE /(4*IOC4_PRD_BYTES))
91
92
93static void
94sgiioc4_init_hwif_ports(hw_regs_t * hw, unsigned long data_port,
95 unsigned long ctrl_port, unsigned long irq_port)
96{
97 unsigned long reg = data_port;
98 int i;
99
100 /* Registers are word (32 bit) aligned */
101 for (i = 0; i <= 7; i++)
102 hw->io_ports_array[i] = reg + i * 4;
103
104 hw->io_ports.ctl_addr = ctrl_port;
105 hw->io_ports.irq_addr = irq_port;
106}
107
108static int
109sgiioc4_checkirq(ide_hwif_t * hwif)
110{
111 unsigned long intr_addr =
112 hwif->io_ports.irq_addr + IOC4_INTR_REG * 4;
113
114 if ((u8)readl((void __iomem *)intr_addr) & 0x03)
115 return 1;
116
117 return 0;
118}
119
120static u8 sgiioc4_read_status(ide_hwif_t *);
121
122static int
123sgiioc4_clearirq(ide_drive_t * drive)
124{
125 u32 intr_reg;
126 ide_hwif_t *hwif = HWIF(drive);
127 struct ide_io_ports *io_ports = &hwif->io_ports;
128 unsigned long other_ir = io_ports->irq_addr + (IOC4_INTR_REG << 2);
129
130 /* Code to check for PCI error conditions */
131 intr_reg = readl((void __iomem *)other_ir);
132 if (intr_reg & 0x03) { /* Valid IOC4-IDE interrupt */
133 /*
134 * Using sgiioc4_read_status to read the Status register has a
135 * side effect of clearing the interrupt. The first read should
136 * clear it if it is set. The second read should return
137 * a "clear" status if it got cleared. If not, then spin
138 * for a bit trying to clear it.
139 */
140 u8 stat = sgiioc4_read_status(hwif);
141 int count = 0;
142
143 stat = sgiioc4_read_status(hwif);
144 while ((stat & ATA_BUSY) && (count++ < 100)) {
145 udelay(1);
146 stat = sgiioc4_read_status(hwif);
147 }
148
149 if (intr_reg & 0x02) {
150 struct pci_dev *dev = to_pci_dev(hwif->dev);
151 /* Error when transferring DMA data on PCI bus */
152 u32 pci_err_addr_low, pci_err_addr_high,
153 pci_stat_cmd_reg;
154
155 pci_err_addr_low =
156 readl((void __iomem *)io_ports->irq_addr);
157 pci_err_addr_high =
158 readl((void __iomem *)(io_ports->irq_addr + 4));
159 pci_read_config_dword(dev, PCI_COMMAND,
160 &pci_stat_cmd_reg);
161 printk(KERN_ERR
162 "%s(%s) : PCI Bus Error when doing DMA:"
163 " status-cmd reg is 0x%x\n",
164 __func__, drive->name, pci_stat_cmd_reg);
165 printk(KERN_ERR
166 "%s(%s) : PCI Error Address is 0x%x%x\n",
167 __func__, drive->name,
168 pci_err_addr_high, pci_err_addr_low);
169 /* Clear the PCI Error indicator */
170 pci_write_config_dword(dev, PCI_COMMAND, 0x00000146);
171 }
172
173 /* Clear the Interrupt, Error bits on the IOC4 */
174 writel(0x03, (void __iomem *)other_ir);
175
176 intr_reg = readl((void __iomem *)other_ir);
177 }
178
179 return intr_reg & 3;
180}
181
182static void sgiioc4_dma_start(ide_drive_t *drive)
183{
184 ide_hwif_t *hwif = HWIF(drive);
185 unsigned long ioc4_dma_addr = hwif->dma_base + IOC4_DMA_CTRL * 4;
186 unsigned int reg = readl((void __iomem *)ioc4_dma_addr);
187 unsigned int temp_reg = reg | IOC4_S_DMA_START;
188
189 writel(temp_reg, (void __iomem *)ioc4_dma_addr);
190}
191
192static u32
193sgiioc4_ide_dma_stop(ide_hwif_t *hwif, u64 dma_base)
194{
195 unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
196 u32 ioc4_dma;
197 int count;
198
199 count = 0;
200 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
201 while ((ioc4_dma & IOC4_S_DMA_STOP) && (count++ < 200)) {
202 udelay(1);
203 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
204 }
205 return ioc4_dma;
206}
207
208/* Stops the IOC4 DMA Engine */
209static int sgiioc4_dma_end(ide_drive_t *drive)
210{
211 u32 ioc4_dma, bc_dev, bc_mem, num, valid = 0, cnt = 0;
212 ide_hwif_t *hwif = HWIF(drive);
213 unsigned long dma_base = hwif->dma_base;
214 int dma_stat = 0;
215 unsigned long *ending_dma = ide_get_hwifdata(hwif);
216
217 writel(IOC4_S_DMA_STOP, (void __iomem *)(dma_base + IOC4_DMA_CTRL * 4));
218
219 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
220
221 if (ioc4_dma & IOC4_S_DMA_STOP) {
222 printk(KERN_ERR
223 "%s(%s): IOC4 DMA STOP bit is still 1 :"
224 "ioc4_dma_reg 0x%x\n",
225 __func__, drive->name, ioc4_dma);
226 dma_stat = 1;
227 }
228
229 /*
230 * The IOC4 will DMA 1's to the ending dma area to indicate that
231 * previous data DMA is complete. This is necessary because of relaxed
232 * ordering between register reads and DMA writes on the Altix.
233 */
234 while ((cnt++ < 200) && (!valid)) {
235 for (num = 0; num < 16; num++) {
236 if (ending_dma[num]) {
237 valid = 1;
238 break;
239 }
240 }
241 udelay(1);
242 }
243 if (!valid) {
244 printk(KERN_ERR "%s(%s) : DMA incomplete\n", __func__,
245 drive->name);
246 dma_stat = 1;
247 }
248
249 bc_dev = readl((void __iomem *)(dma_base + IOC4_BC_DEV * 4));
250 bc_mem = readl((void __iomem *)(dma_base + IOC4_BC_MEM * 4));
251
252 if ((bc_dev & 0x01FF) || (bc_mem & 0x1FF)) {
253 if (bc_dev > bc_mem + 8) {
254 printk(KERN_ERR
255 "%s(%s): WARNING!! byte_count_dev %d "
256 "!= byte_count_mem %d\n",
257 __func__, drive->name, bc_dev, bc_mem);
258 }
259 }
260
261 drive->waiting_for_dma = 0;
262 ide_destroy_dmatable(drive);
263
264 return dma_stat;
265}
266
267static void sgiioc4_set_dma_mode(ide_drive_t *drive, const u8 speed)
268{
269}
270
271/* returns 1 if dma irq issued, 0 otherwise */
272static int sgiioc4_dma_test_irq(ide_drive_t *drive)
273{
274 return sgiioc4_checkirq(HWIF(drive));
275}
276
277static void sgiioc4_dma_host_set(ide_drive_t *drive, int on)
278{
279 if (!on)
280 sgiioc4_clearirq(drive);
281}
282
283static void
284sgiioc4_resetproc(ide_drive_t * drive)
285{
286 sgiioc4_dma_end(drive);
287 sgiioc4_clearirq(drive);
288}
289
290static void
291sgiioc4_dma_lost_irq(ide_drive_t * drive)
292{
293 sgiioc4_resetproc(drive);
294
295 ide_dma_lost_irq(drive);
296}
297
298static u8 sgiioc4_read_status(ide_hwif_t *hwif)
299{
300 unsigned long port = hwif->io_ports.status_addr;
301 u8 reg = (u8) readb((void __iomem *) port);
302
303 if (!(reg & ATA_BUSY)) { /* Not busy... check for interrupt */
304 unsigned long other_ir = port - 0x110;
305 unsigned int intr_reg = (u32) readl((void __iomem *) other_ir);
306
307 /* Clear the Interrupt, Error bits on the IOC4 */
308 if (intr_reg & 0x03) {
309 writel(0x03, (void __iomem *) other_ir);
310 intr_reg = (u32) readl((void __iomem *) other_ir);
311 }
312 }
313
314 return reg;
315}
316
317/* Creates a dma map for the scatter-gather list entries */
318static int __devinit
319ide_dma_sgiioc4(ide_hwif_t *hwif, const struct ide_port_info *d)
320{
321 struct pci_dev *dev = to_pci_dev(hwif->dev);
322 unsigned long dma_base = pci_resource_start(dev, 0) + IOC4_DMA_OFFSET;
323 int num_ports = sizeof (ioc4_dma_regs_t);
324 void *pad;
325
326 printk(KERN_INFO " %s: MMIO-DMA\n", hwif->name);
327
328 if (request_mem_region(dma_base, num_ports, hwif->name) == NULL) {
329 printk(KERN_ERR "%s(%s) -- ERROR: addresses 0x%08lx to 0x%08lx "
330 "already in use\n", __func__, hwif->name,
331 dma_base, dma_base + num_ports - 1);
332 return -1;
333 }
334
335 hwif->dma_base = (unsigned long)hwif->io_ports.irq_addr +
336 IOC4_DMA_OFFSET;
337
338 hwif->sg_max_nents = IOC4_PRD_ENTRIES;
339
340 hwif->prd_max_nents = IOC4_PRD_ENTRIES;
341 hwif->prd_ent_size = IOC4_PRD_BYTES;
342
343 if (ide_allocate_dma_engine(hwif))
344 goto dma_pci_alloc_failure;
345
346 pad = pci_alloc_consistent(dev, IOC4_IDE_CACHELINE_SIZE,
347 (dma_addr_t *)&hwif->extra_base);
348 if (pad) {
349 ide_set_hwifdata(hwif, pad);
350 return 0;
351 }
352
353 ide_release_dma_engine(hwif);
354
355 printk(KERN_ERR "%s(%s) -- ERROR: Unable to allocate DMA maps\n",
356 __func__, hwif->name);
357 printk(KERN_INFO "%s: changing from DMA to PIO mode", hwif->name);
358
359dma_pci_alloc_failure:
360 release_mem_region(dma_base, num_ports);
361
362 return -1;
363}
364
365/* Initializes the IOC4 DMA Engine */
366static void
367sgiioc4_configure_for_dma(int dma_direction, ide_drive_t * drive)
368{
369 u32 ioc4_dma;
370 ide_hwif_t *hwif = HWIF(drive);
371 unsigned long dma_base = hwif->dma_base;
372 unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
373 u32 dma_addr, ending_dma_addr;
374
375 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
376
377 if (ioc4_dma & IOC4_S_DMA_ACTIVE) {
378 printk(KERN_WARNING
379 "%s(%s):Warning!! DMA from previous transfer was still active\n",
380 __func__, drive->name);
381 writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
382 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
383
384 if (ioc4_dma & IOC4_S_DMA_STOP)
385 printk(KERN_ERR
386 "%s(%s) : IOC4 Dma STOP bit is still 1\n",
387 __func__, drive->name);
388 }
389
390 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
391 if (ioc4_dma & IOC4_S_DMA_ERROR) {
392 printk(KERN_WARNING
393 "%s(%s) : Warning!! - DMA Error during Previous"
394 " transfer | status 0x%x\n",
395 __func__, drive->name, ioc4_dma);
396 writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
397 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
398
399 if (ioc4_dma & IOC4_S_DMA_STOP)
400 printk(KERN_ERR
401 "%s(%s) : IOC4 DMA STOP bit is still 1\n",
402 __func__, drive->name);
403 }
404
405 /* Address of the Scatter Gather List */
406 dma_addr = cpu_to_le32(hwif->dmatable_dma);
407 writel(dma_addr, (void __iomem *)(dma_base + IOC4_DMA_PTR_L * 4));
408
409 /* Address of the Ending DMA */
410 memset(ide_get_hwifdata(hwif), 0, IOC4_IDE_CACHELINE_SIZE);
411 ending_dma_addr = cpu_to_le32(hwif->extra_base);
412 writel(ending_dma_addr, (void __iomem *)(dma_base + IOC4_DMA_END_ADDR * 4));
413
414 writel(dma_direction, (void __iomem *)ioc4_dma_addr);
415 drive->waiting_for_dma = 1;
416}
417
418/* IOC4 Scatter Gather list Format */
419/* 128 Bit entries to support 64 bit addresses in the future */
420/* The Scatter Gather list Entry should be in the BIG-ENDIAN Format */
421/* --------------------------------------------------------------------- */
422/* | Upper 32 bits - Zero | Lower 32 bits- address | */
423/* --------------------------------------------------------------------- */
424/* | Upper 32 bits - Zero |EOL| 15 unused | 16 Bit Length| */
425/* --------------------------------------------------------------------- */
426/* Creates the scatter gather list, DMA Table */
427static unsigned int
428sgiioc4_build_dma_table(ide_drive_t * drive, struct request *rq, int ddir)
429{
430 ide_hwif_t *hwif = HWIF(drive);
431 unsigned int *table = hwif->dmatable_cpu;
432 unsigned int count = 0, i = 1;
433 struct scatterlist *sg;
434
435 hwif->sg_nents = i = ide_build_sglist(drive, rq);
436
437 if (!i)
438 return 0; /* sglist of length Zero */
439
440 sg = hwif->sg_table;
441 while (i && sg_dma_len(sg)) {
442 dma_addr_t cur_addr;
443 int cur_len;
444 cur_addr = sg_dma_address(sg);
445 cur_len = sg_dma_len(sg);
446
447 while (cur_len) {
448 if (count++ >= IOC4_PRD_ENTRIES) {
449 printk(KERN_WARNING
450 "%s: DMA table too small\n",
451 drive->name);
452 goto use_pio_instead;
453 } else {
454 u32 bcount =
455 0x10000 - (cur_addr & 0xffff);
456
457 if (bcount > cur_len)
458 bcount = cur_len;
459
460 /* put the addr, length in
461 * the IOC4 dma-table format */
462 *table = 0x0;
463 table++;
464 *table = cpu_to_be32(cur_addr);
465 table++;
466 *table = 0x0;
467 table++;
468
469 *table = cpu_to_be32(bcount);
470 table++;
471
472 cur_addr += bcount;
473 cur_len -= bcount;
474 }
475 }
476
477 sg = sg_next(sg);
478 i--;
479 }
480
481 if (count) {
482 table--;
483 *table |= cpu_to_be32(0x80000000);
484 return count;
485 }
486
487use_pio_instead:
488 ide_destroy_dmatable(drive);
489
490 return 0; /* revert to PIO for this request */
491}
492
493static int sgiioc4_dma_setup(ide_drive_t *drive)
494{
495 struct request *rq = HWGROUP(drive)->rq;
496 unsigned int count = 0;
497 int ddir;
498
499 if (rq_data_dir(rq))
500 ddir = PCI_DMA_TODEVICE;
501 else
502 ddir = PCI_DMA_FROMDEVICE;
503
504 if (!(count = sgiioc4_build_dma_table(drive, rq, ddir))) {
505 /* try PIO instead of DMA */
506 ide_map_sg(drive, rq);
507 return 1;
508 }
509
510 if (rq_data_dir(rq))
511 /* Writes TO the IOC4 FROM Main Memory */
512 ddir = IOC4_DMA_READ;
513 else
514 /* Writes FROM the IOC4 TO Main Memory */
515 ddir = IOC4_DMA_WRITE;
516
517 sgiioc4_configure_for_dma(ddir, drive);
518
519 return 0;
520}
521
522static const struct ide_tp_ops sgiioc4_tp_ops = {
523 .exec_command = ide_exec_command,
524 .read_status = sgiioc4_read_status,
525 .read_altstatus = ide_read_altstatus,
526 .read_sff_dma_status = ide_read_sff_dma_status,
527
528 .set_irq = ide_set_irq,
529
530 .tf_load = ide_tf_load,
531 .tf_read = ide_tf_read,
532
533 .input_data = ide_input_data,
534 .output_data = ide_output_data,
535};
536
537static const struct ide_port_ops sgiioc4_port_ops = {
538 .set_dma_mode = sgiioc4_set_dma_mode,
539 /* reset DMA engine, clear IRQs */
540 .resetproc = sgiioc4_resetproc,
541};
542
543static const struct ide_dma_ops sgiioc4_dma_ops = {
544 .dma_host_set = sgiioc4_dma_host_set,
545 .dma_setup = sgiioc4_dma_setup,
546 .dma_start = sgiioc4_dma_start,
547 .dma_end = sgiioc4_dma_end,
548 .dma_test_irq = sgiioc4_dma_test_irq,
549 .dma_lost_irq = sgiioc4_dma_lost_irq,
550 .dma_timeout = ide_dma_timeout,
551};
552
553static const struct ide_port_info sgiioc4_port_info __devinitdata = {
554 .name = DRV_NAME,
555 .chipset = ide_pci,
556 .init_dma = ide_dma_sgiioc4,
557 .tp_ops = &sgiioc4_tp_ops,
558 .port_ops = &sgiioc4_port_ops,
559 .dma_ops = &sgiioc4_dma_ops,
560 .host_flags = IDE_HFLAG_MMIO,
561 .mwdma_mask = ATA_MWDMA2_ONLY,
562};
563
564static int __devinit
565sgiioc4_ide_setup_pci_device(struct pci_dev *dev)
566{
567 unsigned long cmd_base, irqport;
568 unsigned long bar0, cmd_phys_base, ctl;
569 void __iomem *virt_base;
570 struct ide_host *host;
571 hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
572 struct ide_port_info d = sgiioc4_port_info;
573 int rc;
574
575 /* Get the CmdBlk and CtrlBlk Base Registers */
576 bar0 = pci_resource_start(dev, 0);
577 virt_base = ioremap(bar0, pci_resource_len(dev, 0));
578 if (virt_base == NULL) {
579 printk(KERN_ERR "%s: Unable to remap BAR 0 address: 0x%lx\n",
580 DRV_NAME, bar0);
581 return -ENOMEM;
582 }
583 cmd_base = (unsigned long) virt_base + IOC4_CMD_OFFSET;
584 ctl = (unsigned long) virt_base + IOC4_CTRL_OFFSET;
585 irqport = (unsigned long) virt_base + IOC4_INTR_OFFSET;
586
587 cmd_phys_base = bar0 + IOC4_CMD_OFFSET;
588 if (request_mem_region(cmd_phys_base, IOC4_CMD_CTL_BLK_SIZE,
589 DRV_NAME) == NULL) {
590 printk(KERN_ERR "%s %s -- ERROR: addresses 0x%08lx to 0x%08lx "
591 "already in use\n", DRV_NAME, pci_name(dev),
592 cmd_phys_base, cmd_phys_base + IOC4_CMD_CTL_BLK_SIZE);
593 return -EBUSY;
594 }
595
596 /* Initialize the IO registers */
597 memset(&hw, 0, sizeof(hw));
598 sgiioc4_init_hwif_ports(&hw, cmd_base, ctl, irqport);
599 hw.irq = dev->irq;
600 hw.chipset = ide_pci;
601 hw.dev = &dev->dev;
602
603 /* Initializing chipset IRQ Registers */
604 writel(0x03, (void __iomem *)(irqport + IOC4_INTR_SET * 4));
605
606 host = ide_host_alloc(&d, hws);
607 if (host == NULL) {
608 rc = -ENOMEM;
609 goto err;
610 }
611
612 rc = ide_host_register(host, &d, hws);
613 if (rc)
614 goto err_free;
615
616 return 0;
617err_free:
618 ide_host_free(host);
619err:
620 release_mem_region(cmd_phys_base, IOC4_CMD_CTL_BLK_SIZE);
621 iounmap(virt_base);
622 return rc;
623}
624
625static unsigned int __devinit
626pci_init_sgiioc4(struct pci_dev *dev)
627{
628 int ret;
629
630 printk(KERN_INFO "%s: IDE controller at PCI slot %s, revision %d\n",
631 DRV_NAME, pci_name(dev), dev->revision);
632
633 if (dev->revision < IOC4_SUPPORTED_FIRMWARE_REV) {
634 printk(KERN_ERR "Skipping %s IDE controller in slot %s: "
635 "firmware is obsolete - please upgrade to "
636 "revision46 or higher\n",
637 DRV_NAME, pci_name(dev));
638 ret = -EAGAIN;
639 goto out;
640 }
641 ret = sgiioc4_ide_setup_pci_device(dev);
642out:
643 return ret;
644}
645
646int
647ioc4_ide_attach_one(struct ioc4_driver_data *idd)
648{
649 /* PCI-RT does not bring out IDE connection.
650 * Do not attach to this particular IOC4.
651 */
652 if (idd->idd_variant == IOC4_VARIANT_PCI_RT)
653 return 0;
654
655 return pci_init_sgiioc4(idd->idd_pdev);
656}
657
658static struct ioc4_submodule ioc4_ide_submodule = {
659 .is_name = "IOC4_ide",
660 .is_owner = THIS_MODULE,
661 .is_probe = ioc4_ide_attach_one,
662/* .is_remove = ioc4_ide_remove_one, */
663};
664
665static int __init ioc4_ide_init(void)
666{
667 return ioc4_register_submodule(&ioc4_ide_submodule);
668}
669
670late_initcall(ioc4_ide_init); /* Call only after IDE init is done */
671
672MODULE_AUTHOR("Aniket Malatpure/Jeremy Higdon");
673MODULE_DESCRIPTION("IDE PCI driver module for SGI IOC4 Base-IO Card");
674MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/siimage.c b/drivers/ide/pci/siimage.c
deleted file mode 100644
index eb4faf92c571..000000000000
--- a/drivers/ide/pci/siimage.c
+++ /dev/null
@@ -1,857 +0,0 @@
1/*
2 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
3 * Copyright (C) 2003 Red Hat <alan@redhat.com>
4 * Copyright (C) 2007-2008 MontaVista Software, Inc.
5 * Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz
6 *
7 * May be copied or modified under the terms of the GNU General Public License
8 *
9 * Documentation for CMD680:
10 * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2
11 *
12 * Documentation for SiI 3112:
13 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
14 *
15 * Errata and other documentation only available under NDA.
16 *
17 *
18 * FAQ Items:
19 * If you are using Marvell SATA-IDE adapters with Maxtor drives
20 * ensure the system is set up for ATA100/UDMA5, not UDMA6.
21 *
22 * If you are using WD drives with SATA bridges you must set the
23 * drive to "Single". "Master" will hang.
24 *
25 * If you have strange problems with nVidia chipset systems please
26 * see the SI support documentation and update your system BIOS
27 * if necessary
28 *
29 * The Dell DRAC4 has some interesting features including effectively hot
30 * unplugging/replugging the virtual CD interface when the DRAC is reset.
31 * This often causes drivers/ide/siimage to panic but is ok with the rather
32 * smarter code in libata.
33 *
34 * TODO:
35 * - IORDY fixes
36 * - VDMA support
37 */
38
39#include <linux/types.h>
40#include <linux/module.h>
41#include <linux/pci.h>
42#include <linux/ide.h>
43#include <linux/init.h>
44#include <linux/io.h>
45
46#define DRV_NAME "siimage"
47
48/**
49 * pdev_is_sata - check if device is SATA
50 * @pdev: PCI device to check
51 *
52 * Returns true if this is a SATA controller
53 */
54
55static int pdev_is_sata(struct pci_dev *pdev)
56{
57#ifdef CONFIG_BLK_DEV_IDE_SATA
58 switch (pdev->device) {
59 case PCI_DEVICE_ID_SII_3112:
60 case PCI_DEVICE_ID_SII_1210SA:
61 return 1;
62 case PCI_DEVICE_ID_SII_680:
63 return 0;
64 }
65 BUG();
66#endif
67 return 0;
68}
69
70/**
71 * is_sata - check if hwif is SATA
72 * @hwif: interface to check
73 *
74 * Returns true if this is a SATA controller
75 */
76
77static inline int is_sata(ide_hwif_t *hwif)
78{
79 return pdev_is_sata(to_pci_dev(hwif->dev));
80}
81
82/**
83 * siimage_selreg - return register base
84 * @hwif: interface
85 * @r: config offset
86 *
87 * Turn a config register offset into the right address in either
88 * PCI space or MMIO space to access the control register in question
89 * Thankfully this is a configuration operation, so isn't performance
90 * critical.
91 */
92
93static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
94{
95 unsigned long base = (unsigned long)hwif->hwif_data;
96
97 base += 0xA0 + r;
98 if (hwif->host_flags & IDE_HFLAG_MMIO)
99 base += hwif->channel << 6;
100 else
101 base += hwif->channel << 4;
102 return base;
103}
104
105/**
106 * siimage_seldev - return register base
107 * @hwif: interface
108 * @r: config offset
109 *
110 * Turn a config register offset into the right address in either
111 * PCI space or MMIO space to access the control register in question
112 * including accounting for the unit shift.
113 */
114
115static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
116{
117 ide_hwif_t *hwif = HWIF(drive);
118 unsigned long base = (unsigned long)hwif->hwif_data;
119 u8 unit = drive->dn & 1;
120
121 base += 0xA0 + r;
122 if (hwif->host_flags & IDE_HFLAG_MMIO)
123 base += hwif->channel << 6;
124 else
125 base += hwif->channel << 4;
126 base |= unit << unit;
127 return base;
128}
129
130static u8 sil_ioread8(struct pci_dev *dev, unsigned long addr)
131{
132 struct ide_host *host = pci_get_drvdata(dev);
133 u8 tmp = 0;
134
135 if (host->host_priv)
136 tmp = readb((void __iomem *)addr);
137 else
138 pci_read_config_byte(dev, addr, &tmp);
139
140 return tmp;
141}
142
143static u16 sil_ioread16(struct pci_dev *dev, unsigned long addr)
144{
145 struct ide_host *host = pci_get_drvdata(dev);
146 u16 tmp = 0;
147
148 if (host->host_priv)
149 tmp = readw((void __iomem *)addr);
150 else
151 pci_read_config_word(dev, addr, &tmp);
152
153 return tmp;
154}
155
156static void sil_iowrite8(struct pci_dev *dev, u8 val, unsigned long addr)
157{
158 struct ide_host *host = pci_get_drvdata(dev);
159
160 if (host->host_priv)
161 writeb(val, (void __iomem *)addr);
162 else
163 pci_write_config_byte(dev, addr, val);
164}
165
166static void sil_iowrite16(struct pci_dev *dev, u16 val, unsigned long addr)
167{
168 struct ide_host *host = pci_get_drvdata(dev);
169
170 if (host->host_priv)
171 writew(val, (void __iomem *)addr);
172 else
173 pci_write_config_word(dev, addr, val);
174}
175
176static void sil_iowrite32(struct pci_dev *dev, u32 val, unsigned long addr)
177{
178 struct ide_host *host = pci_get_drvdata(dev);
179
180 if (host->host_priv)
181 writel(val, (void __iomem *)addr);
182 else
183 pci_write_config_dword(dev, addr, val);
184}
185
186/**
187 * sil_udma_filter - compute UDMA mask
188 * @drive: IDE device
189 *
190 * Compute the available UDMA speeds for the device on the interface.
191 *
192 * For the CMD680 this depends on the clocking mode (scsc), for the
193 * SI3112 SATA controller life is a bit simpler.
194 */
195
196static u8 sil_pata_udma_filter(ide_drive_t *drive)
197{
198 ide_hwif_t *hwif = drive->hwif;
199 struct pci_dev *dev = to_pci_dev(hwif->dev);
200 unsigned long base = (unsigned long)hwif->hwif_data;
201 u8 scsc, mask = 0;
202
203 base += (hwif->host_flags & IDE_HFLAG_MMIO) ? 0x4A : 0x8A;
204
205 scsc = sil_ioread8(dev, base);
206
207 switch (scsc & 0x30) {
208 case 0x10: /* 133 */
209 mask = ATA_UDMA6;
210 break;
211 case 0x20: /* 2xPCI */
212 mask = ATA_UDMA6;
213 break;
214 case 0x00: /* 100 */
215 mask = ATA_UDMA5;
216 break;
217 default: /* Disabled ? */
218 BUG();
219 }
220
221 return mask;
222}
223
224static u8 sil_sata_udma_filter(ide_drive_t *drive)
225{
226 char *m = (char *)&drive->id[ATA_ID_PROD];
227
228 return strstr(m, "Maxtor") ? ATA_UDMA5 : ATA_UDMA6;
229}
230
231/**
232 * sil_set_pio_mode - set host controller for PIO mode
233 * @drive: drive
234 * @pio: PIO mode number
235 *
236 * Load the timing settings for this device mode into the
237 * controller. If we are in PIO mode 3 or 4 turn on IORDY
238 * monitoring (bit 9). The TF timing is bits 31:16
239 */
240
241static void sil_set_pio_mode(ide_drive_t *drive, u8 pio)
242{
243 static const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 };
244 static const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
245
246 ide_hwif_t *hwif = HWIF(drive);
247 struct pci_dev *dev = to_pci_dev(hwif->dev);
248 ide_drive_t *pair = ide_get_pair_dev(drive);
249 u32 speedt = 0;
250 u16 speedp = 0;
251 unsigned long addr = siimage_seldev(drive, 0x04);
252 unsigned long tfaddr = siimage_selreg(hwif, 0x02);
253 unsigned long base = (unsigned long)hwif->hwif_data;
254 u8 tf_pio = pio;
255 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
256 u8 addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84)
257 : (mmio ? 0xB4 : 0x80);
258 u8 mode = 0;
259 u8 unit = drive->dn & 1;
260
261 /* trim *taskfile* PIO to the slowest of the master/slave */
262 if (pair) {
263 u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4);
264
265 if (pair_pio < tf_pio)
266 tf_pio = pair_pio;
267 }
268
269 /* cheat for now and use the docs */
270 speedp = data_speed[pio];
271 speedt = tf_speed[tf_pio];
272
273 sil_iowrite16(dev, speedp, addr);
274 sil_iowrite16(dev, speedt, tfaddr);
275
276 /* now set up IORDY */
277 speedp = sil_ioread16(dev, tfaddr - 2);
278 speedp &= ~0x200;
279 if (pio > 2)
280 speedp |= 0x200;
281 sil_iowrite16(dev, speedp, tfaddr - 2);
282
283 mode = sil_ioread8(dev, base + addr_mask);
284 mode &= ~(unit ? 0x30 : 0x03);
285 mode |= unit ? 0x10 : 0x01;
286 sil_iowrite8(dev, mode, base + addr_mask);
287}
288
289/**
290 * sil_set_dma_mode - set host controller for DMA mode
291 * @drive: drive
292 * @speed: DMA mode
293 *
294 * Tune the SiI chipset for the desired DMA mode.
295 */
296
297static void sil_set_dma_mode(ide_drive_t *drive, const u8 speed)
298{
299 static const u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
300 static const u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
301 static const u16 dma[] = { 0x2208, 0x10C2, 0x10C1 };
302
303 ide_hwif_t *hwif = HWIF(drive);
304 struct pci_dev *dev = to_pci_dev(hwif->dev);
305 unsigned long base = (unsigned long)hwif->hwif_data;
306 u16 ultra = 0, multi = 0;
307 u8 mode = 0, unit = drive->dn & 1;
308 u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
309 u8 scsc = 0, addr_mask = hwif->channel ? (mmio ? 0xF4 : 0x84)
310 : (mmio ? 0xB4 : 0x80);
311 unsigned long ma = siimage_seldev(drive, 0x08);
312 unsigned long ua = siimage_seldev(drive, 0x0C);
313
314 scsc = sil_ioread8 (dev, base + (mmio ? 0x4A : 0x8A));
315 mode = sil_ioread8 (dev, base + addr_mask);
316 multi = sil_ioread16(dev, ma);
317 ultra = sil_ioread16(dev, ua);
318
319 mode &= ~(unit ? 0x30 : 0x03);
320 ultra &= ~0x3F;
321 scsc = ((scsc & 0x30) == 0x00) ? 0 : 1;
322
323 scsc = is_sata(hwif) ? 1 : scsc;
324
325 if (speed >= XFER_UDMA_0) {
326 multi = dma[2];
327 ultra |= scsc ? ultra6[speed - XFER_UDMA_0] :
328 ultra5[speed - XFER_UDMA_0];
329 mode |= unit ? 0x30 : 0x03;
330 } else {
331 multi = dma[speed - XFER_MW_DMA_0];
332 mode |= unit ? 0x20 : 0x02;
333 }
334
335 sil_iowrite8 (dev, mode, base + addr_mask);
336 sil_iowrite16(dev, multi, ma);
337 sil_iowrite16(dev, ultra, ua);
338}
339
340/* returns 1 if dma irq issued, 0 otherwise */
341static int siimage_io_dma_test_irq(ide_drive_t *drive)
342{
343 ide_hwif_t *hwif = HWIF(drive);
344 struct pci_dev *dev = to_pci_dev(hwif->dev);
345 u8 dma_altstat = 0;
346 unsigned long addr = siimage_selreg(hwif, 1);
347
348 /* return 1 if INTR asserted */
349 if (inb(hwif->dma_base + ATA_DMA_STATUS) & 4)
350 return 1;
351
352 /* return 1 if Device INTR asserted */
353 pci_read_config_byte(dev, addr, &dma_altstat);
354 if (dma_altstat & 8)
355 return 0; /* return 1; */
356
357 return 0;
358}
359
360/**
361 * siimage_mmio_dma_test_irq - check we caused an IRQ
362 * @drive: drive we are testing
363 *
364 * Check if we caused an IDE DMA interrupt. We may also have caused
365 * SATA status interrupts, if so we clean them up and continue.
366 */
367
368static int siimage_mmio_dma_test_irq(ide_drive_t *drive)
369{
370 ide_hwif_t *hwif = HWIF(drive);
371 unsigned long addr = siimage_selreg(hwif, 0x1);
372 void __iomem *sata_error_addr
373 = (void __iomem *)hwif->sata_scr[SATA_ERROR_OFFSET];
374
375 if (sata_error_addr) {
376 unsigned long base = (unsigned long)hwif->hwif_data;
377 u32 ext_stat = readl((void __iomem *)(base + 0x10));
378 u8 watchdog = 0;
379
380 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
381 u32 sata_error = readl(sata_error_addr);
382
383 writel(sata_error, sata_error_addr);
384 watchdog = (sata_error & 0x00680000) ? 1 : 0;
385 printk(KERN_WARNING "%s: sata_error = 0x%08x, "
386 "watchdog = %d, %s\n",
387 drive->name, sata_error, watchdog, __func__);
388 } else
389 watchdog = (ext_stat & 0x8000) ? 1 : 0;
390
391 ext_stat >>= 16;
392 if (!(ext_stat & 0x0404) && !watchdog)
393 return 0;
394 }
395
396 /* return 1 if INTR asserted */
397 if (readb((void __iomem *)(hwif->dma_base + ATA_DMA_STATUS)) & 4)
398 return 1;
399
400 /* return 1 if Device INTR asserted */
401 if (readb((void __iomem *)addr) & 8)
402 return 0; /* return 1; */
403
404 return 0;
405}
406
407static int siimage_dma_test_irq(ide_drive_t *drive)
408{
409 if (drive->hwif->host_flags & IDE_HFLAG_MMIO)
410 return siimage_mmio_dma_test_irq(drive);
411 else
412 return siimage_io_dma_test_irq(drive);
413}
414
415/**
416 * sil_sata_reset_poll - wait for SATA reset
417 * @drive: drive we are resetting
418 *
419 * Poll the SATA phy and see whether it has come back from the dead
420 * yet.
421 */
422
423static int sil_sata_reset_poll(ide_drive_t *drive)
424{
425 ide_hwif_t *hwif = drive->hwif;
426 void __iomem *sata_status_addr
427 = (void __iomem *)hwif->sata_scr[SATA_STATUS_OFFSET];
428
429 if (sata_status_addr) {
430 /* SATA Status is available only when in MMIO mode */
431 u32 sata_stat = readl(sata_status_addr);
432
433 if ((sata_stat & 0x03) != 0x03) {
434 printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
435 hwif->name, sata_stat);
436 return -ENXIO;
437 }
438 }
439
440 return 0;
441}
442
443/**
444 * sil_sata_pre_reset - reset hook
445 * @drive: IDE device being reset
446 *
447 * For the SATA devices we need to handle recalibration/geometry
448 * differently
449 */
450
451static void sil_sata_pre_reset(ide_drive_t *drive)
452{
453 if (drive->media == ide_disk) {
454 drive->special.b.set_geometry = 0;
455 drive->special.b.recalibrate = 0;
456 }
457}
458
459/**
460 * init_chipset_siimage - set up an SI device
461 * @dev: PCI device
462 *
463 * Perform the initial PCI set up for this device. Attempt to switch
464 * to 133 MHz clocking if the system isn't already set up to do it.
465 */
466
467static unsigned int init_chipset_siimage(struct pci_dev *dev)
468{
469 struct ide_host *host = pci_get_drvdata(dev);
470 void __iomem *ioaddr = host->host_priv;
471 unsigned long base, scsc_addr;
472 u8 rev = dev->revision, tmp;
473
474 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255);
475
476 if (ioaddr)
477 pci_set_master(dev);
478
479 base = (unsigned long)ioaddr;
480
481 if (ioaddr && pdev_is_sata(dev)) {
482 u32 tmp32, irq_mask;
483
484 /* make sure IDE0/1 interrupts are not masked */
485 irq_mask = (1 << 22) | (1 << 23);
486 tmp32 = readl(ioaddr + 0x48);
487 if (tmp32 & irq_mask) {
488 tmp32 &= ~irq_mask;
489 writel(tmp32, ioaddr + 0x48);
490 readl(ioaddr + 0x48); /* flush */
491 }
492 writel(0, ioaddr + 0x148);
493 writel(0, ioaddr + 0x1C8);
494 }
495
496 sil_iowrite8(dev, 0, base ? (base + 0xB4) : 0x80);
497 sil_iowrite8(dev, 0, base ? (base + 0xF4) : 0x84);
498
499 scsc_addr = base ? (base + 0x4A) : 0x8A;
500 tmp = sil_ioread8(dev, scsc_addr);
501
502 switch (tmp & 0x30) {
503 case 0x00:
504 /* On 100 MHz clocking, try and switch to 133 MHz */
505 sil_iowrite8(dev, tmp | 0x10, scsc_addr);
506 break;
507 case 0x30:
508 /* Clocking is disabled, attempt to force 133MHz clocking. */
509 sil_iowrite8(dev, tmp & ~0x20, scsc_addr);
510 case 0x10:
511 /* On 133Mhz clocking. */
512 break;
513 case 0x20:
514 /* On PCIx2 clocking. */
515 break;
516 }
517
518 tmp = sil_ioread8(dev, scsc_addr);
519
520 sil_iowrite8 (dev, 0x72, base + 0xA1);
521 sil_iowrite16(dev, 0x328A, base + 0xA2);
522 sil_iowrite32(dev, 0x62DD62DD, base + 0xA4);
523 sil_iowrite32(dev, 0x43924392, base + 0xA8);
524 sil_iowrite32(dev, 0x40094009, base + 0xAC);
525 sil_iowrite8 (dev, 0x72, base ? (base + 0xE1) : 0xB1);
526 sil_iowrite16(dev, 0x328A, base ? (base + 0xE2) : 0xB2);
527 sil_iowrite32(dev, 0x62DD62DD, base ? (base + 0xE4) : 0xB4);
528 sil_iowrite32(dev, 0x43924392, base ? (base + 0xE8) : 0xB8);
529 sil_iowrite32(dev, 0x40094009, base ? (base + 0xEC) : 0xBC);
530
531 if (base && pdev_is_sata(dev)) {
532 writel(0xFFFF0000, ioaddr + 0x108);
533 writel(0xFFFF0000, ioaddr + 0x188);
534 writel(0x00680000, ioaddr + 0x148);
535 writel(0x00680000, ioaddr + 0x1C8);
536 }
537
538 /* report the clocking mode of the controller */
539 if (!pdev_is_sata(dev)) {
540 static const char *clk_str[] =
541 { "== 100", "== 133", "== 2X PCI", "DISABLED!" };
542
543 tmp >>= 4;
544 printk(KERN_INFO DRV_NAME " %s: BASE CLOCK %s\n",
545 pci_name(dev), clk_str[tmp & 3]);
546 }
547
548 return 0;
549}
550
551/**
552 * init_mmio_iops_siimage - set up the iops for MMIO
553 * @hwif: interface to set up
554 *
555 * The basic setup here is fairly simple, we can use standard MMIO
556 * operations. However we do have to set the taskfile register offsets
557 * by hand as there isn't a standard defined layout for them this time.
558 *
559 * The hardware supports buffered taskfiles and also some rather nice
560 * extended PRD tables. For better SI3112 support use the libata driver
561 */
562
563static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
564{
565 struct pci_dev *dev = to_pci_dev(hwif->dev);
566 struct ide_host *host = pci_get_drvdata(dev);
567 void *addr = host->host_priv;
568 u8 ch = hwif->channel;
569 struct ide_io_ports *io_ports = &hwif->io_ports;
570 unsigned long base;
571
572 /*
573 * Fill in the basic hwif bits
574 */
575 hwif->host_flags |= IDE_HFLAG_MMIO;
576
577 hwif->hwif_data = addr;
578
579 /*
580 * Now set up the hw. We have to do this ourselves as the
581 * MMIO layout isn't the same as the standard port based I/O.
582 */
583 memset(io_ports, 0, sizeof(*io_ports));
584
585 base = (unsigned long)addr;
586 if (ch)
587 base += 0xC0;
588 else
589 base += 0x80;
590
591 /*
592 * The buffered task file doesn't have status/control, so we
593 * can't currently use it sanely since we want to use LBA48 mode.
594 */
595 io_ports->data_addr = base;
596 io_ports->error_addr = base + 1;
597 io_ports->nsect_addr = base + 2;
598 io_ports->lbal_addr = base + 3;
599 io_ports->lbam_addr = base + 4;
600 io_ports->lbah_addr = base + 5;
601 io_ports->device_addr = base + 6;
602 io_ports->status_addr = base + 7;
603 io_ports->ctl_addr = base + 10;
604
605 if (pdev_is_sata(dev)) {
606 base = (unsigned long)addr;
607 if (ch)
608 base += 0x80;
609 hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104;
610 hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108;
611 hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100;
612 }
613
614 hwif->irq = dev->irq;
615
616 hwif->dma_base = (unsigned long)addr + (ch ? 0x08 : 0x00);
617}
618
619static int is_dev_seagate_sata(ide_drive_t *drive)
620{
621 const char *s = (const char *)&drive->id[ATA_ID_PROD];
622 unsigned len = strnlen(s, ATA_ID_PROD_LEN);
623
624 if ((len > 4) && (!memcmp(s, "ST", 2)))
625 if ((!memcmp(s + len - 2, "AS", 2)) ||
626 (!memcmp(s + len - 3, "ASL", 3))) {
627 printk(KERN_INFO "%s: applying pessimistic Seagate "
628 "errata fix\n", drive->name);
629 return 1;
630 }
631
632 return 0;
633}
634
635/**
636 * sil_quirkproc - post probe fixups
637 * @drive: drive
638 *
639 * Called after drive probe we use this to decide whether the
640 * Seagate fixup must be applied. This used to be in init_iops but
641 * that can occur before we know what drives are present.
642 */
643
644static void sil_quirkproc(ide_drive_t *drive)
645{
646 ide_hwif_t *hwif = drive->hwif;
647
648 /* Try and rise the rqsize */
649 if (!is_sata(hwif) || !is_dev_seagate_sata(drive))
650 hwif->rqsize = 128;
651}
652
653/**
654 * init_iops_siimage - set up iops
655 * @hwif: interface to set up
656 *
657 * Do the basic setup for the SIIMAGE hardware interface
658 * and then do the MMIO setup if we can. This is the first
659 * look in we get for setting up the hwif so that we
660 * can get the iops right before using them.
661 */
662
663static void __devinit init_iops_siimage(ide_hwif_t *hwif)
664{
665 struct pci_dev *dev = to_pci_dev(hwif->dev);
666 struct ide_host *host = pci_get_drvdata(dev);
667
668 hwif->hwif_data = NULL;
669
670 /* Pessimal until we finish probing */
671 hwif->rqsize = 15;
672
673 if (host->host_priv)
674 init_mmio_iops_siimage(hwif);
675}
676
677/**
678 * sil_cable_detect - cable detection
679 * @hwif: interface to check
680 *
681 * Check for the presence of an ATA66 capable cable on the interface.
682 */
683
684static u8 sil_cable_detect(ide_hwif_t *hwif)
685{
686 struct pci_dev *dev = to_pci_dev(hwif->dev);
687 unsigned long addr = siimage_selreg(hwif, 0);
688 u8 ata66 = sil_ioread8(dev, addr);
689
690 return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
691}
692
693static const struct ide_port_ops sil_pata_port_ops = {
694 .set_pio_mode = sil_set_pio_mode,
695 .set_dma_mode = sil_set_dma_mode,
696 .quirkproc = sil_quirkproc,
697 .udma_filter = sil_pata_udma_filter,
698 .cable_detect = sil_cable_detect,
699};
700
701static const struct ide_port_ops sil_sata_port_ops = {
702 .set_pio_mode = sil_set_pio_mode,
703 .set_dma_mode = sil_set_dma_mode,
704 .reset_poll = sil_sata_reset_poll,
705 .pre_reset = sil_sata_pre_reset,
706 .quirkproc = sil_quirkproc,
707 .udma_filter = sil_sata_udma_filter,
708 .cable_detect = sil_cable_detect,
709};
710
711static const struct ide_dma_ops sil_dma_ops = {
712 .dma_host_set = ide_dma_host_set,
713 .dma_setup = ide_dma_setup,
714 .dma_exec_cmd = ide_dma_exec_cmd,
715 .dma_start = ide_dma_start,
716 .dma_end = ide_dma_end,
717 .dma_test_irq = siimage_dma_test_irq,
718 .dma_timeout = ide_dma_timeout,
719 .dma_lost_irq = ide_dma_lost_irq,
720};
721
722#define DECLARE_SII_DEV(p_ops) \
723 { \
724 .name = DRV_NAME, \
725 .init_chipset = init_chipset_siimage, \
726 .init_iops = init_iops_siimage, \
727 .port_ops = p_ops, \
728 .dma_ops = &sil_dma_ops, \
729 .pio_mask = ATA_PIO4, \
730 .mwdma_mask = ATA_MWDMA2, \
731 .udma_mask = ATA_UDMA6, \
732 }
733
734static const struct ide_port_info siimage_chipsets[] __devinitdata = {
735 /* 0: SiI680 */ DECLARE_SII_DEV(&sil_pata_port_ops),
736 /* 1: SiI3112 */ DECLARE_SII_DEV(&sil_sata_port_ops)
737};
738
739/**
740 * siimage_init_one - PCI layer discovery entry
741 * @dev: PCI device
742 * @id: ident table entry
743 *
744 * Called by the PCI code when it finds an SiI680 or SiI3112 controller.
745 * We then use the IDE PCI generic helper to do most of the work.
746 */
747
748static int __devinit siimage_init_one(struct pci_dev *dev,
749 const struct pci_device_id *id)
750{
751 void __iomem *ioaddr = NULL;
752 resource_size_t bar5 = pci_resource_start(dev, 5);
753 unsigned long barsize = pci_resource_len(dev, 5);
754 int rc;
755 struct ide_port_info d;
756 u8 idx = id->driver_data;
757 u8 BA5_EN;
758
759 d = siimage_chipsets[idx];
760
761 if (idx) {
762 static int first = 1;
763
764 if (first) {
765 printk(KERN_INFO DRV_NAME ": For full SATA support you "
766 "should use the libata sata_sil module.\n");
767 first = 0;
768 }
769
770 d.host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
771 }
772
773 rc = pci_enable_device(dev);
774 if (rc)
775 return rc;
776
777 pci_read_config_byte(dev, 0x8A, &BA5_EN);
778 if ((BA5_EN & 0x01) || bar5) {
779 /*
780 * Drop back to PIO if we can't map the MMIO. Some systems
781 * seem to get terminally confused in the PCI spaces.
782 */
783 if (!request_mem_region(bar5, barsize, d.name)) {
784 printk(KERN_WARNING DRV_NAME " %s: MMIO ports not "
785 "available\n", pci_name(dev));
786 } else {
787 ioaddr = ioremap(bar5, barsize);
788 if (ioaddr == NULL)
789 release_mem_region(bar5, barsize);
790 }
791 }
792
793 rc = ide_pci_init_one(dev, &d, ioaddr);
794 if (rc) {
795 if (ioaddr) {
796 iounmap(ioaddr);
797 release_mem_region(bar5, barsize);
798 }
799 pci_disable_device(dev);
800 }
801
802 return rc;
803}
804
805static void __devexit siimage_remove(struct pci_dev *dev)
806{
807 struct ide_host *host = pci_get_drvdata(dev);
808 void __iomem *ioaddr = host->host_priv;
809
810 ide_pci_remove(dev);
811
812 if (ioaddr) {
813 resource_size_t bar5 = pci_resource_start(dev, 5);
814 unsigned long barsize = pci_resource_len(dev, 5);
815
816 iounmap(ioaddr);
817 release_mem_region(bar5, barsize);
818 }
819
820 pci_disable_device(dev);
821}
822
823static const struct pci_device_id siimage_pci_tbl[] = {
824 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), 0 },
825#ifdef CONFIG_BLK_DEV_IDE_SATA
826 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_3112), 1 },
827 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_1210SA), 1 },
828#endif
829 { 0, },
830};
831MODULE_DEVICE_TABLE(pci, siimage_pci_tbl);
832
833static struct pci_driver siimage_pci_driver = {
834 .name = "SiI_IDE",
835 .id_table = siimage_pci_tbl,
836 .probe = siimage_init_one,
837 .remove = __devexit_p(siimage_remove),
838 .suspend = ide_pci_suspend,
839 .resume = ide_pci_resume,
840};
841
842static int __init siimage_ide_init(void)
843{
844 return ide_pci_register_driver(&siimage_pci_driver);
845}
846
847static void __exit siimage_ide_exit(void)
848{
849 pci_unregister_driver(&siimage_pci_driver);
850}
851
852module_init(siimage_ide_init);
853module_exit(siimage_ide_exit);
854
855MODULE_AUTHOR("Andre Hedrick, Alan Cox");
856MODULE_DESCRIPTION("PCI driver module for SiI IDE");
857MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/sis5513.c b/drivers/ide/pci/sis5513.c
deleted file mode 100644
index ad32e18c5ba3..000000000000
--- a/drivers/ide/pci/sis5513.c
+++ /dev/null
@@ -1,641 +0,0 @@
1/*
2 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
3 * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
4 * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz>
5 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
6 *
7 * May be copied or modified under the terms of the GNU General Public License
8 *
9 *
10 * Thanks :
11 *
12 * SiS Taiwan : for direct support and hardware.
13 * Daniela Engert : for initial ATA100 advices and numerous others.
14 * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt :
15 * for checking code correctness, providing patches.
16 *
17 *
18 * Original tests and design on the SiS620 chipset.
19 * ATA100 tests and design on the SiS735 chipset.
20 * ATA16/33 support from specs
21 * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
22 * ATA133 961/962/963 fixes by Vojtech Pavlik <vojtech@suse.cz>
23 *
24 * Documentation:
25 * SiS chipset documentation available under NDA to companies only
26 * (not to individuals).
27 */
28
29/*
30 * The original SiS5513 comes from a SiS5511/55112/5513 chipset. The original
31 * SiS5513 was also used in the SiS5596/5513 chipset. Thus if we see a SiS5511
32 * or SiS5596, we can assume we see the first MWDMA-16 capable SiS5513 chip.
33 *
34 * Later SiS chipsets integrated the 5513 functionality into the NorthBridge,
35 * starting with SiS5571 and up to SiS745. The PCI ID didn't change, though. We
36 * can figure out that we have a more modern and more capable 5513 by looking
37 * for the respective NorthBridge IDs.
38 *
39 * Even later (96x family) SiS chipsets use the MuTIOL link and place the 5513
40 * into the SouthBrige. Here we cannot rely on looking up the NorthBridge PCI
41 * ID, while the now ATA-133 capable 5513 still has the same PCI ID.
42 * Fortunately the 5513 can be 'unmasked' by fiddling with some config space
43 * bits, changing its device id to the true one - 5517 for 961 and 5518 for
44 * 962/963.
45 */
46
47#include <linux/types.h>
48#include <linux/module.h>
49#include <linux/kernel.h>
50#include <linux/pci.h>
51#include <linux/init.h>
52#include <linux/ide.h>
53
54#define DRV_NAME "sis5513"
55
56/* registers layout and init values are chipset family dependant */
57
58#define ATA_16 0x01
59#define ATA_33 0x02
60#define ATA_66 0x03
61#define ATA_100a 0x04 /* SiS730/SiS550 is ATA100 with ATA66 layout */
62#define ATA_100 0x05
63#define ATA_133a 0x06 /* SiS961b with 133 support */
64#define ATA_133 0x07 /* SiS962/963 */
65
66static u8 chipset_family;
67
68/*
69 * Devices supported
70 */
71static const struct {
72 const char *name;
73 u16 host_id;
74 u8 chipset_family;
75 u8 flags;
76} SiSHostChipInfo[] = {
77 { "SiS968", PCI_DEVICE_ID_SI_968, ATA_133 },
78 { "SiS966", PCI_DEVICE_ID_SI_966, ATA_133 },
79 { "SiS965", PCI_DEVICE_ID_SI_965, ATA_133 },
80 { "SiS745", PCI_DEVICE_ID_SI_745, ATA_100 },
81 { "SiS735", PCI_DEVICE_ID_SI_735, ATA_100 },
82 { "SiS733", PCI_DEVICE_ID_SI_733, ATA_100 },
83 { "SiS635", PCI_DEVICE_ID_SI_635, ATA_100 },
84 { "SiS633", PCI_DEVICE_ID_SI_633, ATA_100 },
85
86 { "SiS730", PCI_DEVICE_ID_SI_730, ATA_100a },
87 { "SiS550", PCI_DEVICE_ID_SI_550, ATA_100a },
88
89 { "SiS640", PCI_DEVICE_ID_SI_640, ATA_66 },
90 { "SiS630", PCI_DEVICE_ID_SI_630, ATA_66 },
91 { "SiS620", PCI_DEVICE_ID_SI_620, ATA_66 },
92 { "SiS540", PCI_DEVICE_ID_SI_540, ATA_66 },
93 { "SiS530", PCI_DEVICE_ID_SI_530, ATA_66 },
94
95 { "SiS5600", PCI_DEVICE_ID_SI_5600, ATA_33 },
96 { "SiS5598", PCI_DEVICE_ID_SI_5598, ATA_33 },
97 { "SiS5597", PCI_DEVICE_ID_SI_5597, ATA_33 },
98 { "SiS5591/2", PCI_DEVICE_ID_SI_5591, ATA_33 },
99 { "SiS5582", PCI_DEVICE_ID_SI_5582, ATA_33 },
100 { "SiS5581", PCI_DEVICE_ID_SI_5581, ATA_33 },
101
102 { "SiS5596", PCI_DEVICE_ID_SI_5596, ATA_16 },
103 { "SiS5571", PCI_DEVICE_ID_SI_5571, ATA_16 },
104 { "SiS5517", PCI_DEVICE_ID_SI_5517, ATA_16 },
105 { "SiS551x", PCI_DEVICE_ID_SI_5511, ATA_16 },
106};
107
108/* Cycle time bits and values vary across chip dma capabilities
109 These three arrays hold the register layout and the values to set.
110 Indexed by chipset_family and (dma_mode - XFER_UDMA_0) */
111
112/* {0, ATA_16, ATA_33, ATA_66, ATA_100a, ATA_100, ATA_133} */
113static u8 cycle_time_offset[] = { 0, 0, 5, 4, 4, 0, 0 };
114static u8 cycle_time_range[] = { 0, 0, 2, 3, 3, 4, 4 };
115static u8 cycle_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
116 { 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
117 { 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
118 { 3, 2, 1, 0, 0, 0, 0 }, /* ATA_33 */
119 { 7, 5, 3, 2, 1, 0, 0 }, /* ATA_66 */
120 { 7, 5, 3, 2, 1, 0, 0 }, /* ATA_100a (730 specific),
121 different cycle_time range and offset */
122 { 11, 7, 5, 4, 2, 1, 0 }, /* ATA_100 */
123 { 15, 10, 7, 5, 3, 2, 1 }, /* ATA_133a (earliest 691 southbridges) */
124 { 15, 10, 7, 5, 3, 2, 1 }, /* ATA_133 */
125};
126/* CRC Valid Setup Time vary across IDE clock setting 33/66/100/133
127 See SiS962 data sheet for more detail */
128static u8 cvs_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
129 { 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
130 { 0, 0, 0, 0, 0, 0, 0 }, /* no UDMA */
131 { 2, 1, 1, 0, 0, 0, 0 },
132 { 4, 3, 2, 1, 0, 0, 0 },
133 { 4, 3, 2, 1, 0, 0, 0 },
134 { 6, 4, 3, 1, 1, 1, 0 },
135 { 9, 6, 4, 2, 2, 2, 2 },
136 { 9, 6, 4, 2, 2, 2, 2 },
137};
138/* Initialize time, Active time, Recovery time vary across
139 IDE clock settings. These 3 arrays hold the register value
140 for PIO0/1/2/3/4 and DMA0/1/2 mode in order */
141static u8 ini_time_value[][8] = {
142 { 0, 0, 0, 0, 0, 0, 0, 0 },
143 { 0, 0, 0, 0, 0, 0, 0, 0 },
144 { 2, 1, 0, 0, 0, 1, 0, 0 },
145 { 4, 3, 1, 1, 1, 3, 1, 1 },
146 { 4, 3, 1, 1, 1, 3, 1, 1 },
147 { 6, 4, 2, 2, 2, 4, 2, 2 },
148 { 9, 6, 3, 3, 3, 6, 3, 3 },
149 { 9, 6, 3, 3, 3, 6, 3, 3 },
150};
151static u8 act_time_value[][8] = {
152 { 0, 0, 0, 0, 0, 0, 0, 0 },
153 { 0, 0, 0, 0, 0, 0, 0, 0 },
154 { 9, 9, 9, 2, 2, 7, 2, 2 },
155 { 19, 19, 19, 5, 4, 14, 5, 4 },
156 { 19, 19, 19, 5, 4, 14, 5, 4 },
157 { 28, 28, 28, 7, 6, 21, 7, 6 },
158 { 38, 38, 38, 10, 9, 28, 10, 9 },
159 { 38, 38, 38, 10, 9, 28, 10, 9 },
160};
161static u8 rco_time_value[][8] = {
162 { 0, 0, 0, 0, 0, 0, 0, 0 },
163 { 0, 0, 0, 0, 0, 0, 0, 0 },
164 { 9, 2, 0, 2, 0, 7, 1, 1 },
165 { 19, 5, 1, 5, 2, 16, 3, 2 },
166 { 19, 5, 1, 5, 2, 16, 3, 2 },
167 { 30, 9, 3, 9, 4, 25, 6, 4 },
168 { 40, 12, 4, 12, 5, 34, 12, 5 },
169 { 40, 12, 4, 12, 5, 34, 12, 5 },
170};
171
172/*
173 * Printing configuration
174 */
175/* Used for chipset type printing at boot time */
176static char *chipset_capability[] = {
177 "ATA", "ATA 16",
178 "ATA 33", "ATA 66",
179 "ATA 100 (1st gen)", "ATA 100 (2nd gen)",
180 "ATA 133 (1st gen)", "ATA 133 (2nd gen)"
181};
182
183/*
184 * Configuration functions
185 */
186
187static u8 sis_ata133_get_base(ide_drive_t *drive)
188{
189 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
190 u32 reg54 = 0;
191
192 pci_read_config_dword(dev, 0x54, &reg54);
193
194 return ((reg54 & 0x40000000) ? 0x70 : 0x40) + drive->dn * 4;
195}
196
197static void sis_ata16_program_timings(ide_drive_t *drive, const u8 mode)
198{
199 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
200 u16 t1 = 0;
201 u8 drive_pci = 0x40 + drive->dn * 2;
202
203 const u16 pio_timings[] = { 0x000, 0x607, 0x404, 0x303, 0x301 };
204 const u16 mwdma_timings[] = { 0x008, 0x302, 0x301 };
205
206 pci_read_config_word(dev, drive_pci, &t1);
207
208 /* clear active/recovery timings */
209 t1 &= ~0x070f;
210 if (mode >= XFER_MW_DMA_0) {
211 if (chipset_family > ATA_16)
212 t1 &= ~0x8000; /* disable UDMA */
213 t1 |= mwdma_timings[mode - XFER_MW_DMA_0];
214 } else
215 t1 |= pio_timings[mode - XFER_PIO_0];
216
217 pci_write_config_word(dev, drive_pci, t1);
218}
219
220static void sis_ata100_program_timings(ide_drive_t *drive, const u8 mode)
221{
222 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
223 u8 t1, drive_pci = 0x40 + drive->dn * 2;
224
225 /* timing bits: 7:4 active 3:0 recovery */
226 const u8 pio_timings[] = { 0x00, 0x67, 0x44, 0x33, 0x31 };
227 const u8 mwdma_timings[] = { 0x08, 0x32, 0x31 };
228
229 if (mode >= XFER_MW_DMA_0) {
230 u8 t2 = 0;
231
232 pci_read_config_byte(dev, drive_pci, &t2);
233 t2 &= ~0x80; /* disable UDMA */
234 pci_write_config_byte(dev, drive_pci, t2);
235
236 t1 = mwdma_timings[mode - XFER_MW_DMA_0];
237 } else
238 t1 = pio_timings[mode - XFER_PIO_0];
239
240 pci_write_config_byte(dev, drive_pci + 1, t1);
241}
242
243static void sis_ata133_program_timings(ide_drive_t *drive, const u8 mode)
244{
245 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
246 u32 t1 = 0;
247 u8 drive_pci = sis_ata133_get_base(drive), clk, idx;
248
249 pci_read_config_dword(dev, drive_pci, &t1);
250
251 t1 &= 0xc0c00fff;
252 clk = (t1 & 0x08) ? ATA_133 : ATA_100;
253 if (mode >= XFER_MW_DMA_0) {
254 t1 &= ~0x04; /* disable UDMA */
255 idx = mode - XFER_MW_DMA_0 + 5;
256 } else
257 idx = mode - XFER_PIO_0;
258 t1 |= ini_time_value[clk][idx] << 12;
259 t1 |= act_time_value[clk][idx] << 16;
260 t1 |= rco_time_value[clk][idx] << 24;
261
262 pci_write_config_dword(dev, drive_pci, t1);
263}
264
265static void sis_program_timings(ide_drive_t *drive, const u8 mode)
266{
267 if (chipset_family < ATA_100) /* ATA_16/33/66/100a */
268 sis_ata16_program_timings(drive, mode);
269 else if (chipset_family < ATA_133) /* ATA_100/133a */
270 sis_ata100_program_timings(drive, mode);
271 else /* ATA_133 */
272 sis_ata133_program_timings(drive, mode);
273}
274
275static void config_drive_art_rwp(ide_drive_t *drive)
276{
277 ide_hwif_t *hwif = HWIF(drive);
278 struct pci_dev *dev = to_pci_dev(hwif->dev);
279 u8 reg4bh = 0;
280 u8 rw_prefetch = 0;
281
282 pci_read_config_byte(dev, 0x4b, &reg4bh);
283
284 if (drive->media == ide_disk)
285 rw_prefetch = 0x11 << drive->dn;
286
287 if ((reg4bh & (0x11 << drive->dn)) != rw_prefetch)
288 pci_write_config_byte(dev, 0x4b, reg4bh|rw_prefetch);
289}
290
291static void sis_set_pio_mode(ide_drive_t *drive, const u8 pio)
292{
293 config_drive_art_rwp(drive);
294 sis_program_timings(drive, XFER_PIO_0 + pio);
295}
296
297static void sis_ata133_program_udma_timings(ide_drive_t *drive, const u8 mode)
298{
299 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
300 u32 regdw = 0;
301 u8 drive_pci = sis_ata133_get_base(drive), clk, idx;
302
303 pci_read_config_dword(dev, drive_pci, &regdw);
304
305 regdw |= 0x04;
306 regdw &= 0xfffff00f;
307 /* check if ATA133 enable */
308 clk = (regdw & 0x08) ? ATA_133 : ATA_100;
309 idx = mode - XFER_UDMA_0;
310 regdw |= cycle_time_value[clk][idx] << 4;
311 regdw |= cvs_time_value[clk][idx] << 8;
312
313 pci_write_config_dword(dev, drive_pci, regdw);
314}
315
316static void sis_ata33_program_udma_timings(ide_drive_t *drive, const u8 mode)
317{
318 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
319 u8 drive_pci = 0x40 + drive->dn * 2, reg = 0, i = chipset_family;
320
321 pci_read_config_byte(dev, drive_pci + 1, &reg);
322
323 /* force the UDMA bit on if we want to use UDMA */
324 reg |= 0x80;
325 /* clean reg cycle time bits */
326 reg &= ~((0xff >> (8 - cycle_time_range[i])) << cycle_time_offset[i]);
327 /* set reg cycle time bits */
328 reg |= cycle_time_value[i][mode - XFER_UDMA_0] << cycle_time_offset[i];
329
330 pci_write_config_byte(dev, drive_pci + 1, reg);
331}
332
333static void sis_program_udma_timings(ide_drive_t *drive, const u8 mode)
334{
335 if (chipset_family >= ATA_133) /* ATA_133 */
336 sis_ata133_program_udma_timings(drive, mode);
337 else /* ATA_33/66/100a/100/133a */
338 sis_ata33_program_udma_timings(drive, mode);
339}
340
341static void sis_set_dma_mode(ide_drive_t *drive, const u8 speed)
342{
343 if (speed >= XFER_UDMA_0)
344 sis_program_udma_timings(drive, speed);
345 else
346 sis_program_timings(drive, speed);
347}
348
349static u8 sis_ata133_udma_filter(ide_drive_t *drive)
350{
351 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
352 u32 regdw = 0;
353 u8 drive_pci = sis_ata133_get_base(drive);
354
355 pci_read_config_dword(dev, drive_pci, &regdw);
356
357 /* if ATA133 disable, we should not set speed above UDMA5 */
358 return (regdw & 0x08) ? ATA_UDMA6 : ATA_UDMA5;
359}
360
361static int __devinit sis_find_family(struct pci_dev *dev)
362{
363 struct pci_dev *host;
364 int i = 0;
365
366 chipset_family = 0;
367
368 for (i = 0; i < ARRAY_SIZE(SiSHostChipInfo) && !chipset_family; i++) {
369
370 host = pci_get_device(PCI_VENDOR_ID_SI, SiSHostChipInfo[i].host_id, NULL);
371
372 if (!host)
373 continue;
374
375 chipset_family = SiSHostChipInfo[i].chipset_family;
376
377 /* Special case for SiS630 : 630S/ET is ATA_100a */
378 if (SiSHostChipInfo[i].host_id == PCI_DEVICE_ID_SI_630) {
379 if (host->revision >= 0x30)
380 chipset_family = ATA_100a;
381 }
382 pci_dev_put(host);
383
384 printk(KERN_INFO DRV_NAME " %s: %s %s controller\n",
385 pci_name(dev), SiSHostChipInfo[i].name,
386 chipset_capability[chipset_family]);
387 }
388
389 if (!chipset_family) { /* Belongs to pci-quirks */
390
391 u32 idemisc;
392 u16 trueid;
393
394 /* Disable ID masking and register remapping */
395 pci_read_config_dword(dev, 0x54, &idemisc);
396 pci_write_config_dword(dev, 0x54, (idemisc & 0x7fffffff));
397 pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
398 pci_write_config_dword(dev, 0x54, idemisc);
399
400 if (trueid == 0x5518) {
401 printk(KERN_INFO DRV_NAME " %s: SiS 962/963 MuTIOL IDE UDMA133 controller\n",
402 pci_name(dev));
403 chipset_family = ATA_133;
404
405 /* Check for 5513 compability mapping
406 * We must use this, else the port enabled code will fail,
407 * as it expects the enablebits at 0x4a.
408 */
409 if ((idemisc & 0x40000000) == 0) {
410 pci_write_config_dword(dev, 0x54, idemisc | 0x40000000);
411 printk(KERN_INFO DRV_NAME " %s: Switching to 5513 register mapping\n",
412 pci_name(dev));
413 }
414 }
415 }
416
417 if (!chipset_family) { /* Belongs to pci-quirks */
418
419 struct pci_dev *lpc_bridge;
420 u16 trueid;
421 u8 prefctl;
422 u8 idecfg;
423
424 pci_read_config_byte(dev, 0x4a, &idecfg);
425 pci_write_config_byte(dev, 0x4a, idecfg | 0x10);
426 pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
427 pci_write_config_byte(dev, 0x4a, idecfg);
428
429 if (trueid == 0x5517) { /* SiS 961/961B */
430
431 lpc_bridge = pci_get_slot(dev->bus, 0x10); /* Bus 0, Dev 2, Fn 0 */
432 pci_read_config_byte(dev, 0x49, &prefctl);
433 pci_dev_put(lpc_bridge);
434
435 if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) {
436 printk(KERN_INFO DRV_NAME " %s: SiS 961B MuTIOL IDE UDMA133 controller\n",
437 pci_name(dev));
438 chipset_family = ATA_133a;
439 } else {
440 printk(KERN_INFO DRV_NAME " %s: SiS 961 MuTIOL IDE UDMA100 controller\n",
441 pci_name(dev));
442 chipset_family = ATA_100;
443 }
444 }
445 }
446
447 return chipset_family;
448}
449
450static unsigned int init_chipset_sis5513(struct pci_dev *dev)
451{
452 /* Make general config ops here
453 1/ tell IDE channels to operate in Compatibility mode only
454 2/ tell old chips to allow per drive IDE timings */
455
456 u8 reg;
457 u16 regw;
458
459 switch (chipset_family) {
460 case ATA_133:
461 /* SiS962 operation mode */
462 pci_read_config_word(dev, 0x50, &regw);
463 if (regw & 0x08)
464 pci_write_config_word(dev, 0x50, regw&0xfff7);
465 pci_read_config_word(dev, 0x52, &regw);
466 if (regw & 0x08)
467 pci_write_config_word(dev, 0x52, regw&0xfff7);
468 break;
469 case ATA_133a:
470 case ATA_100:
471 /* Fixup latency */
472 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80);
473 /* Set compatibility bit */
474 pci_read_config_byte(dev, 0x49, &reg);
475 if (!(reg & 0x01))
476 pci_write_config_byte(dev, 0x49, reg|0x01);
477 break;
478 case ATA_100a:
479 case ATA_66:
480 /* Fixup latency */
481 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10);
482
483 /* On ATA_66 chips the bit was elsewhere */
484 pci_read_config_byte(dev, 0x52, &reg);
485 if (!(reg & 0x04))
486 pci_write_config_byte(dev, 0x52, reg|0x04);
487 break;
488 case ATA_33:
489 /* On ATA_33 we didn't have a single bit to set */
490 pci_read_config_byte(dev, 0x09, &reg);
491 if ((reg & 0x0f) != 0x00)
492 pci_write_config_byte(dev, 0x09, reg&0xf0);
493 case ATA_16:
494 /* force per drive recovery and active timings
495 needed on ATA_33 and below chips */
496 pci_read_config_byte(dev, 0x52, &reg);
497 if (!(reg & 0x08))
498 pci_write_config_byte(dev, 0x52, reg|0x08);
499 break;
500 }
501
502 return 0;
503}
504
505struct sis_laptop {
506 u16 device;
507 u16 subvendor;
508 u16 subdevice;
509};
510
511static const struct sis_laptop sis_laptop[] = {
512 /* devid, subvendor, subdev */
513 { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */
514 { 0x5513, 0x1734, 0x105f }, /* FSC Amilo A1630 */
515 { 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */
516 /* end marker */
517 { 0, }
518};
519
520static u8 sis_cable_detect(ide_hwif_t *hwif)
521{
522 struct pci_dev *pdev = to_pci_dev(hwif->dev);
523 const struct sis_laptop *lap = &sis_laptop[0];
524 u8 ata66 = 0;
525
526 while (lap->device) {
527 if (lap->device == pdev->device &&
528 lap->subvendor == pdev->subsystem_vendor &&
529 lap->subdevice == pdev->subsystem_device)
530 return ATA_CBL_PATA40_SHORT;
531 lap++;
532 }
533
534 if (chipset_family >= ATA_133) {
535 u16 regw = 0;
536 u16 reg_addr = hwif->channel ? 0x52: 0x50;
537 pci_read_config_word(pdev, reg_addr, &regw);
538 ata66 = (regw & 0x8000) ? 0 : 1;
539 } else if (chipset_family >= ATA_66) {
540 u8 reg48h = 0;
541 u8 mask = hwif->channel ? 0x20 : 0x10;
542 pci_read_config_byte(pdev, 0x48, &reg48h);
543 ata66 = (reg48h & mask) ? 0 : 1;
544 }
545
546 return ata66 ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
547}
548
549static const struct ide_port_ops sis_port_ops = {
550 .set_pio_mode = sis_set_pio_mode,
551 .set_dma_mode = sis_set_dma_mode,
552 .cable_detect = sis_cable_detect,
553};
554
555static const struct ide_port_ops sis_ata133_port_ops = {
556 .set_pio_mode = sis_set_pio_mode,
557 .set_dma_mode = sis_set_dma_mode,
558 .udma_filter = sis_ata133_udma_filter,
559 .cable_detect = sis_cable_detect,
560};
561
562static const struct ide_port_info sis5513_chipset __devinitdata = {
563 .name = DRV_NAME,
564 .init_chipset = init_chipset_sis5513,
565 .enablebits = { {0x4a, 0x02, 0x02}, {0x4a, 0x04, 0x04} },
566 .host_flags = IDE_HFLAG_LEGACY_IRQS | IDE_HFLAG_NO_AUTODMA,
567 .pio_mask = ATA_PIO4,
568 .mwdma_mask = ATA_MWDMA2,
569};
570
571static int __devinit sis5513_init_one(struct pci_dev *dev, const struct pci_device_id *id)
572{
573 struct ide_port_info d = sis5513_chipset;
574 u8 udma_rates[] = { 0x00, 0x00, 0x07, 0x1f, 0x3f, 0x3f, 0x7f, 0x7f };
575 int rc;
576
577 rc = pci_enable_device(dev);
578 if (rc)
579 return rc;
580
581 if (sis_find_family(dev) == 0)
582 return -ENOTSUPP;
583
584 if (chipset_family >= ATA_133)
585 d.port_ops = &sis_ata133_port_ops;
586 else
587 d.port_ops = &sis_port_ops;
588
589 d.udma_mask = udma_rates[chipset_family];
590
591 return ide_pci_init_one(dev, &d, NULL);
592}
593
594static void __devexit sis5513_remove(struct pci_dev *dev)
595{
596 ide_pci_remove(dev);
597 pci_disable_device(dev);
598}
599
600static const struct pci_device_id sis5513_pci_tbl[] = {
601 { PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_5513), 0 },
602 { PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_5518), 0 },
603 { PCI_VDEVICE(SI, PCI_DEVICE_ID_SI_1180), 0 },
604 { 0, },
605};
606MODULE_DEVICE_TABLE(pci, sis5513_pci_tbl);
607
608static struct pci_driver sis5513_pci_driver = {
609 .name = "SIS_IDE",
610 .id_table = sis5513_pci_tbl,
611 .probe = sis5513_init_one,
612 .remove = __devexit_p(sis5513_remove),
613 .suspend = ide_pci_suspend,
614 .resume = ide_pci_resume,
615};
616
617static int __init sis5513_ide_init(void)
618{
619 return ide_pci_register_driver(&sis5513_pci_driver);
620}
621
622static void __exit sis5513_ide_exit(void)
623{
624 pci_unregister_driver(&sis5513_pci_driver);
625}
626
627module_init(sis5513_ide_init);
628module_exit(sis5513_ide_exit);
629
630MODULE_AUTHOR("Lionel Bouton, L C Chang, Andre Hedrick, Vojtech Pavlik");
631MODULE_DESCRIPTION("PCI driver module for SIS IDE");
632MODULE_LICENSE("GPL");
633
634/*
635 * TODO:
636 * - CLEANUP
637 * - More checks in the config registers (force values instead of
638 * relying on the BIOS setting them correctly).
639 * - Further optimisations ?
640 * . for example ATA66+ regs 0x48 & 0x4A
641 */
diff --git a/drivers/ide/pci/sl82c105.c b/drivers/ide/pci/sl82c105.c
deleted file mode 100644
index 84dc33602ff8..000000000000
--- a/drivers/ide/pci/sl82c105.c
+++ /dev/null
@@ -1,371 +0,0 @@
1/*
2 * SL82C105/Winbond 553 IDE driver
3 *
4 * Maintainer unknown.
5 *
6 * Drive tuning added from Rebel.com's kernel sources
7 * -- Russell King (15/11/98) linux@arm.linux.org.uk
8 *
9 * Merge in Russell's HW workarounds, fix various problems
10 * with the timing registers setup.
11 * -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org
12 *
13 * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
14 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
15 */
16
17#include <linux/types.h>
18#include <linux/module.h>
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/ide.h>
22
23#include <asm/io.h>
24
25#define DRV_NAME "sl82c105"
26
27#undef DEBUG
28
29#ifdef DEBUG
30#define DBG(arg) printk arg
31#else
32#define DBG(fmt,...)
33#endif
34/*
35 * SL82C105 PCI config register 0x40 bits.
36 */
37#define CTRL_IDE_IRQB (1 << 30)
38#define CTRL_IDE_IRQA (1 << 28)
39#define CTRL_LEGIRQ (1 << 11)
40#define CTRL_P1F16 (1 << 5)
41#define CTRL_P1EN (1 << 4)
42#define CTRL_P0F16 (1 << 1)
43#define CTRL_P0EN (1 << 0)
44
45/*
46 * Convert a PIO mode and cycle time to the required on/off times
47 * for the interface. This has protection against runaway timings.
48 */
49static unsigned int get_pio_timings(ide_drive_t *drive, u8 pio)
50{
51 struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
52 unsigned int cmd_on, cmd_off;
53 u8 iordy = 0;
54
55 cmd_on = (t->active + 29) / 30;
56 cmd_off = (ide_pio_cycle_time(drive, pio) - 30 * cmd_on + 29) / 30;
57
58 if (cmd_on == 0)
59 cmd_on = 1;
60
61 if (cmd_off == 0)
62 cmd_off = 1;
63
64 if (pio > 2 || ata_id_has_iordy(drive->id))
65 iordy = 0x40;
66
67 return (cmd_on - 1) << 8 | (cmd_off - 1) | iordy;
68}
69
70/*
71 * Configure the chipset for PIO mode.
72 */
73static void sl82c105_set_pio_mode(ide_drive_t *drive, const u8 pio)
74{
75 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
76 int reg = 0x44 + drive->dn * 4;
77 u16 drv_ctrl;
78
79 drv_ctrl = get_pio_timings(drive, pio);
80
81 /*
82 * Store the PIO timings so that we can restore them
83 * in case DMA will be turned off...
84 */
85 drive->drive_data &= 0xffff0000;
86 drive->drive_data |= drv_ctrl;
87
88 pci_write_config_word(dev, reg, drv_ctrl);
89 pci_read_config_word (dev, reg, &drv_ctrl);
90
91 printk(KERN_DEBUG "%s: selected %s (%dns) (%04X)\n", drive->name,
92 ide_xfer_verbose(pio + XFER_PIO_0),
93 ide_pio_cycle_time(drive, pio), drv_ctrl);
94}
95
96/*
97 * Configure the chipset for DMA mode.
98 */
99static void sl82c105_set_dma_mode(ide_drive_t *drive, const u8 speed)
100{
101 static u16 mwdma_timings[] = {0x0707, 0x0201, 0x0200};
102 u16 drv_ctrl;
103
104 DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n",
105 drive->name, ide_xfer_verbose(speed)));
106
107 drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0];
108
109 /*
110 * Store the DMA timings so that we can actually program
111 * them when DMA will be turned on...
112 */
113 drive->drive_data &= 0x0000ffff;
114 drive->drive_data |= (unsigned long)drv_ctrl << 16;
115}
116
117/*
118 * The SL82C105 holds off all IDE interrupts while in DMA mode until
119 * all DMA activity is completed. Sometimes this causes problems (eg,
120 * when the drive wants to report an error condition).
121 *
122 * 0x7e is a "chip testing" register. Bit 2 resets the DMA controller
123 * state machine. We need to kick this to work around various bugs.
124 */
125static inline void sl82c105_reset_host(struct pci_dev *dev)
126{
127 u16 val;
128
129 pci_read_config_word(dev, 0x7e, &val);
130 pci_write_config_word(dev, 0x7e, val | (1 << 2));
131 pci_write_config_word(dev, 0x7e, val & ~(1 << 2));
132}
133
134/*
135 * If we get an IRQ timeout, it might be that the DMA state machine
136 * got confused. Fix from Todd Inglett. Details from Winbond.
137 *
138 * This function is called when the IDE timer expires, the drive
139 * indicates that it is READY, and we were waiting for DMA to complete.
140 */
141static void sl82c105_dma_lost_irq(ide_drive_t *drive)
142{
143 ide_hwif_t *hwif = HWIF(drive);
144 struct pci_dev *dev = to_pci_dev(hwif->dev);
145 u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
146 u8 dma_cmd;
147
148 printk("sl82c105: lost IRQ, resetting host\n");
149
150 /*
151 * Check the raw interrupt from the drive.
152 */
153 pci_read_config_dword(dev, 0x40, &val);
154 if (val & mask)
155 printk("sl82c105: drive was requesting IRQ, but host lost it\n");
156
157 /*
158 * Was DMA enabled? If so, disable it - we're resetting the
159 * host. The IDE layer will be handling the drive for us.
160 */
161 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
162 if (dma_cmd & 1) {
163 outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
164 printk("sl82c105: DMA was enabled\n");
165 }
166
167 sl82c105_reset_host(dev);
168}
169
170/*
171 * ATAPI devices can cause the SL82C105 DMA state machine to go gaga.
172 * Winbond recommend that the DMA state machine is reset prior to
173 * setting the bus master DMA enable bit.
174 *
175 * The generic IDE core will have disabled the BMEN bit before this
176 * function is called.
177 */
178static void sl82c105_dma_start(ide_drive_t *drive)
179{
180 ide_hwif_t *hwif = HWIF(drive);
181 struct pci_dev *dev = to_pci_dev(hwif->dev);
182 int reg = 0x44 + drive->dn * 4;
183
184 DBG(("%s(drive:%s)\n", __func__, drive->name));
185
186 pci_write_config_word(dev, reg, drive->drive_data >> 16);
187
188 sl82c105_reset_host(dev);
189 ide_dma_start(drive);
190}
191
192static void sl82c105_dma_timeout(ide_drive_t *drive)
193{
194 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
195
196 DBG(("sl82c105_dma_timeout(drive:%s)\n", drive->name));
197
198 sl82c105_reset_host(dev);
199 ide_dma_timeout(drive);
200}
201
202static int sl82c105_dma_end(ide_drive_t *drive)
203{
204 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
205 int reg = 0x44 + drive->dn * 4;
206 int ret;
207
208 DBG(("%s(drive:%s)\n", __func__, drive->name));
209
210 ret = ide_dma_end(drive);
211
212 pci_write_config_word(dev, reg, drive->drive_data);
213
214 return ret;
215}
216
217/*
218 * ATA reset will clear the 16 bits mode in the control
219 * register, we need to reprogram it
220 */
221static void sl82c105_resetproc(ide_drive_t *drive)
222{
223 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
224 u32 val;
225
226 DBG(("sl82c105_resetproc(drive:%s)\n", drive->name));
227
228 pci_read_config_dword(dev, 0x40, &val);
229 val |= (CTRL_P1F16 | CTRL_P0F16);
230 pci_write_config_dword(dev, 0x40, val);
231}
232
233/*
234 * Return the revision of the Winbond bridge
235 * which this function is part of.
236 */
237static u8 sl82c105_bridge_revision(struct pci_dev *dev)
238{
239 struct pci_dev *bridge;
240
241 /*
242 * The bridge should be part of the same device, but function 0.
243 */
244 bridge = pci_get_bus_and_slot(dev->bus->number,
245 PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
246 if (!bridge)
247 return -1;
248
249 /*
250 * Make sure it is a Winbond 553 and is an ISA bridge.
251 */
252 if (bridge->vendor != PCI_VENDOR_ID_WINBOND ||
253 bridge->device != PCI_DEVICE_ID_WINBOND_83C553 ||
254 bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) {
255 pci_dev_put(bridge);
256 return -1;
257 }
258 /*
259 * We need to find function 0's revision, not function 1
260 */
261 pci_dev_put(bridge);
262
263 return bridge->revision;
264}
265
266/*
267 * Enable the PCI device
268 *
269 * --BenH: It's arch fixup code that should enable channels that
270 * have not been enabled by firmware. I decided we can still enable
271 * channel 0 here at least, but channel 1 has to be enabled by
272 * firmware or arch code. We still set both to 16 bits mode.
273 */
274static unsigned int init_chipset_sl82c105(struct pci_dev *dev)
275{
276 u32 val;
277
278 DBG(("init_chipset_sl82c105()\n"));
279
280 pci_read_config_dword(dev, 0x40, &val);
281 val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
282 pci_write_config_dword(dev, 0x40, val);
283
284 return dev->irq;
285}
286
287static const struct ide_port_ops sl82c105_port_ops = {
288 .set_pio_mode = sl82c105_set_pio_mode,
289 .set_dma_mode = sl82c105_set_dma_mode,
290 .resetproc = sl82c105_resetproc,
291};
292
293static const struct ide_dma_ops sl82c105_dma_ops = {
294 .dma_host_set = ide_dma_host_set,
295 .dma_setup = ide_dma_setup,
296 .dma_exec_cmd = ide_dma_exec_cmd,
297 .dma_start = sl82c105_dma_start,
298 .dma_end = sl82c105_dma_end,
299 .dma_test_irq = ide_dma_test_irq,
300 .dma_lost_irq = sl82c105_dma_lost_irq,
301 .dma_timeout = sl82c105_dma_timeout,
302};
303
304static const struct ide_port_info sl82c105_chipset __devinitdata = {
305 .name = DRV_NAME,
306 .init_chipset = init_chipset_sl82c105,
307 .enablebits = {{0x40,0x01,0x01}, {0x40,0x10,0x10}},
308 .port_ops = &sl82c105_port_ops,
309 .dma_ops = &sl82c105_dma_ops,
310 .host_flags = IDE_HFLAG_IO_32BIT |
311 IDE_HFLAG_UNMASK_IRQS |
312/* FIXME: check for Compatibility mode in generic IDE PCI code */
313#if defined(CONFIG_LOPEC) || defined(CONFIG_SANDPOINT)
314 IDE_HFLAG_FORCE_LEGACY_IRQS |
315#endif
316 IDE_HFLAG_SERIALIZE_DMA |
317 IDE_HFLAG_NO_AUTODMA,
318 .pio_mask = ATA_PIO5,
319 .mwdma_mask = ATA_MWDMA2,
320};
321
322static int __devinit sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
323{
324 struct ide_port_info d = sl82c105_chipset;
325 u8 rev = sl82c105_bridge_revision(dev);
326
327 if (rev <= 5) {
328 /*
329 * Never ever EVER under any circumstances enable
330 * DMA when the bridge is this old.
331 */
332 printk(KERN_INFO DRV_NAME ": Winbond W83C553 bridge "
333 "revision %d, BM-DMA disabled\n", rev);
334 d.dma_ops = NULL;
335 d.mwdma_mask = 0;
336 d.host_flags &= ~IDE_HFLAG_SERIALIZE_DMA;
337 }
338
339 return ide_pci_init_one(dev, &d, NULL);
340}
341
342static const struct pci_device_id sl82c105_pci_tbl[] = {
343 { PCI_VDEVICE(WINBOND, PCI_DEVICE_ID_WINBOND_82C105), 0 },
344 { 0, },
345};
346MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl);
347
348static struct pci_driver sl82c105_pci_driver = {
349 .name = "W82C105_IDE",
350 .id_table = sl82c105_pci_tbl,
351 .probe = sl82c105_init_one,
352 .remove = ide_pci_remove,
353 .suspend = ide_pci_suspend,
354 .resume = ide_pci_resume,
355};
356
357static int __init sl82c105_ide_init(void)
358{
359 return ide_pci_register_driver(&sl82c105_pci_driver);
360}
361
362static void __exit sl82c105_ide_exit(void)
363{
364 pci_unregister_driver(&sl82c105_pci_driver);
365}
366
367module_init(sl82c105_ide_init);
368module_exit(sl82c105_ide_exit);
369
370MODULE_DESCRIPTION("PCI driver module for W82C105 IDE");
371MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/slc90e66.c b/drivers/ide/pci/slc90e66.c
deleted file mode 100644
index 0f759e4ed779..000000000000
--- a/drivers/ide/pci/slc90e66.c
+++ /dev/null
@@ -1,181 +0,0 @@
1/*
2 * Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
3 * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
4 *
5 * This is a look-alike variation of the ICH0 PIIX4 Ultra-66,
6 * but this keeps the ISA-Bridge and slots alive.
7 *
8 */
9
10#include <linux/types.h>
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/pci.h>
14#include <linux/ide.h>
15#include <linux/init.h>
16
17#define DRV_NAME "slc90e66"
18
19static DEFINE_SPINLOCK(slc90e66_lock);
20
21static void slc90e66_set_pio_mode(ide_drive_t *drive, const u8 pio)
22{
23 ide_hwif_t *hwif = HWIF(drive);
24 struct pci_dev *dev = to_pci_dev(hwif->dev);
25 int is_slave = drive->dn & 1;
26 int master_port = hwif->channel ? 0x42 : 0x40;
27 int slave_port = 0x44;
28 unsigned long flags;
29 u16 master_data;
30 u8 slave_data;
31 int control = 0;
32 /* ISP RTC */
33 static const u8 timings[][2] = {
34 { 0, 0 },
35 { 0, 0 },
36 { 1, 0 },
37 { 2, 1 },
38 { 2, 3 }, };
39
40 spin_lock_irqsave(&slc90e66_lock, flags);
41 pci_read_config_word(dev, master_port, &master_data);
42
43 if (pio > 1)
44 control |= 1; /* Programmable timing on */
45 if (drive->media == ide_disk)
46 control |= 4; /* Prefetch, post write */
47 if (pio > 2)
48 control |= 2; /* IORDY */
49 if (is_slave) {
50 master_data |= 0x4000;
51 master_data &= ~0x0070;
52 if (pio > 1) {
53 /* Set PPE, IE and TIME */
54 master_data |= control << 4;
55 }
56 pci_read_config_byte(dev, slave_port, &slave_data);
57 slave_data &= hwif->channel ? 0x0f : 0xf0;
58 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) <<
59 (hwif->channel ? 4 : 0);
60 } else {
61 master_data &= ~0x3307;
62 if (pio > 1) {
63 /* enable PPE, IE and TIME */
64 master_data |= control;
65 }
66 master_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
67 }
68 pci_write_config_word(dev, master_port, master_data);
69 if (is_slave)
70 pci_write_config_byte(dev, slave_port, slave_data);
71 spin_unlock_irqrestore(&slc90e66_lock, flags);
72}
73
74static void slc90e66_set_dma_mode(ide_drive_t *drive, const u8 speed)
75{
76 ide_hwif_t *hwif = HWIF(drive);
77 struct pci_dev *dev = to_pci_dev(hwif->dev);
78 u8 maslave = hwif->channel ? 0x42 : 0x40;
79 int sitre = 0, a_speed = 7 << (drive->dn * 4);
80 int u_speed = 0, u_flag = 1 << drive->dn;
81 u16 reg4042, reg44, reg48, reg4a;
82
83 pci_read_config_word(dev, maslave, &reg4042);
84 sitre = (reg4042 & 0x4000) ? 1 : 0;
85 pci_read_config_word(dev, 0x44, &reg44);
86 pci_read_config_word(dev, 0x48, &reg48);
87 pci_read_config_word(dev, 0x4a, &reg4a);
88
89 if (speed >= XFER_UDMA_0) {
90 u_speed = (speed - XFER_UDMA_0) << (drive->dn * 4);
91
92 if (!(reg48 & u_flag))
93 pci_write_config_word(dev, 0x48, reg48|u_flag);
94 /* FIXME: (reg4a & a_speed) ? */
95 if ((reg4a & u_speed) != u_speed) {
96 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
97 pci_read_config_word(dev, 0x4a, &reg4a);
98 pci_write_config_word(dev, 0x4a, reg4a|u_speed);
99 }
100 } else {
101 const u8 mwdma_to_pio[] = { 0, 3, 4 };
102 u8 pio;
103
104 if (reg48 & u_flag)
105 pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
106 if (reg4a & a_speed)
107 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
108
109 if (speed >= XFER_MW_DMA_0)
110 pio = mwdma_to_pio[speed - XFER_MW_DMA_0];
111 else
112 pio = 2; /* only SWDMA2 is allowed */
113
114 slc90e66_set_pio_mode(drive, pio);
115 }
116}
117
118static u8 slc90e66_cable_detect(ide_hwif_t *hwif)
119{
120 struct pci_dev *dev = to_pci_dev(hwif->dev);
121 u8 reg47 = 0, mask = hwif->channel ? 0x01 : 0x02;
122
123 pci_read_config_byte(dev, 0x47, &reg47);
124
125 /* bit[0(1)]: 0:80, 1:40 */
126 return (reg47 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
127}
128
129static const struct ide_port_ops slc90e66_port_ops = {
130 .set_pio_mode = slc90e66_set_pio_mode,
131 .set_dma_mode = slc90e66_set_dma_mode,
132 .cable_detect = slc90e66_cable_detect,
133};
134
135static const struct ide_port_info slc90e66_chipset __devinitdata = {
136 .name = DRV_NAME,
137 .enablebits = { {0x41, 0x80, 0x80}, {0x43, 0x80, 0x80} },
138 .port_ops = &slc90e66_port_ops,
139 .host_flags = IDE_HFLAG_LEGACY_IRQS,
140 .pio_mask = ATA_PIO4,
141 .swdma_mask = ATA_SWDMA2_ONLY,
142 .mwdma_mask = ATA_MWDMA12_ONLY,
143 .udma_mask = ATA_UDMA4,
144};
145
146static int __devinit slc90e66_init_one(struct pci_dev *dev, const struct pci_device_id *id)
147{
148 return ide_pci_init_one(dev, &slc90e66_chipset, NULL);
149}
150
151static const struct pci_device_id slc90e66_pci_tbl[] = {
152 { PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1), 0 },
153 { 0, },
154};
155MODULE_DEVICE_TABLE(pci, slc90e66_pci_tbl);
156
157static struct pci_driver slc90e66_pci_driver = {
158 .name = "SLC90e66_IDE",
159 .id_table = slc90e66_pci_tbl,
160 .probe = slc90e66_init_one,
161 .remove = ide_pci_remove,
162 .suspend = ide_pci_suspend,
163 .resume = ide_pci_resume,
164};
165
166static int __init slc90e66_ide_init(void)
167{
168 return ide_pci_register_driver(&slc90e66_pci_driver);
169}
170
171static void __exit slc90e66_ide_exit(void)
172{
173 pci_unregister_driver(&slc90e66_pci_driver);
174}
175
176module_init(slc90e66_ide_init);
177module_exit(slc90e66_ide_exit);
178
179MODULE_AUTHOR("Andre Hedrick");
180MODULE_DESCRIPTION("PCI driver module for SLC90E66 IDE");
181MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/tc86c001.c b/drivers/ide/pci/tc86c001.c
deleted file mode 100644
index 93e2cce4b296..000000000000
--- a/drivers/ide/pci/tc86c001.c
+++ /dev/null
@@ -1,270 +0,0 @@
1/*
2 * Copyright (C) 2002 Toshiba Corporation
3 * Copyright (C) 2005-2006 MontaVista Software, Inc. <source@mvista.com>
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 */
9
10#include <linux/types.h>
11#include <linux/pci.h>
12#include <linux/ide.h>
13
14#define DRV_NAME "tc86c001"
15
16static void tc86c001_set_mode(ide_drive_t *drive, const u8 speed)
17{
18 ide_hwif_t *hwif = HWIF(drive);
19 unsigned long scr_port = hwif->config_data + (drive->dn ? 0x02 : 0x00);
20 u16 mode, scr = inw(scr_port);
21
22 switch (speed) {
23 case XFER_UDMA_4: mode = 0x00c0; break;
24 case XFER_UDMA_3: mode = 0x00b0; break;
25 case XFER_UDMA_2: mode = 0x00a0; break;
26 case XFER_UDMA_1: mode = 0x0090; break;
27 case XFER_UDMA_0: mode = 0x0080; break;
28 case XFER_MW_DMA_2: mode = 0x0070; break;
29 case XFER_MW_DMA_1: mode = 0x0060; break;
30 case XFER_MW_DMA_0: mode = 0x0050; break;
31 case XFER_PIO_4: mode = 0x0400; break;
32 case XFER_PIO_3: mode = 0x0300; break;
33 case XFER_PIO_2: mode = 0x0200; break;
34 case XFER_PIO_1: mode = 0x0100; break;
35 case XFER_PIO_0:
36 default: mode = 0x0000; break;
37 }
38
39 scr &= (speed < XFER_MW_DMA_0) ? 0xf8ff : 0xff0f;
40 scr |= mode;
41 outw(scr, scr_port);
42}
43
44static void tc86c001_set_pio_mode(ide_drive_t *drive, const u8 pio)
45{
46 tc86c001_set_mode(drive, XFER_PIO_0 + pio);
47}
48
49/*
50 * HACKITY HACK
51 *
52 * This is a workaround for the limitation 5 of the TC86C001 IDE controller:
53 * if a DMA transfer terminates prematurely, the controller leaves the device's
54 * interrupt request (INTRQ) pending and does not generate a PCI interrupt (or
55 * set the interrupt bit in the DMA status register), thus no PCI interrupt
56 * will occur until a DMA transfer has been successfully completed.
57 *
58 * We work around this by initiating dummy, zero-length DMA transfer on
59 * a DMA timeout expiration. I found no better way to do this with the current
60 * IDE core than to temporarily replace a higher level driver's timer expiry
61 * handler with our own backing up to that handler in case our recovery fails.
62 */
63static int tc86c001_timer_expiry(ide_drive_t *drive)
64{
65 ide_hwif_t *hwif = HWIF(drive);
66 ide_expiry_t *expiry = ide_get_hwifdata(hwif);
67 ide_hwgroup_t *hwgroup = HWGROUP(drive);
68 u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
69
70 /* Restore a higher level driver's expiry handler first. */
71 hwgroup->expiry = expiry;
72
73 if ((dma_stat & 5) == 1) { /* DMA active and no interrupt */
74 unsigned long sc_base = hwif->config_data;
75 unsigned long twcr_port = sc_base + (drive->dn ? 0x06 : 0x04);
76 u8 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
77
78 printk(KERN_WARNING "%s: DMA interrupt possibly stuck, "
79 "attempting recovery...\n", drive->name);
80
81 /* Stop DMA */
82 outb(dma_cmd & ~0x01, hwif->dma_base + ATA_DMA_CMD);
83
84 /* Setup the dummy DMA transfer */
85 outw(0, sc_base + 0x0a); /* Sector Count */
86 outw(0, twcr_port); /* Transfer Word Count 1 or 2 */
87
88 /* Start the dummy DMA transfer */
89
90 /* clear R_OR_WCTR for write */
91 outb(0x00, hwif->dma_base + ATA_DMA_CMD);
92 /* set START_STOPBM */
93 outb(0x01, hwif->dma_base + ATA_DMA_CMD);
94
95 /*
96 * If an interrupt was pending, it should come thru shortly.
97 * If not, a higher level driver's expiry handler should
98 * eventually cause some kind of recovery from the DMA stall.
99 */
100 return WAIT_MIN_SLEEP;
101 }
102
103 /* Chain to the restored expiry handler if DMA wasn't active. */
104 if (likely(expiry != NULL))
105 return expiry(drive);
106
107 /* If there was no handler, "emulate" that for ide_timer_expiry()... */
108 return -1;
109}
110
111static void tc86c001_dma_start(ide_drive_t *drive)
112{
113 ide_hwif_t *hwif = HWIF(drive);
114 ide_hwgroup_t *hwgroup = HWGROUP(drive);
115 unsigned long sc_base = hwif->config_data;
116 unsigned long twcr_port = sc_base + (drive->dn ? 0x06 : 0x04);
117 unsigned long nsectors = hwgroup->rq->nr_sectors;
118
119 /*
120 * We have to manually load the sector count and size into
121 * the appropriate system control registers for DMA to work
122 * with LBA48 and ATAPI devices...
123 */
124 outw(nsectors, sc_base + 0x0a); /* Sector Count */
125 outw(SECTOR_SIZE / 2, twcr_port); /* Transfer Word Count 1/2 */
126
127 /* Install our timeout expiry hook, saving the current handler... */
128 ide_set_hwifdata(hwif, hwgroup->expiry);
129 hwgroup->expiry = &tc86c001_timer_expiry;
130
131 ide_dma_start(drive);
132}
133
134static u8 tc86c001_cable_detect(ide_hwif_t *hwif)
135{
136 struct pci_dev *dev = to_pci_dev(hwif->dev);
137 unsigned long sc_base = pci_resource_start(dev, 5);
138 u16 scr1 = inw(sc_base + 0x00);
139
140 /*
141 * System Control 1 Register bit 13 (PDIAGN):
142 * 0=80-pin cable, 1=40-pin cable
143 */
144 return (scr1 & 0x2000) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
145}
146
147static void __devinit init_hwif_tc86c001(ide_hwif_t *hwif)
148{
149 struct pci_dev *dev = to_pci_dev(hwif->dev);
150 unsigned long sc_base = pci_resource_start(dev, 5);
151 u16 scr1 = inw(sc_base + 0x00);
152
153 /* System Control 1 Register bit 15 (Soft Reset) set */
154 outw(scr1 | 0x8000, sc_base + 0x00);
155
156 /* System Control 1 Register bit 14 (FIFO Reset) set */
157 outw(scr1 | 0x4000, sc_base + 0x00);
158
159 /* System Control 1 Register: reset clear */
160 outw(scr1 & ~0xc000, sc_base + 0x00);
161
162 /* Store the system control register base for convenience... */
163 hwif->config_data = sc_base;
164
165 if (!hwif->dma_base)
166 return;
167
168 /*
169 * Sector Count Control Register bits 0 and 1 set:
170 * software sets Sector Count Register for master and slave device
171 */
172 outw(0x0003, sc_base + 0x0c);
173
174 /* Sector Count Register limit */
175 hwif->rqsize = 0xffff;
176}
177
178static const struct ide_port_ops tc86c001_port_ops = {
179 .set_pio_mode = tc86c001_set_pio_mode,
180 .set_dma_mode = tc86c001_set_mode,
181 .cable_detect = tc86c001_cable_detect,
182};
183
184static const struct ide_dma_ops tc86c001_dma_ops = {
185 .dma_host_set = ide_dma_host_set,
186 .dma_setup = ide_dma_setup,
187 .dma_exec_cmd = ide_dma_exec_cmd,
188 .dma_start = tc86c001_dma_start,
189 .dma_end = ide_dma_end,
190 .dma_test_irq = ide_dma_test_irq,
191 .dma_lost_irq = ide_dma_lost_irq,
192 .dma_timeout = ide_dma_timeout,
193};
194
195static const struct ide_port_info tc86c001_chipset __devinitdata = {
196 .name = DRV_NAME,
197 .init_hwif = init_hwif_tc86c001,
198 .port_ops = &tc86c001_port_ops,
199 .dma_ops = &tc86c001_dma_ops,
200 .host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_OFF_BOARD,
201 .pio_mask = ATA_PIO4,
202 .mwdma_mask = ATA_MWDMA2,
203 .udma_mask = ATA_UDMA4,
204};
205
206static int __devinit tc86c001_init_one(struct pci_dev *dev,
207 const struct pci_device_id *id)
208{
209 int rc;
210
211 rc = pci_enable_device(dev);
212 if (rc)
213 goto out;
214
215 rc = pci_request_region(dev, 5, DRV_NAME);
216 if (rc) {
217 printk(KERN_ERR DRV_NAME ": system control regs already in use");
218 goto out_disable;
219 }
220
221 rc = ide_pci_init_one(dev, &tc86c001_chipset, NULL);
222 if (rc)
223 goto out_release;
224
225 goto out;
226
227out_release:
228 pci_release_region(dev, 5);
229out_disable:
230 pci_disable_device(dev);
231out:
232 return rc;
233}
234
235static void __devexit tc86c001_remove(struct pci_dev *dev)
236{
237 ide_pci_remove(dev);
238 pci_release_region(dev, 5);
239 pci_disable_device(dev);
240}
241
242static const struct pci_device_id tc86c001_pci_tbl[] = {
243 { PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE), 0 },
244 { 0, }
245};
246MODULE_DEVICE_TABLE(pci, tc86c001_pci_tbl);
247
248static struct pci_driver tc86c001_pci_driver = {
249 .name = "TC86C001",
250 .id_table = tc86c001_pci_tbl,
251 .probe = tc86c001_init_one,
252 .remove = __devexit_p(tc86c001_remove),
253};
254
255static int __init tc86c001_ide_init(void)
256{
257 return ide_pci_register_driver(&tc86c001_pci_driver);
258}
259
260static void __exit tc86c001_ide_exit(void)
261{
262 pci_unregister_driver(&tc86c001_pci_driver);
263}
264
265module_init(tc86c001_ide_init);
266module_exit(tc86c001_ide_exit);
267
268MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
269MODULE_DESCRIPTION("PCI driver module for TC86C001 IDE");
270MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/triflex.c b/drivers/ide/pci/triflex.c
deleted file mode 100644
index b6ff40336aa9..000000000000
--- a/drivers/ide/pci/triflex.c
+++ /dev/null
@@ -1,142 +0,0 @@
1/*
2 * IDE Chipset driver for the Compaq TriFlex IDE controller.
3 *
4 * Known to work with the Compaq Workstation 5x00 series.
5 *
6 * Copyright (C) 2002 Hewlett-Packard Development Group, L.P.
7 * Author: Torben Mathiasen <torben.mathiasen@hp.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 * Loosely based on the piix & svwks drivers.
23 *
24 * Documentation:
25 * Not publically available.
26 */
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/kernel.h>
31#include <linux/pci.h>
32#include <linux/ide.h>
33#include <linux/init.h>
34
35#define DRV_NAME "triflex"
36
37static void triflex_set_mode(ide_drive_t *drive, const u8 speed)
38{
39 ide_hwif_t *hwif = HWIF(drive);
40 struct pci_dev *dev = to_pci_dev(hwif->dev);
41 u32 triflex_timings = 0;
42 u16 timing = 0;
43 u8 channel_offset = hwif->channel ? 0x74 : 0x70, unit = drive->dn & 1;
44
45 pci_read_config_dword(dev, channel_offset, &triflex_timings);
46
47 switch(speed) {
48 case XFER_MW_DMA_2:
49 timing = 0x0103;
50 break;
51 case XFER_MW_DMA_1:
52 timing = 0x0203;
53 break;
54 case XFER_MW_DMA_0:
55 timing = 0x0808;
56 break;
57 case XFER_SW_DMA_2:
58 case XFER_SW_DMA_1:
59 case XFER_SW_DMA_0:
60 timing = 0x0f0f;
61 break;
62 case XFER_PIO_4:
63 timing = 0x0202;
64 break;
65 case XFER_PIO_3:
66 timing = 0x0204;
67 break;
68 case XFER_PIO_2:
69 timing = 0x0404;
70 break;
71 case XFER_PIO_1:
72 timing = 0x0508;
73 break;
74 case XFER_PIO_0:
75 timing = 0x0808;
76 break;
77 }
78
79 triflex_timings &= ~(0xFFFF << (16 * unit));
80 triflex_timings |= (timing << (16 * unit));
81
82 pci_write_config_dword(dev, channel_offset, triflex_timings);
83}
84
85static void triflex_set_pio_mode(ide_drive_t *drive, const u8 pio)
86{
87 triflex_set_mode(drive, XFER_PIO_0 + pio);
88}
89
90static const struct ide_port_ops triflex_port_ops = {
91 .set_pio_mode = triflex_set_pio_mode,
92 .set_dma_mode = triflex_set_mode,
93};
94
95static const struct ide_port_info triflex_device __devinitdata = {
96 .name = DRV_NAME,
97 .enablebits = {{0x80, 0x01, 0x01}, {0x80, 0x02, 0x02}},
98 .port_ops = &triflex_port_ops,
99 .pio_mask = ATA_PIO4,
100 .swdma_mask = ATA_SWDMA2,
101 .mwdma_mask = ATA_MWDMA2,
102};
103
104static int __devinit triflex_init_one(struct pci_dev *dev,
105 const struct pci_device_id *id)
106{
107 return ide_pci_init_one(dev, &triflex_device, NULL);
108}
109
110static const struct pci_device_id triflex_pci_tbl[] = {
111 { PCI_VDEVICE(COMPAQ, PCI_DEVICE_ID_COMPAQ_TRIFLEX_IDE), 0 },
112 { 0, },
113};
114MODULE_DEVICE_TABLE(pci, triflex_pci_tbl);
115
116static struct pci_driver triflex_pci_driver = {
117 .name = "TRIFLEX_IDE",
118 .id_table = triflex_pci_tbl,
119 .probe = triflex_init_one,
120 .remove = ide_pci_remove,
121 .suspend = ide_pci_suspend,
122 .resume = ide_pci_resume,
123};
124
125static int __init triflex_ide_init(void)
126{
127 return ide_pci_register_driver(&triflex_pci_driver);
128}
129
130static void __exit triflex_ide_exit(void)
131{
132 pci_unregister_driver(&triflex_pci_driver);
133}
134
135module_init(triflex_ide_init);
136module_exit(triflex_ide_exit);
137
138MODULE_AUTHOR("Torben Mathiasen");
139MODULE_DESCRIPTION("PCI driver module for Compaq Triflex IDE");
140MODULE_LICENSE("GPL");
141
142
diff --git a/drivers/ide/pci/trm290.c b/drivers/ide/pci/trm290.c
deleted file mode 100644
index 75ea61526566..000000000000
--- a/drivers/ide/pci/trm290.c
+++ /dev/null
@@ -1,375 +0,0 @@
1/*
2 * Copyright (c) 1997-1998 Mark Lord
3 * Copyright (c) 2007 MontaVista Software, Inc. <source@mvista.com>
4 *
5 * May be copied or modified under the terms of the GNU General Public License
6 *
7 * June 22, 2004 - get rid of check_region
8 * - Jesper Juhl
9 *
10 */
11
12/*
13 * This module provides support for the bus-master IDE DMA function
14 * of the Tekram TRM290 chip, used on a variety of PCI IDE add-on boards,
15 * including a "Precision Instruments" board. The TRM290 pre-dates
16 * the sff-8038 standard (ide-dma.c) by a few months, and differs
17 * significantly enough to warrant separate routines for some functions,
18 * while re-using others from ide-dma.c.
19 *
20 * EXPERIMENTAL! It works for me (a sample of one).
21 *
22 * Works reliably for me in DMA mode (READs only),
23 * DMA WRITEs are disabled by default (see #define below);
24 *
25 * DMA is not enabled automatically for this chipset,
26 * but can be turned on manually (with "hdparm -d1") at run time.
27 *
28 * I need volunteers with "spare" drives for further testing
29 * and development, and maybe to help figure out the peculiarities.
30 * Even knowing the registers (below), some things behave strangely.
31 */
32
33#define TRM290_NO_DMA_WRITES /* DMA writes seem unreliable sometimes */
34
35/*
36 * TRM-290 PCI-IDE2 Bus Master Chip
37 * ================================
38 * The configuration registers are addressed in normal I/O port space
39 * and are used as follows:
40 *
41 * trm290_base depends on jumper settings, and is probed for by ide-dma.c
42 *
43 * trm290_base+2 when WRITTEN: chiptest register (byte, write-only)
44 * bit7 must always be written as "1"
45 * bits6-2 undefined
46 * bit1 1=legacy_compatible_mode, 0=native_pci_mode
47 * bit0 1=test_mode, 0=normal(default)
48 *
49 * trm290_base+2 when READ: status register (byte, read-only)
50 * bits7-2 undefined
51 * bit1 channel0 busmaster interrupt status 0=none, 1=asserted
52 * bit0 channel0 interrupt status 0=none, 1=asserted
53 *
54 * trm290_base+3 Interrupt mask register
55 * bits7-5 undefined
56 * bit4 legacy_header: 1=present, 0=absent
57 * bit3 channel1 busmaster interrupt status 0=none, 1=asserted (read only)
58 * bit2 channel1 interrupt status 0=none, 1=asserted (read only)
59 * bit1 channel1 interrupt mask: 1=masked, 0=unmasked(default)
60 * bit0 channel0 interrupt mask: 1=masked, 0=unmasked(default)
61 *
62 * trm290_base+1 "CPR" Config Pointer Register (byte)
63 * bit7 1=autoincrement CPR bits 2-0 after each access of CDR
64 * bit6 1=min. 1 wait-state posted write cycle (default), 0=0 wait-state
65 * bit5 0=enabled master burst access (default), 1=disable (write only)
66 * bit4 PCI DEVSEL# timing select: 1=medium(default), 0=fast
67 * bit3 0=primary IDE channel, 1=secondary IDE channel
68 * bits2-0 register index for accesses through CDR port
69 *
70 * trm290_base+0 "CDR" Config Data Register (word)
71 * two sets of seven config registers,
72 * selected by CPR bit 3 (channel) and CPR bits 2-0 (index 0 to 6),
73 * each index defined below:
74 *
75 * Index-0 Base address register for command block (word)
76 * defaults: 0x1f0 for primary, 0x170 for secondary
77 *
78 * Index-1 general config register (byte)
79 * bit7 1=DMA enable, 0=DMA disable
80 * bit6 1=activate IDE_RESET, 0=no action (default)
81 * bit5 1=enable IORDY, 0=disable IORDY (default)
82 * bit4 0=16-bit data port(default), 1=8-bit (XT) data port
83 * bit3 interrupt polarity: 1=active_low, 0=active_high(default)
84 * bit2 power-saving-mode(?): 1=enable, 0=disable(default) (write only)
85 * bit1 bus_master_mode(?): 1=enable, 0=disable(default)
86 * bit0 enable_io_ports: 1=enable(default), 0=disable
87 *
88 * Index-2 read-ahead counter preload bits 0-7 (byte, write only)
89 * bits7-0 bits7-0 of readahead count
90 *
91 * Index-3 read-ahead config register (byte, write only)
92 * bit7 1=enable_readahead, 0=disable_readahead(default)
93 * bit6 1=clear_FIFO, 0=no_action
94 * bit5 undefined
95 * bit4 mode4 timing control: 1=enable, 0=disable(default)
96 * bit3 undefined
97 * bit2 undefined
98 * bits1-0 bits9-8 of read-ahead count
99 *
100 * Index-4 base address register for control block (word)
101 * defaults: 0x3f6 for primary, 0x376 for secondary
102 *
103 * Index-5 data port timings (shared by both drives) (byte)
104 * standard PCI "clk" (clock) counts, default value = 0xf5
105 *
106 * bits7-6 setup time: 00=1clk, 01=2clk, 10=3clk, 11=4clk
107 * bits5-3 hold time: 000=1clk, 001=2clk, 010=3clk,
108 * 011=4clk, 100=5clk, 101=6clk,
109 * 110=8clk, 111=12clk
110 * bits2-0 active time: 000=2clk, 001=3clk, 010=4clk,
111 * 011=5clk, 100=6clk, 101=8clk,
112 * 110=12clk, 111=16clk
113 *
114 * Index-6 command/control port timings (shared by both drives) (byte)
115 * same layout as Index-5, default value = 0xde
116 *
117 * Suggested CDR programming for PIO mode0 (600ns):
118 * 0x01f0,0x21,0xff,0x80,0x03f6,0xf5,0xde ; primary
119 * 0x0170,0x21,0xff,0x80,0x0376,0xf5,0xde ; secondary
120 *
121 * Suggested CDR programming for PIO mode3 (180ns):
122 * 0x01f0,0x21,0xff,0x80,0x03f6,0x09,0xde ; primary
123 * 0x0170,0x21,0xff,0x80,0x0376,0x09,0xde ; secondary
124 *
125 * Suggested CDR programming for PIO mode4 (120ns):
126 * 0x01f0,0x21,0xff,0x80,0x03f6,0x00,0xde ; primary
127 * 0x0170,0x21,0xff,0x80,0x0376,0x00,0xde ; secondary
128 *
129 */
130
131#include <linux/types.h>
132#include <linux/module.h>
133#include <linux/kernel.h>
134#include <linux/ioport.h>
135#include <linux/interrupt.h>
136#include <linux/blkdev.h>
137#include <linux/init.h>
138#include <linux/pci.h>
139#include <linux/ide.h>
140
141#include <asm/io.h>
142
143#define DRV_NAME "trm290"
144
145static void trm290_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
146{
147 ide_hwif_t *hwif = HWIF(drive);
148 u16 reg = 0;
149 unsigned long flags;
150
151 /* select PIO or DMA */
152 reg = use_dma ? (0x21 | 0x82) : (0x21 & ~0x82);
153
154 local_irq_save(flags);
155
156 if (reg != hwif->select_data) {
157 hwif->select_data = reg;
158 /* set PIO/DMA */
159 outb(0x51 | (hwif->channel << 3), hwif->config_data + 1);
160 outw(reg & 0xff, hwif->config_data);
161 }
162
163 /* enable IRQ if not probing */
164 if (drive->dev_flags & IDE_DFLAG_PRESENT) {
165 reg = inw(hwif->config_data + 3);
166 reg &= 0x13;
167 reg &= ~(1 << hwif->channel);
168 outw(reg, hwif->config_data + 3);
169 }
170
171 local_irq_restore(flags);
172}
173
174static void trm290_selectproc (ide_drive_t *drive)
175{
176 trm290_prepare_drive(drive, !!(drive->dev_flags & IDE_DFLAG_USING_DMA));
177}
178
179static void trm290_dma_exec_cmd(ide_drive_t *drive, u8 command)
180{
181 ide_execute_command(drive, command, &ide_dma_intr, WAIT_CMD, NULL);
182}
183
184static int trm290_dma_setup(ide_drive_t *drive)
185{
186 ide_hwif_t *hwif = drive->hwif;
187 struct request *rq = hwif->hwgroup->rq;
188 unsigned int count, rw;
189
190 if (rq_data_dir(rq)) {
191#ifdef TRM290_NO_DMA_WRITES
192 /* always use PIO for writes */
193 trm290_prepare_drive(drive, 0); /* select PIO xfer */
194 return 1;
195#endif
196 rw = 1;
197 } else
198 rw = 2;
199
200 if (!(count = ide_build_dmatable(drive, rq))) {
201 /* try PIO instead of DMA */
202 trm290_prepare_drive(drive, 0); /* select PIO xfer */
203 return 1;
204 }
205 /* select DMA xfer */
206 trm290_prepare_drive(drive, 1);
207 outl(hwif->dmatable_dma | rw, hwif->dma_base);
208 drive->waiting_for_dma = 1;
209 /* start DMA */
210 outw(count * 2 - 1, hwif->dma_base + 2);
211 return 0;
212}
213
214static void trm290_dma_start(ide_drive_t *drive)
215{
216}
217
218static int trm290_dma_end(ide_drive_t *drive)
219{
220 u16 status;
221
222 drive->waiting_for_dma = 0;
223 /* purge DMA mappings */
224 ide_destroy_dmatable(drive);
225 status = inw(HWIF(drive)->dma_base + 2);
226 return status != 0x00ff;
227}
228
229static int trm290_dma_test_irq(ide_drive_t *drive)
230{
231 u16 status;
232
233 status = inw(HWIF(drive)->dma_base + 2);
234 return status == 0x00ff;
235}
236
237static void trm290_dma_host_set(ide_drive_t *drive, int on)
238{
239}
240
241static void __devinit init_hwif_trm290(ide_hwif_t *hwif)
242{
243 struct pci_dev *dev = to_pci_dev(hwif->dev);
244 unsigned int cfg_base = pci_resource_start(dev, 4);
245 unsigned long flags;
246 u8 reg = 0;
247
248 if ((dev->class & 5) && cfg_base)
249 printk(KERN_INFO DRV_NAME " %s: chip", pci_name(dev));
250 else {
251 cfg_base = 0x3df0;
252 printk(KERN_INFO DRV_NAME " %s: using default", pci_name(dev));
253 }
254 printk(KERN_CONT " config base at 0x%04x\n", cfg_base);
255 hwif->config_data = cfg_base;
256 hwif->dma_base = (cfg_base + 4) ^ (hwif->channel ? 0x80 : 0);
257
258 printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n",
259 hwif->name, hwif->dma_base, hwif->dma_base + 3);
260
261 if (ide_allocate_dma_engine(hwif))
262 return;
263
264 local_irq_save(flags);
265 /* put config reg into first byte of hwif->select_data */
266 outb(0x51 | (hwif->channel << 3), hwif->config_data + 1);
267 /* select PIO as default */
268 hwif->select_data = 0x21;
269 outb(hwif->select_data, hwif->config_data);
270 /* get IRQ info */
271 reg = inb(hwif->config_data + 3);
272 /* mask IRQs for both ports */
273 reg = (reg & 0x10) | 0x03;
274 outb(reg, hwif->config_data + 3);
275 local_irq_restore(flags);
276
277 if (reg & 0x10)
278 /* legacy mode */
279 hwif->irq = hwif->channel ? 15 : 14;
280 else if (!hwif->irq && hwif->mate && hwif->mate->irq)
281 /* sharing IRQ with mate */
282 hwif->irq = hwif->mate->irq;
283
284#if 1
285 {
286 /*
287 * My trm290-based card doesn't seem to work with all possible values
288 * for the control basereg, so this kludge ensures that we use only
289 * values that are known to work. Ugh. -ml
290 */
291 u16 new, old, compat = hwif->channel ? 0x374 : 0x3f4;
292 static u16 next_offset = 0;
293 u8 old_mask;
294
295 outb(0x54 | (hwif->channel << 3), hwif->config_data + 1);
296 old = inw(hwif->config_data);
297 old &= ~1;
298 old_mask = inb(old + 2);
299 if (old != compat && old_mask == 0xff) {
300 /* leave lower 10 bits untouched */
301 compat += (next_offset += 0x400);
302 hwif->io_ports.ctl_addr = compat + 2;
303 outw(compat | 1, hwif->config_data);
304 new = inw(hwif->config_data);
305 printk(KERN_INFO "%s: control basereg workaround: "
306 "old=0x%04x, new=0x%04x\n",
307 hwif->name, old, new & ~1);
308 }
309 }
310#endif
311}
312
313static const struct ide_port_ops trm290_port_ops = {
314 .selectproc = trm290_selectproc,
315};
316
317static struct ide_dma_ops trm290_dma_ops = {
318 .dma_host_set = trm290_dma_host_set,
319 .dma_setup = trm290_dma_setup,
320 .dma_exec_cmd = trm290_dma_exec_cmd,
321 .dma_start = trm290_dma_start,
322 .dma_end = trm290_dma_end,
323 .dma_test_irq = trm290_dma_test_irq,
324 .dma_lost_irq = ide_dma_lost_irq,
325 .dma_timeout = ide_dma_timeout,
326};
327
328static const struct ide_port_info trm290_chipset __devinitdata = {
329 .name = DRV_NAME,
330 .init_hwif = init_hwif_trm290,
331 .chipset = ide_trm290,
332 .port_ops = &trm290_port_ops,
333 .dma_ops = &trm290_dma_ops,
334 .host_flags = IDE_HFLAG_NO_ATAPI_DMA |
335#if 0 /* play it safe for now */
336 IDE_HFLAG_TRUST_BIOS_FOR_DMA |
337#endif
338 IDE_HFLAG_NO_AUTODMA |
339 IDE_HFLAG_NO_LBA48,
340};
341
342static int __devinit trm290_init_one(struct pci_dev *dev, const struct pci_device_id *id)
343{
344 return ide_pci_init_one(dev, &trm290_chipset, NULL);
345}
346
347static const struct pci_device_id trm290_pci_tbl[] = {
348 { PCI_VDEVICE(TEKRAM, PCI_DEVICE_ID_TEKRAM_DC290), 0 },
349 { 0, },
350};
351MODULE_DEVICE_TABLE(pci, trm290_pci_tbl);
352
353static struct pci_driver trm290_pci_driver = {
354 .name = "TRM290_IDE",
355 .id_table = trm290_pci_tbl,
356 .probe = trm290_init_one,
357 .remove = ide_pci_remove,
358};
359
360static int __init trm290_ide_init(void)
361{
362 return ide_pci_register_driver(&trm290_pci_driver);
363}
364
365static void __exit trm290_ide_exit(void)
366{
367 pci_unregister_driver(&trm290_pci_driver);
368}
369
370module_init(trm290_ide_init);
371module_exit(trm290_ide_exit);
372
373MODULE_AUTHOR("Mark Lord");
374MODULE_DESCRIPTION("PCI driver module for Tekram TRM290 IDE");
375MODULE_LICENSE("GPL");
diff --git a/drivers/ide/pci/via82cxxx.c b/drivers/ide/pci/via82cxxx.c
deleted file mode 100644
index 2a812d3207e9..000000000000
--- a/drivers/ide/pci/via82cxxx.c
+++ /dev/null
@@ -1,514 +0,0 @@
1/*
2 * VIA IDE driver for Linux. Supported southbridges:
3 *
4 * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
5 * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
6 * vt8235, vt8237, vt8237a
7 *
8 * Copyright (c) 2000-2002 Vojtech Pavlik
9 * Copyright (c) 2007 Bartlomiej Zolnierkiewicz
10 *
11 * Based on the work of:
12 * Michel Aubry
13 * Jeff Garzik
14 * Andre Hedrick
15 *
16 * Documentation:
17 * Obsolete device documentation publically available from via.com.tw
18 * Current device documentation available under NDA only
19 */
20
21/*
22 * This program is free software; you can redistribute it and/or modify it
23 * under the terms of the GNU General Public License version 2 as published by
24 * the Free Software Foundation.
25 */
26
27#include <linux/module.h>
28#include <linux/kernel.h>
29#include <linux/pci.h>
30#include <linux/init.h>
31#include <linux/ide.h>
32#include <linux/dmi.h>
33
34#ifdef CONFIG_PPC_CHRP
35#include <asm/processor.h>
36#endif
37
38#define DRV_NAME "via82cxxx"
39
40#define VIA_IDE_ENABLE 0x40
41#define VIA_IDE_CONFIG 0x41
42#define VIA_FIFO_CONFIG 0x43
43#define VIA_MISC_1 0x44
44#define VIA_MISC_2 0x45
45#define VIA_MISC_3 0x46
46#define VIA_DRIVE_TIMING 0x48
47#define VIA_8BIT_TIMING 0x4e
48#define VIA_ADDRESS_SETUP 0x4c
49#define VIA_UDMA_TIMING 0x50
50
51#define VIA_BAD_PREQ 0x01 /* Crashes if PREQ# till DDACK# set */
52#define VIA_BAD_CLK66 0x02 /* 66 MHz clock doesn't work correctly */
53#define VIA_SET_FIFO 0x04 /* Needs to have FIFO split set */
54#define VIA_NO_UNMASK 0x08 /* Doesn't work with IRQ unmasking on */
55#define VIA_BAD_ID 0x10 /* Has wrong vendor ID (0x1107) */
56#define VIA_BAD_AST 0x20 /* Don't touch Address Setup Timing */
57
58/*
59 * VIA SouthBridge chips.
60 */
61
62static struct via_isa_bridge {
63 char *name;
64 u16 id;
65 u8 rev_min;
66 u8 rev_max;
67 u8 udma_mask;
68 u8 flags;
69} via_isa_bridges[] = {
70 { "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
71 { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
72 { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
73 { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
74 { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
75 { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
76 { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
77 { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
78 { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, ATA_UDMA6, VIA_BAD_AST },
79 { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, ATA_UDMA5, },
80 { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, ATA_UDMA5, },
81 { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, ATA_UDMA5, },
82 { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, ATA_UDMA5, },
83 { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, ATA_UDMA4, },
84 { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
85 { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, ATA_UDMA4, },
86 { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, ATA_UDMA2, VIA_BAD_CLK66 },
87 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, ATA_UDMA2, VIA_SET_FIFO },
88 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, ATA_UDMA2, VIA_SET_FIFO | VIA_BAD_PREQ },
89 { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, ATA_UDMA2, VIA_SET_FIFO },
90 { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, ATA_UDMA2, VIA_SET_FIFO },
91 { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, 0x00, VIA_SET_FIFO },
92 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK },
93 { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, 0x00, VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
94 { NULL }
95};
96
97static unsigned int via_clock;
98static char *via_dma[] = { "16", "25", "33", "44", "66", "100", "133" };
99
100struct via82cxxx_dev
101{
102 struct via_isa_bridge *via_config;
103 unsigned int via_80w;
104};
105
106/**
107 * via_set_speed - write timing registers
108 * @dev: PCI device
109 * @dn: device
110 * @timing: IDE timing data to use
111 *
112 * via_set_speed writes timing values to the chipset registers
113 */
114
115static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing)
116{
117 struct pci_dev *dev = to_pci_dev(hwif->dev);
118 struct ide_host *host = pci_get_drvdata(dev);
119 struct via82cxxx_dev *vdev = host->host_priv;
120 u8 t;
121
122 if (~vdev->via_config->flags & VIA_BAD_AST) {
123 pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
124 t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
125 pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t);
126 }
127
128 pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)),
129 ((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1));
130
131 pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn),
132 ((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing->recover, 1, 16) - 1));
133
134 switch (vdev->via_config->udma_mask) {
135 case ATA_UDMA2: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break;
136 case ATA_UDMA4: t = timing->udma ? (0xe8 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x0f; break;
137 case ATA_UDMA5: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break;
138 case ATA_UDMA6: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break;
139 default: return;
140 }
141
142 pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t);
143}
144
145/**
146 * via_set_drive - configure transfer mode
147 * @drive: Drive to set up
148 * @speed: desired speed
149 *
150 * via_set_drive() computes timing values configures the chipset to
151 * a desired transfer mode. It also can be called by upper layers.
152 */
153
154static void via_set_drive(ide_drive_t *drive, const u8 speed)
155{
156 ide_hwif_t *hwif = drive->hwif;
157 ide_drive_t *peer = ide_get_pair_dev(drive);
158 struct pci_dev *dev = to_pci_dev(hwif->dev);
159 struct ide_host *host = pci_get_drvdata(dev);
160 struct via82cxxx_dev *vdev = host->host_priv;
161 struct ide_timing t, p;
162 unsigned int T, UT;
163
164 T = 1000000000 / via_clock;
165
166 switch (vdev->via_config->udma_mask) {
167 case ATA_UDMA2: UT = T; break;
168 case ATA_UDMA4: UT = T/2; break;
169 case ATA_UDMA5: UT = T/3; break;
170 case ATA_UDMA6: UT = T/4; break;
171 default: UT = T;
172 }
173
174 ide_timing_compute(drive, speed, &t, T, UT);
175
176 if (peer) {
177 ide_timing_compute(peer, peer->current_speed, &p, T, UT);
178 ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
179 }
180
181 via_set_speed(HWIF(drive), drive->dn, &t);
182}
183
184/**
185 * via_set_pio_mode - set host controller for PIO mode
186 * @drive: drive
187 * @pio: PIO mode number
188 *
189 * A callback from the upper layers for PIO-only tuning.
190 */
191
192static void via_set_pio_mode(ide_drive_t *drive, const u8 pio)
193{
194 via_set_drive(drive, XFER_PIO_0 + pio);
195}
196
197static struct via_isa_bridge *via_config_find(struct pci_dev **isa)
198{
199 struct via_isa_bridge *via_config;
200
201 for (via_config = via_isa_bridges; via_config->id; via_config++)
202 if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA +
203 !!(via_config->flags & VIA_BAD_ID),
204 via_config->id, NULL))) {
205
206 if ((*isa)->revision >= via_config->rev_min &&
207 (*isa)->revision <= via_config->rev_max)
208 break;
209 pci_dev_put(*isa);
210 }
211
212 return via_config;
213}
214
215/*
216 * Check and handle 80-wire cable presence
217 */
218static void via_cable_detect(struct via82cxxx_dev *vdev, u32 u)
219{
220 int i;
221
222 switch (vdev->via_config->udma_mask) {
223 case ATA_UDMA4:
224 for (i = 24; i >= 0; i -= 8)
225 if (((u >> (i & 16)) & 8) &&
226 ((u >> i) & 0x20) &&
227 (((u >> i) & 7) < 2)) {
228 /*
229 * 2x PCI clock and
230 * UDMA w/ < 3T/cycle
231 */
232 vdev->via_80w |= (1 << (1 - (i >> 4)));
233 }
234 break;
235
236 case ATA_UDMA5:
237 for (i = 24; i >= 0; i -= 8)
238 if (((u >> i) & 0x10) ||
239 (((u >> i) & 0x20) &&
240 (((u >> i) & 7) < 4))) {
241 /* BIOS 80-wire bit or
242 * UDMA w/ < 60ns/cycle
243 */
244 vdev->via_80w |= (1 << (1 - (i >> 4)));
245 }
246 break;
247
248 case ATA_UDMA6:
249 for (i = 24; i >= 0; i -= 8)
250 if (((u >> i) & 0x10) ||
251 (((u >> i) & 0x20) &&
252 (((u >> i) & 7) < 6))) {
253 /* BIOS 80-wire bit or
254 * UDMA w/ < 60ns/cycle
255 */
256 vdev->via_80w |= (1 << (1 - (i >> 4)));
257 }
258 break;
259 }
260}
261
262/**
263 * init_chipset_via82cxxx - initialization handler
264 * @dev: PCI device
265 *
266 * The initialization callback. Here we determine the IDE chip type
267 * and initialize its drive independent registers.
268 */
269
270static unsigned int init_chipset_via82cxxx(struct pci_dev *dev)
271{
272 struct ide_host *host = pci_get_drvdata(dev);
273 struct via82cxxx_dev *vdev = host->host_priv;
274 struct via_isa_bridge *via_config = vdev->via_config;
275 u8 t, v;
276 u32 u;
277
278 /*
279 * Detect cable and configure Clk66
280 */
281 pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
282
283 via_cable_detect(vdev, u);
284
285 if (via_config->udma_mask == ATA_UDMA4) {
286 /* Enable Clk66 */
287 pci_write_config_dword(dev, VIA_UDMA_TIMING, u|0x80008);
288 } else if (via_config->flags & VIA_BAD_CLK66) {
289 /* Would cause trouble on 596a and 686 */
290 pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008);
291 }
292
293 /*
294 * Check whether interfaces are enabled.
295 */
296
297 pci_read_config_byte(dev, VIA_IDE_ENABLE, &v);
298
299 /*
300 * Set up FIFO sizes and thresholds.
301 */
302
303 pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t);
304
305 /* Disable PREQ# till DDACK# */
306 if (via_config->flags & VIA_BAD_PREQ) {
307 /* Would crash on 586b rev 41 */
308 t &= 0x7f;
309 }
310
311 /* Fix FIFO split between channels */
312 if (via_config->flags & VIA_SET_FIFO) {
313 t &= (t & 0x9f);
314 switch (v & 3) {
315 case 2: t |= 0x00; break; /* 16 on primary */
316 case 1: t |= 0x60; break; /* 16 on secondary */
317 case 3: t |= 0x20; break; /* 8 pri 8 sec */
318 }
319 }
320
321 pci_write_config_byte(dev, VIA_FIFO_CONFIG, t);
322
323 return 0;
324}
325
326/*
327 * Cable special cases
328 */
329
330static const struct dmi_system_id cable_dmi_table[] = {
331 {
332 .ident = "Acer Ferrari 3400",
333 .matches = {
334 DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."),
335 DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"),
336 },
337 },
338 { }
339};
340
341static int via_cable_override(struct pci_dev *pdev)
342{
343 /* Systems by DMI */
344 if (dmi_check_system(cable_dmi_table))
345 return 1;
346
347 /* Arima W730-K8/Targa Visionary 811/... */
348 if (pdev->subsystem_vendor == 0x161F &&
349 pdev->subsystem_device == 0x2032)
350 return 1;
351
352 return 0;
353}
354
355static u8 via82cxxx_cable_detect(ide_hwif_t *hwif)
356{
357 struct pci_dev *pdev = to_pci_dev(hwif->dev);
358 struct ide_host *host = pci_get_drvdata(pdev);
359 struct via82cxxx_dev *vdev = host->host_priv;
360
361 if (via_cable_override(pdev))
362 return ATA_CBL_PATA40_SHORT;
363
364 if ((vdev->via_80w >> hwif->channel) & 1)
365 return ATA_CBL_PATA80;
366 else
367 return ATA_CBL_PATA40;
368}
369
370static const struct ide_port_ops via_port_ops = {
371 .set_pio_mode = via_set_pio_mode,
372 .set_dma_mode = via_set_drive,
373 .cable_detect = via82cxxx_cable_detect,
374};
375
376static const struct ide_port_info via82cxxx_chipset __devinitdata = {
377 .name = DRV_NAME,
378 .init_chipset = init_chipset_via82cxxx,
379 .enablebits = { { 0x40, 0x02, 0x02 }, { 0x40, 0x01, 0x01 } },
380 .port_ops = &via_port_ops,
381 .host_flags = IDE_HFLAG_PIO_NO_BLACKLIST |
382 IDE_HFLAG_POST_SET_MODE |
383 IDE_HFLAG_IO_32BIT,
384 .pio_mask = ATA_PIO5,
385 .swdma_mask = ATA_SWDMA2,
386 .mwdma_mask = ATA_MWDMA2,
387};
388
389static int __devinit via_init_one(struct pci_dev *dev, const struct pci_device_id *id)
390{
391 struct pci_dev *isa = NULL;
392 struct via_isa_bridge *via_config;
393 struct via82cxxx_dev *vdev;
394 int rc;
395 u8 idx = id->driver_data;
396 struct ide_port_info d;
397
398 d = via82cxxx_chipset;
399
400 /*
401 * Find the ISA bridge and check we know what it is.
402 */
403 via_config = via_config_find(&isa);
404 if (!via_config->id) {
405 printk(KERN_WARNING DRV_NAME " %s: unknown chipset, skipping\n",
406 pci_name(dev));
407 return -ENODEV;
408 }
409
410 /*
411 * Print the boot message.
412 */
413 printk(KERN_INFO DRV_NAME " %s: VIA %s (rev %02x) IDE %sDMA%s\n",
414 pci_name(dev), via_config->name, isa->revision,
415 via_config->udma_mask ? "U" : "MW",
416 via_dma[via_config->udma_mask ?
417 (fls(via_config->udma_mask) - 1) : 0]);
418
419 pci_dev_put(isa);
420
421 /*
422 * Determine system bus clock.
423 */
424 via_clock = (ide_pci_clk ? ide_pci_clk : 33) * 1000;
425
426 switch (via_clock) {
427 case 33000: via_clock = 33333; break;
428 case 37000: via_clock = 37500; break;
429 case 41000: via_clock = 41666; break;
430 }
431
432 if (via_clock < 20000 || via_clock > 50000) {
433 printk(KERN_WARNING DRV_NAME ": User given PCI clock speed "
434 "impossible (%d), using 33 MHz instead.\n", via_clock);
435 printk(KERN_WARNING DRV_NAME ": Use ide0=ata66 if you want "
436 "to assume 80-wire cable.\n");
437 via_clock = 33333;
438 }
439
440 if (idx == 0)
441 d.host_flags |= IDE_HFLAG_NO_AUTODMA;
442 else
443 d.enablebits[1].reg = d.enablebits[0].reg = 0;
444
445 if ((via_config->flags & VIA_NO_UNMASK) == 0)
446 d.host_flags |= IDE_HFLAG_UNMASK_IRQS;
447
448#ifdef CONFIG_PPC_CHRP
449 if (machine_is(chrp) && _chrp_type == _CHRP_Pegasos)
450 d.host_flags |= IDE_HFLAG_FORCE_LEGACY_IRQS;
451#endif
452
453 d.udma_mask = via_config->udma_mask;
454
455 vdev = kzalloc(sizeof(*vdev), GFP_KERNEL);
456 if (!vdev) {
457 printk(KERN_ERR DRV_NAME " %s: out of memory :(\n",
458 pci_name(dev));
459 return -ENOMEM;
460 }
461
462 vdev->via_config = via_config;
463
464 rc = ide_pci_init_one(dev, &d, vdev);
465 if (rc)
466 kfree(vdev);
467
468 return rc;
469}
470
471static void __devexit via_remove(struct pci_dev *dev)
472{
473 struct ide_host *host = pci_get_drvdata(dev);
474 struct via82cxxx_dev *vdev = host->host_priv;
475
476 ide_pci_remove(dev);
477 kfree(vdev);
478}
479
480static const struct pci_device_id via_pci_tbl[] = {
481 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1), 0 },
482 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1), 0 },
483 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_CX700_IDE), 0 },
484 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410), 1 },
485 { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), 1 },
486 { 0, },
487};
488MODULE_DEVICE_TABLE(pci, via_pci_tbl);
489
490static struct pci_driver via_pci_driver = {
491 .name = "VIA_IDE",
492 .id_table = via_pci_tbl,
493 .probe = via_init_one,
494 .remove = __devexit_p(via_remove),
495 .suspend = ide_pci_suspend,
496 .resume = ide_pci_resume,
497};
498
499static int __init via_ide_init(void)
500{
501 return ide_pci_register_driver(&via_pci_driver);
502}
503
504static void __exit via_ide_exit(void)
505{
506 pci_unregister_driver(&via_pci_driver);
507}
508
509module_init(via_ide_init);
510module_exit(via_ide_exit);
511
512MODULE_AUTHOR("Vojtech Pavlik, Michel Aubry, Jeff Garzik, Andre Hedrick");
513MODULE_DESCRIPTION("PCI driver module for VIA IDE");
514MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 08:43:26 -0500