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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/ide/pci/trm290.c
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/ide/pci/trm290.c')
-rw-r--r--drivers/ide/pci/trm290.c369
1 files changed, 369 insertions, 0 deletions
diff --git a/drivers/ide/pci/trm290.c b/drivers/ide/pci/trm290.c
new file mode 100644
index 000000000000..8b5eea5405ef
--- /dev/null
+++ b/drivers/ide/pci/trm290.c
@@ -0,0 +1,369 @@
1/*
2 * linux/drivers/ide/pci/trm290.c Version 1.02 Mar. 18, 2000
3 *
4 * Copyright (c) 1997-1998 Mark Lord
5 * May be copied or modified under the terms of the GNU General Public License
6 *
7 * June 22, 2004 - get rid of check_region
8 * Jesper Juhl <juhl-lkml@dif.dk>
9 *
10 */
11
12/*
13 * This module provides support for the bus-master IDE DMA function
14 * of the Tekram TRM290 chip, used on a variety of PCI IDE add-on boards,
15 * including a "Precision Instruments" board. The TRM290 pre-dates
16 * the sff-8038 standard (ide-dma.c) by a few months, and differs
17 * significantly enough to warrant separate routines for some functions,
18 * while re-using others from ide-dma.c.
19 *
20 * EXPERIMENTAL! It works for me (a sample of one).
21 *
22 * Works reliably for me in DMA mode (READs only),
23 * DMA WRITEs are disabled by default (see #define below);
24 *
25 * DMA is not enabled automatically for this chipset,
26 * but can be turned on manually (with "hdparm -d1") at run time.
27 *
28 * I need volunteers with "spare" drives for further testing
29 * and development, and maybe to help figure out the peculiarities.
30 * Even knowing the registers (below), some things behave strangely.
31 */
32
33#define TRM290_NO_DMA_WRITES /* DMA writes seem unreliable sometimes */
34
35/*
36 * TRM-290 PCI-IDE2 Bus Master Chip
37 * ================================
38 * The configuration registers are addressed in normal I/O port space
39 * and are used as follows:
40 *
41 * trm290_base depends on jumper settings, and is probed for by ide-dma.c
42 *
43 * trm290_base+2 when WRITTEN: chiptest register (byte, write-only)
44 * bit7 must always be written as "1"
45 * bits6-2 undefined
46 * bit1 1=legacy_compatible_mode, 0=native_pci_mode
47 * bit0 1=test_mode, 0=normal(default)
48 *
49 * trm290_base+2 when READ: status register (byte, read-only)
50 * bits7-2 undefined
51 * bit1 channel0 busmaster interrupt status 0=none, 1=asserted
52 * bit0 channel0 interrupt status 0=none, 1=asserted
53 *
54 * trm290_base+3 Interrupt mask register
55 * bits7-5 undefined
56 * bit4 legacy_header: 1=present, 0=absent
57 * bit3 channel1 busmaster interrupt status 0=none, 1=asserted (read only)
58 * bit2 channel1 interrupt status 0=none, 1=asserted (read only)
59 * bit1 channel1 interrupt mask: 1=masked, 0=unmasked(default)
60 * bit0 channel0 interrupt mask: 1=masked, 0=unmasked(default)
61 *
62 * trm290_base+1 "CPR" Config Pointer Register (byte)
63 * bit7 1=autoincrement CPR bits 2-0 after each access of CDR
64 * bit6 1=min. 1 wait-state posted write cycle (default), 0=0 wait-state
65 * bit5 0=enabled master burst access (default), 1=disable (write only)
66 * bit4 PCI DEVSEL# timing select: 1=medium(default), 0=fast
67 * bit3 0=primary IDE channel, 1=secondary IDE channel
68 * bits2-0 register index for accesses through CDR port
69 *
70 * trm290_base+0 "CDR" Config Data Register (word)
71 * two sets of seven config registers,
72 * selected by CPR bit 3 (channel) and CPR bits 2-0 (index 0 to 6),
73 * each index defined below:
74 *
75 * Index-0 Base address register for command block (word)
76 * defaults: 0x1f0 for primary, 0x170 for secondary
77 *
78 * Index-1 general config register (byte)
79 * bit7 1=DMA enable, 0=DMA disable
80 * bit6 1=activate IDE_RESET, 0=no action (default)
81 * bit5 1=enable IORDY, 0=disable IORDY (default)
82 * bit4 0=16-bit data port(default), 1=8-bit (XT) data port
83 * bit3 interrupt polarity: 1=active_low, 0=active_high(default)
84 * bit2 power-saving-mode(?): 1=enable, 0=disable(default) (write only)
85 * bit1 bus_master_mode(?): 1=enable, 0=disable(default)
86 * bit0 enable_io_ports: 1=enable(default), 0=disable
87 *
88 * Index-2 read-ahead counter preload bits 0-7 (byte, write only)
89 * bits7-0 bits7-0 of readahead count
90 *
91 * Index-3 read-ahead config register (byte, write only)
92 * bit7 1=enable_readahead, 0=disable_readahead(default)
93 * bit6 1=clear_FIFO, 0=no_action
94 * bit5 undefined
95 * bit4 mode4 timing control: 1=enable, 0=disable(default)
96 * bit3 undefined
97 * bit2 undefined
98 * bits1-0 bits9-8 of read-ahead count
99 *
100 * Index-4 base address register for control block (word)
101 * defaults: 0x3f6 for primary, 0x376 for secondary
102 *
103 * Index-5 data port timings (shared by both drives) (byte)
104 * standard PCI "clk" (clock) counts, default value = 0xf5
105 *
106 * bits7-6 setup time: 00=1clk, 01=2clk, 10=3clk, 11=4clk
107 * bits5-3 hold time: 000=1clk, 001=2clk, 010=3clk,
108 * 011=4clk, 100=5clk, 101=6clk,
109 * 110=8clk, 111=12clk
110 * bits2-0 active time: 000=2clk, 001=3clk, 010=4clk,
111 * 011=5clk, 100=6clk, 101=8clk,
112 * 110=12clk, 111=16clk
113 *
114 * Index-6 command/control port timings (shared by both drives) (byte)
115 * same layout as Index-5, default value = 0xde
116 *
117 * Suggested CDR programming for PIO mode0 (600ns):
118 * 0x01f0,0x21,0xff,0x80,0x03f6,0xf5,0xde ; primary
119 * 0x0170,0x21,0xff,0x80,0x0376,0xf5,0xde ; secondary
120 *
121 * Suggested CDR programming for PIO mode3 (180ns):
122 * 0x01f0,0x21,0xff,0x80,0x03f6,0x09,0xde ; primary
123 * 0x0170,0x21,0xff,0x80,0x0376,0x09,0xde ; secondary
124 *
125 * Suggested CDR programming for PIO mode4 (120ns):
126 * 0x01f0,0x21,0xff,0x80,0x03f6,0x00,0xde ; primary
127 * 0x0170,0x21,0xff,0x80,0x0376,0x00,0xde ; secondary
128 *
129 */
130
131#include <linux/config.h>
132#include <linux/types.h>
133#include <linux/module.h>
134#include <linux/kernel.h>
135#include <linux/mm.h>
136#include <linux/ioport.h>
137#include <linux/interrupt.h>
138#include <linux/blkdev.h>
139#include <linux/init.h>
140#include <linux/hdreg.h>
141#include <linux/pci.h>
142#include <linux/delay.h>
143#include <linux/ide.h>
144
145#include <asm/io.h>
146
147static void trm290_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
148{
149 ide_hwif_t *hwif = HWIF(drive);
150 u16 reg = 0;
151 unsigned long flags;
152
153 /* select PIO or DMA */
154 reg = use_dma ? (0x21 | 0x82) : (0x21 & ~0x82);
155
156 local_irq_save(flags);
157
158 if (reg != hwif->select_data) {
159 hwif->select_data = reg;
160 /* set PIO/DMA */
161 hwif->OUTB(0x51|(hwif->channel<<3), hwif->config_data+1);
162 hwif->OUTW(reg & 0xff, hwif->config_data);
163 }
164
165 /* enable IRQ if not probing */
166 if (drive->present) {
167 reg = hwif->INW(hwif->config_data + 3);
168 reg &= 0x13;
169 reg &= ~(1 << hwif->channel);
170 hwif->OUTW(reg, hwif->config_data+3);
171 }
172
173 local_irq_restore(flags);
174}
175
176static void trm290_selectproc (ide_drive_t *drive)
177{
178 trm290_prepare_drive(drive, drive->using_dma);
179}
180
181#ifdef CONFIG_BLK_DEV_IDEDMA
182static void trm290_ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
183{
184 ide_hwif_t *hwif = HWIF(drive);
185
186 if (HWGROUP(drive)->handler != NULL) /* paranoia check */
187 BUG();
188 ide_set_handler(drive, &ide_dma_intr, WAIT_CMD, NULL);
189 /* issue cmd to drive */
190 hwif->OUTB(command, IDE_COMMAND_REG);
191}
192
193static int trm290_ide_dma_setup(ide_drive_t *drive)
194{
195 ide_hwif_t *hwif = drive->hwif;
196 struct request *rq = hwif->hwgroup->rq;
197 unsigned int count, rw;
198
199 if (rq_data_dir(rq)) {
200#ifdef TRM290_NO_DMA_WRITES
201 /* always use PIO for writes */
202 trm290_prepare_drive(drive, 0); /* select PIO xfer */
203 return 1;
204#endif
205 rw = 1;
206 } else
207 rw = 2;
208
209 if (!(count = ide_build_dmatable(drive, rq))) {
210 /* try PIO instead of DMA */
211 trm290_prepare_drive(drive, 0); /* select PIO xfer */
212 return 1;
213 }
214 /* select DMA xfer */
215 trm290_prepare_drive(drive, 1);
216 hwif->OUTL(hwif->dmatable_dma|rw, hwif->dma_command);
217 drive->waiting_for_dma = 1;
218 /* start DMA */
219 hwif->OUTW((count * 2) - 1, hwif->dma_status);
220 return 0;
221}
222
223static void trm290_ide_dma_start(ide_drive_t *drive)
224{
225}
226
227static int trm290_ide_dma_end (ide_drive_t *drive)
228{
229 ide_hwif_t *hwif = HWIF(drive);
230 u16 status = 0;
231
232 drive->waiting_for_dma = 0;
233 /* purge DMA mappings */
234 ide_destroy_dmatable(drive);
235 status = hwif->INW(hwif->dma_status);
236 return (status != 0x00ff);
237}
238
239static int trm290_ide_dma_test_irq (ide_drive_t *drive)
240{
241 ide_hwif_t *hwif = HWIF(drive);
242 u16 status = 0;
243
244 status = hwif->INW(hwif->dma_status);
245 return (status == 0x00ff);
246}
247#endif /* CONFIG_BLK_DEV_IDEDMA */
248
249/*
250 * Invoked from ide-dma.c at boot time.
251 */
252static void __devinit init_hwif_trm290(ide_hwif_t *hwif)
253{
254 unsigned int cfgbase = 0;
255 unsigned long flags;
256 u8 reg = 0;
257 struct pci_dev *dev = hwif->pci_dev;
258
259 hwif->no_lba48 = 1;
260 hwif->chipset = ide_trm290;
261 cfgbase = pci_resource_start(dev, 4);
262 if ((dev->class & 5) && cfgbase) {
263 hwif->config_data = cfgbase;
264 printk(KERN_INFO "TRM290: chip config base at 0x%04lx\n",
265 hwif->config_data);
266 } else {
267 hwif->config_data = 0x3df0;
268 printk(KERN_INFO "TRM290: using default config base at 0x%04lx\n",
269 hwif->config_data);
270 }
271
272 local_irq_save(flags);
273 /* put config reg into first byte of hwif->select_data */
274 hwif->OUTB(0x51|(hwif->channel<<3), hwif->config_data+1);
275 /* select PIO as default */
276 hwif->select_data = 0x21;
277 hwif->OUTB(hwif->select_data, hwif->config_data);
278 /* get IRQ info */
279 reg = hwif->INB(hwif->config_data+3);
280 /* mask IRQs for both ports */
281 reg = (reg & 0x10) | 0x03;
282 hwif->OUTB(reg, hwif->config_data+3);
283 local_irq_restore(flags);
284
285 if ((reg & 0x10))
286 /* legacy mode */
287 hwif->irq = hwif->channel ? 15 : 14;
288 else if (!hwif->irq && hwif->mate && hwif->mate->irq)
289 /* sharing IRQ with mate */
290 hwif->irq = hwif->mate->irq;
291
292 ide_setup_dma(hwif, (hwif->config_data + 4) ^ (hwif->channel ? 0x0080 : 0x0000), 3);
293
294#ifdef CONFIG_BLK_DEV_IDEDMA
295 hwif->dma_setup = &trm290_ide_dma_setup;
296 hwif->dma_exec_cmd = &trm290_ide_dma_exec_cmd;
297 hwif->dma_start = &trm290_ide_dma_start;
298 hwif->ide_dma_end = &trm290_ide_dma_end;
299 hwif->ide_dma_test_irq = &trm290_ide_dma_test_irq;
300#endif /* CONFIG_BLK_DEV_IDEDMA */
301
302 hwif->selectproc = &trm290_selectproc;
303 hwif->autodma = 0; /* play it safe for now */
304 hwif->drives[0].autodma = hwif->autodma;
305 hwif->drives[1].autodma = hwif->autodma;
306#if 1
307 {
308 /*
309 * My trm290-based card doesn't seem to work with all possible values
310 * for the control basereg, so this kludge ensures that we use only
311 * values that are known to work. Ugh. -ml
312 */
313 u16 new, old, compat = hwif->channel ? 0x374 : 0x3f4;
314 static u16 next_offset = 0;
315 u8 old_mask;
316
317 hwif->OUTB(0x54|(hwif->channel<<3), hwif->config_data+1);
318 old = hwif->INW(hwif->config_data);
319 old &= ~1;
320 old_mask = hwif->INB(old+2);
321 if (old != compat && old_mask == 0xff) {
322 /* leave lower 10 bits untouched */
323 compat += (next_offset += 0x400);
324 hwif->io_ports[IDE_CONTROL_OFFSET] = compat + 2;
325 hwif->OUTW(compat|1, hwif->config_data);
326 new = hwif->INW(hwif->config_data);
327 printk(KERN_INFO "%s: control basereg workaround: "
328 "old=0x%04x, new=0x%04x\n",
329 hwif->name, old, new & ~1);
330 }
331 }
332#endif
333}
334
335static ide_pci_device_t trm290_chipset __devinitdata = {
336 .name = "TRM290",
337 .init_hwif = init_hwif_trm290,
338 .channels = 2,
339 .autodma = NOAUTODMA,
340 .bootable = ON_BOARD,
341};
342
343static int __devinit trm290_init_one(struct pci_dev *dev, const struct pci_device_id *id)
344{
345 return ide_setup_pci_device(dev, &trm290_chipset);
346}
347
348static struct pci_device_id trm290_pci_tbl[] = {
349 { PCI_VENDOR_ID_TEKRAM, PCI_DEVICE_ID_TEKRAM_DC290, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
350 { 0, },
351};
352MODULE_DEVICE_TABLE(pci, trm290_pci_tbl);
353
354static struct pci_driver driver = {
355 .name = "TRM290_IDE",
356 .id_table = trm290_pci_tbl,
357 .probe = trm290_init_one,
358};
359
360static int trm290_ide_init(void)
361{
362 return ide_pci_register_driver(&driver);
363}
364
365module_init(trm290_ide_init);
366
367MODULE_AUTHOR("Mark Lord");
368MODULE_DESCRIPTION("PCI driver module for Tekram TRM290 IDE");
369MODULE_LICENSE("GPL");