aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/ide/pci/sl82c105.c
diff options
context:
space:
mode:
authorRussell King <rmk@dyn-67.arm.linux.org.uk>2005-11-12 11:57:29 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2005-11-12 11:57:29 -0500
commit9648f552f9e08548a3979643b99f14c21c7d8f5b (patch)
tree56ad9baae4679e1fecdb9ba5a754a57b79332b56 /drivers/ide/pci/sl82c105.c
parent6460177f42358a744e110cc583adbe8a36f6aa08 (diff)
[ARM] Fix broken sl82c105 DMA prevention
We must _never_ _ever_ on pain of death enable IDE DMA on SL82C105 chipsets where the southbridge revision is <= 5, otherwise data corruption will occur. Strangely this used to work, but something has changed in the upper echelons of the IDE layer to break the hosts decision to deny DMA. Let's make it crystal clear to the IDE layer that we know best. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'drivers/ide/pci/sl82c105.c')
-rw-r--r--drivers/ide/pci/sl82c105.c80
1 files changed, 36 insertions, 44 deletions
diff --git a/drivers/ide/pci/sl82c105.c b/drivers/ide/pci/sl82c105.c
index ea0806c82be0..6466db5f0170 100644
--- a/drivers/ide/pci/sl82c105.c
+++ b/drivers/ide/pci/sl82c105.c
@@ -399,34 +399,6 @@ static unsigned int __devinit init_chipset_sl82c105(struct pci_dev *dev, const c
399 return dev->irq; 399 return dev->irq;
400} 400}
401 401
402static void __devinit init_dma_sl82c105(ide_hwif_t *hwif, unsigned long dma_base)
403{
404 unsigned int rev;
405 u8 dma_state;
406
407 DBG(("init_dma_sl82c105(hwif: ide%d, dma_base: 0x%08x)\n", hwif->index, dma_base));
408
409 hwif->autodma = 0;
410
411 if (!dma_base)
412 return;
413
414 dma_state = hwif->INB(dma_base + 2);
415 rev = sl82c105_bridge_revision(hwif->pci_dev);
416 if (rev <= 5) {
417 printk(" %s: Winbond 553 bridge revision %d, BM-DMA disabled\n",
418 hwif->name, rev);
419 dma_state &= ~0x60;
420 } else {
421 dma_state |= 0x60;
422 if (!noautodma)
423 hwif->autodma = 1;
424 }
425 hwif->OUTB(dma_state, dma_base + 2);
426
427 ide_setup_dma(hwif, dma_base, 8);
428}
429
430/* 402/*
431 * Initialise the chip 403 * Initialise the chip
432 */ 404 */
@@ -434,6 +406,8 @@ static void __devinit init_dma_sl82c105(ide_hwif_t *hwif, unsigned long dma_base
434static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif) 406static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif)
435{ 407{
436 struct pci_dev *dev = hwif->pci_dev; 408 struct pci_dev *dev = hwif->pci_dev;
409 unsigned int rev;
410 u8 dma_state;
437 u32 val; 411 u32 val;
438 412
439 DBG(("init_hwif_sl82c105(hwif: ide%d)\n", hwif->index)); 413 DBG(("init_hwif_sl82c105(hwif: ide%d)\n", hwif->index));
@@ -455,33 +429,51 @@ static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif)
455 pci_read_config_dword(dev, 0x40, &val); 429 pci_read_config_dword(dev, 0x40, &val);
456 *((u32 *)&hwif->hwif_data) = val; 430 *((u32 *)&hwif->hwif_data) = val;
457 431
432 hwif->atapi_dma = 0;
433 hwif->mwdma_mask = 0;
434 hwif->swdma_mask = 0;
435 hwif->autodma = 0;
436
458 if (!hwif->dma_base) 437 if (!hwif->dma_base)
459 return; 438 return;
460 439
461 hwif->atapi_dma = 1; 440 dma_state = hwif->INB(hwif->dma_base + 2) & ~0x60;
462 hwif->mwdma_mask = 0x07; 441 rev = sl82c105_bridge_revision(hwif->pci_dev);
463 hwif->swdma_mask = 0x07; 442 if (rev <= 5) {
464 443 /*
444 * Never ever EVER under any circumstances enable
445 * DMA when the bridge is this old.
446 */
447 printk(" %s: Winbond 553 bridge revision %d, BM-DMA disabled\n",
448 hwif->name, rev);
449 } else {
465#ifdef CONFIG_BLK_DEV_IDEDMA 450#ifdef CONFIG_BLK_DEV_IDEDMA
466 hwif->ide_dma_check = &sl82c105_check_drive; 451 dma_state |= 0x60;
467 hwif->ide_dma_on = &sl82c105_ide_dma_on; 452
468 hwif->ide_dma_off_quietly = &sl82c105_ide_dma_off_quietly; 453 hwif->atapi_dma = 1;
469 hwif->ide_dma_lostirq = &sl82c105_ide_dma_lost_irq; 454 hwif->mwdma_mask = 0x07;
470 hwif->dma_start = &sl82c105_ide_dma_start; 455 hwif->swdma_mask = 0x07;
471 hwif->ide_dma_timeout = &sl82c105_ide_dma_timeout; 456
472 457 hwif->ide_dma_check = &sl82c105_check_drive;
473 if (!noautodma) 458 hwif->ide_dma_on = &sl82c105_ide_dma_on;
474 hwif->autodma = 1; 459 hwif->ide_dma_off_quietly = &sl82c105_ide_dma_off_quietly;
475 hwif->drives[0].autodma = hwif->autodma; 460 hwif->ide_dma_lostirq = &sl82c105_ide_dma_lost_irq;
476 hwif->drives[1].autodma = hwif->autodma; 461 hwif->dma_start = &sl82c105_ide_dma_start;
462 hwif->ide_dma_timeout = &sl82c105_ide_dma_timeout;
463
464 if (!noautodma)
465 hwif->autodma = 1;
466 hwif->drives[0].autodma = hwif->autodma;
467 hwif->drives[1].autodma = hwif->autodma;
477#endif /* CONFIG_BLK_DEV_IDEDMA */ 468#endif /* CONFIG_BLK_DEV_IDEDMA */
469 }
470 hwif->OUTB(dma_state, hwif->dma_base + 2);
478} 471}
479 472
480static ide_pci_device_t sl82c105_chipset __devinitdata = { 473static ide_pci_device_t sl82c105_chipset __devinitdata = {
481 .name = "W82C105", 474 .name = "W82C105",
482 .init_chipset = init_chipset_sl82c105, 475 .init_chipset = init_chipset_sl82c105,
483 .init_hwif = init_hwif_sl82c105, 476 .init_hwif = init_hwif_sl82c105,
484 .init_dma = init_dma_sl82c105,
485 .channels = 2, 477 .channels = 2,
486 .autodma = NOAUTODMA, 478 .autodma = NOAUTODMA,
487 .enablebits = {{0x40,0x01,0x01}, {0x40,0x10,0x10}}, 479 .enablebits = {{0x40,0x01,0x01}, {0x40,0x10,0x10}},