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authorBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2008-04-17 18:46:26 -0400
committerBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2008-04-17 18:46:26 -0400
commit23579a2a170265aacf78069f4817a41c1d6e9323 (patch)
treea20db3f337b64b13e482a2cb2f41e03b13d52e66 /drivers/ide/pci/sgiioc4.c
parent7616c0ad2087c7d244b8985390c63059a6223c45 (diff)
ide: remove IDE_*_REG macros
* Add IDE_{ALTSTATUS,IREASON,BCOUNTL,BCOUNTH}_OFFSET defines. * Remove IDE_*_REG macros - this results in more readable and slightly smaller code. There should be no functional changes caused by this patch. Cc: Borislav Petkov <petkovbb@gmail.com> Acked-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Diffstat (limited to 'drivers/ide/pci/sgiioc4.c')
-rw-r--r--drivers/ide/pci/sgiioc4.c19
1 files changed, 9 insertions, 10 deletions
diff --git a/drivers/ide/pci/sgiioc4.c b/drivers/ide/pci/sgiioc4.c
index 9046a69117ff..9d1a3038af9b 100644
--- a/drivers/ide/pci/sgiioc4.c
+++ b/drivers/ide/pci/sgiioc4.c
@@ -112,10 +112,9 @@ static void
112sgiioc4_maskproc(ide_drive_t * drive, int mask) 112sgiioc4_maskproc(ide_drive_t * drive, int mask)
113{ 113{
114 writeb(mask ? (drive->ctl | 2) : (drive->ctl & ~2), 114 writeb(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
115 (void __iomem *)IDE_CONTROL_REG); 115 (void __iomem *)drive->hwif->io_ports[IDE_CONTROL_OFFSET]);
116} 116}
117 117
118
119static int 118static int
120sgiioc4_checkirq(ide_hwif_t * hwif) 119sgiioc4_checkirq(ide_hwif_t * hwif)
121{ 120{
@@ -142,18 +141,18 @@ sgiioc4_clearirq(ide_drive_t * drive)
142 intr_reg = readl((void __iomem *)other_ir); 141 intr_reg = readl((void __iomem *)other_ir);
143 if (intr_reg & 0x03) { /* Valid IOC4-IDE interrupt */ 142 if (intr_reg & 0x03) { /* Valid IOC4-IDE interrupt */
144 /* 143 /*
145 * Using sgiioc4_INB to read the IDE_STATUS_REG has a side effect 144 * Using sgiioc4_INB to read the Status register has a side
146 * of clearing the interrupt. The first read should clear it 145 * effect of clearing the interrupt. The first read should
147 * if it is set. The second read should return a "clear" status 146 * clear it if it is set. The second read should return
148 * if it got cleared. If not, then spin for a bit trying to 147 * a "clear" status if it got cleared. If not, then spin
149 * clear it. 148 * for a bit trying to clear it.
150 */ 149 */
151 u8 stat = sgiioc4_INB(IDE_STATUS_REG); 150 u8 stat = sgiioc4_INB(hwif->io_ports[IDE_STATUS_OFFSET]);
152 int count = 0; 151 int count = 0;
153 stat = sgiioc4_INB(IDE_STATUS_REG); 152 stat = sgiioc4_INB(hwif->io_ports[IDE_STATUS_OFFSET]);
154 while ((stat & 0x80) && (count++ < 100)) { 153 while ((stat & 0x80) && (count++ < 100)) {
155 udelay(1); 154 udelay(1);
156 stat = sgiioc4_INB(IDE_STATUS_REG); 155 stat = sgiioc4_INB(hwif->io_ports[IDE_STATUS_OFFSET]);
157 } 156 }
158 157
159 if (intr_reg & 0x02) { 158 if (intr_reg & 0x02) {