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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/ide/pci/pdc202xx_old.c
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/ide/pci/pdc202xx_old.c')
-rw-r--r--drivers/ide/pci/pdc202xx_old.c892
1 files changed, 892 insertions, 0 deletions
diff --git a/drivers/ide/pci/pdc202xx_old.c b/drivers/ide/pci/pdc202xx_old.c
new file mode 100644
index 000000000000..ad9d95817f95
--- /dev/null
+++ b/drivers/ide/pci/pdc202xx_old.c
@@ -0,0 +1,892 @@
1/*
2 * linux/drivers/ide/pci/pdc202xx_old.c Version 0.36 Sept 11, 2002
3 *
4 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
5 *
6 * Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
7 * compiled into the kernel if you have more than one card installed.
8 * Note that BIOS v1.29 is reported to fix the problem. Since this is
9 * safe chipset tuning, including this support is harmless
10 *
11 * Promise Ultra66 cards with BIOS v1.11 this
12 * compiled into the kernel if you have more than one card installed.
13 *
14 * Promise Ultra100 cards.
15 *
16 * The latest chipset code will support the following ::
17 * Three Ultra33 controllers and 12 drives.
18 * 8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
19 * The 8/4 ratio is a BIOS code limit by promise.
20 *
21 * UNLESS you enable "CONFIG_PDC202XX_BURST"
22 *
23 */
24
25/*
26 * Portions Copyright (C) 1999 Promise Technology, Inc.
27 * Author: Frank Tiernan (frankt@promise.com)
28 * Released under terms of General Public License
29 */
30
31#include <linux/config.h>
32#include <linux/types.h>
33#include <linux/module.h>
34#include <linux/kernel.h>
35#include <linux/delay.h>
36#include <linux/timer.h>
37#include <linux/mm.h>
38#include <linux/ioport.h>
39#include <linux/blkdev.h>
40#include <linux/hdreg.h>
41#include <linux/interrupt.h>
42#include <linux/pci.h>
43#include <linux/init.h>
44#include <linux/ide.h>
45
46#include <asm/io.h>
47#include <asm/irq.h>
48
49#define PDC202_DEBUG_CABLE 0
50#define PDC202XX_DEBUG_DRIVE_INFO 0
51
52static const char *pdc_quirk_drives[] = {
53 "QUANTUM FIREBALLlct08 08",
54 "QUANTUM FIREBALLP KA6.4",
55 "QUANTUM FIREBALLP KA9.1",
56 "QUANTUM FIREBALLP LM20.4",
57 "QUANTUM FIREBALLP KX13.6",
58 "QUANTUM FIREBALLP KX20.5",
59 "QUANTUM FIREBALLP KX27.3",
60 "QUANTUM FIREBALLP LM20.5",
61 NULL
62};
63
64/* A Register */
65#define SYNC_ERRDY_EN 0xC0
66
67#define SYNC_IN 0x80 /* control bit, different for master vs. slave drives */
68#define ERRDY_EN 0x40 /* control bit, different for master vs. slave drives */
69#define IORDY_EN 0x20 /* PIO: IOREADY */
70#define PREFETCH_EN 0x10 /* PIO: PREFETCH */
71
72#define PA3 0x08 /* PIO"A" timing */
73#define PA2 0x04 /* PIO"A" timing */
74#define PA1 0x02 /* PIO"A" timing */
75#define PA0 0x01 /* PIO"A" timing */
76
77/* B Register */
78
79#define MB2 0x80 /* DMA"B" timing */
80#define MB1 0x40 /* DMA"B" timing */
81#define MB0 0x20 /* DMA"B" timing */
82
83#define PB4 0x10 /* PIO_FORCE 1:0 */
84
85#define PB3 0x08 /* PIO"B" timing */ /* PIO flow Control mode */
86#define PB2 0x04 /* PIO"B" timing */ /* PIO 4 */
87#define PB1 0x02 /* PIO"B" timing */ /* PIO 3 half */
88#define PB0 0x01 /* PIO"B" timing */ /* PIO 3 other half */
89
90/* C Register */
91#define IORDYp_NO_SPEED 0x4F
92#define SPEED_DIS 0x0F
93
94#define DMARQp 0x80
95#define IORDYp 0x40
96#define DMAR_EN 0x20
97#define DMAW_EN 0x10
98
99#define MC3 0x08 /* DMA"C" timing */
100#define MC2 0x04 /* DMA"C" timing */
101#define MC1 0x02 /* DMA"C" timing */
102#define MC0 0x01 /* DMA"C" timing */
103
104#if 0
105 unsigned long bibma = pci_resource_start(dev, 4);
106 u8 hi = 0, lo = 0;
107
108 u8 sc1c = inb_p((u16)bibma + 0x1c);
109 u8 sc1e = inb_p((u16)bibma + 0x1e);
110 u8 sc1f = inb_p((u16)bibma + 0x1f);
111
112 p += sprintf(p, "Host Mode : %s\n",
113 (sc1f & 0x08) ? "Tri-Stated" : "Normal");
114 p += sprintf(p, "Bus Clocking : %s\n",
115 ((sc1f & 0xC0) == 0xC0) ? "100 External" :
116 ((sc1f & 0x80) == 0x80) ? "66 External" :
117 ((sc1f & 0x40) == 0x40) ? "33 External" : "33 PCI Internal");
118 p += sprintf(p, "IO pad select : %s mA\n",
119 ((sc1c & 0x03) == 0x03) ? "10" :
120 ((sc1c & 0x02) == 0x02) ? "8" :
121 ((sc1c & 0x01) == 0x01) ? "6" :
122 ((sc1c & 0x00) == 0x00) ? "4" : "??");
123 hi = sc1e >> 4;
124 lo = sc1e & 0xf;
125 p += sprintf(p, "Status Polling Period : %d\n", hi);
126 p += sprintf(p, "Interrupt Check Status Polling Delay : %d\n", lo);
127#endif
128
129static u8 pdc202xx_ratemask (ide_drive_t *drive)
130{
131 u8 mode;
132
133 switch(HWIF(drive)->pci_dev->device) {
134 case PCI_DEVICE_ID_PROMISE_20267:
135 case PCI_DEVICE_ID_PROMISE_20265:
136 mode = 3;
137 break;
138 case PCI_DEVICE_ID_PROMISE_20263:
139 case PCI_DEVICE_ID_PROMISE_20262:
140 mode = 2;
141 break;
142 case PCI_DEVICE_ID_PROMISE_20246:
143 return 1;
144 default:
145 return 0;
146 }
147 if (!eighty_ninty_three(drive))
148 mode = min(mode, (u8)1);
149 return mode;
150}
151
152static int check_in_drive_lists (ide_drive_t *drive, const char **list)
153{
154 struct hd_driveid *id = drive->id;
155
156 if (pdc_quirk_drives == list) {
157 while (*list) {
158 if (strstr(id->model, *list++)) {
159 return 2;
160 }
161 }
162 } else {
163 while (*list) {
164 if (!strcmp(*list++,id->model)) {
165 return 1;
166 }
167 }
168 }
169 return 0;
170}
171
172static int pdc202xx_tune_chipset (ide_drive_t *drive, u8 xferspeed)
173{
174 ide_hwif_t *hwif = HWIF(drive);
175 struct pci_dev *dev = hwif->pci_dev;
176 u8 drive_pci = 0x60 + (drive->dn << 2);
177 u8 speed = ide_rate_filter(pdc202xx_ratemask(drive), xferspeed);
178
179 u32 drive_conf;
180 u8 AP, BP, CP, DP;
181 u8 TA = 0, TB = 0, TC = 0;
182
183 if ((drive->media != ide_disk) && (speed < XFER_SW_DMA_0))
184 return -1;
185
186 pci_read_config_dword(dev, drive_pci, &drive_conf);
187 pci_read_config_byte(dev, (drive_pci), &AP);
188 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
189 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
190 pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
191
192 if (speed < XFER_SW_DMA_0) {
193 if ((AP & 0x0F) || (BP & 0x07)) {
194 /* clear PIO modes of lower 8421 bits of A Register */
195 pci_write_config_byte(dev, (drive_pci), AP &~0x0F);
196 pci_read_config_byte(dev, (drive_pci), &AP);
197
198 /* clear PIO modes of lower 421 bits of B Register */
199 pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0x07);
200 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
201
202 pci_read_config_byte(dev, (drive_pci), &AP);
203 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
204 }
205 } else {
206 if ((BP & 0xF0) && (CP & 0x0F)) {
207 /* clear DMA modes of upper 842 bits of B Register */
208 /* clear PIO forced mode upper 1 bit of B Register */
209 pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0xF0);
210 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
211
212 /* clear DMA modes of lower 8421 bits of C Register */
213 pci_write_config_byte(dev, (drive_pci)|0x02, CP &~0x0F);
214 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
215 }
216 }
217
218 pci_read_config_byte(dev, (drive_pci), &AP);
219 pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
220 pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
221
222 switch(speed) {
223 case XFER_UDMA_6: speed = XFER_UDMA_5;
224 case XFER_UDMA_5:
225 case XFER_UDMA_4: TB = 0x20; TC = 0x01; break;
226 case XFER_UDMA_2: TB = 0x20; TC = 0x01; break;
227 case XFER_UDMA_3:
228 case XFER_UDMA_1: TB = 0x40; TC = 0x02; break;
229 case XFER_UDMA_0:
230 case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
231 case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
232 case XFER_MW_DMA_0:
233 case XFER_SW_DMA_2: TB = 0x60; TC = 0x05; break;
234 case XFER_SW_DMA_1: TB = 0x80; TC = 0x06; break;
235 case XFER_SW_DMA_0: TB = 0xC0; TC = 0x0B; break;
236 case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
237 case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
238 case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
239 case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
240 case XFER_PIO_0:
241 default: TA = 0x09; TB = 0x13; break;
242 }
243
244 if (speed < XFER_SW_DMA_0) {
245 pci_write_config_byte(dev, (drive_pci), AP|TA);
246 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
247 } else {
248 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
249 pci_write_config_byte(dev, (drive_pci)|0x02, CP|TC);
250 }
251
252#if PDC202XX_DEBUG_DRIVE_INFO
253 printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
254 drive->name, ide_xfer_verbose(speed),
255 drive->dn, drive_conf);
256 pci_read_config_dword(dev, drive_pci, &drive_conf);
257 printk("0x%08x\n", drive_conf);
258#endif /* PDC202XX_DEBUG_DRIVE_INFO */
259
260 return (ide_config_drive_speed(drive, speed));
261}
262
263
264/* 0 1 2 3 4 5 6 7 8
265 * 960, 480, 390, 300, 240, 180, 120, 90, 60
266 * 180, 150, 120, 90, 60
267 * DMA_Speed
268 * 180, 120, 90, 90, 90, 60, 30
269 * 11, 5, 4, 3, 2, 1, 0
270 */
271static void config_chipset_for_pio (ide_drive_t *drive, u8 pio)
272{
273 u8 speed = 0;
274
275 if (pio == 5) pio = 4;
276 speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, pio, NULL);
277
278 pdc202xx_tune_chipset(drive, speed);
279}
280
281static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
282{
283 u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);
284 pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
285 return (CIS & mask) ? 1 : 0;
286}
287
288/*
289 * Set the control register to use the 66MHz system
290 * clock for UDMA 3/4/5 mode operation when necessary.
291 *
292 * It may also be possible to leave the 66MHz clock on
293 * and readjust the timing parameters.
294 */
295static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
296{
297 unsigned long clock_reg = hwif->dma_master + 0x11;
298 u8 clock = hwif->INB(clock_reg);
299
300 hwif->OUTB(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
301}
302
303static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
304{
305 unsigned long clock_reg = hwif->dma_master + 0x11;
306 u8 clock = hwif->INB(clock_reg);
307
308 hwif->OUTB(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
309}
310
311static int config_chipset_for_dma (ide_drive_t *drive)
312{
313 struct hd_driveid *id = drive->id;
314 ide_hwif_t *hwif = HWIF(drive);
315 struct pci_dev *dev = hwif->pci_dev;
316 u32 drive_conf = 0;
317 u8 drive_pci = 0x60 + (drive->dn << 2);
318 u8 test1 = 0, test2 = 0, speed = -1;
319 u8 AP = 0, cable = 0;
320
321 u8 ultra_66 = ((id->dma_ultra & 0x0010) ||
322 (id->dma_ultra & 0x0008)) ? 1 : 0;
323
324 if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
325 cable = pdc202xx_old_cable_detect(hwif);
326 else
327 ultra_66 = 0;
328
329 if (ultra_66 && cable) {
330 printk(KERN_WARNING "Warning: %s channel requires an 80-pin cable for operation.\n", hwif->channel ? "Secondary":"Primary");
331 printk(KERN_WARNING "%s reduced to Ultra33 mode.\n", drive->name);
332 }
333
334 if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
335 pdc_old_disable_66MHz_clock(drive->hwif);
336
337 drive_pci = 0x60 + (drive->dn << 2);
338 pci_read_config_dword(dev, drive_pci, &drive_conf);
339 if ((drive_conf != 0x004ff304) && (drive_conf != 0x004ff3c4))
340 goto chipset_is_set;
341
342 pci_read_config_byte(dev, drive_pci, &test1);
343 if (!(test1 & SYNC_ERRDY_EN)) {
344 if (drive->select.b.unit & 0x01) {
345 pci_read_config_byte(dev, drive_pci - 4, &test2);
346 if ((test2 & SYNC_ERRDY_EN) &&
347 !(test1 & SYNC_ERRDY_EN)) {
348 pci_write_config_byte(dev, drive_pci,
349 test1|SYNC_ERRDY_EN);
350 }
351 } else {
352 pci_write_config_byte(dev, drive_pci,
353 test1|SYNC_ERRDY_EN);
354 }
355 }
356
357chipset_is_set:
358
359 if (drive->media == ide_disk) {
360 pci_read_config_byte(dev, (drive_pci), &AP);
361 if (id->capability & 4) /* IORDY_EN */
362 pci_write_config_byte(dev, (drive_pci), AP|IORDY_EN);
363 pci_read_config_byte(dev, (drive_pci), &AP);
364 if (drive->media == ide_disk) /* PREFETCH_EN */
365 pci_write_config_byte(dev, (drive_pci), AP|PREFETCH_EN);
366 }
367
368 speed = ide_dma_speed(drive, pdc202xx_ratemask(drive));
369
370 if (!(speed)) {
371 /* restore original pci-config space */
372 pci_write_config_dword(dev, drive_pci, drive_conf);
373 hwif->tuneproc(drive, 5);
374 return 0;
375 }
376
377 (void) hwif->speedproc(drive, speed);
378 return ide_dma_enable(drive);
379}
380
381static int pdc202xx_config_drive_xfer_rate (ide_drive_t *drive)
382{
383 ide_hwif_t *hwif = HWIF(drive);
384 struct hd_driveid *id = drive->id;
385
386 drive->init_speed = 0;
387
388 if (id && (id->capability & 1) && drive->autodma) {
389
390 if (ide_use_dma(drive)) {
391 if (config_chipset_for_dma(drive))
392 return hwif->ide_dma_on(drive);
393 }
394
395 goto fast_ata_pio;
396
397 } else if ((id->capability & 8) || (id->field_valid & 2)) {
398fast_ata_pio:
399 hwif->tuneproc(drive, 5);
400 return hwif->ide_dma_off_quietly(drive);
401 }
402 /* IORDY not supported */
403 return 0;
404}
405
406static int pdc202xx_quirkproc (ide_drive_t *drive)
407{
408 return ((int) check_in_drive_lists(drive, pdc_quirk_drives));
409}
410
411static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
412{
413 if (drive->current_speed > XFER_UDMA_2)
414 pdc_old_enable_66MHz_clock(drive->hwif);
415 if (drive->addressing == 1) {
416 struct request *rq = HWGROUP(drive)->rq;
417 ide_hwif_t *hwif = HWIF(drive);
418// struct pci_dev *dev = hwif->pci_dev;
419// unsgned long high_16 = pci_resource_start(dev, 4);
420 unsigned long high_16 = hwif->dma_master;
421 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
422 u32 word_count = 0;
423 u8 clock = hwif->INB(high_16 + 0x11);
424
425 hwif->OUTB(clock|(hwif->channel ? 0x08 : 0x02), high_16+0x11);
426 word_count = (rq->nr_sectors << 8);
427 word_count = (rq_data_dir(rq) == READ) ?
428 word_count | 0x05000000 :
429 word_count | 0x06000000;
430 hwif->OUTL(word_count, atapi_reg);
431 }
432 ide_dma_start(drive);
433}
434
435static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
436{
437 if (drive->addressing == 1) {
438 ide_hwif_t *hwif = HWIF(drive);
439// unsigned long high_16 = pci_resource_start(hwif->pci_dev, 4);
440 unsigned long high_16 = hwif->dma_master;
441 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
442 u8 clock = 0;
443
444 hwif->OUTL(0, atapi_reg); /* zero out extra */
445 clock = hwif->INB(high_16 + 0x11);
446 hwif->OUTB(clock & ~(hwif->channel ? 0x08:0x02), high_16+0x11);
447 }
448 if (drive->current_speed > XFER_UDMA_2)
449 pdc_old_disable_66MHz_clock(drive->hwif);
450 return __ide_dma_end(drive);
451}
452
453static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
454{
455 ide_hwif_t *hwif = HWIF(drive);
456// struct pci_dev *dev = hwif->pci_dev;
457// unsigned long high_16 = pci_resource_start(dev, 4);
458 unsigned long high_16 = hwif->dma_master;
459 u8 dma_stat = hwif->INB(hwif->dma_status);
460 u8 sc1d = hwif->INB((high_16 + 0x001d));
461
462 if (hwif->channel) {
463 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
464 if ((sc1d & 0x50) == 0x50)
465 goto somebody_else;
466 else if ((sc1d & 0x40) == 0x40)
467 return (dma_stat & 4) == 4;
468 } else {
469 /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
470 if ((sc1d & 0x05) == 0x05)
471 goto somebody_else;
472 else if ((sc1d & 0x04) == 0x04)
473 return (dma_stat & 4) == 4;
474 }
475somebody_else:
476 return (dma_stat & 4) == 4; /* return 1 if INTR asserted */
477}
478
479static int pdc202xx_ide_dma_lostirq(ide_drive_t *drive)
480{
481 if (HWIF(drive)->resetproc != NULL)
482 HWIF(drive)->resetproc(drive);
483 return __ide_dma_lostirq(drive);
484}
485
486static int pdc202xx_ide_dma_timeout(ide_drive_t *drive)
487{
488 if (HWIF(drive)->resetproc != NULL)
489 HWIF(drive)->resetproc(drive);
490 return __ide_dma_timeout(drive);
491}
492
493static void pdc202xx_reset_host (ide_hwif_t *hwif)
494{
495#ifdef CONFIG_BLK_DEV_IDEDMA
496// unsigned long high_16 = hwif->dma_base - (8*(hwif->channel));
497 unsigned long high_16 = hwif->dma_master;
498#else /* !CONFIG_BLK_DEV_IDEDMA */
499 unsigned long high_16 = pci_resource_start(hwif->pci_dev, 4);
500#endif /* CONFIG_BLK_DEV_IDEDMA */
501 u8 udma_speed_flag = hwif->INB(high_16|0x001f);
502
503 hwif->OUTB((udma_speed_flag | 0x10), (high_16|0x001f));
504 mdelay(100);
505 hwif->OUTB((udma_speed_flag & ~0x10), (high_16|0x001f));
506 mdelay(2000); /* 2 seconds ?! */
507
508 printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
509 hwif->channel ? "Secondary" : "Primary");
510}
511
512static void pdc202xx_reset (ide_drive_t *drive)
513{
514 ide_hwif_t *hwif = HWIF(drive);
515 ide_hwif_t *mate = hwif->mate;
516
517 pdc202xx_reset_host(hwif);
518 pdc202xx_reset_host(mate);
519#if 0
520 /*
521 * FIXME: Have to kick all the drives again :-/
522 * What a pain in the ACE!
523 */
524 if (hwif->present) {
525 u16 hunit = 0;
526 for (hunit = 0; hunit < MAX_DRIVES; ++hunit) {
527 ide_drive_t *hdrive = &hwif->drives[hunit];
528 if (hdrive->present) {
529 if (hwif->ide_dma_check)
530 hwif->ide_dma_check(hdrive);
531 else
532 hwif->tuneproc(hdrive, 5);
533 }
534 }
535 }
536 if (mate->present) {
537 u16 munit = 0;
538 for (munit = 0; munit < MAX_DRIVES; ++munit) {
539 ide_drive_t *mdrive = &mate->drives[munit];
540 if (mdrive->present) {
541 if (mate->ide_dma_check)
542 mate->ide_dma_check(mdrive);
543 else
544 mate->tuneproc(mdrive, 5);
545 }
546 }
547 }
548#else
549 hwif->tuneproc(drive, 5);
550#endif
551}
552
553/*
554 * Since SUN Cobalt is attempting to do this operation, I should disclose
555 * this has been a long time ago Thu Jul 27 16:40:57 2000 was the patch date
556 * HOTSWAP ATA Infrastructure.
557 */
558static int pdc202xx_tristate (ide_drive_t * drive, int state)
559{
560 ide_hwif_t *hwif = HWIF(drive);
561// unsigned long high_16 = hwif->dma_base - (8*(hwif->channel));
562 unsigned long high_16 = hwif->dma_master;
563 u8 sc1f = hwif->INB(high_16|0x001f);
564
565 if (!hwif)
566 return -EINVAL;
567
568// hwif->bus_state = state;
569
570 if (state) {
571 hwif->OUTB(sc1f | 0x08, (high_16|0x001f));
572 } else {
573 hwif->OUTB(sc1f & ~0x08, (high_16|0x001f));
574 }
575 return 0;
576}
577
578static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev, const char *name)
579{
580 if (dev->resource[PCI_ROM_RESOURCE].start) {
581 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
582 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
583 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n",
584 name, dev->resource[PCI_ROM_RESOURCE].start);
585 }
586
587 /*
588 * software reset - this is required because the bios
589 * will set UDMA timing on if the hdd supports it. The
590 * user may want to turn udma off. A bug in the pdc20262
591 * is that it cannot handle a downgrade in timing from
592 * UDMA to DMA. Disk accesses after issuing a set
593 * feature command will result in errors. A software
594 * reset leaves the timing registers intact,
595 * but resets the drives.
596 */
597#if 0
598 if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
599 (dev->device == PCI_DEVICE_ID_PROMISE_20265) ||
600 (dev->device == PCI_DEVICE_ID_PROMISE_20263) ||
601 (dev->device == PCI_DEVICE_ID_PROMISE_20262)) {
602 unsigned long high_16 = pci_resource_start(dev, 4);
603 byte udma_speed_flag = inb(high_16 + 0x001f);
604 outb(udma_speed_flag | 0x10, high_16 + 0x001f);
605 mdelay(100);
606 outb(udma_speed_flag & ~0x10, high_16 + 0x001f);
607 mdelay(2000); /* 2 seconds ?! */
608 }
609
610#endif
611 return dev->irq;
612}
613
614static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
615{
616 struct pci_dev *dev = hwif->pci_dev;
617
618 /* PDC20265 has problems with large LBA48 requests */
619 if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
620 (dev->device == PCI_DEVICE_ID_PROMISE_20265))
621 hwif->rqsize = 256;
622
623 hwif->autodma = 0;
624 hwif->tuneproc = &config_chipset_for_pio;
625 hwif->quirkproc = &pdc202xx_quirkproc;
626
627 if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
628 hwif->busproc = &pdc202xx_tristate;
629 hwif->resetproc = &pdc202xx_reset;
630 }
631
632 hwif->speedproc = &pdc202xx_tune_chipset;
633
634 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
635
636 hwif->ultra_mask = 0x3f;
637 hwif->mwdma_mask = 0x07;
638 hwif->swdma_mask = 0x07;
639
640 hwif->ide_dma_check = &pdc202xx_config_drive_xfer_rate;
641 hwif->ide_dma_lostirq = &pdc202xx_ide_dma_lostirq;
642 hwif->ide_dma_timeout = &pdc202xx_ide_dma_timeout;
643
644 if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
645 if (!(hwif->udma_four))
646 hwif->udma_four = (pdc202xx_old_cable_detect(hwif)) ? 0 : 1;
647 hwif->dma_start = &pdc202xx_old_ide_dma_start;
648 hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
649 }
650 hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
651
652 if (!noautodma)
653 hwif->autodma = 1;
654 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
655#if PDC202_DEBUG_CABLE
656 printk(KERN_DEBUG "%s: %s-pin cable\n",
657 hwif->name, hwif->udma_four ? "80" : "40");
658#endif /* PDC202_DEBUG_CABLE */
659}
660
661static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
662{
663 u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
664
665 if (hwif->channel) {
666 ide_setup_dma(hwif, dmabase, 8);
667 return;
668 }
669
670 udma_speed_flag = hwif->INB((dmabase|0x1f));
671 primary_mode = hwif->INB((dmabase|0x1a));
672 secondary_mode = hwif->INB((dmabase|0x1b));
673 printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
674 "Primary %s Mode " \
675 "Secondary %s Mode.\n", hwif->cds->name,
676 (udma_speed_flag & 1) ? "EN" : "DIS",
677 (primary_mode & 1) ? "MASTER" : "PCI",
678 (secondary_mode & 1) ? "MASTER" : "PCI" );
679
680#ifdef CONFIG_PDC202XX_BURST
681 if (!(udma_speed_flag & 1)) {
682 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
683 hwif->cds->name, udma_speed_flag,
684 (udma_speed_flag|1));
685 hwif->OUTB(udma_speed_flag|1,(dmabase|0x1f));
686 printk("%sACTIVE\n",
687 (hwif->INB(dmabase|0x1f)&1) ? "":"IN");
688 }
689#endif /* CONFIG_PDC202XX_BURST */
690#ifdef CONFIG_PDC202XX_MASTER
691 if (!(primary_mode & 1)) {
692 printk(KERN_INFO "%s: FORCING PRIMARY MODE BIT "
693 "0x%02x -> 0x%02x ", hwif->cds->name,
694 primary_mode, (primary_mode|1));
695 hwif->OUTB(primary_mode|1, (dmabase|0x1a));
696 printk("%s\n",
697 (hwif->INB((dmabase|0x1a)) & 1) ? "MASTER" : "PCI");
698 }
699
700 if (!(secondary_mode & 1)) {
701 printk(KERN_INFO "%s: FORCING SECONDARY MODE BIT "
702 "0x%02x -> 0x%02x ", hwif->cds->name,
703 secondary_mode, (secondary_mode|1));
704 hwif->OUTB(secondary_mode|1, (dmabase|0x1b));
705 printk("%s\n",
706 (hwif->INB((dmabase|0x1b)) & 1) ? "MASTER" : "PCI");
707 }
708#endif /* CONFIG_PDC202XX_MASTER */
709
710 ide_setup_dma(hwif, dmabase, 8);
711}
712
713static int __devinit init_setup_pdc202ata4(struct pci_dev *dev,
714 ide_pci_device_t *d)
715{
716 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
717 u8 irq = 0, irq2 = 0;
718 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
719 /* 0xbc */
720 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
721 if (irq != irq2) {
722 pci_write_config_byte(dev,
723 (PCI_INTERRUPT_LINE)|0x80, irq); /* 0xbc */
724 printk(KERN_INFO "%s: pci-config space interrupt "
725 "mirror fixed.\n", d->name);
726 }
727 }
728
729#if 0
730 if (dev->device == PCI_DEVICE_ID_PROMISE_20262)
731 if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) ||
732 (tmp & e->mask) != e->val))
733
734 if (d->enablebits[0].reg != d->enablebits[1].reg) {
735 d->enablebits[0].reg = d->enablebits[1].reg;
736 d->enablebits[0].mask = d->enablebits[1].mask;
737 d->enablebits[0].val = d->enablebits[1].val;
738 }
739#endif
740
741 return ide_setup_pci_device(dev, d);
742}
743
744static int __devinit init_setup_pdc20265(struct pci_dev *dev,
745 ide_pci_device_t *d)
746{
747 if ((dev->bus->self) &&
748 (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
749 ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
750 (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
751 printk(KERN_INFO "ide: Skipping Promise PDC20265 "
752 "attached to I2O RAID controller.\n");
753 return -ENODEV;
754 }
755
756#if 0
757 {
758 u8 pri = 0, sec = 0;
759
760 if (e->reg && (pci_read_config_byte(dev, e->reg, &tmp) ||
761 (tmp & e->mask) != e->val))
762
763 if (d->enablebits[0].reg != d->enablebits[1].reg) {
764 d->enablebits[0].reg = d->enablebits[1].reg;
765 d->enablebits[0].mask = d->enablebits[1].mask;
766 d->enablebits[0].val = d->enablebits[1].val;
767 }
768 }
769#endif
770
771 return ide_setup_pci_device(dev, d);
772}
773
774static int __devinit init_setup_pdc202xx(struct pci_dev *dev,
775 ide_pci_device_t *d)
776{
777 return ide_setup_pci_device(dev, d);
778}
779
780static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
781 { /* 0 */
782 .name = "PDC20246",
783 .init_setup = init_setup_pdc202ata4,
784 .init_chipset = init_chipset_pdc202xx,
785 .init_hwif = init_hwif_pdc202xx,
786 .init_dma = init_dma_pdc202xx,
787 .channels = 2,
788 .autodma = AUTODMA,
789#ifndef CONFIG_PDC202XX_FORCE
790 .enablebits = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
791#endif
792 .bootable = OFF_BOARD,
793 .extra = 16,
794 },{ /* 1 */
795 .name = "PDC20262",
796 .init_setup = init_setup_pdc202ata4,
797 .init_chipset = init_chipset_pdc202xx,
798 .init_hwif = init_hwif_pdc202xx,
799 .init_dma = init_dma_pdc202xx,
800 .channels = 2,
801 .autodma = AUTODMA,
802#ifndef CONFIG_PDC202XX_FORCE
803 .enablebits = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
804#endif
805 .bootable = OFF_BOARD,
806 .extra = 48,
807 .flags = IDEPCI_FLAG_FORCE_PDC,
808 },{ /* 2 */
809 .name = "PDC20263",
810 .init_setup = init_setup_pdc202ata4,
811 .init_chipset = init_chipset_pdc202xx,
812 .init_hwif = init_hwif_pdc202xx,
813 .init_dma = init_dma_pdc202xx,
814 .channels = 2,
815 .autodma = AUTODMA,
816#ifndef CONFIG_PDC202XX_FORCE
817 .enablebits = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
818#endif
819 .bootable = OFF_BOARD,
820 .extra = 48,
821 },{ /* 3 */
822 .name = "PDC20265",
823 .init_setup = init_setup_pdc20265,
824 .init_chipset = init_chipset_pdc202xx,
825 .init_hwif = init_hwif_pdc202xx,
826 .init_dma = init_dma_pdc202xx,
827 .channels = 2,
828 .autodma = AUTODMA,
829#ifndef CONFIG_PDC202XX_FORCE
830 .enablebits = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
831#endif
832 .bootable = OFF_BOARD,
833 .extra = 48,
834 .flags = IDEPCI_FLAG_FORCE_PDC,
835 },{ /* 4 */
836 .name = "PDC20267",
837 .init_setup = init_setup_pdc202xx,
838 .init_chipset = init_chipset_pdc202xx,
839 .init_hwif = init_hwif_pdc202xx,
840 .init_dma = init_dma_pdc202xx,
841 .channels = 2,
842 .autodma = AUTODMA,
843#ifndef CONFIG_PDC202XX_FORCE
844 .enablebits = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
845#endif
846 .bootable = OFF_BOARD,
847 .extra = 48,
848 }
849};
850
851/**
852 * pdc202xx_init_one - called when a PDC202xx is found
853 * @dev: the pdc202xx device
854 * @id: the matching pci id
855 *
856 * Called when the PCI registration layer (or the IDE initialization)
857 * finds a device matching our IDE device tables.
858 */
859
860static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
861{
862 ide_pci_device_t *d = &pdc202xx_chipsets[id->driver_data];
863
864 return d->init_setup(dev, d);
865}
866
867static struct pci_device_id pdc202xx_pci_tbl[] = {
868 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
869 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
870 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
871 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
872 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
873 { 0, },
874};
875MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
876
877static struct pci_driver driver = {
878 .name = "Promise_Old_IDE",
879 .id_table = pdc202xx_pci_tbl,
880 .probe = pdc202xx_init_one,
881};
882
883static int pdc202xx_ide_init(void)
884{
885 return ide_pci_register_driver(&driver);
886}
887
888module_init(pdc202xx_ide_init);
889
890MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
891MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
892MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-01 19:32:10 -0400