diff options
author | Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> | 2007-10-11 17:53:59 -0400 |
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committer | Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> | 2007-10-11 17:53:59 -0400 |
commit | f212ff28f08e4ddcef9f25b13463c45cc4204a0c (patch) | |
tree | e8fe63044c2ebec404689cbd55d75497aa77da0a /drivers/ide/pci/pdc202xx_new.c | |
parent | 3160d5416f39da9d9221fec7cb9d64399b706bbc (diff) |
ide: move ide_rate_filter() calls to the upper layer (take 2)
* Move ide_rate_filter() calls from host drivers to IDE core.
* Make ide_rate_filter() static.
* Make 'speed' argument of ->speedproc const.
v2:
* Fix it8213_tune_chipset() comment.
There should be no functionality changes caused by this patch.
Acked-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Diffstat (limited to 'drivers/ide/pci/pdc202xx_new.c')
-rw-r--r-- | drivers/ide/pci/pdc202xx_new.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/drivers/ide/pci/pdc202xx_new.c b/drivers/ide/pci/pdc202xx_new.c index 7c5544d10b9a..3787194a2249 100644 --- a/drivers/ide/pci/pdc202xx_new.c +++ b/drivers/ide/pci/pdc202xx_new.c | |||
@@ -146,14 +146,12 @@ static struct udma_timing { | |||
146 | { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */ | 146 | { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */ |
147 | }; | 147 | }; |
148 | 148 | ||
149 | static int pdcnew_tune_chipset(ide_drive_t *drive, u8 speed) | 149 | static int pdcnew_tune_chipset(ide_drive_t *drive, const u8 speed) |
150 | { | 150 | { |
151 | ide_hwif_t *hwif = HWIF(drive); | 151 | ide_hwif_t *hwif = HWIF(drive); |
152 | u8 adj = (drive->dn & 1) ? 0x08 : 0x00; | 152 | u8 adj = (drive->dn & 1) ? 0x08 : 0x00; |
153 | int err; | 153 | int err; |
154 | 154 | ||
155 | speed = ide_rate_filter(drive, speed); | ||
156 | |||
157 | /* | 155 | /* |
158 | * Issue SETFEATURES_XFER to the drive first. PDC202xx hardware will | 156 | * Issue SETFEATURES_XFER to the drive first. PDC202xx hardware will |
159 | * automatically set the timing registers based on 100 MHz PLL output. | 157 | * automatically set the timing registers based on 100 MHz PLL output. |