ide: use PIO/MMIO operations directly where possible (v2)

This results in smaller/faster/simpler code and allows future optimizations.
Also remove no longer needed ide[_mm]_{inl,outl}() and ide_hwif_t.{INL,OUTL}.

v2:
* updated for scc_pata

Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>

1 files changed, 32 insertions, 31 deletions

diff --git a/drivers/ide/pci/opti621.c b/drivers/ide/pci/opti621.c
index 22bbf613f948..9ca60dd2185e 100644
--- a/drivers/ide/pci/opti621.c
+++ b/drivers/ide/pci/opti621.c
@@ -176,34 +176,35 @@ static int cmpt_clk(int time, int bus_speed)
         return ((time*bus_speed+999)/1000);
 }
 
-static void write_reg(ide_hwif_t *hwif, u8 value, int reg)
 /* Write value to register reg, base of register
  * is at reg_base (0x1f0 primary, 0x170 secondary,
  * if not changed by PCI configuration).
  * This is from setupvic.exe program.
  */
+static void write_reg(u8 value, int reg)
 {
-        hwif->INW(reg_base+1);
-        hwif->INW(reg_base+1);
-        hwif->OUTB(3, reg_base+2);
-        hwif->OUTB(value, reg_base+reg);
-        hwif->OUTB(0x83, reg_base+2);
+        inw(reg_base + 1);
+        inw(reg_base + 1);
+        outb(3, reg_base + 2);
+        outb(value, reg_base + reg);
+        outb(0x83, reg_base + 2);
 }
 
-static u8 read_reg(ide_hwif_t *hwif, int reg)
 /* Read value from register reg, base of register
  * is at reg_base (0x1f0 primary, 0x170 secondary,
  * if not changed by PCI configuration).
  * This is from setupvic.exe program.
  */
+static u8 read_reg(int reg)
 {
         u8 ret = 0;
 
-        hwif->INW(reg_base+1);
-        hwif->INW(reg_base+1);
-        hwif->OUTB(3, reg_base+2);
-        ret = hwif->INB(reg_base+reg);
-        hwif->OUTB(0x83, reg_base+2);
+        inw(reg_base + 1);
+        inw(reg_base + 1);
+        outb(3, reg_base + 2);
+        ret = inb(reg_base + reg);
+        outb(0x83, reg_base + 2);
+
         return ret;
 }
 
@@ -286,39 +287,39 @@ static void opti621_tune_drive (ide_drive_t *drive, u8 pio)
         reg_base = hwif->io_ports[IDE_DATA_OFFSET];
 
         /* allow Register-B */
-        hwif->OUTB(0xc0, reg_base+CNTRL_REG);
+        outb(0xc0, reg_base + CNTRL_REG);
         /* hmm, setupvic.exe does this ;-) */
-        hwif->OUTB(0xff, reg_base+5);
+        outb(0xff, reg_base + 5);
         /* if reads 0xff, adapter not exist? */
-        (void) hwif->INB(reg_base+CNTRL_REG);
+        (void)inb(reg_base + CNTRL_REG);
         /* if reads 0xc0, no interface exist? */
-        read_reg(hwif, CNTRL_REG);
+        read_reg(CNTRL_REG);
         /* read version, probably 0 */
-        read_reg(hwif, STRAP_REG);
+        read_reg(STRAP_REG);
 
         /* program primary drive */
-                /* select Index-0 for Register-A */
-        write_reg(hwif, 0,      MISC_REG);
-                /* set read cycle timings */
-        write_reg(hwif, cycle1, READ_REG);
-                /* set write cycle timings */
-        write_reg(hwif, cycle1, WRITE_REG);
+        /* select Index-0 for Register-A */
+        write_reg(0, MISC_REG);
+        /* set read cycle timings */
+        write_reg(cycle1, READ_REG);
+        /* set write cycle timings */
+        write_reg(cycle1, WRITE_REG);
 
         /* program secondary drive */
-                /* select Index-1 for Register-B */
-        write_reg(hwif, 1,      MISC_REG);
-                /* set read cycle timings */
-        write_reg(hwif, cycle2, READ_REG);
-                /* set write cycle timings */
-        write_reg(hwif, cycle2, WRITE_REG);
+        /* select Index-1 for Register-B */
+        write_reg(1, MISC_REG);
+        /* set read cycle timings */
+        write_reg(cycle2, READ_REG);
+        /* set write cycle timings */
+        write_reg(cycle2, WRITE_REG);
 
         /* use Register-A for drive 0 */
         /* use Register-B for drive 1 */
-        write_reg(hwif, 0x85, CNTRL_REG);
+        write_reg(0x85, CNTRL_REG);
 
         /* set address setup, DRDY timings,   */
         /*  and read prefetch for both drives */
-        write_reg(hwif, misc, MISC_REG);
+        write_reg(misc, MISC_REG);
 
         spin_unlock_irqrestore(&ide_lock, flags);
 }