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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/ide/pci/hpt366.c
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/ide/pci/hpt366.c')
-rw-r--r--drivers/ide/pci/hpt366.c1745
1 files changed, 1745 insertions, 0 deletions
diff --git a/drivers/ide/pci/hpt366.c b/drivers/ide/pci/hpt366.c
new file mode 100644
index 000000000000..c8ee0b8c0292
--- /dev/null
+++ b/drivers/ide/pci/hpt366.c
@@ -0,0 +1,1745 @@
1/*
2 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
3 *
4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
5 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
6 * Portions Copyright (C) 2003 Red Hat Inc
7 *
8 * Thanks to HighPoint Technologies for their assistance, and hardware.
9 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
10 * donation of an ABit BP6 mainboard, processor, and memory acellerated
11 * development and support.
12 *
13 * Note that final HPT370 support was done by force extraction of GPL.
14 *
15 * - add function for getting/setting power status of drive
16 * - the HPT370's state machine can get confused. reset it before each dma
17 * xfer to prevent that from happening.
18 * - reset state engine whenever we get an error.
19 * - check for busmaster state at end of dma.
20 * - use new highpoint timings.
21 * - detect bus speed using highpoint register.
22 * - use pll if we don't have a clock table. added a 66MHz table that's
23 * just 2x the 33MHz table.
24 * - removed turnaround. NOTE: we never want to switch between pll and
25 * pci clocks as the chip can glitch in those cases. the highpoint
26 * approved workaround slows everything down too much to be useful. in
27 * addition, we would have to serialize access to each chip.
28 * Adrian Sun <a.sun@sun.com>
29 *
30 * add drive timings for 66MHz PCI bus,
31 * fix ATA Cable signal detection, fix incorrect /proc info
32 * add /proc display for per-drive PIO/DMA/UDMA mode and
33 * per-channel ATA-33/66 Cable detect.
34 * Duncan Laurie <void@sun.com>
35 *
36 * fixup /proc output for multiple controllers
37 * Tim Hockin <thockin@sun.com>
38 *
39 * On hpt366:
40 * Reset the hpt366 on error, reset on dma
41 * Fix disabling Fast Interrupt hpt366.
42 * Mike Waychison <crlf@sun.com>
43 *
44 * Added support for 372N clocking and clock switching. The 372N needs
45 * different clocks on read/write. This requires overloading rw_disk and
46 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
47 * keeping me sane.
48 * Alan Cox <alan@redhat.com>
49 *
50 */
51
52
53#include <linux/config.h>
54#include <linux/types.h>
55#include <linux/module.h>
56#include <linux/kernel.h>
57#include <linux/delay.h>
58#include <linux/timer.h>
59#include <linux/mm.h>
60#include <linux/ioport.h>
61#include <linux/blkdev.h>
62#include <linux/hdreg.h>
63
64#include <linux/interrupt.h>
65#include <linux/pci.h>
66#include <linux/init.h>
67#include <linux/ide.h>
68
69#include <asm/uaccess.h>
70#include <asm/io.h>
71#include <asm/irq.h>
72
73/* various tuning parameters */
74#define HPT_RESET_STATE_ENGINE
75#undef HPT_DELAY_INTERRUPT
76#undef HPT_SERIALIZE_IO
77
78static const char *quirk_drives[] = {
79 "QUANTUM FIREBALLlct08 08",
80 "QUANTUM FIREBALLP KA6.4",
81 "QUANTUM FIREBALLP LM20.4",
82 "QUANTUM FIREBALLP LM20.5",
83 NULL
84};
85
86static const char *bad_ata100_5[] = {
87 "IBM-DTLA-307075",
88 "IBM-DTLA-307060",
89 "IBM-DTLA-307045",
90 "IBM-DTLA-307030",
91 "IBM-DTLA-307020",
92 "IBM-DTLA-307015",
93 "IBM-DTLA-305040",
94 "IBM-DTLA-305030",
95 "IBM-DTLA-305020",
96 "IC35L010AVER07-0",
97 "IC35L020AVER07-0",
98 "IC35L030AVER07-0",
99 "IC35L040AVER07-0",
100 "IC35L060AVER07-0",
101 "WDC AC310200R",
102 NULL
103};
104
105static const char *bad_ata66_4[] = {
106 "IBM-DTLA-307075",
107 "IBM-DTLA-307060",
108 "IBM-DTLA-307045",
109 "IBM-DTLA-307030",
110 "IBM-DTLA-307020",
111 "IBM-DTLA-307015",
112 "IBM-DTLA-305040",
113 "IBM-DTLA-305030",
114 "IBM-DTLA-305020",
115 "IC35L010AVER07-0",
116 "IC35L020AVER07-0",
117 "IC35L030AVER07-0",
118 "IC35L040AVER07-0",
119 "IC35L060AVER07-0",
120 "WDC AC310200R",
121 NULL
122};
123
124static const char *bad_ata66_3[] = {
125 "WDC AC310200R",
126 NULL
127};
128
129static const char *bad_ata33[] = {
130 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
131 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
132 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
133 "Maxtor 90510D4",
134 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
135 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
136 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
137 NULL
138};
139
140struct chipset_bus_clock_list_entry {
141 u8 xfer_speed;
142 unsigned int chipset_settings;
143};
144
145/* key for bus clock timings
146 * bit
147 * 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
148 * DMA. cycles = value + 1
149 * 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
150 * DMA. cycles = value + 1
151 * 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
152 * register access.
153 * 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
154 * register access.
155 * 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
156 * during task file register access.
157 * 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
158 * xfer.
159 * 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
160 * register access.
161 * 28 UDMA enable
162 * 29 DMA enable
163 * 30 PIO_MST enable. if set, the chip is in bus master mode during
164 * PIO.
165 * 31 FIFO enable.
166 */
167static struct chipset_bus_clock_list_entry forty_base_hpt366[] = {
168 { XFER_UDMA_4, 0x900fd943 },
169 { XFER_UDMA_3, 0x900ad943 },
170 { XFER_UDMA_2, 0x900bd943 },
171 { XFER_UDMA_1, 0x9008d943 },
172 { XFER_UDMA_0, 0x9008d943 },
173
174 { XFER_MW_DMA_2, 0xa008d943 },
175 { XFER_MW_DMA_1, 0xa010d955 },
176 { XFER_MW_DMA_0, 0xa010d9fc },
177
178 { XFER_PIO_4, 0xc008d963 },
179 { XFER_PIO_3, 0xc010d974 },
180 { XFER_PIO_2, 0xc010d997 },
181 { XFER_PIO_1, 0xc010d9c7 },
182 { XFER_PIO_0, 0xc018d9d9 },
183 { 0, 0x0120d9d9 }
184};
185
186static struct chipset_bus_clock_list_entry thirty_three_base_hpt366[] = {
187 { XFER_UDMA_4, 0x90c9a731 },
188 { XFER_UDMA_3, 0x90cfa731 },
189 { XFER_UDMA_2, 0x90caa731 },
190 { XFER_UDMA_1, 0x90cba731 },
191 { XFER_UDMA_0, 0x90c8a731 },
192
193 { XFER_MW_DMA_2, 0xa0c8a731 },
194 { XFER_MW_DMA_1, 0xa0c8a732 }, /* 0xa0c8a733 */
195 { XFER_MW_DMA_0, 0xa0c8a797 },
196
197 { XFER_PIO_4, 0xc0c8a731 },
198 { XFER_PIO_3, 0xc0c8a742 },
199 { XFER_PIO_2, 0xc0d0a753 },
200 { XFER_PIO_1, 0xc0d0a7a3 }, /* 0xc0d0a793 */
201 { XFER_PIO_0, 0xc0d0a7aa }, /* 0xc0d0a7a7 */
202 { 0, 0x0120a7a7 }
203};
204
205static struct chipset_bus_clock_list_entry twenty_five_base_hpt366[] = {
206 { XFER_UDMA_4, 0x90c98521 },
207 { XFER_UDMA_3, 0x90cf8521 },
208 { XFER_UDMA_2, 0x90cf8521 },
209 { XFER_UDMA_1, 0x90cb8521 },
210 { XFER_UDMA_0, 0x90cb8521 },
211
212 { XFER_MW_DMA_2, 0xa0ca8521 },
213 { XFER_MW_DMA_1, 0xa0ca8532 },
214 { XFER_MW_DMA_0, 0xa0ca8575 },
215
216 { XFER_PIO_4, 0xc0ca8521 },
217 { XFER_PIO_3, 0xc0ca8532 },
218 { XFER_PIO_2, 0xc0ca8542 },
219 { XFER_PIO_1, 0xc0d08572 },
220 { XFER_PIO_0, 0xc0d08585 },
221 { 0, 0x01208585 }
222};
223
224/* from highpoint documentation. these are old values */
225static struct chipset_bus_clock_list_entry thirty_three_base_hpt370[] = {
226/* { XFER_UDMA_5, 0x1A85F442, 0x16454e31 }, */
227 { XFER_UDMA_5, 0x16454e31 },
228 { XFER_UDMA_4, 0x16454e31 },
229 { XFER_UDMA_3, 0x166d4e31 },
230 { XFER_UDMA_2, 0x16494e31 },
231 { XFER_UDMA_1, 0x164d4e31 },
232 { XFER_UDMA_0, 0x16514e31 },
233
234 { XFER_MW_DMA_2, 0x26514e21 },
235 { XFER_MW_DMA_1, 0x26514e33 },
236 { XFER_MW_DMA_0, 0x26514e97 },
237
238 { XFER_PIO_4, 0x06514e21 },
239 { XFER_PIO_3, 0x06514e22 },
240 { XFER_PIO_2, 0x06514e33 },
241 { XFER_PIO_1, 0x06914e43 },
242 { XFER_PIO_0, 0x06914e57 },
243 { 0, 0x06514e57 }
244};
245
246static struct chipset_bus_clock_list_entry sixty_six_base_hpt370[] = {
247 { XFER_UDMA_5, 0x14846231 },
248 { XFER_UDMA_4, 0x14886231 },
249 { XFER_UDMA_3, 0x148c6231 },
250 { XFER_UDMA_2, 0x148c6231 },
251 { XFER_UDMA_1, 0x14906231 },
252 { XFER_UDMA_0, 0x14986231 },
253
254 { XFER_MW_DMA_2, 0x26514e21 },
255 { XFER_MW_DMA_1, 0x26514e33 },
256 { XFER_MW_DMA_0, 0x26514e97 },
257
258 { XFER_PIO_4, 0x06514e21 },
259 { XFER_PIO_3, 0x06514e22 },
260 { XFER_PIO_2, 0x06514e33 },
261 { XFER_PIO_1, 0x06914e43 },
262 { XFER_PIO_0, 0x06914e57 },
263 { 0, 0x06514e57 }
264};
265
266/* these are the current (4 sep 2001) timings from highpoint */
267static struct chipset_bus_clock_list_entry thirty_three_base_hpt370a[] = {
268 { XFER_UDMA_5, 0x12446231 },
269 { XFER_UDMA_4, 0x12446231 },
270 { XFER_UDMA_3, 0x126c6231 },
271 { XFER_UDMA_2, 0x12486231 },
272 { XFER_UDMA_1, 0x124c6233 },
273 { XFER_UDMA_0, 0x12506297 },
274
275 { XFER_MW_DMA_2, 0x22406c31 },
276 { XFER_MW_DMA_1, 0x22406c33 },
277 { XFER_MW_DMA_0, 0x22406c97 },
278
279 { XFER_PIO_4, 0x06414e31 },
280 { XFER_PIO_3, 0x06414e42 },
281 { XFER_PIO_2, 0x06414e53 },
282 { XFER_PIO_1, 0x06814e93 },
283 { XFER_PIO_0, 0x06814ea7 },
284 { 0, 0x06814ea7 }
285};
286
287/* 2x 33MHz timings */
288static struct chipset_bus_clock_list_entry sixty_six_base_hpt370a[] = {
289 { XFER_UDMA_5, 0x1488e673 },
290 { XFER_UDMA_4, 0x1488e673 },
291 { XFER_UDMA_3, 0x1498e673 },
292 { XFER_UDMA_2, 0x1490e673 },
293 { XFER_UDMA_1, 0x1498e677 },
294 { XFER_UDMA_0, 0x14a0e73f },
295
296 { XFER_MW_DMA_2, 0x2480fa73 },
297 { XFER_MW_DMA_1, 0x2480fa77 },
298 { XFER_MW_DMA_0, 0x2480fb3f },
299
300 { XFER_PIO_4, 0x0c82be73 },
301 { XFER_PIO_3, 0x0c82be95 },
302 { XFER_PIO_2, 0x0c82beb7 },
303 { XFER_PIO_1, 0x0d02bf37 },
304 { XFER_PIO_0, 0x0d02bf5f },
305 { 0, 0x0d02bf5f }
306};
307
308static struct chipset_bus_clock_list_entry fifty_base_hpt370a[] = {
309 { XFER_UDMA_5, 0x12848242 },
310 { XFER_UDMA_4, 0x12ac8242 },
311 { XFER_UDMA_3, 0x128c8242 },
312 { XFER_UDMA_2, 0x120c8242 },
313 { XFER_UDMA_1, 0x12148254 },
314 { XFER_UDMA_0, 0x121882ea },
315
316 { XFER_MW_DMA_2, 0x22808242 },
317 { XFER_MW_DMA_1, 0x22808254 },
318 { XFER_MW_DMA_0, 0x228082ea },
319
320 { XFER_PIO_4, 0x0a81f442 },
321 { XFER_PIO_3, 0x0a81f443 },
322 { XFER_PIO_2, 0x0a81f454 },
323 { XFER_PIO_1, 0x0ac1f465 },
324 { XFER_PIO_0, 0x0ac1f48a },
325 { 0, 0x0ac1f48a }
326};
327
328static struct chipset_bus_clock_list_entry thirty_three_base_hpt372[] = {
329 { XFER_UDMA_6, 0x1c81dc62 },
330 { XFER_UDMA_5, 0x1c6ddc62 },
331 { XFER_UDMA_4, 0x1c8ddc62 },
332 { XFER_UDMA_3, 0x1c8edc62 }, /* checkme */
333 { XFER_UDMA_2, 0x1c91dc62 },
334 { XFER_UDMA_1, 0x1c9adc62 }, /* checkme */
335 { XFER_UDMA_0, 0x1c82dc62 }, /* checkme */
336
337 { XFER_MW_DMA_2, 0x2c829262 },
338 { XFER_MW_DMA_1, 0x2c829266 }, /* checkme */
339 { XFER_MW_DMA_0, 0x2c82922e }, /* checkme */
340
341 { XFER_PIO_4, 0x0c829c62 },
342 { XFER_PIO_3, 0x0c829c84 },
343 { XFER_PIO_2, 0x0c829ca6 },
344 { XFER_PIO_1, 0x0d029d26 },
345 { XFER_PIO_0, 0x0d029d5e },
346 { 0, 0x0d029d5e }
347};
348
349static struct chipset_bus_clock_list_entry fifty_base_hpt372[] = {
350 { XFER_UDMA_5, 0x12848242 },
351 { XFER_UDMA_4, 0x12ac8242 },
352 { XFER_UDMA_3, 0x128c8242 },
353 { XFER_UDMA_2, 0x120c8242 },
354 { XFER_UDMA_1, 0x12148254 },
355 { XFER_UDMA_0, 0x121882ea },
356
357 { XFER_MW_DMA_2, 0x22808242 },
358 { XFER_MW_DMA_1, 0x22808254 },
359 { XFER_MW_DMA_0, 0x228082ea },
360
361 { XFER_PIO_4, 0x0a81f442 },
362 { XFER_PIO_3, 0x0a81f443 },
363 { XFER_PIO_2, 0x0a81f454 },
364 { XFER_PIO_1, 0x0ac1f465 },
365 { XFER_PIO_0, 0x0ac1f48a },
366 { 0, 0x0a81f443 }
367};
368
369static struct chipset_bus_clock_list_entry sixty_six_base_hpt372[] = {
370 { XFER_UDMA_6, 0x1c869c62 },
371 { XFER_UDMA_5, 0x1cae9c62 },
372 { XFER_UDMA_4, 0x1c8a9c62 },
373 { XFER_UDMA_3, 0x1c8e9c62 },
374 { XFER_UDMA_2, 0x1c929c62 },
375 { XFER_UDMA_1, 0x1c9a9c62 },
376 { XFER_UDMA_0, 0x1c829c62 },
377
378 { XFER_MW_DMA_2, 0x2c829c62 },
379 { XFER_MW_DMA_1, 0x2c829c66 },
380 { XFER_MW_DMA_0, 0x2c829d2e },
381
382 { XFER_PIO_4, 0x0c829c62 },
383 { XFER_PIO_3, 0x0c829c84 },
384 { XFER_PIO_2, 0x0c829ca6 },
385 { XFER_PIO_1, 0x0d029d26 },
386 { XFER_PIO_0, 0x0d029d5e },
387 { 0, 0x0d029d26 }
388};
389
390static struct chipset_bus_clock_list_entry thirty_three_base_hpt374[] = {
391 { XFER_UDMA_6, 0x12808242 },
392 { XFER_UDMA_5, 0x12848242 },
393 { XFER_UDMA_4, 0x12ac8242 },
394 { XFER_UDMA_3, 0x128c8242 },
395 { XFER_UDMA_2, 0x120c8242 },
396 { XFER_UDMA_1, 0x12148254 },
397 { XFER_UDMA_0, 0x121882ea },
398
399 { XFER_MW_DMA_2, 0x22808242 },
400 { XFER_MW_DMA_1, 0x22808254 },
401 { XFER_MW_DMA_0, 0x228082ea },
402
403 { XFER_PIO_4, 0x0a81f442 },
404 { XFER_PIO_3, 0x0a81f443 },
405 { XFER_PIO_2, 0x0a81f454 },
406 { XFER_PIO_1, 0x0ac1f465 },
407 { XFER_PIO_0, 0x0ac1f48a },
408 { 0, 0x06814e93 }
409};
410
411/* FIXME: 50MHz timings for HPT374 */
412
413#if 0
414static struct chipset_bus_clock_list_entry sixty_six_base_hpt374[] = {
415 { XFER_UDMA_6, 0x12406231 }, /* checkme */
416 { XFER_UDMA_5, 0x12446231 }, /* 0x14846231 */
417 { XFER_UDMA_4, 0x16814ea7 }, /* 0x14886231 */
418 { XFER_UDMA_3, 0x16814ea7 }, /* 0x148c6231 */
419 { XFER_UDMA_2, 0x16814ea7 }, /* 0x148c6231 */
420 { XFER_UDMA_1, 0x16814ea7 }, /* 0x14906231 */
421 { XFER_UDMA_0, 0x16814ea7 }, /* 0x14986231 */
422 { XFER_MW_DMA_2, 0x16814ea7 }, /* 0x26514e21 */
423 { XFER_MW_DMA_1, 0x16814ea7 }, /* 0x26514e97 */
424 { XFER_MW_DMA_0, 0x16814ea7 }, /* 0x26514e97 */
425 { XFER_PIO_4, 0x06814ea7 }, /* 0x06514e21 */
426 { XFER_PIO_3, 0x06814ea7 }, /* 0x06514e22 */
427 { XFER_PIO_2, 0x06814ea7 }, /* 0x06514e33 */
428 { XFER_PIO_1, 0x06814ea7 }, /* 0x06914e43 */
429 { XFER_PIO_0, 0x06814ea7 }, /* 0x06914e57 */
430 { 0, 0x06814ea7 }
431};
432#endif
433
434#define HPT366_DEBUG_DRIVE_INFO 0
435#define HPT374_ALLOW_ATA133_6 0
436#define HPT371_ALLOW_ATA133_6 0
437#define HPT302_ALLOW_ATA133_6 0
438#define HPT372_ALLOW_ATA133_6 1
439#define HPT370_ALLOW_ATA100_5 1
440#define HPT366_ALLOW_ATA66_4 1
441#define HPT366_ALLOW_ATA66_3 1
442#define HPT366_MAX_DEVS 8
443
444#define F_LOW_PCI_33 0x23
445#define F_LOW_PCI_40 0x29
446#define F_LOW_PCI_50 0x2d
447#define F_LOW_PCI_66 0x42
448
449/* FIXME: compare with driver's code before removing */
450#if 0
451 if (hpt_minimum_revision(dev, 3)) {
452 u8 cbl;
453 cbl = inb(iobase + 0x7b);
454 outb(cbl | 1, iobase + 0x7b);
455 outb(cbl & ~1, iobase + 0x7b);
456 cbl = inb(iobase + 0x7a);
457 p += sprintf(p, "Cable: ATA-%d"
458 " ATA-%d\n",
459 (cbl & 0x02) ? 33 : 66,
460 (cbl & 0x01) ? 33 : 66);
461 p += sprintf(p, "\n");
462 }
463 {
464 u8 c2, c3;
465 /* older revs don't have these registers mapped
466 * into io space */
467 pci_read_config_byte(dev, 0x43, &c0);
468 pci_read_config_byte(dev, 0x47, &c1);
469 pci_read_config_byte(dev, 0x4b, &c2);
470 pci_read_config_byte(dev, 0x4f, &c3);
471
472 p += sprintf(p, "Mode: %s %s"
473 " %s %s\n",
474 (c0 & 0x10) ? "UDMA" : (c0 & 0x20) ? "DMA " :
475 (c0 & 0x80) ? "PIO " : "off ",
476 (c1 & 0x10) ? "UDMA" : (c1 & 0x20) ? "DMA " :
477 (c1 & 0x80) ? "PIO " : "off ",
478 (c2 & 0x10) ? "UDMA" : (c2 & 0x20) ? "DMA " :
479 (c2 & 0x80) ? "PIO " : "off ",
480 (c3 & 0x10) ? "UDMA" : (c3 & 0x20) ? "DMA " :
481 (c3 & 0x80) ? "PIO " : "off ");
482 }
483 }
484#endif
485
486static u32 hpt_revision (struct pci_dev *dev)
487{
488 u32 class_rev;
489 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
490 class_rev &= 0xff;
491
492 switch(dev->device) {
493 /* Remap new 372N onto 372 */
494 case PCI_DEVICE_ID_TTI_HPT372N:
495 class_rev = PCI_DEVICE_ID_TTI_HPT372; break;
496 case PCI_DEVICE_ID_TTI_HPT374:
497 class_rev = PCI_DEVICE_ID_TTI_HPT374; break;
498 case PCI_DEVICE_ID_TTI_HPT371:
499 class_rev = PCI_DEVICE_ID_TTI_HPT371; break;
500 case PCI_DEVICE_ID_TTI_HPT302:
501 class_rev = PCI_DEVICE_ID_TTI_HPT302; break;
502 case PCI_DEVICE_ID_TTI_HPT372:
503 class_rev = PCI_DEVICE_ID_TTI_HPT372; break;
504 default:
505 break;
506 }
507 return class_rev;
508}
509
510static u32 hpt_minimum_revision (struct pci_dev *dev, int revision)
511{
512 unsigned int class_rev = hpt_revision(dev);
513 revision--;
514 return ((int) (class_rev > revision) ? 1 : 0);
515}
516
517static int check_in_drive_lists(ide_drive_t *drive, const char **list);
518
519static u8 hpt3xx_ratemask (ide_drive_t *drive)
520{
521 struct pci_dev *dev = HWIF(drive)->pci_dev;
522 u8 mode = 0;
523
524 if (hpt_minimum_revision(dev, 8)) { /* HPT374 */
525 mode = (HPT374_ALLOW_ATA133_6) ? 4 : 3;
526 } else if (hpt_minimum_revision(dev, 7)) { /* HPT371 */
527 mode = (HPT371_ALLOW_ATA133_6) ? 4 : 3;
528 } else if (hpt_minimum_revision(dev, 6)) { /* HPT302 */
529 mode = (HPT302_ALLOW_ATA133_6) ? 4 : 3;
530 } else if (hpt_minimum_revision(dev, 5)) { /* HPT372 */
531 mode = (HPT372_ALLOW_ATA133_6) ? 4 : 3;
532 } else if (hpt_minimum_revision(dev, 4)) { /* HPT370A */
533 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
534 } else if (hpt_minimum_revision(dev, 3)) { /* HPT370 */
535 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
536 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : mode;
537 } else { /* HPT366 and HPT368 */
538 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : 2;
539 }
540 if (!eighty_ninty_three(drive) && (mode))
541 mode = min(mode, (u8)1);
542 return mode;
543}
544
545/*
546 * Note for the future; the SATA hpt37x we must set
547 * either PIO or UDMA modes 0,4,5
548 */
549
550static u8 hpt3xx_ratefilter (ide_drive_t *drive, u8 speed)
551{
552 struct pci_dev *dev = HWIF(drive)->pci_dev;
553 u8 mode = hpt3xx_ratemask(drive);
554
555 if (drive->media != ide_disk)
556 return min(speed, (u8)XFER_PIO_4);
557
558 switch(mode) {
559 case 0x04:
560 speed = min(speed, (u8)XFER_UDMA_6);
561 break;
562 case 0x03:
563 speed = min(speed, (u8)XFER_UDMA_5);
564 if (hpt_minimum_revision(dev, 5))
565 break;
566 if (check_in_drive_lists(drive, bad_ata100_5))
567 speed = min(speed, (u8)XFER_UDMA_4);
568 break;
569 case 0x02:
570 speed = min(speed, (u8)XFER_UDMA_4);
571 /*
572 * CHECK ME, Does this need to be set to 5 ??
573 */
574 if (hpt_minimum_revision(dev, 3))
575 break;
576 if ((check_in_drive_lists(drive, bad_ata66_4)) ||
577 (!(HPT366_ALLOW_ATA66_4)))
578 speed = min(speed, (u8)XFER_UDMA_3);
579 if ((check_in_drive_lists(drive, bad_ata66_3)) ||
580 (!(HPT366_ALLOW_ATA66_3)))
581 speed = min(speed, (u8)XFER_UDMA_2);
582 break;
583 case 0x01:
584 speed = min(speed, (u8)XFER_UDMA_2);
585 /*
586 * CHECK ME, Does this need to be set to 5 ??
587 */
588 if (hpt_minimum_revision(dev, 3))
589 break;
590 if (check_in_drive_lists(drive, bad_ata33))
591 speed = min(speed, (u8)XFER_MW_DMA_2);
592 break;
593 case 0x00:
594 default:
595 speed = min(speed, (u8)XFER_MW_DMA_2);
596 break;
597 }
598 return speed;
599}
600
601static int check_in_drive_lists (ide_drive_t *drive, const char **list)
602{
603 struct hd_driveid *id = drive->id;
604
605 if (quirk_drives == list) {
606 while (*list)
607 if (strstr(id->model, *list++))
608 return 1;
609 } else {
610 while (*list)
611 if (!strcmp(*list++,id->model))
612 return 1;
613 }
614 return 0;
615}
616
617static unsigned int pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
618{
619 for ( ; chipset_table->xfer_speed ; chipset_table++)
620 if (chipset_table->xfer_speed == speed)
621 return chipset_table->chipset_settings;
622 return chipset_table->chipset_settings;
623}
624
625static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
626{
627 struct pci_dev *dev = HWIF(drive)->pci_dev;
628 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
629// u8 speed = ide_rate_filter(hpt3xx_ratemask(drive), xferspeed);
630 u8 regtime = (drive->select.b.unit & 0x01) ? 0x44 : 0x40;
631 u8 regfast = (HWIF(drive)->channel) ? 0x55 : 0x51;
632 u8 drive_fast = 0;
633 u32 reg1 = 0, reg2 = 0;
634
635 /*
636 * Disable the "fast interrupt" prediction.
637 */
638 pci_read_config_byte(dev, regfast, &drive_fast);
639#if 0
640 if (drive_fast & 0x02)
641 pci_write_config_byte(dev, regfast, drive_fast & ~0x20);
642#else
643 if (drive_fast & 0x80)
644 pci_write_config_byte(dev, regfast, drive_fast & ~0x80);
645#endif
646
647 reg2 = pci_bus_clock_list(speed,
648 (struct chipset_bus_clock_list_entry *) pci_get_drvdata(dev));
649 /*
650 * Disable on-chip PIO FIFO/buffer
651 * (to avoid problems handling I/O errors later)
652 */
653 pci_read_config_dword(dev, regtime, &reg1);
654 if (speed >= XFER_MW_DMA_0) {
655 reg2 = (reg2 & ~0xc0000000) | (reg1 & 0xc0000000);
656 } else {
657 reg2 = (reg2 & ~0x30070000) | (reg1 & 0x30070000);
658 }
659 reg2 &= ~0x80000000;
660
661 pci_write_config_dword(dev, regtime, reg2);
662
663 return ide_config_drive_speed(drive, speed);
664}
665
666static int hpt370_tune_chipset(ide_drive_t *drive, u8 xferspeed)
667{
668 struct pci_dev *dev = HWIF(drive)->pci_dev;
669 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
670// u8 speed = ide_rate_filter(hpt3xx_ratemask(drive), xferspeed);
671 u8 regfast = (HWIF(drive)->channel) ? 0x55 : 0x51;
672 u8 drive_pci = 0x40 + (drive->dn * 4);
673 u8 new_fast = 0, drive_fast = 0;
674 u32 list_conf = 0, drive_conf = 0;
675 u32 conf_mask = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
676
677 /*
678 * Disable the "fast interrupt" prediction.
679 * don't holdoff on interrupts. (== 0x01 despite what the docs say)
680 */
681 pci_read_config_byte(dev, regfast, &drive_fast);
682 new_fast = drive_fast;
683 if (new_fast & 0x02)
684 new_fast &= ~0x02;
685
686#ifdef HPT_DELAY_INTERRUPT
687 if (new_fast & 0x01)
688 new_fast &= ~0x01;
689#else
690 if ((new_fast & 0x01) == 0)
691 new_fast |= 0x01;
692#endif
693 if (new_fast != drive_fast)
694 pci_write_config_byte(dev, regfast, new_fast);
695
696 list_conf = pci_bus_clock_list(speed,
697 (struct chipset_bus_clock_list_entry *)
698 pci_get_drvdata(dev));
699
700 pci_read_config_dword(dev, drive_pci, &drive_conf);
701 list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
702
703 if (speed < XFER_MW_DMA_0) {
704 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
705 }
706
707 pci_write_config_dword(dev, drive_pci, list_conf);
708
709 return ide_config_drive_speed(drive, speed);
710}
711
712static int hpt372_tune_chipset(ide_drive_t *drive, u8 xferspeed)
713{
714 struct pci_dev *dev = HWIF(drive)->pci_dev;
715 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
716// u8 speed = ide_rate_filter(hpt3xx_ratemask(drive), xferspeed);
717 u8 regfast = (HWIF(drive)->channel) ? 0x55 : 0x51;
718 u8 drive_fast = 0, drive_pci = 0x40 + (drive->dn * 4);
719 u32 list_conf = 0, drive_conf = 0;
720 u32 conf_mask = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
721
722 /*
723 * Disable the "fast interrupt" prediction.
724 * don't holdoff on interrupts. (== 0x01 despite what the docs say)
725 */
726 pci_read_config_byte(dev, regfast, &drive_fast);
727 drive_fast &= ~0x07;
728 pci_write_config_byte(dev, regfast, drive_fast);
729
730 list_conf = pci_bus_clock_list(speed,
731 (struct chipset_bus_clock_list_entry *)
732 pci_get_drvdata(dev));
733 pci_read_config_dword(dev, drive_pci, &drive_conf);
734 list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
735 if (speed < XFER_MW_DMA_0)
736 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
737 pci_write_config_dword(dev, drive_pci, list_conf);
738
739 return ide_config_drive_speed(drive, speed);
740}
741
742static int hpt3xx_tune_chipset (ide_drive_t *drive, u8 speed)
743{
744 struct pci_dev *dev = HWIF(drive)->pci_dev;
745
746 if (hpt_minimum_revision(dev, 8))
747 return hpt372_tune_chipset(drive, speed); /* not a typo */
748#if 0
749 else if (hpt_minimum_revision(dev, 7))
750 hpt371_tune_chipset(drive, speed);
751 else if (hpt_minimum_revision(dev, 6))
752 hpt302_tune_chipset(drive, speed);
753#endif
754 else if (hpt_minimum_revision(dev, 5))
755 return hpt372_tune_chipset(drive, speed);
756 else if (hpt_minimum_revision(dev, 3))
757 return hpt370_tune_chipset(drive, speed);
758 else /* hpt368: hpt_minimum_revision(dev, 2) */
759 return hpt36x_tune_chipset(drive, speed);
760}
761
762static void hpt3xx_tune_drive (ide_drive_t *drive, u8 pio)
763{
764 pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
765 (void) hpt3xx_tune_chipset(drive, (XFER_PIO_0 + pio));
766}
767
768/*
769 * This allows the configuration of ide_pci chipset registers
770 * for cards that learn about the drive's UDMA, DMA, PIO capabilities
771 * after the drive is reported by the OS. Initially for designed for
772 * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
773 *
774 * check_in_drive_lists(drive, bad_ata66_4)
775 * check_in_drive_lists(drive, bad_ata66_3)
776 * check_in_drive_lists(drive, bad_ata33)
777 *
778 */
779static int config_chipset_for_dma (ide_drive_t *drive)
780{
781 u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive));
782
783 if (!(speed))
784 return 0;
785
786 (void) hpt3xx_tune_chipset(drive, speed);
787 return ide_dma_enable(drive);
788}
789
790static int hpt3xx_quirkproc (ide_drive_t *drive)
791{
792 return ((int) check_in_drive_lists(drive, quirk_drives));
793}
794
795static void hpt3xx_intrproc (ide_drive_t *drive)
796{
797 ide_hwif_t *hwif = HWIF(drive);
798
799 if (drive->quirk_list)
800 return;
801 /* drives in the quirk_list may not like intr setups/cleanups */
802 hwif->OUTB(drive->ctl|2, IDE_CONTROL_REG);
803}
804
805static void hpt3xx_maskproc (ide_drive_t *drive, int mask)
806{
807 struct pci_dev *dev = HWIF(drive)->pci_dev;
808
809 if (drive->quirk_list) {
810 if (hpt_minimum_revision(dev,3)) {
811 u8 reg5a = 0;
812 pci_read_config_byte(dev, 0x5a, &reg5a);
813 if (((reg5a & 0x10) >> 4) != mask)
814 pci_write_config_byte(dev, 0x5a, mask ? (reg5a | 0x10) : (reg5a & ~0x10));
815 } else {
816 if (mask) {
817 disable_irq(HWIF(drive)->irq);
818 } else {
819 enable_irq(HWIF(drive)->irq);
820 }
821 }
822 } else {
823 if (IDE_CONTROL_REG)
824 HWIF(drive)->OUTB(mask ? (drive->ctl | 2) :
825 (drive->ctl & ~2),
826 IDE_CONTROL_REG);
827 }
828}
829
830static int hpt366_config_drive_xfer_rate (ide_drive_t *drive)
831{
832 ide_hwif_t *hwif = HWIF(drive);
833 struct hd_driveid *id = drive->id;
834
835 drive->init_speed = 0;
836
837 if (id && (id->capability & 1) && drive->autodma) {
838
839 if (ide_use_dma(drive)) {
840 if (config_chipset_for_dma(drive))
841 return hwif->ide_dma_on(drive);
842 }
843
844 goto fast_ata_pio;
845
846 } else if ((id->capability & 8) || (id->field_valid & 2)) {
847fast_ata_pio:
848 hpt3xx_tune_drive(drive, 5);
849 return hwif->ide_dma_off_quietly(drive);
850 }
851 /* IORDY not supported */
852 return 0;
853}
854
855/*
856 * This is specific to the HPT366 UDMA bios chipset
857 * by HighPoint|Triones Technologies, Inc.
858 */
859static int hpt366_ide_dma_lostirq (ide_drive_t *drive)
860{
861 struct pci_dev *dev = HWIF(drive)->pci_dev;
862 u8 reg50h = 0, reg52h = 0, reg5ah = 0;
863
864 pci_read_config_byte(dev, 0x50, &reg50h);
865 pci_read_config_byte(dev, 0x52, &reg52h);
866 pci_read_config_byte(dev, 0x5a, &reg5ah);
867 printk("%s: (%s) reg50h=0x%02x, reg52h=0x%02x, reg5ah=0x%02x\n",
868 drive->name, __FUNCTION__, reg50h, reg52h, reg5ah);
869 if (reg5ah & 0x10)
870 pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
871#if 0
872 /* how about we flush and reset, mmmkay? */
873 pci_write_config_byte(dev, 0x51, 0x1F);
874 /* fall through to a reset */
875 case dma_start:
876 case ide_dma_end:
877 /* reset the chips state over and over.. */
878 pci_write_config_byte(dev, 0x51, 0x13);
879#endif
880 return __ide_dma_lostirq(drive);
881}
882
883static void hpt370_clear_engine (ide_drive_t *drive)
884{
885 u8 regstate = HWIF(drive)->channel ? 0x54 : 0x50;
886 pci_write_config_byte(HWIF(drive)->pci_dev, regstate, 0x37);
887 udelay(10);
888}
889
890static void hpt370_ide_dma_start(ide_drive_t *drive)
891{
892#ifdef HPT_RESET_STATE_ENGINE
893 hpt370_clear_engine(drive);
894#endif
895 ide_dma_start(drive);
896}
897
898static int hpt370_ide_dma_end (ide_drive_t *drive)
899{
900 ide_hwif_t *hwif = HWIF(drive);
901 u8 dma_stat = hwif->INB(hwif->dma_status);
902
903 if (dma_stat & 0x01) {
904 /* wait a little */
905 udelay(20);
906 dma_stat = hwif->INB(hwif->dma_status);
907 }
908 if ((dma_stat & 0x01) != 0)
909 /* fallthrough */
910 (void) HWIF(drive)->ide_dma_timeout(drive);
911
912 return __ide_dma_end(drive);
913}
914
915static void hpt370_lostirq_timeout (ide_drive_t *drive)
916{
917 ide_hwif_t *hwif = HWIF(drive);
918 u8 bfifo = 0, reginfo = hwif->channel ? 0x56 : 0x52;
919 u8 dma_stat = 0, dma_cmd = 0;
920
921 pci_read_config_byte(HWIF(drive)->pci_dev, reginfo, &bfifo);
922 printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
923 hpt370_clear_engine(drive);
924 /* get dma command mode */
925 dma_cmd = hwif->INB(hwif->dma_command);
926 /* stop dma */
927 hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
928 dma_stat = hwif->INB(hwif->dma_status);
929 /* clear errors */
930 hwif->OUTB(dma_stat | 0x6, hwif->dma_status);
931}
932
933static int hpt370_ide_dma_timeout (ide_drive_t *drive)
934{
935 hpt370_lostirq_timeout(drive);
936 hpt370_clear_engine(drive);
937 return __ide_dma_timeout(drive);
938}
939
940static int hpt370_ide_dma_lostirq (ide_drive_t *drive)
941{
942 hpt370_lostirq_timeout(drive);
943 hpt370_clear_engine(drive);
944 return __ide_dma_lostirq(drive);
945}
946
947/* returns 1 if DMA IRQ issued, 0 otherwise */
948static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
949{
950 ide_hwif_t *hwif = HWIF(drive);
951 u16 bfifo = 0;
952 u8 reginfo = hwif->channel ? 0x56 : 0x52;
953 u8 dma_stat;
954
955 pci_read_config_word(hwif->pci_dev, reginfo, &bfifo);
956 if (bfifo & 0x1FF) {
957// printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
958 return 0;
959 }
960
961 dma_stat = hwif->INB(hwif->dma_status);
962 /* return 1 if INTR asserted */
963 if ((dma_stat & 4) == 4)
964 return 1;
965
966 if (!drive->waiting_for_dma)
967 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
968 drive->name, __FUNCTION__);
969 return 0;
970}
971
972static int hpt374_ide_dma_end (ide_drive_t *drive)
973{
974 struct pci_dev *dev = HWIF(drive)->pci_dev;
975 ide_hwif_t *hwif = HWIF(drive);
976 u8 msc_stat = 0, mscreg = hwif->channel ? 0x54 : 0x50;
977 u8 bwsr_stat = 0, bwsr_mask = hwif->channel ? 0x02 : 0x01;
978
979 pci_read_config_byte(dev, 0x6a, &bwsr_stat);
980 pci_read_config_byte(dev, mscreg, &msc_stat);
981 if ((bwsr_stat & bwsr_mask) == bwsr_mask)
982 pci_write_config_byte(dev, mscreg, msc_stat|0x30);
983 return __ide_dma_end(drive);
984}
985
986/**
987 * hpt372n_set_clock - perform clock switching dance
988 * @drive: Drive to switch
989 * @mode: Switching mode (0x21 for write, 0x23 otherwise)
990 *
991 * Switch the DPLL clock on the HPT372N devices. This is a
992 * right mess.
993 */
994
995static void hpt372n_set_clock(ide_drive_t *drive, int mode)
996{
997 ide_hwif_t *hwif = HWIF(drive);
998
999 /* FIXME: should we check for DMA active and BUG() */
1000 /* Tristate the bus */
1001 outb(0x80, hwif->dma_base+0x73);
1002 outb(0x80, hwif->dma_base+0x77);
1003
1004 /* Switch clock and reset channels */
1005 outb(mode, hwif->dma_base+0x7B);
1006 outb(0xC0, hwif->dma_base+0x79);
1007
1008 /* Reset state machines */
1009 outb(0x37, hwif->dma_base+0x70);
1010 outb(0x37, hwif->dma_base+0x74);
1011
1012 /* Complete reset */
1013 outb(0x00, hwif->dma_base+0x79);
1014
1015 /* Reconnect channels to bus */
1016 outb(0x00, hwif->dma_base+0x73);
1017 outb(0x00, hwif->dma_base+0x77);
1018}
1019
1020/**
1021 * hpt372n_rw_disk - prepare for I/O
1022 * @drive: drive for command
1023 * @rq: block request structure
1024 *
1025 * This is called when a disk I/O is issued to the 372N.
1026 * We need it because of the clock switching.
1027 */
1028
1029static void hpt372n_rw_disk(ide_drive_t *drive, struct request *rq)
1030{
1031 ide_hwif_t *hwif = drive->hwif;
1032 int wantclock;
1033
1034 wantclock = rq_data_dir(rq) ? 0x23 : 0x21;
1035
1036 if (hwif->config_data != wantclock) {
1037 hpt372n_set_clock(drive, wantclock);
1038 hwif->config_data = wantclock;
1039 }
1040}
1041
1042/*
1043 * Since SUN Cobalt is attempting to do this operation, I should disclose
1044 * this has been a long time ago Thu Jul 27 16:40:57 2000 was the patch date
1045 * HOTSWAP ATA Infrastructure.
1046 */
1047
1048static void hpt3xx_reset (ide_drive_t *drive)
1049{
1050#if 0
1051 unsigned long high_16 = pci_resource_start(HWIF(drive)->pci_dev, 4);
1052 u8 reset = (HWIF(drive)->channel) ? 0x80 : 0x40;
1053 u8 reg59h = 0;
1054
1055 pci_read_config_byte(HWIF(drive)->pci_dev, 0x59, &reg59h);
1056 pci_write_config_byte(HWIF(drive)->pci_dev, 0x59, reg59h|reset);
1057 pci_write_config_byte(HWIF(drive)->pci_dev, 0x59, reg59h);
1058#endif
1059}
1060
1061static int hpt3xx_tristate (ide_drive_t * drive, int state)
1062{
1063 ide_hwif_t *hwif = HWIF(drive);
1064 struct pci_dev *dev = hwif->pci_dev;
1065 u8 reg59h = 0, reset = (hwif->channel) ? 0x80 : 0x40;
1066 u8 regXXh = 0, state_reg= (hwif->channel) ? 0x57 : 0x53;
1067
1068// hwif->bus_state = state;
1069
1070 pci_read_config_byte(dev, 0x59, &reg59h);
1071 pci_read_config_byte(dev, state_reg, &regXXh);
1072
1073 if (state) {
1074 (void) ide_do_reset(drive);
1075 pci_write_config_byte(dev, state_reg, regXXh|0x80);
1076 pci_write_config_byte(dev, 0x59, reg59h|reset);
1077 } else {
1078 pci_write_config_byte(dev, 0x59, reg59h & ~(reset));
1079 pci_write_config_byte(dev, state_reg, regXXh & ~(0x80));
1080 (void) ide_do_reset(drive);
1081 }
1082 return 0;
1083}
1084
1085/*
1086 * set/get power state for a drive.
1087 * turning the power off does the following things:
1088 * 1) soft-reset the drive
1089 * 2) tri-states the ide bus
1090 *
1091 * when we turn things back on, we need to re-initialize things.
1092 */
1093#define TRISTATE_BIT 0x8000
1094static int hpt370_busproc(ide_drive_t * drive, int state)
1095{
1096 ide_hwif_t *hwif = HWIF(drive);
1097 struct pci_dev *dev = hwif->pci_dev;
1098 u8 tristate = 0, resetmask = 0, bus_reg = 0;
1099 u16 tri_reg;
1100
1101 hwif->bus_state = state;
1102
1103 if (hwif->channel) {
1104 /* secondary channel */
1105 tristate = 0x56;
1106 resetmask = 0x80;
1107 } else {
1108 /* primary channel */
1109 tristate = 0x52;
1110 resetmask = 0x40;
1111 }
1112
1113 /* grab status */
1114 pci_read_config_word(dev, tristate, &tri_reg);
1115 pci_read_config_byte(dev, 0x59, &bus_reg);
1116
1117 /* set the state. we don't set it if we don't need to do so.
1118 * make sure that the drive knows that it has failed if it's off */
1119 switch (state) {
1120 case BUSSTATE_ON:
1121 hwif->drives[0].failures = 0;
1122 hwif->drives[1].failures = 0;
1123 if ((bus_reg & resetmask) == 0)
1124 return 0;
1125 tri_reg &= ~TRISTATE_BIT;
1126 bus_reg &= ~resetmask;
1127 break;
1128 case BUSSTATE_OFF:
1129 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
1130 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
1131 if ((tri_reg & TRISTATE_BIT) == 0 && (bus_reg & resetmask))
1132 return 0;
1133 tri_reg &= ~TRISTATE_BIT;
1134 bus_reg |= resetmask;
1135 break;
1136 case BUSSTATE_TRISTATE:
1137 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
1138 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
1139 if ((tri_reg & TRISTATE_BIT) && (bus_reg & resetmask))
1140 return 0;
1141 tri_reg |= TRISTATE_BIT;
1142 bus_reg |= resetmask;
1143 break;
1144 }
1145 pci_write_config_byte(dev, 0x59, bus_reg);
1146 pci_write_config_word(dev, tristate, tri_reg);
1147
1148 return 0;
1149}
1150
1151static int __devinit init_hpt37x(struct pci_dev *dev)
1152{
1153 int adjust, i;
1154 u16 freq;
1155 u32 pll;
1156 u8 reg5bh;
1157 u8 reg5ah = 0;
1158 unsigned long dmabase = pci_resource_start(dev, 4);
1159 u8 did, rid;
1160 int is_372n = 0;
1161
1162 pci_read_config_byte(dev, 0x5a, &reg5ah);
1163 /* interrupt force enable */
1164 pci_write_config_byte(dev, 0x5a, (reg5ah & ~0x10));
1165
1166 if(dmabase)
1167 {
1168 did = inb(dmabase + 0x22);
1169 rid = inb(dmabase + 0x28);
1170
1171 if((did == 4 && rid == 6) || (did == 5 && rid > 1))
1172 is_372n = 1;
1173 }
1174
1175 /*
1176 * default to pci clock. make sure MA15/16 are set to output
1177 * to prevent drives having problems with 40-pin cables.
1178 */
1179 pci_write_config_byte(dev, 0x5b, 0x23);
1180
1181 /*
1182 * set up the PLL. we need to adjust it so that it's stable.
1183 * freq = Tpll * 192 / Tpci
1184 *
1185 * Todo. For non x86 should probably check the dword is
1186 * set to 0xABCDExxx indicating the BIOS saved f_CNT
1187 */
1188 pci_read_config_word(dev, 0x78, &freq);
1189 freq &= 0x1FF;
1190
1191 /*
1192 * The 372N uses different PCI clock information and has
1193 * some other complications
1194 * On PCI33 timing we must clock switch
1195 * On PCI66 timing we must NOT use the PCI clock
1196 *
1197 * Currently we always set up the PLL for the 372N
1198 */
1199
1200 pci_set_drvdata(dev, NULL);
1201
1202 if(is_372n)
1203 {
1204 printk(KERN_INFO "hpt: HPT372N detected, using 372N timing.\n");
1205 if(freq < 0x55)
1206 pll = F_LOW_PCI_33;
1207 else if(freq < 0x70)
1208 pll = F_LOW_PCI_40;
1209 else if(freq < 0x7F)
1210 pll = F_LOW_PCI_50;
1211 else
1212 pll = F_LOW_PCI_66;
1213
1214 printk(KERN_INFO "FREQ: %d PLL: %d\n", freq, pll);
1215
1216 /* We always use the pll not the PCI clock on 372N */
1217 }
1218 else
1219 {
1220 if(freq < 0x9C)
1221 pll = F_LOW_PCI_33;
1222 else if(freq < 0xb0)
1223 pll = F_LOW_PCI_40;
1224 else if(freq <0xc8)
1225 pll = F_LOW_PCI_50;
1226 else
1227 pll = F_LOW_PCI_66;
1228
1229 if (pll == F_LOW_PCI_33) {
1230 if (hpt_minimum_revision(dev,8))
1231 pci_set_drvdata(dev, (void *) thirty_three_base_hpt374);
1232 else if (hpt_minimum_revision(dev,5))
1233 pci_set_drvdata(dev, (void *) thirty_three_base_hpt372);
1234 else if (hpt_minimum_revision(dev,4))
1235 pci_set_drvdata(dev, (void *) thirty_three_base_hpt370a);
1236 else
1237 pci_set_drvdata(dev, (void *) thirty_three_base_hpt370);
1238 printk("HPT37X: using 33MHz PCI clock\n");
1239 } else if (pll == F_LOW_PCI_40) {
1240 /* Unsupported */
1241 } else if (pll == F_LOW_PCI_50) {
1242 if (hpt_minimum_revision(dev,8))
1243 pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
1244 else if (hpt_minimum_revision(dev,5))
1245 pci_set_drvdata(dev, (void *) fifty_base_hpt372);
1246 else if (hpt_minimum_revision(dev,4))
1247 pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
1248 else
1249 pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
1250 printk("HPT37X: using 50MHz PCI clock\n");
1251 } else {
1252 if (hpt_minimum_revision(dev,8))
1253 {
1254 printk(KERN_ERR "HPT37x: 66MHz timings are not supported.\n");
1255 }
1256 else if (hpt_minimum_revision(dev,5))
1257 pci_set_drvdata(dev, (void *) sixty_six_base_hpt372);
1258 else if (hpt_minimum_revision(dev,4))
1259 pci_set_drvdata(dev, (void *) sixty_six_base_hpt370a);
1260 else
1261 pci_set_drvdata(dev, (void *) sixty_six_base_hpt370);
1262 printk("HPT37X: using 66MHz PCI clock\n");
1263 }
1264 }
1265
1266 /*
1267 * only try the pll if we don't have a table for the clock
1268 * speed that we're running at. NOTE: the internal PLL will
1269 * result in slow reads when using a 33MHz PCI clock. we also
1270 * don't like to use the PLL because it will cause glitches
1271 * on PRST/SRST when the HPT state engine gets reset.
1272 */
1273 if (pci_get_drvdata(dev))
1274 goto init_hpt37X_done;
1275
1276 /*
1277 * adjust PLL based upon PCI clock, enable it, and wait for
1278 * stabilization.
1279 */
1280 adjust = 0;
1281 freq = (pll < F_LOW_PCI_50) ? 2 : 4;
1282 while (adjust++ < 6) {
1283 pci_write_config_dword(dev, 0x5c, (freq + pll) << 16 |
1284 pll | 0x100);
1285
1286 /* wait for clock stabilization */
1287 for (i = 0; i < 0x50000; i++) {
1288 pci_read_config_byte(dev, 0x5b, &reg5bh);
1289 if (reg5bh & 0x80) {
1290 /* spin looking for the clock to destabilize */
1291 for (i = 0; i < 0x1000; ++i) {
1292 pci_read_config_byte(dev, 0x5b,
1293 &reg5bh);
1294 if ((reg5bh & 0x80) == 0)
1295 goto pll_recal;
1296 }
1297 pci_read_config_dword(dev, 0x5c, &pll);
1298 pci_write_config_dword(dev, 0x5c,
1299 pll & ~0x100);
1300 pci_write_config_byte(dev, 0x5b, 0x21);
1301 if (hpt_minimum_revision(dev,8))
1302 pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
1303 else if (hpt_minimum_revision(dev,5))
1304 pci_set_drvdata(dev, (void *) fifty_base_hpt372);
1305 else if (hpt_minimum_revision(dev,4))
1306 pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
1307 else
1308 pci_set_drvdata(dev, (void *) fifty_base_hpt370a);
1309 printk("HPT37X: using 50MHz internal PLL\n");
1310 goto init_hpt37X_done;
1311 }
1312 }
1313pll_recal:
1314 if (adjust & 1)
1315 pll -= (adjust >> 1);
1316 else
1317 pll += (adjust >> 1);
1318 }
1319
1320init_hpt37X_done:
1321 /* reset state engine */
1322 pci_write_config_byte(dev, 0x50, 0x37);
1323 pci_write_config_byte(dev, 0x54, 0x37);
1324 udelay(100);
1325 return 0;
1326}
1327
1328static int __devinit init_hpt366(struct pci_dev *dev)
1329{
1330 u32 reg1 = 0;
1331 u8 drive_fast = 0;
1332
1333 /*
1334 * Disable the "fast interrupt" prediction.
1335 */
1336 pci_read_config_byte(dev, 0x51, &drive_fast);
1337 if (drive_fast & 0x80)
1338 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
1339 pci_read_config_dword(dev, 0x40, &reg1);
1340
1341 /* detect bus speed by looking at control reg timing: */
1342 switch((reg1 >> 8) & 7) {
1343 case 5:
1344 pci_set_drvdata(dev, (void *) forty_base_hpt366);
1345 break;
1346 case 9:
1347 pci_set_drvdata(dev, (void *) twenty_five_base_hpt366);
1348 break;
1349 case 7:
1350 default:
1351 pci_set_drvdata(dev, (void *) thirty_three_base_hpt366);
1352 break;
1353 }
1354
1355 if (!pci_get_drvdata(dev))
1356 {
1357 printk(KERN_ERR "hpt366: unknown bus timing.\n");
1358 pci_set_drvdata(dev, NULL);
1359 }
1360 return 0;
1361}
1362
1363static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
1364{
1365 int ret = 0;
1366 u8 test = 0;
1367
1368 if (dev->resource[PCI_ROM_RESOURCE].start)
1369 pci_write_config_byte(dev, PCI_ROM_ADDRESS,
1370 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
1371
1372 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &test);
1373 if (test != (L1_CACHE_BYTES / 4))
1374 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
1375 (L1_CACHE_BYTES / 4));
1376
1377 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &test);
1378 if (test != 0x78)
1379 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1380
1381 pci_read_config_byte(dev, PCI_MIN_GNT, &test);
1382 if (test != 0x08)
1383 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1384
1385 pci_read_config_byte(dev, PCI_MAX_LAT, &test);
1386 if (test != 0x08)
1387 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1388
1389 if (hpt_minimum_revision(dev, 3)) {
1390 ret = init_hpt37x(dev);
1391 } else {
1392 ret =init_hpt366(dev);
1393 }
1394 if (ret)
1395 return ret;
1396
1397 return dev->irq;
1398}
1399
1400static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1401{
1402 struct pci_dev *dev = hwif->pci_dev;
1403 u8 ata66 = 0, regmask = (hwif->channel) ? 0x01 : 0x02;
1404 u8 did, rid;
1405 unsigned long dmabase = hwif->dma_base;
1406 int is_372n = 0;
1407
1408 if(dmabase)
1409 {
1410 did = inb(dmabase + 0x22);
1411 rid = inb(dmabase + 0x28);
1412
1413 if((did == 4 && rid == 6) || (did == 5 && rid > 1))
1414 is_372n = 1;
1415 }
1416
1417 hwif->tuneproc = &hpt3xx_tune_drive;
1418 hwif->speedproc = &hpt3xx_tune_chipset;
1419 hwif->quirkproc = &hpt3xx_quirkproc;
1420 hwif->intrproc = &hpt3xx_intrproc;
1421 hwif->maskproc = &hpt3xx_maskproc;
1422
1423 if(is_372n)
1424 hwif->rw_disk = &hpt372n_rw_disk;
1425
1426 /*
1427 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1428 * address lines to access an external eeprom. To read valid
1429 * cable detect state the pins must be enabled as inputs.
1430 */
1431 if (hpt_minimum_revision(dev, 8) && PCI_FUNC(dev->devfn) & 1) {
1432 /*
1433 * HPT374 PCI function 1
1434 * - set bit 15 of reg 0x52 to enable TCBLID as input
1435 * - set bit 15 of reg 0x56 to enable FCBLID as input
1436 */
1437 u16 mcr3, mcr6;
1438 pci_read_config_word(dev, 0x52, &mcr3);
1439 pci_read_config_word(dev, 0x56, &mcr6);
1440 pci_write_config_word(dev, 0x52, mcr3 | 0x8000);
1441 pci_write_config_word(dev, 0x56, mcr6 | 0x8000);
1442 /* now read cable id register */
1443 pci_read_config_byte(dev, 0x5a, &ata66);
1444 pci_write_config_word(dev, 0x52, mcr3);
1445 pci_write_config_word(dev, 0x56, mcr6);
1446 } else if (hpt_minimum_revision(dev, 3)) {
1447 /*
1448 * HPT370/372 and 374 pcifn 0
1449 * - clear bit 0 of 0x5b to enable P/SCBLID as inputs
1450 */
1451 u8 scr2;
1452 pci_read_config_byte(dev, 0x5b, &scr2);
1453 pci_write_config_byte(dev, 0x5b, scr2 & ~1);
1454 /* now read cable id register */
1455 pci_read_config_byte(dev, 0x5a, &ata66);
1456 pci_write_config_byte(dev, 0x5b, scr2);
1457 } else {
1458 pci_read_config_byte(dev, 0x5a, &ata66);
1459 }
1460
1461#ifdef DEBUG
1462 printk("HPT366: reg5ah=0x%02x ATA-%s Cable Port%d\n",
1463 ata66, (ata66 & regmask) ? "33" : "66",
1464 PCI_FUNC(hwif->pci_dev->devfn));
1465#endif /* DEBUG */
1466
1467#ifdef HPT_SERIALIZE_IO
1468 /* serialize access to this device */
1469 if (hwif->mate)
1470 hwif->serialized = hwif->mate->serialized = 1;
1471#endif
1472
1473 if (hpt_minimum_revision(dev,3)) {
1474 u8 reg5ah = 0;
1475 pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
1476 /*
1477 * set up ioctl for power status.
1478 * note: power affects both
1479 * drives on each channel
1480 */
1481 hwif->resetproc = &hpt3xx_reset;
1482 hwif->busproc = &hpt370_busproc;
1483// hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
1484 } else if (hpt_minimum_revision(dev,2)) {
1485 hwif->resetproc = &hpt3xx_reset;
1486 hwif->busproc = &hpt3xx_tristate;
1487 } else {
1488 hwif->resetproc = &hpt3xx_reset;
1489 hwif->busproc = &hpt3xx_tristate;
1490 }
1491
1492 if (!hwif->dma_base) {
1493 hwif->drives[0].autotune = 1;
1494 hwif->drives[1].autotune = 1;
1495 return;
1496 }
1497
1498 hwif->ultra_mask = 0x7f;
1499 hwif->mwdma_mask = 0x07;
1500
1501 if (!(hwif->udma_four))
1502 hwif->udma_four = ((ata66 & regmask) ? 0 : 1);
1503 hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
1504
1505 if (hpt_minimum_revision(dev,8)) {
1506 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1507 hwif->ide_dma_end = &hpt374_ide_dma_end;
1508 } else if (hpt_minimum_revision(dev,5)) {
1509 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1510 hwif->ide_dma_end = &hpt374_ide_dma_end;
1511 } else if (hpt_minimum_revision(dev,3)) {
1512 hwif->dma_start = &hpt370_ide_dma_start;
1513 hwif->ide_dma_end = &hpt370_ide_dma_end;
1514 hwif->ide_dma_timeout = &hpt370_ide_dma_timeout;
1515 hwif->ide_dma_lostirq = &hpt370_ide_dma_lostirq;
1516 } else if (hpt_minimum_revision(dev,2))
1517 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1518 else
1519 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1520
1521 if (!noautodma)
1522 hwif->autodma = 1;
1523 hwif->drives[0].autodma = hwif->autodma;
1524 hwif->drives[1].autodma = hwif->autodma;
1525}
1526
1527static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1528{
1529 u8 masterdma = 0, slavedma = 0;
1530 u8 dma_new = 0, dma_old = 0;
1531 u8 primary = hwif->channel ? 0x4b : 0x43;
1532 u8 secondary = hwif->channel ? 0x4f : 0x47;
1533 unsigned long flags;
1534
1535 if (!dmabase)
1536 return;
1537
1538 if(pci_get_drvdata(hwif->pci_dev) == NULL)
1539 {
1540 printk(KERN_WARNING "hpt: no known IDE timings, disabling DMA.\n");
1541 return;
1542 }
1543
1544 dma_old = hwif->INB(dmabase+2);
1545
1546 local_irq_save(flags);
1547
1548 dma_new = dma_old;
1549 pci_read_config_byte(hwif->pci_dev, primary, &masterdma);
1550 pci_read_config_byte(hwif->pci_dev, secondary, &slavedma);
1551
1552 if (masterdma & 0x30) dma_new |= 0x20;
1553 if (slavedma & 0x30) dma_new |= 0x40;
1554 if (dma_new != dma_old)
1555 hwif->OUTB(dma_new, dmabase+2);
1556
1557 local_irq_restore(flags);
1558
1559 ide_setup_dma(hwif, dmabase, 8);
1560}
1561
1562static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1563{
1564 struct pci_dev *findev = NULL;
1565
1566 if (PCI_FUNC(dev->devfn) & 1)
1567 return -ENODEV;
1568
1569 while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1570 if ((findev->vendor == dev->vendor) &&
1571 (findev->device == dev->device) &&
1572 ((findev->devfn - dev->devfn) == 1) &&
1573 (PCI_FUNC(findev->devfn) & 1)) {
1574 if (findev->irq != dev->irq) {
1575 /* FIXME: we need a core pci_set_interrupt() */
1576 findev->irq = dev->irq;
1577 printk(KERN_WARNING "%s: pci-config space interrupt "
1578 "fixed.\n", d->name);
1579 }
1580 return ide_setup_pci_devices(dev, findev, d);
1581 }
1582 }
1583 return ide_setup_pci_device(dev, d);
1584}
1585
1586static int __devinit init_setup_hpt37x(struct pci_dev *dev, ide_pci_device_t *d)
1587{
1588 return ide_setup_pci_device(dev, d);
1589}
1590
1591static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1592{
1593 struct pci_dev *findev = NULL;
1594 u8 pin1 = 0, pin2 = 0;
1595 unsigned int class_rev;
1596 char *chipset_names[] = {"HPT366", "HPT366", "HPT368",
1597 "HPT370", "HPT370A", "HPT372",
1598 "HPT372N" };
1599
1600 if (PCI_FUNC(dev->devfn) & 1)
1601 return -ENODEV;
1602
1603 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
1604 class_rev &= 0xff;
1605
1606 if(dev->device == PCI_DEVICE_ID_TTI_HPT372N)
1607 class_rev = 6;
1608
1609 if(class_rev <= 6)
1610 d->name = chipset_names[class_rev];
1611
1612 switch(class_rev) {
1613 case 6:
1614 case 5:
1615 case 4:
1616 case 3:
1617 goto init_single;
1618 default:
1619 break;
1620 }
1621
1622 d->channels = 1;
1623
1624 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1625 while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1626 if ((findev->vendor == dev->vendor) &&
1627 (findev->device == dev->device) &&
1628 ((findev->devfn - dev->devfn) == 1) &&
1629 (PCI_FUNC(findev->devfn) & 1)) {
1630 pci_read_config_byte(findev, PCI_INTERRUPT_PIN, &pin2);
1631 if ((pin1 != pin2) && (dev->irq == findev->irq)) {
1632 d->bootable = ON_BOARD;
1633 printk("%s: onboard version of chipset, "
1634 "pin1=%d pin2=%d\n", d->name,
1635 pin1, pin2);
1636 }
1637 return ide_setup_pci_devices(dev, findev, d);
1638 }
1639 }
1640init_single:
1641 return ide_setup_pci_device(dev, d);
1642}
1643
1644static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1645 { /* 0 */
1646 .name = "HPT366",
1647 .init_setup = init_setup_hpt366,
1648 .init_chipset = init_chipset_hpt366,
1649 .init_hwif = init_hwif_hpt366,
1650 .init_dma = init_dma_hpt366,
1651 .channels = 2,
1652 .autodma = AUTODMA,
1653 .bootable = OFF_BOARD,
1654 .extra = 240
1655 },{ /* 1 */
1656 .name = "HPT372A",
1657 .init_setup = init_setup_hpt37x,
1658 .init_chipset = init_chipset_hpt366,
1659 .init_hwif = init_hwif_hpt366,
1660 .init_dma = init_dma_hpt366,
1661 .channels = 2,
1662 .autodma = AUTODMA,
1663 .bootable = OFF_BOARD,
1664 },{ /* 2 */
1665 .name = "HPT302",
1666 .init_setup = init_setup_hpt37x,
1667 .init_chipset = init_chipset_hpt366,
1668 .init_hwif = init_hwif_hpt366,
1669 .init_dma = init_dma_hpt366,
1670 .channels = 2,
1671 .autodma = AUTODMA,
1672 .bootable = OFF_BOARD,
1673 },{ /* 3 */
1674 .name = "HPT371",
1675 .init_setup = init_setup_hpt37x,
1676 .init_chipset = init_chipset_hpt366,
1677 .init_hwif = init_hwif_hpt366,
1678 .init_dma = init_dma_hpt366,
1679 .channels = 2,
1680 .autodma = AUTODMA,
1681 .bootable = OFF_BOARD,
1682 },{ /* 4 */
1683 .name = "HPT374",
1684 .init_setup = init_setup_hpt374,
1685 .init_chipset = init_chipset_hpt366,
1686 .init_hwif = init_hwif_hpt366,
1687 .init_dma = init_dma_hpt366,
1688 .channels = 2, /* 4 */
1689 .autodma = AUTODMA,
1690 .bootable = OFF_BOARD,
1691 },{ /* 5 */
1692 .name = "HPT372N",
1693 .init_setup = init_setup_hpt37x,
1694 .init_chipset = init_chipset_hpt366,
1695 .init_hwif = init_hwif_hpt366,
1696 .init_dma = init_dma_hpt366,
1697 .channels = 2, /* 4 */
1698 .autodma = AUTODMA,
1699 .bootable = OFF_BOARD,
1700 }
1701};
1702
1703/**
1704 * hpt366_init_one - called when an HPT366 is found
1705 * @dev: the hpt366 device
1706 * @id: the matching pci id
1707 *
1708 * Called when the PCI registration layer (or the IDE initialization)
1709 * finds a device matching our IDE device tables.
1710 */
1711
1712static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1713{
1714 ide_pci_device_t *d = &hpt366_chipsets[id->driver_data];
1715
1716 return d->init_setup(dev, d);
1717}
1718
1719static struct pci_device_id hpt366_pci_tbl[] = {
1720 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1721 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1722 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1723 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
1724 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1725 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
1726 { 0, },
1727};
1728MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1729
1730static struct pci_driver driver = {
1731 .name = "HPT366_IDE",
1732 .id_table = hpt366_pci_tbl,
1733 .probe = hpt366_init_one,
1734};
1735
1736static int hpt366_ide_init(void)
1737{
1738 return ide_pci_register_driver(&driver);
1739}
1740
1741module_init(hpt366_ide_init);
1742
1743MODULE_AUTHOR("Andre Hedrick");
1744MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1745MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-13 09:58:54 -0500