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authorSergei Shtylyov <sshtylyov@ru.mvista.com>2006-12-13 03:35:49 -0500
committerLinus Torvalds <torvalds@woody.osdl.org>2006-12-13 12:05:55 -0500
commit9448732f6c9ef4932b226056338d1084f3669752 (patch)
tree8bd2e9bdb2e71b8a1b16471d3bef822d270d5686 /drivers/ide/pci/hpt366.c
parent836c0063c74cc088ffe370d007e1c6cac95e7caa (diff)
[PATCH] ide: fix HPT37x timing tables
Fix/remove bad/unused timing tables: HPT370/A 66 MHz tables weren't really needed (the chips are not UltraATA/133 capable and shouldn't support 66 MHz PCI) and had many modes over- and underclocked, HPT372 33 MHz table was in fact for 66 MHz and 50 MHz table missed UltraDMA mode 6, HPT374 33 MHz table was really for 50 MHz... (Actually, HPT370/A 33 MHz tables also have issues. e.g. HPT370 has PIO modes 0/1 overlocked.) There's also no need in the separate HPT374 tables because HPT372 timings should be the same (and those tables has UltraDMA mode 6 which HPT374 supports depending on HPT374_ALLOW_ATA133_6 #define)... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Cc: Bartlomiej Zolnierkiewicz <B.Zolnierkiewicz@elka.pw.edu.pl> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'drivers/ide/pci/hpt366.c')
-rw-r--r--drivers/ide/pci/hpt366.c149
1 files changed, 29 insertions, 120 deletions
diff --git a/drivers/ide/pci/hpt366.c b/drivers/ide/pci/hpt366.c
index 7534171c2c61..51f40f2db772 100644
--- a/drivers/ide/pci/hpt366.c
+++ b/drivers/ide/pci/hpt366.c
@@ -67,6 +67,10 @@
67 * - add support for HPT302N and HPT371N clocking (the same as for HPT372N) 67 * - add support for HPT302N and HPT371N clocking (the same as for HPT372N)
68 * - HPT371/N are single channel chips, so avoid touching the primary channel 68 * - HPT371/N are single channel chips, so avoid touching the primary channel
69 * which exists only virtually (there's no pins for it) 69 * which exists only virtually (there's no pins for it)
70 * - fix/remove bad/unused timing tables: HPT370/A 66 MHz tables weren't really
71 * needed and had many modes over- and underclocked, HPT372 33 MHz table was
72 * for 66 MHz and 50 MHz table missed UltraDMA mode 6, HPT374 33 MHz table was
73 * really for 50 MHz; switch to using HPT372 tables for HPT374...
70 * <source@mvista.com> 74 * <source@mvista.com>
71 * 75 *
72 */ 76 */
@@ -264,26 +268,6 @@ static struct chipset_bus_clock_list_entry thirty_three_base_hpt370[] = {
264 { 0, 0x06514e57 } 268 { 0, 0x06514e57 }
265}; 269};
266 270
267static struct chipset_bus_clock_list_entry sixty_six_base_hpt370[] = {
268 { XFER_UDMA_5, 0x14846231 },
269 { XFER_UDMA_4, 0x14886231 },
270 { XFER_UDMA_3, 0x148c6231 },
271 { XFER_UDMA_2, 0x148c6231 },
272 { XFER_UDMA_1, 0x14906231 },
273 { XFER_UDMA_0, 0x14986231 },
274
275 { XFER_MW_DMA_2, 0x26514e21 },
276 { XFER_MW_DMA_1, 0x26514e33 },
277 { XFER_MW_DMA_0, 0x26514e97 },
278
279 { XFER_PIO_4, 0x06514e21 },
280 { XFER_PIO_3, 0x06514e22 },
281 { XFER_PIO_2, 0x06514e33 },
282 { XFER_PIO_1, 0x06914e43 },
283 { XFER_PIO_0, 0x06914e57 },
284 { 0, 0x06514e57 }
285};
286
287/* these are the current (4 sep 2001) timings from highpoint */ 271/* these are the current (4 sep 2001) timings from highpoint */
288static struct chipset_bus_clock_list_entry thirty_three_base_hpt370a[] = { 272static struct chipset_bus_clock_list_entry thirty_three_base_hpt370a[] = {
289 { XFER_UDMA_5, 0x12446231 }, 273 { XFER_UDMA_5, 0x12446231 },
@@ -305,27 +289,6 @@ static struct chipset_bus_clock_list_entry thirty_three_base_hpt370a[] = {
305 { 0, 0x06814ea7 } 289 { 0, 0x06814ea7 }
306}; 290};
307 291
308/* 2x 33MHz timings */
309static struct chipset_bus_clock_list_entry sixty_six_base_hpt370a[] = {
310 { XFER_UDMA_5, 0x1488e673 },
311 { XFER_UDMA_4, 0x1488e673 },
312 { XFER_UDMA_3, 0x1498e673 },
313 { XFER_UDMA_2, 0x1490e673 },
314 { XFER_UDMA_1, 0x1498e677 },
315 { XFER_UDMA_0, 0x14a0e73f },
316
317 { XFER_MW_DMA_2, 0x2480fa73 },
318 { XFER_MW_DMA_1, 0x2480fa77 },
319 { XFER_MW_DMA_0, 0x2480fb3f },
320
321 { XFER_PIO_4, 0x0c82be73 },
322 { XFER_PIO_3, 0x0c82be95 },
323 { XFER_PIO_2, 0x0c82beb7 },
324 { XFER_PIO_1, 0x0d02bf37 },
325 { XFER_PIO_0, 0x0d02bf5f },
326 { 0, 0x0d02bf5f }
327};
328
329static struct chipset_bus_clock_list_entry fifty_base_hpt370a[] = { 292static struct chipset_bus_clock_list_entry fifty_base_hpt370a[] = {
330 { XFER_UDMA_5, 0x12848242 }, 293 { XFER_UDMA_5, 0x12848242 },
331 { XFER_UDMA_4, 0x12ac8242 }, 294 { XFER_UDMA_4, 0x12ac8242 },
@@ -347,27 +310,28 @@ static struct chipset_bus_clock_list_entry fifty_base_hpt370a[] = {
347}; 310};
348 311
349static struct chipset_bus_clock_list_entry thirty_three_base_hpt372[] = { 312static struct chipset_bus_clock_list_entry thirty_three_base_hpt372[] = {
350 { XFER_UDMA_6, 0x1c81dc62 }, 313 { XFER_UDMA_6, 0x12446231 }, /* 0x12646231 ?? */
351 { XFER_UDMA_5, 0x1c6ddc62 }, 314 { XFER_UDMA_5, 0x12446231 },
352 { XFER_UDMA_4, 0x1c8ddc62 }, 315 { XFER_UDMA_4, 0x12446231 },
353 { XFER_UDMA_3, 0x1c8edc62 }, /* checkme */ 316 { XFER_UDMA_3, 0x126c6231 },
354 { XFER_UDMA_2, 0x1c91dc62 }, 317 { XFER_UDMA_2, 0x12486231 },
355 { XFER_UDMA_1, 0x1c9adc62 }, /* checkme */ 318 { XFER_UDMA_1, 0x124c6233 },
356 { XFER_UDMA_0, 0x1c82dc62 }, /* checkme */ 319 { XFER_UDMA_0, 0x12506297 },
357
358 { XFER_MW_DMA_2, 0x2c829262 },
359 { XFER_MW_DMA_1, 0x2c829266 }, /* checkme */
360 { XFER_MW_DMA_0, 0x2c82922e }, /* checkme */
361 320
362 { XFER_PIO_4, 0x0c829c62 }, 321 { XFER_MW_DMA_2, 0x22406c31 },
363 { XFER_PIO_3, 0x0c829c84 }, 322 { XFER_MW_DMA_1, 0x22406c33 },
364 { XFER_PIO_2, 0x0c829ca6 }, 323 { XFER_MW_DMA_0, 0x22406c97 },
365 { XFER_PIO_1, 0x0d029d26 }, 324
366 { XFER_PIO_0, 0x0d029d5e }, 325 { XFER_PIO_4, 0x06414e31 },
367 { 0, 0x0d029d5e } 326 { XFER_PIO_3, 0x06414e42 },
327 { XFER_PIO_2, 0x06414e53 },
328 { XFER_PIO_1, 0x06814e93 },
329 { XFER_PIO_0, 0x06814ea7 },
330 { 0, 0x06814ea7 }
368}; 331};
369 332
370static struct chipset_bus_clock_list_entry fifty_base_hpt372[] = { 333static struct chipset_bus_clock_list_entry fifty_base_hpt372[] = {
334 { XFER_UDMA_6, 0x12848242 },
371 { XFER_UDMA_5, 0x12848242 }, 335 { XFER_UDMA_5, 0x12848242 },
372 { XFER_UDMA_4, 0x12ac8242 }, 336 { XFER_UDMA_4, 0x12ac8242 },
373 { XFER_UDMA_3, 0x128c8242 }, 337 { XFER_UDMA_3, 0x128c8242 },
@@ -389,7 +353,7 @@ static struct chipset_bus_clock_list_entry fifty_base_hpt372[] = {
389 353
390static struct chipset_bus_clock_list_entry sixty_six_base_hpt372[] = { 354static struct chipset_bus_clock_list_entry sixty_six_base_hpt372[] = {
391 { XFER_UDMA_6, 0x1c869c62 }, 355 { XFER_UDMA_6, 0x1c869c62 },
392 { XFER_UDMA_5, 0x1cae9c62 }, 356 { XFER_UDMA_5, 0x1cae9c62 }, /* 0x1c8a9c62 */
393 { XFER_UDMA_4, 0x1c8a9c62 }, 357 { XFER_UDMA_4, 0x1c8a9c62 },
394 { XFER_UDMA_3, 0x1c8e9c62 }, 358 { XFER_UDMA_3, 0x1c8e9c62 },
395 { XFER_UDMA_2, 0x1c929c62 }, 359 { XFER_UDMA_2, 0x1c929c62 },
@@ -408,50 +372,6 @@ static struct chipset_bus_clock_list_entry sixty_six_base_hpt372[] = {
408 { 0, 0x0d029d26 } 372 { 0, 0x0d029d26 }
409}; 373};
410 374
411static struct chipset_bus_clock_list_entry thirty_three_base_hpt374[] = {
412 { XFER_UDMA_6, 0x12808242 },
413 { XFER_UDMA_5, 0x12848242 },
414 { XFER_UDMA_4, 0x12ac8242 },
415 { XFER_UDMA_3, 0x128c8242 },
416 { XFER_UDMA_2, 0x120c8242 },
417 { XFER_UDMA_1, 0x12148254 },
418 { XFER_UDMA_0, 0x121882ea },
419
420 { XFER_MW_DMA_2, 0x22808242 },
421 { XFER_MW_DMA_1, 0x22808254 },
422 { XFER_MW_DMA_0, 0x228082ea },
423
424 { XFER_PIO_4, 0x0a81f442 },
425 { XFER_PIO_3, 0x0a81f443 },
426 { XFER_PIO_2, 0x0a81f454 },
427 { XFER_PIO_1, 0x0ac1f465 },
428 { XFER_PIO_0, 0x0ac1f48a },
429 { 0, 0x06814e93 }
430};
431
432/* FIXME: 50MHz timings for HPT374 */
433
434#if 0
435static struct chipset_bus_clock_list_entry sixty_six_base_hpt374[] = {
436 { XFER_UDMA_6, 0x12406231 }, /* checkme */
437 { XFER_UDMA_5, 0x12446231 }, /* 0x14846231 */
438 { XFER_UDMA_4, 0x16814ea7 }, /* 0x14886231 */
439 { XFER_UDMA_3, 0x16814ea7 }, /* 0x148c6231 */
440 { XFER_UDMA_2, 0x16814ea7 }, /* 0x148c6231 */
441 { XFER_UDMA_1, 0x16814ea7 }, /* 0x14906231 */
442 { XFER_UDMA_0, 0x16814ea7 }, /* 0x14986231 */
443 { XFER_MW_DMA_2, 0x16814ea7 }, /* 0x26514e21 */
444 { XFER_MW_DMA_1, 0x16814ea7 }, /* 0x26514e97 */
445 { XFER_MW_DMA_0, 0x16814ea7 }, /* 0x26514e97 */
446 { XFER_PIO_4, 0x06814ea7 }, /* 0x06514e21 */
447 { XFER_PIO_3, 0x06814ea7 }, /* 0x06514e22 */
448 { XFER_PIO_2, 0x06814ea7 }, /* 0x06514e33 */
449 { XFER_PIO_1, 0x06814ea7 }, /* 0x06914e43 */
450 { XFER_PIO_0, 0x06814ea7 }, /* 0x06914e57 */
451 { 0, 0x06814ea7 }
452};
453#endif
454
455#define HPT366_DEBUG_DRIVE_INFO 0 375#define HPT366_DEBUG_DRIVE_INFO 0
456#define HPT374_ALLOW_ATA133_6 0 376#define HPT374_ALLOW_ATA133_6 0
457#define HPT371_ALLOW_ATA133_6 0 377#define HPT371_ALLOW_ATA133_6 0
@@ -1211,9 +1131,7 @@ static void __devinit hpt37x_clocking(ide_hwif_t *hwif)
1211 pll = F_LOW_PCI_66; 1131 pll = F_LOW_PCI_66;
1212 1132
1213 if (pll == F_LOW_PCI_33) { 1133 if (pll == F_LOW_PCI_33) {
1214 if (info->revision >= 8) 1134 if (info->revision >= 5)
1215 info->speed = thirty_three_base_hpt374;
1216 else if (info->revision >= 5)
1217 info->speed = thirty_three_base_hpt372; 1135 info->speed = thirty_three_base_hpt372;
1218 else if (info->revision >= 4) 1136 else if (info->revision >= 4)
1219 info->speed = thirty_three_base_hpt370a; 1137 info->speed = thirty_three_base_hpt370a;
@@ -1223,26 +1141,17 @@ static void __devinit hpt37x_clocking(ide_hwif_t *hwif)
1223 } else if (pll == F_LOW_PCI_40) { 1141 } else if (pll == F_LOW_PCI_40) {
1224 /* Unsupported */ 1142 /* Unsupported */
1225 } else if (pll == F_LOW_PCI_50) { 1143 } else if (pll == F_LOW_PCI_50) {
1226 if (info->revision >= 8) 1144 if (info->revision >= 5)
1227 info->speed = fifty_base_hpt370a;
1228 else if (info->revision >= 5)
1229 info->speed = fifty_base_hpt372; 1145 info->speed = fifty_base_hpt372;
1230 else if (info->revision >= 4)
1231 info->speed = fifty_base_hpt370a;
1232 else 1146 else
1233 info->speed = fifty_base_hpt370a; 1147 info->speed = fifty_base_hpt370a;
1234 printk(KERN_DEBUG "HPT37X: using 50MHz PCI clock\n"); 1148 printk(KERN_DEBUG "HPT37X: using 50MHz PCI clock\n");
1235 } else { 1149 } else {
1236 if (info->revision >= 8) { 1150 if (info->revision >= 5) {
1237 printk(KERN_ERR "HPT37x: 66MHz timings are not supported.\n");
1238 }
1239 else if (info->revision >= 5)
1240 info->speed = sixty_six_base_hpt372; 1151 info->speed = sixty_six_base_hpt372;
1241 else if (info->revision >= 4) 1152 printk(KERN_DEBUG "HPT37X: using 66MHz PCI clock\n");
1242 info->speed = sixty_six_base_hpt370a; 1153 } else
1243 else 1154 printk(KERN_ERR "HPT37x: 66MHz timings not supported.\n");
1244 info->speed = sixty_six_base_hpt370;
1245 printk(KERN_DEBUG "HPT37X: using 66MHz PCI clock\n");
1246 } 1155 }
1247 } 1156 }
1248 1157
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