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authorSergei Shtylyov <sshtylyov@ru.mvista.com>2006-12-13 03:35:47 -0500
committerLinus Torvalds <torvalds@woody.osdl.org>2006-12-13 12:05:55 -0500
commit836c0063c74cc088ffe370d007e1c6cac95e7caa (patch)
tree1a8120b43384873a8a77ca8c39d2ec3ea5f0206a /drivers/ide/pci/hpt366.c
parentcd7175edf963a92b2c3cd491d3e34afd357e7284 (diff)
[PATCH] ide: HPT3xxN clocking fixes
Fix serious problems with the HPT372N clock turnaround code: - the wrong ports were written to when called for the secondary channel; - it didn't serialize access to the channels; - turnaround shou;dn't be done on 66 MHz PCI; - caching the clock mode per-channel caused it to get out of sync with the actual register value. Additionally, avoid calibrating PLL twice (for each channel) as the second try results in a wrong PCI frequency and thus in the wrong timings. Make the driver deal with HPT302N and HPT371N correctly -- the clocking and (seemingly) a need for clock tunaround is the same as for HPT372N. HPT371/N chips have only one, secondary channel, so avoid touching their "pure virtual" primary channel, and disable it if the BIOS haven't done this already. Also, while at it, disable UltraATA/133 for HPT372 by default -- 50 MHz DPLL clock don't allow for this speed anyway. And remove the traces of the former bad patch that wasn't even applicable to this version of driver. Has been tested on HPT370/371N, unfortunately I don't have an instant access to the other chips... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Cc: Bartlomiej Zolnierkiewicz <B.Zolnierkiewicz@elka.pw.edu.pl> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'drivers/ide/pci/hpt366.c')
-rw-r--r--drivers/ide/pci/hpt366.c223
1 files changed, 139 insertions, 84 deletions
diff --git a/drivers/ide/pci/hpt366.c b/drivers/ide/pci/hpt366.c
index e993a51f250e..7534171c2c61 100644
--- a/drivers/ide/pci/hpt366.c
+++ b/drivers/ide/pci/hpt366.c
@@ -4,6 +4,7 @@
4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> 4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
5 * Portions Copyright (C) 2001 Sun Microsystems, Inc. 5 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
6 * Portions Copyright (C) 2003 Red Hat Inc 6 * Portions Copyright (C) 2003 Red Hat Inc
7 * Portions Copyright (C) 2005-2006 MontaVista Software, Inc.
7 * 8 *
8 * Thanks to HighPoint Technologies for their assistance, and hardware. 9 * Thanks to HighPoint Technologies for their assistance, and hardware.
9 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his 10 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
@@ -11,9 +12,11 @@
11 * development and support. 12 * development and support.
12 * 13 *
13 * 14 *
14 * Highpoint have their own driver (source except for the raid part) 15 * HighPoint has its own drivers (open source except for the RAID part)
15 * available from http://www.highpoint-tech.com/hpt3xx-opensource-v131.tgz 16 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
16 * This may be useful to anyone wanting to work on the mainstream hpt IDE. 17 * This may be useful to anyone wanting to work on this driver, however do not
18 * trust them too much since the code tends to become less and less meaningful
19 * as the time passes... :-/
17 * 20 *
18 * Note that final HPT370 support was done by force extraction of GPL. 21 * Note that final HPT370 support was done by force extraction of GPL.
19 * 22 *
@@ -52,6 +55,20 @@
52 * keeping me sane. 55 * keeping me sane.
53 * Alan Cox <alan@redhat.com> 56 * Alan Cox <alan@redhat.com>
54 * 57 *
58 * - fix the clock turnaround code: it was writing to the wrong ports when
59 * called for the secondary channel, caching the current clock mode per-
60 * channel caused the cached register value to get out of sync with the
61 * actual one, the channels weren't serialized, the turnaround shouldn't
62 * be done on 66 MHz PCI bus
63 * - avoid calibrating PLL twice as the second time results in a wrong PCI
64 * frequency and thus in the wrong timings for the secondary channel
65 * - disable UltraATA/133 for HPT372 by default (50 MHz DPLL clock do not
66 * allow for this speed anyway)
67 * - add support for HPT302N and HPT371N clocking (the same as for HPT372N)
68 * - HPT371/N are single channel chips, so avoid touching the primary channel
69 * which exists only virtually (there's no pins for it)
70 * <source@mvista.com>
71 *
55 */ 72 */
56 73
57 74
@@ -76,8 +93,8 @@
76 93
77/* various tuning parameters */ 94/* various tuning parameters */
78#define HPT_RESET_STATE_ENGINE 95#define HPT_RESET_STATE_ENGINE
79#undef HPT_DELAY_INTERRUPT 96#undef HPT_DELAY_INTERRUPT
80#undef HPT_SERIALIZE_IO 97#define HPT_SERIALIZE_IO 0
81 98
82static const char *quirk_drives[] = { 99static const char *quirk_drives[] = {
83 "QUANTUM FIREBALLlct08 08", 100 "QUANTUM FIREBALLlct08 08",
@@ -439,7 +456,7 @@ static struct chipset_bus_clock_list_entry sixty_six_base_hpt374[] = {
439#define HPT374_ALLOW_ATA133_6 0 456#define HPT374_ALLOW_ATA133_6 0
440#define HPT371_ALLOW_ATA133_6 0 457#define HPT371_ALLOW_ATA133_6 0
441#define HPT302_ALLOW_ATA133_6 0 458#define HPT302_ALLOW_ATA133_6 0
442#define HPT372_ALLOW_ATA133_6 1 459#define HPT372_ALLOW_ATA133_6 0
443#define HPT370_ALLOW_ATA100_5 1 460#define HPT370_ALLOW_ATA100_5 1
444#define HPT366_ALLOW_ATA66_4 1 461#define HPT366_ALLOW_ATA66_4 1
445#define HPT366_ALLOW_ATA66_3 1 462#define HPT366_ALLOW_ATA66_3 1
@@ -461,7 +478,8 @@ struct hpt_info
461 int revision; /* Chipset revision */ 478 int revision; /* Chipset revision */
462 int flags; /* Chipset properties */ 479 int flags; /* Chipset properties */
463#define PLL_MODE 1 480#define PLL_MODE 1
464#define IS_372N 2 481#define IS_3xxN 2
482#define PCI_66MHZ 4
465 /* Speed table */ 483 /* Speed table */
466 struct chipset_bus_clock_list_entry *speed; 484 struct chipset_bus_clock_list_entry *speed;
467}; 485};
@@ -956,59 +974,63 @@ static int hpt374_ide_dma_end (ide_drive_t *drive)
956} 974}
957 975
958/** 976/**
959 * hpt372n_set_clock - perform clock switching dance 977 * hpt3xxn_set_clock - perform clock switching dance
960 * @drive: Drive to switch 978 * @hwif: hwif to switch
961 * @mode: Switching mode (0x21 for write, 0x23 otherwise) 979 * @mode: clocking mode (0x21 for write, 0x23 otherwise)
962 * 980 *
963 * Switch the DPLL clock on the HPT372N devices. This is a 981 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
964 * right mess. 982 * NOTE: avoid touching the disabled primary channel on HPT371N -- it
983 * doesn't physically exist anyway...
965 */ 984 */
966 985
967static void hpt372n_set_clock(ide_drive_t *drive, int mode) 986static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
968{ 987{
969 ide_hwif_t *hwif = HWIF(drive); 988 u8 mcr1, scr2 = hwif->INB(hwif->dma_master + 0x7b);
970 989
971 /* FIXME: should we check for DMA active and BUG() */ 990 if ((scr2 & 0x7f) == mode)
991 return;
992
993 /* MISC. control register 1 has the channel enable bit... */
994 mcr1 = hwif->INB(hwif->dma_master + 0x70);
995
972 /* Tristate the bus */ 996 /* Tristate the bus */
973 outb(0x80, hwif->dma_base+0x73); 997 if (mcr1 & 0x04)
974 outb(0x80, hwif->dma_base+0x77); 998 hwif->OUTB(0x80, hwif->dma_master + 0x73);
975 999 hwif->OUTB(0x80, hwif->dma_master + 0x77);
1000
976 /* Switch clock and reset channels */ 1001 /* Switch clock and reset channels */
977 outb(mode, hwif->dma_base+0x7B); 1002 hwif->OUTB(mode, hwif->dma_master + 0x7b);
978 outb(0xC0, hwif->dma_base+0x79); 1003 hwif->OUTB(0xc0, hwif->dma_master + 0x79);
979 1004
980 /* Reset state machines */ 1005 /* Reset state machines */
981 outb(0x37, hwif->dma_base+0x70); 1006 if (mcr1 & 0x04)
982 outb(0x37, hwif->dma_base+0x74); 1007 hwif->OUTB(0x37, hwif->dma_master + 0x70);
983 1008 hwif->OUTB(0x37, hwif->dma_master + 0x74);
1009
984 /* Complete reset */ 1010 /* Complete reset */
985 outb(0x00, hwif->dma_base+0x79); 1011 hwif->OUTB(0x00, hwif->dma_master + 0x79);
986 1012
987 /* Reconnect channels to bus */ 1013 /* Reconnect channels to bus */
988 outb(0x00, hwif->dma_base+0x73); 1014 if (mcr1 & 0x04)
989 outb(0x00, hwif->dma_base+0x77); 1015 hwif->OUTB(0x00, hwif->dma_master + 0x73);
1016 hwif->OUTB(0x00, hwif->dma_master + 0x77);
990} 1017}
991 1018
992/** 1019/**
993 * hpt372n_rw_disk - prepare for I/O 1020 * hpt3xxn_rw_disk - prepare for I/O
994 * @drive: drive for command 1021 * @drive: drive for command
995 * @rq: block request structure 1022 * @rq: block request structure
996 * 1023 *
997 * This is called when a disk I/O is issued to the 372N. 1024 * This is called when a disk I/O is issued to HPT3xxN.
998 * We need it because of the clock switching. 1025 * We need it because of the clock switching.
999 */ 1026 */
1000 1027
1001static void hpt372n_rw_disk(ide_drive_t *drive, struct request *rq) 1028static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
1002{ 1029{
1003 ide_hwif_t *hwif = drive->hwif; 1030 ide_hwif_t *hwif = HWIF(drive);
1004 int wantclock; 1031 u8 wantclock = rq_data_dir(rq) ? 0x23 : 0x21;
1005
1006 wantclock = rq_data_dir(rq) ? 0x23 : 0x21;
1007 1032
1008 if (hwif->config_data != wantclock) { 1033 hpt3xxn_set_clock(hwif, wantclock);
1009 hpt372n_set_clock(drive, wantclock);
1010 hwif->config_data = wantclock;
1011 }
1012} 1034}
1013 1035
1014/* 1036/*
@@ -1138,7 +1160,7 @@ static void __devinit hpt37x_clocking(ide_hwif_t *hwif)
1138 int adjust, i; 1160 int adjust, i;
1139 u16 freq; 1161 u16 freq;
1140 u32 pll; 1162 u32 pll;
1141 u8 reg5bh; 1163 u8 reg5bh = 0, mcr1 = 0;
1142 1164
1143 /* 1165 /*
1144 * default to pci clock. make sure MA15/16 are set to output 1166 * default to pci clock. make sure MA15/16 are set to output
@@ -1161,17 +1183,11 @@ static void __devinit hpt37x_clocking(ide_hwif_t *hwif)
1161 freq &= 0x1FF; 1183 freq &= 0x1FF;
1162 1184
1163 /* 1185 /*
1164 * The 372N uses different PCI clock information and has 1186 * HPT3xxN chips use different PCI clock information.
1165 * some other complications 1187 * Currently we always set up the PLL for them.
1166 * On PCI33 timing we must clock switch
1167 * On PCI66 timing we must NOT use the PCI clock
1168 *
1169 * Currently we always set up the PLL for the 372N
1170 */ 1188 */
1171 1189
1172 if(info->flags & IS_372N) 1190 if (info->flags & IS_3xxN) {
1173 {
1174 printk(KERN_INFO "hpt: HPT372N detected, using 372N timing.\n");
1175 if(freq < 0x55) 1191 if(freq < 0x55)
1176 pll = F_LOW_PCI_33; 1192 pll = F_LOW_PCI_33;
1177 else if(freq < 0x70) 1193 else if(freq < 0x70)
@@ -1180,10 +1196,8 @@ static void __devinit hpt37x_clocking(ide_hwif_t *hwif)
1180 pll = F_LOW_PCI_50; 1196 pll = F_LOW_PCI_50;
1181 else 1197 else
1182 pll = F_LOW_PCI_66; 1198 pll = F_LOW_PCI_66;
1183 1199
1184 printk(KERN_INFO "FREQ: %d PLL: %d\n", freq, pll); 1200 printk(KERN_INFO "HPT3xxN detected, FREQ: %d, PLL: %d\n", freq, pll);
1185
1186 /* We always use the pll not the PCI clock on 372N */
1187 } 1201 }
1188 else 1202 else
1189 { 1203 {
@@ -1231,7 +1245,10 @@ static void __devinit hpt37x_clocking(ide_hwif_t *hwif)
1231 printk(KERN_DEBUG "HPT37X: using 66MHz PCI clock\n"); 1245 printk(KERN_DEBUG "HPT37X: using 66MHz PCI clock\n");
1232 } 1246 }
1233 } 1247 }
1234 1248
1249 if (pll == F_LOW_PCI_66)
1250 info->flags |= PCI_66MHZ;
1251
1235 /* 1252 /*
1236 * only try the pll if we don't have a table for the clock 1253 * only try the pll if we don't have a table for the clock
1237 * speed that we're running at. NOTE: the internal PLL will 1254 * speed that we're running at. NOTE: the internal PLL will
@@ -1287,10 +1304,6 @@ static void __devinit hpt37x_clocking(ide_hwif_t *hwif)
1287 goto init_hpt37X_done; 1304 goto init_hpt37X_done;
1288 } 1305 }
1289 } 1306 }
1290 if (!pci_get_drvdata(dev)) {
1291 printk("No Clock Stabilization!!!\n");
1292 return;
1293 }
1294pll_recal: 1307pll_recal:
1295 if (adjust & 1) 1308 if (adjust & 1)
1296 pll -= (adjust >> 1); 1309 pll -= (adjust >> 1);
@@ -1300,11 +1313,16 @@ pll_recal:
1300 1313
1301init_hpt37X_done: 1314init_hpt37X_done:
1302 if (!info->speed) 1315 if (!info->speed)
1303 printk(KERN_ERR "HPT37X%s: unknown bus timing [%d %d].\n", 1316 printk(KERN_ERR "HPT37x%s: unknown bus timing [%d %d].\n",
1304 (info->flags & IS_372N)?"N":"", pll, freq); 1317 (info->flags & IS_3xxN) ? "N" : "", pll, freq);
1305 /* reset state engine */ 1318 /*
1306 pci_write_config_byte(dev, 0x50, 0x37); 1319 * Reset the state engines.
1307 pci_write_config_byte(dev, 0x54, 0x37); 1320 * NOTE: avoid accidentally enabling the primary channel on HPT371N.
1321 */
1322 pci_read_config_byte(dev, 0x50, &mcr1);
1323 if (mcr1 & 0x04)
1324 pci_write_config_byte(dev, 0x50, 0x37);
1325 pci_write_config_byte(dev, 0x54, 0x37);
1308 udelay(100); 1326 udelay(100);
1309} 1327}
1310 1328
@@ -1367,6 +1385,7 @@ static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1367 struct pci_dev *dev = hwif->pci_dev; 1385 struct pci_dev *dev = hwif->pci_dev;
1368 struct hpt_info *info = ide_get_hwifdata(hwif); 1386 struct hpt_info *info = ide_get_hwifdata(hwif);
1369 u8 ata66 = 0, regmask = (hwif->channel) ? 0x01 : 0x02; 1387 u8 ata66 = 0, regmask = (hwif->channel) ? 0x01 : 0x02;
1388 int serialize = HPT_SERIALIZE_IO;
1370 1389
1371 hwif->tuneproc = &hpt3xx_tune_drive; 1390 hwif->tuneproc = &hpt3xx_tune_drive;
1372 hwif->speedproc = &hpt3xx_tune_chipset; 1391 hwif->speedproc = &hpt3xx_tune_chipset;
@@ -1374,8 +1393,20 @@ static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1374 hwif->intrproc = &hpt3xx_intrproc; 1393 hwif->intrproc = &hpt3xx_intrproc;
1375 hwif->maskproc = &hpt3xx_maskproc; 1394 hwif->maskproc = &hpt3xx_maskproc;
1376 1395
1377 if(info->flags & IS_372N) 1396 /*
1378 hwif->rw_disk = &hpt372n_rw_disk; 1397 * HPT3xxN chips have some complications:
1398 *
1399 * - on 33 MHz PCI we must clock switch
1400 * - on 66 MHz PCI we must NOT use the PCI clock
1401 */
1402 if ((info->flags & (IS_3xxN | PCI_66MHZ)) == IS_3xxN) {
1403 /*
1404 * Clock is shared between the channels,
1405 * so we'll have to serialize them... :-(
1406 */
1407 serialize = 1;
1408 hwif->rw_disk = &hpt3xxn_rw_disk;
1409 }
1379 1410
1380 /* 1411 /*
1381 * The HPT37x uses the CBLID pins as outputs for MA15/MA16 1412 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
@@ -1418,11 +1449,9 @@ static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1418 PCI_FUNC(hwif->pci_dev->devfn)); 1449 PCI_FUNC(hwif->pci_dev->devfn));
1419#endif /* DEBUG */ 1450#endif /* DEBUG */
1420 1451
1421#ifdef HPT_SERIALIZE_IO 1452 /* Serialize access to this device */
1422 /* serialize access to this device */ 1453 if (serialize && hwif->mate)
1423 if (hwif->mate)
1424 hwif->serialized = hwif->mate->serialized = 1; 1454 hwif->serialized = hwif->mate->serialized = 1;
1425#endif
1426 1455
1427 if (info->revision >= 3) { 1456 if (info->revision >= 3) {
1428 u8 reg5ah = 0; 1457 u8 reg5ah = 0;
@@ -1490,7 +1519,7 @@ static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1490 return; 1519 return;
1491 1520
1492 if(info->speed == NULL) { 1521 if(info->speed == NULL) {
1493 printk(KERN_WARNING "hpt: no known IDE timings, disabling DMA.\n"); 1522 printk(KERN_WARNING "hpt366: no known IDE timings, disabling DMA.\n");
1494 return; 1523 return;
1495 } 1524 }
1496 1525
@@ -1519,9 +1548,10 @@ static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1519 1548
1520static void __devinit init_iops_hpt366(ide_hwif_t *hwif) 1549static void __devinit init_iops_hpt366(ide_hwif_t *hwif)
1521{ 1550{
1522 struct hpt_info *info = kzalloc(sizeof(struct hpt_info), GFP_KERNEL); 1551 struct hpt_info *info = kzalloc(sizeof(struct hpt_info), GFP_KERNEL);
1523 unsigned long dmabase = pci_resource_start(hwif->pci_dev, 4); 1552 struct pci_dev *dev = hwif->pci_dev;
1524 u8 did, rid; 1553 u16 did = dev->device;
1554 u8 rid = 0;
1525 1555
1526 if(info == NULL) { 1556 if(info == NULL) {
1527 printk(KERN_WARNING "hpt366: out of memory.\n"); 1557 printk(KERN_WARNING "hpt366: out of memory.\n");
@@ -1529,15 +1559,22 @@ static void __devinit init_iops_hpt366(ide_hwif_t *hwif)
1529 } 1559 }
1530 ide_set_hwifdata(hwif, info); 1560 ide_set_hwifdata(hwif, info);
1531 1561
1532 if(dmabase) { 1562 /* Avoid doing the same thing twice. */
1533 did = inb(dmabase + 0x22); 1563 if (hwif->channel && hwif->mate) {
1534 rid = inb(dmabase + 0x28); 1564 memcpy(info, ide_get_hwifdata(hwif->mate), sizeof(struct hpt_info));
1535 1565 return;
1536 if((did == 4 && rid == 6) || (did == 5 && rid > 1))
1537 info->flags |= IS_372N;
1538 } 1566 }
1539 1567
1540 info->revision = hpt_revision(hwif->pci_dev); 1568 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rid);
1569
1570 if (( did == PCI_DEVICE_ID_TTI_HPT366 && rid == 6) ||
1571 ((did == PCI_DEVICE_ID_TTI_HPT372 ||
1572 did == PCI_DEVICE_ID_TTI_HPT302 ||
1573 did == PCI_DEVICE_ID_TTI_HPT371) && rid > 1) ||
1574 did == PCI_DEVICE_ID_TTI_HPT372N)
1575 info->flags |= IS_3xxN;
1576
1577 info->revision = hpt_revision(dev);
1541 1578
1542 if (info->revision >= 3) 1579 if (info->revision >= 3)
1543 hpt37x_clocking(hwif); 1580 hpt37x_clocking(hwif);
@@ -1574,6 +1611,23 @@ static int __devinit init_setup_hpt37x(struct pci_dev *dev, ide_pci_device_t *d)
1574 return ide_setup_pci_device(dev, d); 1611 return ide_setup_pci_device(dev, d);
1575} 1612}
1576 1613
1614static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
1615{
1616 u8 mcr1 = 0;
1617
1618 /*
1619 * HPT371 chips physically have only one channel, the secondary one,
1620 * but the primary channel registers do exist! Go figure...
1621 * So, we manually disable the non-existing channel here
1622 * (if the BIOS hasn't done this already).
1623 */
1624 pci_read_config_byte(dev, 0x50, &mcr1);
1625 if (mcr1 & 0x04)
1626 pci_write_config_byte(dev, 0x50, (mcr1 & ~0x04));
1627
1628 return ide_setup_pci_device(dev, d);
1629}
1630
1577static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d) 1631static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1578{ 1632{
1579 struct pci_dev *findev = NULL; 1633 struct pci_dev *findev = NULL;
@@ -1661,13 +1715,14 @@ static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1661 .bootable = OFF_BOARD, 1715 .bootable = OFF_BOARD,
1662 },{ /* 3 */ 1716 },{ /* 3 */
1663 .name = "HPT371", 1717 .name = "HPT371",
1664 .init_setup = init_setup_hpt37x, 1718 .init_setup = init_setup_hpt371,
1665 .init_chipset = init_chipset_hpt366, 1719 .init_chipset = init_chipset_hpt366,
1666 .init_iops = init_iops_hpt366, 1720 .init_iops = init_iops_hpt366,
1667 .init_hwif = init_hwif_hpt366, 1721 .init_hwif = init_hwif_hpt366,
1668 .init_dma = init_dma_hpt366, 1722 .init_dma = init_dma_hpt366,
1669 .channels = 2, 1723 .channels = 2,
1670 .autodma = AUTODMA, 1724 .autodma = AUTODMA,
1725 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1671 .bootable = OFF_BOARD, 1726 .bootable = OFF_BOARD,
1672 },{ /* 4 */ 1727 },{ /* 4 */
1673 .name = "HPT374", 1728 .name = "HPT374",