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authorBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2008-10-21 14:57:23 -0400
committerBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2008-10-21 14:57:23 -0400
commit2bfba3c444fe8b2ab1c38112a89d8f03b61136ca (patch)
tree17580eee63d868c9d6b97a6bc956a08f25631532 /drivers/ide/pci/cmd64x.c
parent2515ddc6db8eb49a79f0fe5e67ff09ac7c81eab4 (diff)
ide: remove useless subdirs from drivers/ide/
Suggested-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Diffstat (limited to 'drivers/ide/pci/cmd64x.c')
-rw-r--r--drivers/ide/pci/cmd64x.c532
1 files changed, 0 insertions, 532 deletions
diff --git a/drivers/ide/pci/cmd64x.c b/drivers/ide/pci/cmd64x.c
deleted file mode 100644
index 935385c77e06..000000000000
--- a/drivers/ide/pci/cmd64x.c
+++ /dev/null
@@ -1,532 +0,0 @@
1/*
2 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
3 * Due to massive hardware bugs, UltraDMA is only supported
4 * on the 646U2 and not on the 646U.
5 *
6 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
7 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
8 *
9 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
10 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
11 */
12
13#include <linux/module.h>
14#include <linux/types.h>
15#include <linux/pci.h>
16#include <linux/ide.h>
17#include <linux/init.h>
18
19#include <asm/io.h>
20
21#define DRV_NAME "cmd64x"
22
23#define CMD_DEBUG 0
24
25#if CMD_DEBUG
26#define cmdprintk(x...) printk(x)
27#else
28#define cmdprintk(x...)
29#endif
30
31/*
32 * CMD64x specific registers definition.
33 */
34#define CFR 0x50
35#define CFR_INTR_CH0 0x04
36
37#define CMDTIM 0x52
38#define ARTTIM0 0x53
39#define DRWTIM0 0x54
40#define ARTTIM1 0x55
41#define DRWTIM1 0x56
42#define ARTTIM23 0x57
43#define ARTTIM23_DIS_RA2 0x04
44#define ARTTIM23_DIS_RA3 0x08
45#define ARTTIM23_INTR_CH1 0x10
46#define DRWTIM2 0x58
47#define BRST 0x59
48#define DRWTIM3 0x5b
49
50#define BMIDECR0 0x70
51#define MRDMODE 0x71
52#define MRDMODE_INTR_CH0 0x04
53#define MRDMODE_INTR_CH1 0x08
54#define UDIDETCR0 0x73
55#define DTPR0 0x74
56#define BMIDECR1 0x78
57#define BMIDECSR 0x79
58#define UDIDETCR1 0x7B
59#define DTPR1 0x7C
60
61static u8 quantize_timing(int timing, int quant)
62{
63 return (timing + quant - 1) / quant;
64}
65
66/*
67 * This routine calculates active/recovery counts and then writes them into
68 * the chipset registers.
69 */
70static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time)
71{
72 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
73 int clock_time = 1000 / (ide_pci_clk ? ide_pci_clk : 33);
74 u8 cycle_count, active_count, recovery_count, drwtim;
75 static const u8 recovery_values[] =
76 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
77 static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
78
79 cmdprintk("program_cycle_times parameters: total=%d, active=%d\n",
80 cycle_time, active_time);
81
82 cycle_count = quantize_timing( cycle_time, clock_time);
83 active_count = quantize_timing(active_time, clock_time);
84 recovery_count = cycle_count - active_count;
85
86 /*
87 * In case we've got too long recovery phase, try to lengthen
88 * the active phase
89 */
90 if (recovery_count > 16) {
91 active_count += recovery_count - 16;
92 recovery_count = 16;
93 }
94 if (active_count > 16) /* shouldn't actually happen... */
95 active_count = 16;
96
97 cmdprintk("Final counts: total=%d, active=%d, recovery=%d\n",
98 cycle_count, active_count, recovery_count);
99
100 /*
101 * Convert values to internal chipset representation
102 */
103 recovery_count = recovery_values[recovery_count];
104 active_count &= 0x0f;
105
106 /* Program the active/recovery counts into the DRWTIM register */
107 drwtim = (active_count << 4) | recovery_count;
108 (void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim);
109 cmdprintk("Write 0x%02x to reg 0x%x\n", drwtim, drwtim_regs[drive->dn]);
110}
111
112/*
113 * This routine writes into the chipset registers
114 * PIO setup/active/recovery timings.
115 */
116static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio)
117{
118 ide_hwif_t *hwif = HWIF(drive);
119 struct pci_dev *dev = to_pci_dev(hwif->dev);
120 struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
121 unsigned int cycle_time;
122 u8 setup_count, arttim = 0;
123
124 static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
125 static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
126
127 cycle_time = ide_pio_cycle_time(drive, pio);
128
129 program_cycle_times(drive, cycle_time, t->active);
130
131 setup_count = quantize_timing(t->setup,
132 1000 / (ide_pci_clk ? ide_pci_clk : 33));
133
134 /*
135 * The primary channel has individual address setup timing registers
136 * for each drive and the hardware selects the slowest timing itself.
137 * The secondary channel has one common register and we have to select
138 * the slowest address setup timing ourselves.
139 */
140 if (hwif->channel) {
141 ide_drive_t *drives = hwif->drives;
142
143 drive->drive_data = setup_count;
144 setup_count = max(drives[0].drive_data, drives[1].drive_data);
145 }
146
147 if (setup_count > 5) /* shouldn't actually happen... */
148 setup_count = 5;
149 cmdprintk("Final address setup count: %d\n", setup_count);
150
151 /*
152 * Program the address setup clocks into the ARTTIM registers.
153 * Avoid clearing the secondary channel's interrupt bit.
154 */
155 (void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
156 if (hwif->channel)
157 arttim &= ~ARTTIM23_INTR_CH1;
158 arttim &= ~0xc0;
159 arttim |= setup_values[setup_count];
160 (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
161 cmdprintk("Write 0x%02x to reg 0x%x\n", arttim, arttim_regs[drive->dn]);
162}
163
164/*
165 * Attempts to set drive's PIO mode.
166 * Special cases are 8: prefetch off, 9: prefetch on (both never worked)
167 */
168
169static void cmd64x_set_pio_mode(ide_drive_t *drive, const u8 pio)
170{
171 /*
172 * Filter out the prefetch control values
173 * to prevent PIO5 from being programmed
174 */
175 if (pio == 8 || pio == 9)
176 return;
177
178 cmd64x_tune_pio(drive, pio);
179}
180
181static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed)
182{
183 ide_hwif_t *hwif = HWIF(drive);
184 struct pci_dev *dev = to_pci_dev(hwif->dev);
185 u8 unit = drive->dn & 0x01;
186 u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0;
187
188 if (speed >= XFER_SW_DMA_0) {
189 (void) pci_read_config_byte(dev, pciU, &regU);
190 regU &= ~(unit ? 0xCA : 0x35);
191 }
192
193 switch(speed) {
194 case XFER_UDMA_5:
195 regU |= unit ? 0x0A : 0x05;
196 break;
197 case XFER_UDMA_4:
198 regU |= unit ? 0x4A : 0x15;
199 break;
200 case XFER_UDMA_3:
201 regU |= unit ? 0x8A : 0x25;
202 break;
203 case XFER_UDMA_2:
204 regU |= unit ? 0x42 : 0x11;
205 break;
206 case XFER_UDMA_1:
207 regU |= unit ? 0x82 : 0x21;
208 break;
209 case XFER_UDMA_0:
210 regU |= unit ? 0xC2 : 0x31;
211 break;
212 case XFER_MW_DMA_2:
213 program_cycle_times(drive, 120, 70);
214 break;
215 case XFER_MW_DMA_1:
216 program_cycle_times(drive, 150, 80);
217 break;
218 case XFER_MW_DMA_0:
219 program_cycle_times(drive, 480, 215);
220 break;
221 }
222
223 if (speed >= XFER_SW_DMA_0)
224 (void) pci_write_config_byte(dev, pciU, regU);
225}
226
227static int cmd648_dma_end(ide_drive_t *drive)
228{
229 ide_hwif_t *hwif = HWIF(drive);
230 unsigned long base = hwif->dma_base - (hwif->channel * 8);
231 int err = ide_dma_end(drive);
232 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
233 MRDMODE_INTR_CH0;
234 u8 mrdmode = inb(base + 1);
235
236 /* clear the interrupt bit */
237 outb((mrdmode & ~(MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1)) | irq_mask,
238 base + 1);
239
240 return err;
241}
242
243static int cmd64x_dma_end(ide_drive_t *drive)
244{
245 ide_hwif_t *hwif = HWIF(drive);
246 struct pci_dev *dev = to_pci_dev(hwif->dev);
247 int irq_reg = hwif->channel ? ARTTIM23 : CFR;
248 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
249 CFR_INTR_CH0;
250 u8 irq_stat = 0;
251 int err = ide_dma_end(drive);
252
253 (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
254 /* clear the interrupt bit */
255 (void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask);
256
257 return err;
258}
259
260static int cmd648_dma_test_irq(ide_drive_t *drive)
261{
262 ide_hwif_t *hwif = HWIF(drive);
263 unsigned long base = hwif->dma_base - (hwif->channel * 8);
264 u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 :
265 MRDMODE_INTR_CH0;
266 u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
267 u8 mrdmode = inb(base + 1);
268
269#ifdef DEBUG
270 printk("%s: dma_stat: 0x%02x mrdmode: 0x%02x irq_mask: 0x%02x\n",
271 drive->name, dma_stat, mrdmode, irq_mask);
272#endif
273 if (!(mrdmode & irq_mask))
274 return 0;
275
276 /* return 1 if INTR asserted */
277 if (dma_stat & 4)
278 return 1;
279
280 return 0;
281}
282
283static int cmd64x_dma_test_irq(ide_drive_t *drive)
284{
285 ide_hwif_t *hwif = HWIF(drive);
286 struct pci_dev *dev = to_pci_dev(hwif->dev);
287 int irq_reg = hwif->channel ? ARTTIM23 : CFR;
288 u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 :
289 CFR_INTR_CH0;
290 u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
291 u8 irq_stat = 0;
292
293 (void) pci_read_config_byte(dev, irq_reg, &irq_stat);
294
295#ifdef DEBUG
296 printk("%s: dma_stat: 0x%02x irq_stat: 0x%02x irq_mask: 0x%02x\n",
297 drive->name, dma_stat, irq_stat, irq_mask);
298#endif
299 if (!(irq_stat & irq_mask))
300 return 0;
301
302 /* return 1 if INTR asserted */
303 if (dma_stat & 4)
304 return 1;
305
306 return 0;
307}
308
309/*
310 * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
311 * event order for DMA transfers.
312 */
313
314static int cmd646_1_dma_end(ide_drive_t *drive)
315{
316 ide_hwif_t *hwif = HWIF(drive);
317 u8 dma_stat = 0, dma_cmd = 0;
318
319 drive->waiting_for_dma = 0;
320 /* get DMA status */
321 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
322 /* read DMA command state */
323 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
324 /* stop DMA */
325 outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
326 /* clear the INTR & ERROR bits */
327 outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS);
328 /* and free any DMA resources */
329 ide_destroy_dmatable(drive);
330 /* verify good DMA status */
331 return (dma_stat & 7) != 4;
332}
333
334static unsigned int init_chipset_cmd64x(struct pci_dev *dev)
335{
336 u8 mrdmode = 0;
337
338 /* Set a good latency timer and cache line size value. */
339 (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
340 /* FIXME: pci_set_master() to ensure a good latency timer value */
341
342 /*
343 * Enable interrupts, select MEMORY READ LINE for reads.
344 *
345 * NOTE: although not mentioned in the PCI0646U specs,
346 * bits 0-1 are write only and won't be read back as
347 * set or not -- PCI0646U2 specs clarify this point.
348 */
349 (void) pci_read_config_byte (dev, MRDMODE, &mrdmode);
350 mrdmode &= ~0x30;
351 (void) pci_write_config_byte(dev, MRDMODE, (mrdmode | 0x02));
352
353 return 0;
354}
355
356static u8 cmd64x_cable_detect(ide_hwif_t *hwif)
357{
358 struct pci_dev *dev = to_pci_dev(hwif->dev);
359 u8 bmidecsr = 0, mask = hwif->channel ? 0x02 : 0x01;
360
361 switch (dev->device) {
362 case PCI_DEVICE_ID_CMD_648:
363 case PCI_DEVICE_ID_CMD_649:
364 pci_read_config_byte(dev, BMIDECSR, &bmidecsr);
365 return (bmidecsr & mask) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
366 default:
367 return ATA_CBL_PATA40;
368 }
369}
370
371static const struct ide_port_ops cmd64x_port_ops = {
372 .set_pio_mode = cmd64x_set_pio_mode,
373 .set_dma_mode = cmd64x_set_dma_mode,
374 .cable_detect = cmd64x_cable_detect,
375};
376
377static const struct ide_dma_ops cmd64x_dma_ops = {
378 .dma_host_set = ide_dma_host_set,
379 .dma_setup = ide_dma_setup,
380 .dma_exec_cmd = ide_dma_exec_cmd,
381 .dma_start = ide_dma_start,
382 .dma_end = cmd64x_dma_end,
383 .dma_test_irq = cmd64x_dma_test_irq,
384 .dma_lost_irq = ide_dma_lost_irq,
385 .dma_timeout = ide_dma_timeout,
386};
387
388static const struct ide_dma_ops cmd646_rev1_dma_ops = {
389 .dma_host_set = ide_dma_host_set,
390 .dma_setup = ide_dma_setup,
391 .dma_exec_cmd = ide_dma_exec_cmd,
392 .dma_start = ide_dma_start,
393 .dma_end = cmd646_1_dma_end,
394 .dma_test_irq = ide_dma_test_irq,
395 .dma_lost_irq = ide_dma_lost_irq,
396 .dma_timeout = ide_dma_timeout,
397};
398
399static const struct ide_dma_ops cmd648_dma_ops = {
400 .dma_host_set = ide_dma_host_set,
401 .dma_setup = ide_dma_setup,
402 .dma_exec_cmd = ide_dma_exec_cmd,
403 .dma_start = ide_dma_start,
404 .dma_end = cmd648_dma_end,
405 .dma_test_irq = cmd648_dma_test_irq,
406 .dma_lost_irq = ide_dma_lost_irq,
407 .dma_timeout = ide_dma_timeout,
408};
409
410static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
411 { /* 0: CMD643 */
412 .name = DRV_NAME,
413 .init_chipset = init_chipset_cmd64x,
414 .enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
415 .port_ops = &cmd64x_port_ops,
416 .dma_ops = &cmd64x_dma_ops,
417 .host_flags = IDE_HFLAG_CLEAR_SIMPLEX |
418 IDE_HFLAG_ABUSE_PREFETCH,
419 .pio_mask = ATA_PIO5,
420 .mwdma_mask = ATA_MWDMA2,
421 .udma_mask = 0x00, /* no udma */
422 },
423 { /* 1: CMD646 */
424 .name = DRV_NAME,
425 .init_chipset = init_chipset_cmd64x,
426 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
427 .chipset = ide_cmd646,
428 .port_ops = &cmd64x_port_ops,
429 .dma_ops = &cmd648_dma_ops,
430 .host_flags = IDE_HFLAG_ABUSE_PREFETCH,
431 .pio_mask = ATA_PIO5,
432 .mwdma_mask = ATA_MWDMA2,
433 .udma_mask = ATA_UDMA2,
434 },
435 { /* 2: CMD648 */
436 .name = DRV_NAME,
437 .init_chipset = init_chipset_cmd64x,
438 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
439 .port_ops = &cmd64x_port_ops,
440 .dma_ops = &cmd648_dma_ops,
441 .host_flags = IDE_HFLAG_ABUSE_PREFETCH,
442 .pio_mask = ATA_PIO5,
443 .mwdma_mask = ATA_MWDMA2,
444 .udma_mask = ATA_UDMA4,
445 },
446 { /* 3: CMD649 */
447 .name = DRV_NAME,
448 .init_chipset = init_chipset_cmd64x,
449 .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
450 .port_ops = &cmd64x_port_ops,
451 .dma_ops = &cmd648_dma_ops,
452 .host_flags = IDE_HFLAG_ABUSE_PREFETCH,
453 .pio_mask = ATA_PIO5,
454 .mwdma_mask = ATA_MWDMA2,
455 .udma_mask = ATA_UDMA5,
456 }
457};
458
459static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
460{
461 struct ide_port_info d;
462 u8 idx = id->driver_data;
463
464 d = cmd64x_chipsets[idx];
465
466 if (idx == 1) {
467 /*
468 * UltraDMA only supported on PCI646U and PCI646U2, which
469 * correspond to revisions 0x03, 0x05 and 0x07 respectively.
470 * Actually, although the CMD tech support people won't
471 * tell me the details, the 0x03 revision cannot support
472 * UDMA correctly without hardware modifications, and even
473 * then it only works with Quantum disks due to some
474 * hold time assumptions in the 646U part which are fixed
475 * in the 646U2.
476 *
477 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
478 */
479 if (dev->revision < 5) {
480 d.udma_mask = 0x00;
481 /*
482 * The original PCI0646 didn't have the primary
483 * channel enable bit, it appeared starting with
484 * PCI0646U (i.e. revision ID 3).
485 */
486 if (dev->revision < 3) {
487 d.enablebits[0].reg = 0;
488 if (dev->revision == 1)
489 d.dma_ops = &cmd646_rev1_dma_ops;
490 else
491 d.dma_ops = &cmd64x_dma_ops;
492 }
493 }
494 }
495
496 return ide_pci_init_one(dev, &d, NULL);
497}
498
499static const struct pci_device_id cmd64x_pci_tbl[] = {
500 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_643), 0 },
501 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_646), 1 },
502 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_648), 2 },
503 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_CMD_649), 3 },
504 { 0, },
505};
506MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);
507
508static struct pci_driver cmd64x_pci_driver = {
509 .name = "CMD64x_IDE",
510 .id_table = cmd64x_pci_tbl,
511 .probe = cmd64x_init_one,
512 .remove = ide_pci_remove,
513 .suspend = ide_pci_suspend,
514 .resume = ide_pci_resume,
515};
516
517static int __init cmd64x_ide_init(void)
518{
519 return ide_pci_register_driver(&cmd64x_pci_driver);
520}
521
522static void __exit cmd64x_ide_exit(void)
523{
524 pci_unregister_driver(&cmd64x_pci_driver);
525}
526
527module_init(cmd64x_ide_init);
528module_exit(cmd64x_ide_exit);
529
530MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick");
531MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
532MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 09:20:43 -0500