diff options
author | Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> | 2007-10-19 18:32:30 -0400 |
---|---|---|
committer | Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> | 2007-10-19 18:32:30 -0400 |
commit | cad221aa82c6f434c1d78bee1d485b5b69c626f8 (patch) | |
tree | 83c9d96966abe922fe9a1d5ff262b3f07e7617b8 /drivers/ide/pci/alim15x3.c | |
parent | caea7602f309cbd55ba609800fd3c3e5d19ab684 (diff) |
alim15x3: fix CD_ROM DMA and PIO FIFO settings setup
* Setup CD_ROM DMA and PIO FIFO settings in init_chipset_ali15x3() instead
of ata66_ali15x3(). The latter is called from init_hwif_common_ali15x3()
only if DMA base exists (which insists m5529_revision > 0x20).
This changes makes CD_ROM DMA / PIO FIFO bits being set only once
and also when "idex=ata66" kernel parameter is used.
* While at it move also chip_is_1543c_e setup from ata66_ali15x3() to
init_chipset_ali15x3() and check if isa_dev exists before accessing it.
* Bump driver version.
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Diffstat (limited to 'drivers/ide/pci/alim15x3.c')
-rw-r--r-- | drivers/ide/pci/alim15x3.c | 60 |
1 files changed, 31 insertions, 29 deletions
diff --git a/drivers/ide/pci/alim15x3.c b/drivers/ide/pci/alim15x3.c index 8ee2b48d105d..1ab769b31e64 100644 --- a/drivers/ide/pci/alim15x3.c +++ b/drivers/ide/pci/alim15x3.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * linux/drivers/ide/pci/alim15x3.c Version 0.27 Aug 27 2007 | 2 | * linux/drivers/ide/pci/alim15x3.c Version 0.28 Sep 15 2007 |
3 | * | 3 | * |
4 | * Copyright (C) 1998-2000 Michel Aubry, Maintainer | 4 | * Copyright (C) 1998-2000 Michel Aubry, Maintainer |
5 | * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer | 5 | * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer |
@@ -492,6 +492,13 @@ static unsigned int __devinit init_chipset_ali15x3 (struct pci_dev *dev, const c | |||
492 | * clear bit 7 | 492 | * clear bit 7 |
493 | */ | 493 | */ |
494 | pci_write_config_byte(dev, 0x4b, tmpbyte & 0x7F); | 494 | pci_write_config_byte(dev, 0x4b, tmpbyte & 0x7F); |
495 | /* | ||
496 | * check m1533, 0x5e, bit 1~4 == 1001 => & 00011110 = 00010010 | ||
497 | */ | ||
498 | if (m5229_revision >= 0x20 && isa_dev) { | ||
499 | pci_read_config_byte(isa_dev, 0x5e, &tmpbyte); | ||
500 | chip_is_1543c_e = ((tmpbyte & 0x1e) == 0x12) ? 1: 0; | ||
501 | } | ||
495 | goto out; | 502 | goto out; |
496 | } | 503 | } |
497 | 504 | ||
@@ -537,7 +544,30 @@ static unsigned int __devinit init_chipset_ali15x3 (struct pci_dev *dev, const c | |||
537 | pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x02); | 544 | pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x02); |
538 | } | 545 | } |
539 | } | 546 | } |
547 | |||
540 | out: | 548 | out: |
549 | /* | ||
550 | * CD_ROM DMA on (m5229, 0x53, bit0) | ||
551 | * Enable this bit even if we want to use PIO. | ||
552 | * PIO FIFO off (m5229, 0x53, bit1) | ||
553 | * The hardware will use 0x54h and 0x55h to control PIO FIFO. | ||
554 | * (Not on later devices it seems) | ||
555 | * | ||
556 | * 0x53 changes meaning on later revs - we must no touch | ||
557 | * bit 1 on them. Need to check if 0x20 is the right break. | ||
558 | */ | ||
559 | if (m5229_revision >= 0x20) { | ||
560 | pci_read_config_byte(dev, 0x53, &tmpbyte); | ||
561 | |||
562 | if (m5229_revision <= 0x20) | ||
563 | tmpbyte = (tmpbyte & (~0x02)) | 0x01; | ||
564 | else if (m5229_revision == 0xc7 || m5229_revision == 0xc8) | ||
565 | tmpbyte |= 0x03; | ||
566 | else | ||
567 | tmpbyte |= 0x01; | ||
568 | |||
569 | pci_write_config_byte(dev, 0x53, tmpbyte); | ||
570 | } | ||
541 | pci_dev_put(north); | 571 | pci_dev_put(north); |
542 | pci_dev_put(isa_dev); | 572 | pci_dev_put(isa_dev); |
543 | local_irq_restore(flags); | 573 | local_irq_restore(flags); |
@@ -616,36 +646,8 @@ static u8 __devinit ata66_ali15x3(ide_hwif_t *hwif) | |||
616 | if ((tmpbyte & (1 << hwif->channel)) == 0) | 646 | if ((tmpbyte & (1 << hwif->channel)) == 0) |
617 | cbl = ATA_CBL_PATA80; | 647 | cbl = ATA_CBL_PATA80; |
618 | } | 648 | } |
619 | } else { | ||
620 | /* | ||
621 | * check m1533, 0x5e, bit 1~4 == 1001 => & 00011110 = 00010010 | ||
622 | */ | ||
623 | pci_read_config_byte(isa_dev, 0x5e, &tmpbyte); | ||
624 | chip_is_1543c_e = ((tmpbyte & 0x1e) == 0x12) ? 1: 0; | ||
625 | } | 649 | } |
626 | 650 | ||
627 | /* | ||
628 | * CD_ROM DMA on (m5229, 0x53, bit0) | ||
629 | * Enable this bit even if we want to use PIO | ||
630 | * PIO FIFO off (m5229, 0x53, bit1) | ||
631 | * The hardware will use 0x54h and 0x55h to control PIO FIFO | ||
632 | * (Not on later devices it seems) | ||
633 | * | ||
634 | * 0x53 changes meaning on later revs - we must no touch | ||
635 | * bit 1 on them. Need to check if 0x20 is the right break | ||
636 | */ | ||
637 | |||
638 | pci_read_config_byte(dev, 0x53, &tmpbyte); | ||
639 | |||
640 | if(m5229_revision <= 0x20) | ||
641 | tmpbyte = (tmpbyte & (~0x02)) | 0x01; | ||
642 | else if (m5229_revision == 0xc7 || m5229_revision == 0xc8) | ||
643 | tmpbyte |= 0x03; | ||
644 | else | ||
645 | tmpbyte |= 0x01; | ||
646 | |||
647 | pci_write_config_byte(dev, 0x53, tmpbyte); | ||
648 | |||
649 | local_irq_restore(flags); | 651 | local_irq_restore(flags); |
650 | 652 | ||
651 | return cbl; | 653 | return cbl; |