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authorDavid Brownell <dbrownell@users.sourceforge.net>2009-04-22 14:33:40 -0400
committerBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2009-04-22 14:33:40 -0400
commitdb2f38c22ea3f545be3b5772e5f9dc5861b74536 (patch)
tree57b07f93fb6e474761a31446c96a9821e1aa98d8 /drivers/ide/palm_bk3710.c
parent15da90b516e9da92cc1d90001e640fd6707d0e27 (diff)
palm_bk3710: UDMA performance fix
Fix UDMA throughput bug: tCYC averages t2CYCTYP/2, but the code previously assumed it was the same as t2CYCTYP. (That is, it was using just one clock edge, not both.) Move the table's type declaration so it's adjacent to the table, making it more clear what those numbers mean. On one system this change increased throughput by almost 4x: UDMA/66 sometimes topped 23 MB/sec (on a drive known to do much better). On another system it was around a 10% win (UDMA/66 up to 7+ MB/sec). The difference might be caused by the ratio between memory and IDE clocks. In the system with large speedup, this was exactly 2 (as a workaround for a rev 1.1 silicon bug). The other system used a more standard ratio of 1.63 (and rev 2.1 silicon) ... clock domain synch might have some issues, they're not unheard-of. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Acked-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Diffstat (limited to 'drivers/ide/palm_bk3710.c')
-rw-r--r--drivers/ide/palm_bk3710.c26
1 files changed, 12 insertions, 14 deletions
diff --git a/drivers/ide/palm_bk3710.c b/drivers/ide/palm_bk3710.c
index c7acca0b8733..d1513b4a457c 100644
--- a/drivers/ide/palm_bk3710.c
+++ b/drivers/ide/palm_bk3710.c
@@ -39,14 +39,6 @@
39/* Primary Control Offset */ 39/* Primary Control Offset */
40#define IDE_PALM_ATA_PRI_CTL_OFFSET 0x3F6 40#define IDE_PALM_ATA_PRI_CTL_OFFSET 0x3F6
41 41
42/*
43 * PalmChip 3710 IDE Controller UDMA timing structure Definition
44 */
45struct palm_bk3710_udmatiming {
46 unsigned int rptime; /* Ready to pause time */
47 unsigned int cycletime; /* Cycle Time */
48};
49
50#define BK3710_BMICP 0x00 42#define BK3710_BMICP 0x00
51#define BK3710_BMISP 0x02 43#define BK3710_BMISP 0x02
52#define BK3710_BMIDTP 0x04 44#define BK3710_BMIDTP 0x04
@@ -75,13 +67,19 @@ struct palm_bk3710_udmatiming {
75 67
76static unsigned ideclk_period; /* in nanoseconds */ 68static unsigned ideclk_period; /* in nanoseconds */
77 69
70struct palm_bk3710_udmatiming {
71 unsigned int rptime; /* tRP -- Ready to pause time (nsec) */
72 unsigned int cycletime; /* tCYCTYP2/2 -- avg Cycle Time (nsec) */
73 /* tENV is always a minimum of 20 nsec */
74};
75
78static const struct palm_bk3710_udmatiming palm_bk3710_udmatimings[6] = { 76static const struct palm_bk3710_udmatiming palm_bk3710_udmatimings[6] = {
79 {160, 240}, /* UDMA Mode 0 */ 77 {160, 240 / 2,}, /* UDMA Mode 0 */
80 {125, 160}, /* UDMA Mode 1 */ 78 {125, 160 / 2,}, /* UDMA Mode 1 */
81 {100, 120}, /* UDMA Mode 2 */ 79 {100, 120 / 2,}, /* UDMA Mode 2 */
82 {100, 90}, /* UDMA Mode 3 */ 80 {100, 90 / 2,}, /* UDMA Mode 3 */
83 {100, 60}, /* UDMA Mode 4 */ 81 {100, 60 / 2,}, /* UDMA Mode 4 */
84 {85, 40}, /* UDMA Mode 5 */ 82 {85, 40 / 2,}, /* UDMA Mode 5 */
85}; 83};
86 84
87static void palm_bk3710_setudmamode(void __iomem *base, unsigned int dev, 85static void palm_bk3710_setudmamode(void __iomem *base, unsigned int dev,