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authorBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2008-10-21 14:57:23 -0400
committerBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2008-10-21 14:57:23 -0400
commit2bfba3c444fe8b2ab1c38112a89d8f03b61136ca (patch)
tree17580eee63d868c9d6b97a6bc956a08f25631532 /drivers/ide/it821x.c
parent2515ddc6db8eb49a79f0fe5e67ff09ac7c81eab4 (diff)
ide: remove useless subdirs from drivers/ide/
Suggested-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Diffstat (limited to 'drivers/ide/it821x.c')
-rw-r--r--drivers/ide/it821x.c706
1 files changed, 706 insertions, 0 deletions
diff --git a/drivers/ide/it821x.c b/drivers/ide/it821x.c
new file mode 100644
index 000000000000..995e18bb3139
--- /dev/null
+++ b/drivers/ide/it821x.c
@@ -0,0 +1,706 @@
1/*
2 * Copyright (C) 2004 Red Hat <alan@redhat.com>
3 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
4 *
5 * May be copied or modified under the terms of the GNU General Public License
6 * Based in part on the ITE vendor provided SCSI driver.
7 *
8 * Documentation available from
9 * http://www.ite.com.tw/pc/IT8212F_V04.pdf
10 * Some other documents are NDA.
11 *
12 * The ITE8212 isn't exactly a standard IDE controller. It has two
13 * modes. In pass through mode then it is an IDE controller. In its smart
14 * mode its actually quite a capable hardware raid controller disguised
15 * as an IDE controller. Smart mode only understands DMA read/write and
16 * identify, none of the fancier commands apply. The IT8211 is identical
17 * in other respects but lacks the raid mode.
18 *
19 * Errata:
20 * o Rev 0x10 also requires master/slave hold the same DMA timings and
21 * cannot do ATAPI MWDMA.
22 * o The identify data for raid volumes lacks CHS info (technically ok)
23 * but also fails to set the LBA28 and other bits. We fix these in
24 * the IDE probe quirk code.
25 * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode
26 * raid then the controller firmware dies
27 * o Smart mode without RAID doesn't clear all the necessary identify
28 * bits to reduce the command set to the one used
29 *
30 * This has a few impacts on the driver
31 * - In pass through mode we do all the work you would expect
32 * - In smart mode the clocking set up is done by the controller generally
33 * but we must watch the other limits and filter.
34 * - There are a few extra vendor commands that actually talk to the
35 * controller but only work PIO with no IRQ.
36 *
37 * Vendor areas of the identify block in smart mode are used for the
38 * timing and policy set up. Each HDD in raid mode also has a serial
39 * block on the disk. The hardware extra commands are get/set chip status,
40 * rebuild, get rebuild status.
41 *
42 * In Linux the driver supports pass through mode as if the device was
43 * just another IDE controller. If the smart mode is running then
44 * volumes are managed by the controller firmware and each IDE "disk"
45 * is a raid volume. Even more cute - the controller can do automated
46 * hotplug and rebuild.
47 *
48 * The pass through controller itself is a little demented. It has a
49 * flaw that it has a single set of PIO/MWDMA timings per channel so
50 * non UDMA devices restrict each others performance. It also has a
51 * single clock source per channel so mixed UDMA100/133 performance
52 * isn't perfect and we have to pick a clock. Thankfully none of this
53 * matters in smart mode. ATAPI DMA is not currently supported.
54 *
55 * It seems the smart mode is a win for RAID1/RAID10 but otherwise not.
56 *
57 * TODO
58 * - ATAPI UDMA is ok but not MWDMA it seems
59 * - RAID configuration ioctls
60 * - Move to libata once it grows up
61 */
62
63#include <linux/types.h>
64#include <linux/module.h>
65#include <linux/pci.h>
66#include <linux/ide.h>
67#include <linux/init.h>
68
69#define DRV_NAME "it821x"
70
71struct it821x_dev
72{
73 unsigned int smart:1, /* Are we in smart raid mode */
74 timing10:1; /* Rev 0x10 */
75 u8 clock_mode; /* 0, ATA_50 or ATA_66 */
76 u8 want[2][2]; /* Mode/Pri log for master slave */
77 /* We need these for switching the clock when DMA goes on/off
78 The high byte is the 66Mhz timing */
79 u16 pio[2]; /* Cached PIO values */
80 u16 mwdma[2]; /* Cached MWDMA values */
81 u16 udma[2]; /* Cached UDMA values (per drive) */
82};
83
84#define ATA_66 0
85#define ATA_50 1
86#define ATA_ANY 2
87
88#define UDMA_OFF 0
89#define MWDMA_OFF 0
90
91/*
92 * We allow users to force the card into non raid mode without
93 * flashing the alternative BIOS. This is also necessary right now
94 * for embedded platforms that cannot run a PC BIOS but are using this
95 * device.
96 */
97
98static int it8212_noraid;
99
100/**
101 * it821x_program - program the PIO/MWDMA registers
102 * @drive: drive to tune
103 * @timing: timing info
104 *
105 * Program the PIO/MWDMA timing for this channel according to the
106 * current clock.
107 */
108
109static void it821x_program(ide_drive_t *drive, u16 timing)
110{
111 ide_hwif_t *hwif = drive->hwif;
112 struct pci_dev *dev = to_pci_dev(hwif->dev);
113 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
114 int channel = hwif->channel;
115 u8 conf;
116
117 /* Program PIO/MWDMA timing bits */
118 if(itdev->clock_mode == ATA_66)
119 conf = timing >> 8;
120 else
121 conf = timing & 0xFF;
122
123 pci_write_config_byte(dev, 0x54 + 4 * channel, conf);
124}
125
126/**
127 * it821x_program_udma - program the UDMA registers
128 * @drive: drive to tune
129 * @timing: timing info
130 *
131 * Program the UDMA timing for this drive according to the
132 * current clock.
133 */
134
135static void it821x_program_udma(ide_drive_t *drive, u16 timing)
136{
137 ide_hwif_t *hwif = drive->hwif;
138 struct pci_dev *dev = to_pci_dev(hwif->dev);
139 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
140 int channel = hwif->channel;
141 u8 unit = drive->dn & 1, conf;
142
143 /* Program UDMA timing bits */
144 if(itdev->clock_mode == ATA_66)
145 conf = timing >> 8;
146 else
147 conf = timing & 0xFF;
148
149 if (itdev->timing10 == 0)
150 pci_write_config_byte(dev, 0x56 + 4 * channel + unit, conf);
151 else {
152 pci_write_config_byte(dev, 0x56 + 4 * channel, conf);
153 pci_write_config_byte(dev, 0x56 + 4 * channel + 1, conf);
154 }
155}
156
157/**
158 * it821x_clock_strategy
159 * @drive: drive to set up
160 *
161 * Select between the 50 and 66Mhz base clocks to get the best
162 * results for this interface.
163 */
164
165static void it821x_clock_strategy(ide_drive_t *drive)
166{
167 ide_hwif_t *hwif = drive->hwif;
168 struct pci_dev *dev = to_pci_dev(hwif->dev);
169 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
170 ide_drive_t *pair;
171 int clock, altclock, sel = 0;
172 u8 unit = drive->dn & 1, v;
173
174 pair = &hwif->drives[1 - unit];
175
176 if(itdev->want[0][0] > itdev->want[1][0]) {
177 clock = itdev->want[0][1];
178 altclock = itdev->want[1][1];
179 } else {
180 clock = itdev->want[1][1];
181 altclock = itdev->want[0][1];
182 }
183
184 /*
185 * if both clocks can be used for the mode with the higher priority
186 * use the clock needed by the mode with the lower priority
187 */
188 if (clock == ATA_ANY)
189 clock = altclock;
190
191 /* Nobody cares - keep the same clock */
192 if(clock == ATA_ANY)
193 return;
194 /* No change */
195 if(clock == itdev->clock_mode)
196 return;
197
198 /* Load this into the controller ? */
199 if(clock == ATA_66)
200 itdev->clock_mode = ATA_66;
201 else {
202 itdev->clock_mode = ATA_50;
203 sel = 1;
204 }
205
206 pci_read_config_byte(dev, 0x50, &v);
207 v &= ~(1 << (1 + hwif->channel));
208 v |= sel << (1 + hwif->channel);
209 pci_write_config_byte(dev, 0x50, v);
210
211 /*
212 * Reprogram the UDMA/PIO of the pair drive for the switch
213 * MWDMA will be dealt with by the dma switcher
214 */
215 if(pair && itdev->udma[1-unit] != UDMA_OFF) {
216 it821x_program_udma(pair, itdev->udma[1-unit]);
217 it821x_program(pair, itdev->pio[1-unit]);
218 }
219 /*
220 * Reprogram the UDMA/PIO of our drive for the switch.
221 * MWDMA will be dealt with by the dma switcher
222 */
223 if(itdev->udma[unit] != UDMA_OFF) {
224 it821x_program_udma(drive, itdev->udma[unit]);
225 it821x_program(drive, itdev->pio[unit]);
226 }
227}
228
229/**
230 * it821x_set_pio_mode - set host controller for PIO mode
231 * @drive: drive
232 * @pio: PIO mode number
233 *
234 * Tune the host to the desired PIO mode taking into the consideration
235 * the maximum PIO mode supported by the other device on the cable.
236 */
237
238static void it821x_set_pio_mode(ide_drive_t *drive, const u8 pio)
239{
240 ide_hwif_t *hwif = drive->hwif;
241 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
242 ide_drive_t *pair;
243 u8 unit = drive->dn & 1, set_pio = pio;
244
245 /* Spec says 89 ref driver uses 88 */
246 static u16 pio_timings[]= { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 };
247 static u8 pio_want[] = { ATA_66, ATA_66, ATA_66, ATA_66, ATA_ANY };
248
249 pair = &hwif->drives[1 - unit];
250
251 /*
252 * Compute the best PIO mode we can for a given device. We must
253 * pick a speed that does not cause problems with the other device
254 * on the cable.
255 */
256 if (pair) {
257 u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4);
258 /* trim PIO to the slowest of the master/slave */
259 if (pair_pio < set_pio)
260 set_pio = pair_pio;
261 }
262
263 /* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */
264 itdev->want[unit][1] = pio_want[set_pio];
265 itdev->want[unit][0] = 1; /* PIO is lowest priority */
266 itdev->pio[unit] = pio_timings[set_pio];
267 it821x_clock_strategy(drive);
268 it821x_program(drive, itdev->pio[unit]);
269}
270
271/**
272 * it821x_tune_mwdma - tune a channel for MWDMA
273 * @drive: drive to set up
274 * @mode_wanted: the target operating mode
275 *
276 * Load the timing settings for this device mode into the
277 * controller when doing MWDMA in pass through mode. The caller
278 * must manage the whole lack of per device MWDMA/PIO timings and
279 * the shared MWDMA/PIO timing register.
280 */
281
282static void it821x_tune_mwdma (ide_drive_t *drive, byte mode_wanted)
283{
284 ide_hwif_t *hwif = drive->hwif;
285 struct pci_dev *dev = to_pci_dev(hwif->dev);
286 struct it821x_dev *itdev = (void *)ide_get_hwifdata(hwif);
287 u8 unit = drive->dn & 1, channel = hwif->channel, conf;
288
289 static u16 dma[] = { 0x8866, 0x3222, 0x3121 };
290 static u8 mwdma_want[] = { ATA_ANY, ATA_66, ATA_ANY };
291
292 itdev->want[unit][1] = mwdma_want[mode_wanted];
293 itdev->want[unit][0] = 2; /* MWDMA is low priority */
294 itdev->mwdma[unit] = dma[mode_wanted];
295 itdev->udma[unit] = UDMA_OFF;
296
297 /* UDMA bits off - Revision 0x10 do them in pairs */
298 pci_read_config_byte(dev, 0x50, &conf);
299 if (itdev->timing10)
300 conf |= channel ? 0x60: 0x18;
301 else
302 conf |= 1 << (3 + 2 * channel + unit);
303 pci_write_config_byte(dev, 0x50, conf);
304
305 it821x_clock_strategy(drive);
306 /* FIXME: do we need to program this ? */
307 /* it821x_program(drive, itdev->mwdma[unit]); */
308}
309
310/**
311 * it821x_tune_udma - tune a channel for UDMA
312 * @drive: drive to set up
313 * @mode_wanted: the target operating mode
314 *
315 * Load the timing settings for this device mode into the
316 * controller when doing UDMA modes in pass through.
317 */
318
319static void it821x_tune_udma (ide_drive_t *drive, byte mode_wanted)
320{
321 ide_hwif_t *hwif = drive->hwif;
322 struct pci_dev *dev = to_pci_dev(hwif->dev);
323 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
324 u8 unit = drive->dn & 1, channel = hwif->channel, conf;
325
326 static u16 udma[] = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 };
327 static u8 udma_want[] = { ATA_ANY, ATA_50, ATA_ANY, ATA_66, ATA_66, ATA_50, ATA_66 };
328
329 itdev->want[unit][1] = udma_want[mode_wanted];
330 itdev->want[unit][0] = 3; /* UDMA is high priority */
331 itdev->mwdma[unit] = MWDMA_OFF;
332 itdev->udma[unit] = udma[mode_wanted];
333 if(mode_wanted >= 5)
334 itdev->udma[unit] |= 0x8080; /* UDMA 5/6 select on */
335
336 /* UDMA on. Again revision 0x10 must do the pair */
337 pci_read_config_byte(dev, 0x50, &conf);
338 if (itdev->timing10)
339 conf &= channel ? 0x9F: 0xE7;
340 else
341 conf &= ~ (1 << (3 + 2 * channel + unit));
342 pci_write_config_byte(dev, 0x50, conf);
343
344 it821x_clock_strategy(drive);
345 it821x_program_udma(drive, itdev->udma[unit]);
346
347}
348
349/**
350 * it821x_dma_read - DMA hook
351 * @drive: drive for DMA
352 *
353 * The IT821x has a single timing register for MWDMA and for PIO
354 * operations. As we flip back and forth we have to reload the
355 * clock. In addition the rev 0x10 device only works if the same
356 * timing value is loaded into the master and slave UDMA clock
357 * so we must also reload that.
358 *
359 * FIXME: we could figure out in advance if we need to do reloads
360 */
361
362static void it821x_dma_start(ide_drive_t *drive)
363{
364 ide_hwif_t *hwif = drive->hwif;
365 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
366 u8 unit = drive->dn & 1;
367
368 if(itdev->mwdma[unit] != MWDMA_OFF)
369 it821x_program(drive, itdev->mwdma[unit]);
370 else if(itdev->udma[unit] != UDMA_OFF && itdev->timing10)
371 it821x_program_udma(drive, itdev->udma[unit]);
372 ide_dma_start(drive);
373}
374
375/**
376 * it821x_dma_write - DMA hook
377 * @drive: drive for DMA stop
378 *
379 * The IT821x has a single timing register for MWDMA and for PIO
380 * operations. As we flip back and forth we have to reload the
381 * clock.
382 */
383
384static int it821x_dma_end(ide_drive_t *drive)
385{
386 ide_hwif_t *hwif = drive->hwif;
387 struct it821x_dev *itdev = ide_get_hwifdata(hwif);
388 int ret = ide_dma_end(drive);
389 u8 unit = drive->dn & 1;
390
391 if(itdev->mwdma[unit] != MWDMA_OFF)
392 it821x_program(drive, itdev->pio[unit]);
393 return ret;
394}
395
396/**
397 * it821x_set_dma_mode - set host controller for DMA mode
398 * @drive: drive
399 * @speed: DMA mode
400 *
401 * Tune the ITE chipset for the desired DMA mode.
402 */
403
404static void it821x_set_dma_mode(ide_drive_t *drive, const u8 speed)
405{
406 /*
407 * MWDMA tuning is really hard because our MWDMA and PIO
408 * timings are kept in the same place. We can switch in the
409 * host dma on/off callbacks.
410 */
411 if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_6)
412 it821x_tune_udma(drive, speed - XFER_UDMA_0);
413 else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
414 it821x_tune_mwdma(drive, speed - XFER_MW_DMA_0);
415}
416
417/**
418 * it821x_cable_detect - cable detection
419 * @hwif: interface to check
420 *
421 * Check for the presence of an ATA66 capable cable on the
422 * interface. Problematic as it seems some cards don't have
423 * the needed logic onboard.
424 */
425
426static u8 it821x_cable_detect(ide_hwif_t *hwif)
427{
428 /* The reference driver also only does disk side */
429 return ATA_CBL_PATA80;
430}
431
432/**
433 * it821x_quirkproc - post init callback
434 * @drive: drive
435 *
436 * This callback is run after the drive has been probed but
437 * before anything gets attached. It allows drivers to do any
438 * final tuning that is needed, or fixups to work around bugs.
439 */
440
441static void it821x_quirkproc(ide_drive_t *drive)
442{
443 struct it821x_dev *itdev = ide_get_hwifdata(drive->hwif);
444 u16 *id = drive->id;
445
446 if (!itdev->smart) {
447 /*
448 * If we are in pass through mode then not much
449 * needs to be done, but we do bother to clear the
450 * IRQ mask as we may well be in PIO (eg rev 0x10)
451 * for now and we know unmasking is safe on this chipset.
452 */
453 drive->dev_flags |= IDE_DFLAG_UNMASK;
454 } else {
455 /*
456 * Perform fixups on smart mode. We need to "lose" some
457 * capabilities the firmware lacks but does not filter, and
458 * also patch up some capability bits that it forgets to set
459 * in RAID mode.
460 */
461
462 /* Check for RAID v native */
463 if (strstr((char *)&id[ATA_ID_PROD],
464 "Integrated Technology Express")) {
465 /* In raid mode the ident block is slightly buggy
466 We need to set the bits so that the IDE layer knows
467 LBA28. LBA48 and DMA ar valid */
468 id[ATA_ID_CAPABILITY] |= (3 << 8); /* LBA28, DMA */
469 id[ATA_ID_COMMAND_SET_2] |= 0x0400; /* LBA48 valid */
470 id[ATA_ID_CFS_ENABLE_2] |= 0x0400; /* LBA48 on */
471 /* Reporting logic */
472 printk(KERN_INFO "%s: IT8212 %sRAID %d volume",
473 drive->name, id[147] ? "Bootable " : "",
474 id[ATA_ID_CSFO]);
475 if (id[ATA_ID_CSFO] != 1)
476 printk(KERN_CONT "(%dK stripe)", id[146]);
477 printk(KERN_CONT ".\n");
478 } else {
479 /* Non RAID volume. Fixups to stop the core code
480 doing unsupported things */
481 id[ATA_ID_FIELD_VALID] &= 3;
482 id[ATA_ID_QUEUE_DEPTH] = 0;
483 id[ATA_ID_COMMAND_SET_1] = 0;
484 id[ATA_ID_COMMAND_SET_2] &= 0xC400;
485 id[ATA_ID_CFSSE] &= 0xC000;
486 id[ATA_ID_CFS_ENABLE_1] = 0;
487 id[ATA_ID_CFS_ENABLE_2] &= 0xC400;
488 id[ATA_ID_CSF_DEFAULT] &= 0xC000;
489 id[127] = 0;
490 id[ATA_ID_DLF] = 0;
491 id[ATA_ID_CSFO] = 0;
492 id[ATA_ID_CFA_POWER] = 0;
493 printk(KERN_INFO "%s: Performing identify fixups.\n",
494 drive->name);
495 }
496
497 /*
498 * Set MWDMA0 mode as enabled/support - just to tell
499 * IDE core that DMA is supported (it821x hardware
500 * takes care of DMA mode programming).
501 */
502 if (ata_id_has_dma(id)) {
503 id[ATA_ID_MWDMA_MODES] |= 0x0101;
504 drive->current_speed = XFER_MW_DMA_0;
505 }
506 }
507
508}
509
510static struct ide_dma_ops it821x_pass_through_dma_ops = {
511 .dma_host_set = ide_dma_host_set,
512 .dma_setup = ide_dma_setup,
513 .dma_exec_cmd = ide_dma_exec_cmd,
514 .dma_start = it821x_dma_start,
515 .dma_end = it821x_dma_end,
516 .dma_test_irq = ide_dma_test_irq,
517 .dma_timeout = ide_dma_timeout,
518 .dma_lost_irq = ide_dma_lost_irq,
519};
520
521/**
522 * init_hwif_it821x - set up hwif structs
523 * @hwif: interface to set up
524 *
525 * We do the basic set up of the interface structure. The IT8212
526 * requires several custom handlers so we override the default
527 * ide DMA handlers appropriately
528 */
529
530static void __devinit init_hwif_it821x(ide_hwif_t *hwif)
531{
532 struct pci_dev *dev = to_pci_dev(hwif->dev);
533 struct ide_host *host = pci_get_drvdata(dev);
534 struct it821x_dev *itdevs = host->host_priv;
535 struct it821x_dev *idev = itdevs + hwif->channel;
536 u8 conf;
537
538 ide_set_hwifdata(hwif, idev);
539
540 pci_read_config_byte(dev, 0x50, &conf);
541 if (conf & 1) {
542 idev->smart = 1;
543 hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
544 /* Long I/O's although allowed in LBA48 space cause the
545 onboard firmware to enter the twighlight zone */
546 hwif->rqsize = 256;
547 }
548
549 /* Pull the current clocks from 0x50 also */
550 if (conf & (1 << (1 + hwif->channel)))
551 idev->clock_mode = ATA_50;
552 else
553 idev->clock_mode = ATA_66;
554
555 idev->want[0][1] = ATA_ANY;
556 idev->want[1][1] = ATA_ANY;
557
558 /*
559 * Not in the docs but according to the reference driver
560 * this is necessary.
561 */
562
563 pci_read_config_byte(dev, 0x08, &conf);
564 if (conf == 0x10) {
565 idev->timing10 = 1;
566 hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
567 if (idev->smart == 0)
568 printk(KERN_WARNING DRV_NAME " %s: revision 0x10, "
569 "workarounds activated\n", pci_name(dev));
570 }
571
572 if (idev->smart == 0) {
573 /* MWDMA/PIO clock switching for pass through mode */
574 hwif->dma_ops = &it821x_pass_through_dma_ops;
575 } else
576 hwif->host_flags |= IDE_HFLAG_NO_SET_MODE;
577
578 if (hwif->dma_base == 0)
579 return;
580
581 hwif->ultra_mask = ATA_UDMA6;
582 hwif->mwdma_mask = ATA_MWDMA2;
583}
584
585static void it8212_disable_raid(struct pci_dev *dev)
586{
587 /* Reset local CPU, and set BIOS not ready */
588 pci_write_config_byte(dev, 0x5E, 0x01);
589
590 /* Set to bypass mode, and reset PCI bus */
591 pci_write_config_byte(dev, 0x50, 0x00);
592 pci_write_config_word(dev, PCI_COMMAND,
593 PCI_COMMAND_PARITY | PCI_COMMAND_IO |
594 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
595 pci_write_config_word(dev, 0x40, 0xA0F3);
596
597 pci_write_config_dword(dev,0x4C, 0x02040204);
598 pci_write_config_byte(dev, 0x42, 0x36);
599 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
600}
601
602static unsigned int init_chipset_it821x(struct pci_dev *dev)
603{
604 u8 conf;
605 static char *mode[2] = { "pass through", "smart" };
606
607 /* Force the card into bypass mode if so requested */
608 if (it8212_noraid) {
609 printk(KERN_INFO DRV_NAME " %s: forcing bypass mode\n",
610 pci_name(dev));
611 it8212_disable_raid(dev);
612 }
613 pci_read_config_byte(dev, 0x50, &conf);
614 printk(KERN_INFO DRV_NAME " %s: controller in %s mode\n",
615 pci_name(dev), mode[conf & 1]);
616 return 0;
617}
618
619static const struct ide_port_ops it821x_port_ops = {
620 /* it821x_set_{pio,dma}_mode() are only used in pass-through mode */
621 .set_pio_mode = it821x_set_pio_mode,
622 .set_dma_mode = it821x_set_dma_mode,
623 .quirkproc = it821x_quirkproc,
624 .cable_detect = it821x_cable_detect,
625};
626
627static const struct ide_port_info it821x_chipset __devinitdata = {
628 .name = DRV_NAME,
629 .init_chipset = init_chipset_it821x,
630 .init_hwif = init_hwif_it821x,
631 .port_ops = &it821x_port_ops,
632 .pio_mask = ATA_PIO4,
633};
634
635/**
636 * it821x_init_one - pci layer discovery entry
637 * @dev: PCI device
638 * @id: ident table entry
639 *
640 * Called by the PCI code when it finds an ITE821x controller.
641 * We then use the IDE PCI generic helper to do most of the work.
642 */
643
644static int __devinit it821x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
645{
646 struct it821x_dev *itdevs;
647 int rc;
648
649 itdevs = kzalloc(2 * sizeof(*itdevs), GFP_KERNEL);
650 if (itdevs == NULL) {
651 printk(KERN_ERR DRV_NAME " %s: out of memory\n", pci_name(dev));
652 return -ENOMEM;
653 }
654
655 rc = ide_pci_init_one(dev, &it821x_chipset, itdevs);
656 if (rc)
657 kfree(itdevs);
658
659 return rc;
660}
661
662static void __devexit it821x_remove(struct pci_dev *dev)
663{
664 struct ide_host *host = pci_get_drvdata(dev);
665 struct it821x_dev *itdevs = host->host_priv;
666
667 ide_pci_remove(dev);
668 kfree(itdevs);
669}
670
671static const struct pci_device_id it821x_pci_tbl[] = {
672 { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8211), 0 },
673 { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8212), 0 },
674 { 0, },
675};
676
677MODULE_DEVICE_TABLE(pci, it821x_pci_tbl);
678
679static struct pci_driver it821x_pci_driver = {
680 .name = "ITE821x IDE",
681 .id_table = it821x_pci_tbl,
682 .probe = it821x_init_one,
683 .remove = __devexit_p(it821x_remove),
684 .suspend = ide_pci_suspend,
685 .resume = ide_pci_resume,
686};
687
688static int __init it821x_ide_init(void)
689{
690 return ide_pci_register_driver(&it821x_pci_driver);
691}
692
693static void __exit it821x_ide_exit(void)
694{
695 pci_unregister_driver(&it821x_pci_driver);
696}
697
698module_init(it821x_ide_init);
699module_exit(it821x_ide_exit);
700
701module_param_named(noraid, it8212_noraid, int, S_IRUGO);
702MODULE_PARM_DESC(noraid, "Force card into bypass mode");
703
704MODULE_AUTHOR("Alan Cox");
705MODULE_DESCRIPTION("PCI driver module for the ITE 821x");
706MODULE_LICENSE("GPL");