diff options
author | Sergei Shtylyov <sshtylyov@ru.mvista.com> | 2009-06-15 12:52:59 -0400 |
---|---|---|
committer | Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> | 2009-06-15 12:52:59 -0400 |
commit | 628df2f33d99dace08838779d8a02bf1deaff100 (patch) | |
tree | 464e46724fbeef97593159ed4844f5dccb065f30 /drivers/ide/cmd64x.c | |
parent | 87441db22f95f03d4a91e2e250d88eafb1622b22 (diff) |
cmd64x: implement test_irq() method
Convert the driver's two dma_test_irq() methods into test_irq() methods. The
driver will now use the standard dma_test_irq() method implementation which
allows to remove 'cmd54x_dma_ops' and 'cmd648_dma_ops' that become identical
to 'sff_dma_ops'...
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Diffstat (limited to 'drivers/ide/cmd64x.c')
-rw-r--r-- | drivers/ide/cmd64x.c | 69 |
1 files changed, 12 insertions, 57 deletions
diff --git a/drivers/ide/cmd64x.c b/drivers/ide/cmd64x.c index 9f5cde7a731a..fd904e923a9f 100644 --- a/drivers/ide/cmd64x.c +++ b/drivers/ide/cmd64x.c | |||
@@ -254,53 +254,34 @@ static void cmd64x_clear_irq(ide_drive_t *drive) | |||
254 | (void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask); | 254 | (void) pci_write_config_byte(dev, irq_reg, irq_stat | irq_mask); |
255 | } | 255 | } |
256 | 256 | ||
257 | static int cmd648_dma_test_irq(ide_drive_t *drive) | 257 | static int cmd648_test_irq(ide_hwif_t *hwif) |
258 | { | 258 | { |
259 | ide_hwif_t *hwif = drive->hwif; | 259 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
260 | unsigned long base = hwif->dma_base - (hwif->channel * 8); | 260 | unsigned long base = pci_resource_start(dev, 4); |
261 | u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 : | 261 | u8 irq_mask = hwif->channel ? MRDMODE_INTR_CH1 : |
262 | MRDMODE_INTR_CH0; | 262 | MRDMODE_INTR_CH0; |
263 | u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS); | ||
264 | u8 mrdmode = inb(base + 1); | 263 | u8 mrdmode = inb(base + 1); |
265 | 264 | ||
266 | #ifdef DEBUG | 265 | pr_debug("%s: mrdmode: 0x%02x irq_mask: 0x%02x\n", |
267 | printk("%s: dma_stat: 0x%02x mrdmode: 0x%02x irq_mask: 0x%02x\n", | 266 | hwif->name, mrdmode, irq_mask); |
268 | drive->name, dma_stat, mrdmode, irq_mask); | ||
269 | #endif | ||
270 | if (!(mrdmode & irq_mask)) | ||
271 | return 0; | ||
272 | 267 | ||
273 | /* return 1 if INTR asserted */ | 268 | return (mrdmode & irq_mask) ? 1 : 0; |
274 | if (dma_stat & 4) | ||
275 | return 1; | ||
276 | |||
277 | return 0; | ||
278 | } | 269 | } |
279 | 270 | ||
280 | static int cmd64x_dma_test_irq(ide_drive_t *drive) | 271 | static int cmd64x_test_irq(ide_hwif_t *hwif) |
281 | { | 272 | { |
282 | ide_hwif_t *hwif = drive->hwif; | ||
283 | struct pci_dev *dev = to_pci_dev(hwif->dev); | 273 | struct pci_dev *dev = to_pci_dev(hwif->dev); |
284 | int irq_reg = hwif->channel ? ARTTIM23 : CFR; | 274 | int irq_reg = hwif->channel ? ARTTIM23 : CFR; |
285 | u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 : | 275 | u8 irq_mask = hwif->channel ? ARTTIM23_INTR_CH1 : |
286 | CFR_INTR_CH0; | 276 | CFR_INTR_CH0; |
287 | u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS); | ||
288 | u8 irq_stat = 0; | 277 | u8 irq_stat = 0; |
289 | 278 | ||
290 | (void) pci_read_config_byte(dev, irq_reg, &irq_stat); | 279 | (void) pci_read_config_byte(dev, irq_reg, &irq_stat); |
291 | 280 | ||
292 | #ifdef DEBUG | 281 | pr_debug("%s: irq_stat: 0x%02x irq_mask: 0x%02x\n", |
293 | printk("%s: dma_stat: 0x%02x irq_stat: 0x%02x irq_mask: 0x%02x\n", | 282 | hwif->name, irq_stat, irq_mask); |
294 | drive->name, dma_stat, irq_stat, irq_mask); | ||
295 | #endif | ||
296 | if (!(irq_stat & irq_mask)) | ||
297 | return 0; | ||
298 | |||
299 | /* return 1 if INTR asserted */ | ||
300 | if (dma_stat & 4) | ||
301 | return 1; | ||
302 | 283 | ||
303 | return 0; | 284 | return (irq_stat & irq_mask) ? 1 : 0; |
304 | } | 285 | } |
305 | 286 | ||
306 | /* | 287 | /* |
@@ -366,6 +347,7 @@ static const struct ide_port_ops cmd64x_port_ops = { | |||
366 | .set_pio_mode = cmd64x_set_pio_mode, | 347 | .set_pio_mode = cmd64x_set_pio_mode, |
367 | .set_dma_mode = cmd64x_set_dma_mode, | 348 | .set_dma_mode = cmd64x_set_dma_mode, |
368 | .clear_irq = cmd64x_clear_irq, | 349 | .clear_irq = cmd64x_clear_irq, |
350 | .test_irq = cmd64x_test_irq, | ||
369 | .cable_detect = cmd64x_cable_detect, | 351 | .cable_detect = cmd64x_cable_detect, |
370 | }; | 352 | }; |
371 | 353 | ||
@@ -373,20 +355,10 @@ static const struct ide_port_ops cmd648_port_ops = { | |||
373 | .set_pio_mode = cmd64x_set_pio_mode, | 355 | .set_pio_mode = cmd64x_set_pio_mode, |
374 | .set_dma_mode = cmd64x_set_dma_mode, | 356 | .set_dma_mode = cmd64x_set_dma_mode, |
375 | .clear_irq = cmd648_clear_irq, | 357 | .clear_irq = cmd648_clear_irq, |
358 | .test_irq = cmd648_test_irq, | ||
376 | .cable_detect = cmd64x_cable_detect, | 359 | .cable_detect = cmd64x_cable_detect, |
377 | }; | 360 | }; |
378 | 361 | ||
379 | static const struct ide_dma_ops cmd64x_dma_ops = { | ||
380 | .dma_host_set = ide_dma_host_set, | ||
381 | .dma_setup = ide_dma_setup, | ||
382 | .dma_start = ide_dma_start, | ||
383 | .dma_end = ide_dma_end, | ||
384 | .dma_test_irq = cmd64x_dma_test_irq, | ||
385 | .dma_lost_irq = ide_dma_lost_irq, | ||
386 | .dma_timer_expiry = ide_dma_sff_timer_expiry, | ||
387 | .dma_sff_read_status = ide_dma_sff_read_status, | ||
388 | }; | ||
389 | |||
390 | static const struct ide_dma_ops cmd646_rev1_dma_ops = { | 362 | static const struct ide_dma_ops cmd646_rev1_dma_ops = { |
391 | .dma_host_set = ide_dma_host_set, | 363 | .dma_host_set = ide_dma_host_set, |
392 | .dma_setup = ide_dma_setup, | 364 | .dma_setup = ide_dma_setup, |
@@ -398,24 +370,12 @@ static const struct ide_dma_ops cmd646_rev1_dma_ops = { | |||
398 | .dma_sff_read_status = ide_dma_sff_read_status, | 370 | .dma_sff_read_status = ide_dma_sff_read_status, |
399 | }; | 371 | }; |
400 | 372 | ||
401 | static const struct ide_dma_ops cmd648_dma_ops = { | ||
402 | .dma_host_set = ide_dma_host_set, | ||
403 | .dma_setup = ide_dma_setup, | ||
404 | .dma_start = ide_dma_start, | ||
405 | .dma_end = ide_dma_end, | ||
406 | .dma_test_irq = cmd648_dma_test_irq, | ||
407 | .dma_lost_irq = ide_dma_lost_irq, | ||
408 | .dma_timer_expiry = ide_dma_sff_timer_expiry, | ||
409 | .dma_sff_read_status = ide_dma_sff_read_status, | ||
410 | }; | ||
411 | |||
412 | static const struct ide_port_info cmd64x_chipsets[] __devinitdata = { | 373 | static const struct ide_port_info cmd64x_chipsets[] __devinitdata = { |
413 | { /* 0: CMD643 */ | 374 | { /* 0: CMD643 */ |
414 | .name = DRV_NAME, | 375 | .name = DRV_NAME, |
415 | .init_chipset = init_chipset_cmd64x, | 376 | .init_chipset = init_chipset_cmd64x, |
416 | .enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}}, | 377 | .enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}}, |
417 | .port_ops = &cmd64x_port_ops, | 378 | .port_ops = &cmd64x_port_ops, |
418 | .dma_ops = &cmd64x_dma_ops, | ||
419 | .host_flags = IDE_HFLAG_CLEAR_SIMPLEX | | 379 | .host_flags = IDE_HFLAG_CLEAR_SIMPLEX | |
420 | IDE_HFLAG_ABUSE_PREFETCH, | 380 | IDE_HFLAG_ABUSE_PREFETCH, |
421 | .pio_mask = ATA_PIO5, | 381 | .pio_mask = ATA_PIO5, |
@@ -427,7 +387,6 @@ static const struct ide_port_info cmd64x_chipsets[] __devinitdata = { | |||
427 | .init_chipset = init_chipset_cmd64x, | 387 | .init_chipset = init_chipset_cmd64x, |
428 | .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, | 388 | .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, |
429 | .port_ops = &cmd648_port_ops, | 389 | .port_ops = &cmd648_port_ops, |
430 | .dma_ops = &cmd648_dma_ops, | ||
431 | .host_flags = IDE_HFLAG_SERIALIZE | | 390 | .host_flags = IDE_HFLAG_SERIALIZE | |
432 | IDE_HFLAG_ABUSE_PREFETCH, | 391 | IDE_HFLAG_ABUSE_PREFETCH, |
433 | .pio_mask = ATA_PIO5, | 392 | .pio_mask = ATA_PIO5, |
@@ -439,7 +398,6 @@ static const struct ide_port_info cmd64x_chipsets[] __devinitdata = { | |||
439 | .init_chipset = init_chipset_cmd64x, | 398 | .init_chipset = init_chipset_cmd64x, |
440 | .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, | 399 | .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, |
441 | .port_ops = &cmd648_port_ops, | 400 | .port_ops = &cmd648_port_ops, |
442 | .dma_ops = &cmd648_dma_ops, | ||
443 | .host_flags = IDE_HFLAG_ABUSE_PREFETCH, | 401 | .host_flags = IDE_HFLAG_ABUSE_PREFETCH, |
444 | .pio_mask = ATA_PIO5, | 402 | .pio_mask = ATA_PIO5, |
445 | .mwdma_mask = ATA_MWDMA2, | 403 | .mwdma_mask = ATA_MWDMA2, |
@@ -450,7 +408,6 @@ static const struct ide_port_info cmd64x_chipsets[] __devinitdata = { | |||
450 | .init_chipset = init_chipset_cmd64x, | 408 | .init_chipset = init_chipset_cmd64x, |
451 | .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, | 409 | .enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}}, |
452 | .port_ops = &cmd648_port_ops, | 410 | .port_ops = &cmd648_port_ops, |
453 | .dma_ops = &cmd648_dma_ops, | ||
454 | .host_flags = IDE_HFLAG_ABUSE_PREFETCH, | 411 | .host_flags = IDE_HFLAG_ABUSE_PREFETCH, |
455 | .pio_mask = ATA_PIO5, | 412 | .pio_mask = ATA_PIO5, |
456 | .mwdma_mask = ATA_MWDMA2, | 413 | .mwdma_mask = ATA_MWDMA2, |
@@ -490,8 +447,6 @@ static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_devic | |||
490 | d.port_ops = &cmd64x_port_ops; | 447 | d.port_ops = &cmd64x_port_ops; |
491 | if (dev->revision == 1) | 448 | if (dev->revision == 1) |
492 | d.dma_ops = &cmd646_rev1_dma_ops; | 449 | d.dma_ops = &cmd646_rev1_dma_ops; |
493 | else | ||
494 | d.dma_ops = &cmd64x_dma_ops; | ||
495 | } | 450 | } |
496 | } | 451 | } |
497 | } | 452 | } |