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authorStanislaw Gruszka <stf_xl@wp.pl>2009-03-05 10:10:58 -0500
committerBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2009-03-05 10:10:58 -0500
commit6e5f1e1115bb041993f9f247036996364b4c84d5 (patch)
tree51f3bd4bce0ddb4afdcaf8fac10c7905d8119882 /drivers/ide/at91_ide.c
parent849d7130001ab740a5a4778a561049841fdd77c9 (diff)
ide: add at91_ide driver
This is IDE host driver for AT91 (SAM9, CAP9, AT572D940HF) Static Memory Controller with Compact Flash True IDE Mode logic. Driver have to switch 8/16 bit bus width when accessing Task Tile or Data Register. Moreover some extra things need to be done when setting PIO mode. Only PIO mode is used, hardware have no DMA support. If interrupt line is connected through GPIO extra quirk is needed to cope with fake interrupts. Signed-off-by: Stanislaw Gruszka <stf_xl@wp.pl> Cc: Andrew Victor <avictor.za@gmail.com> Acked-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Diffstat (limited to 'drivers/ide/at91_ide.c')
-rw-r--r--drivers/ide/at91_ide.c467
1 files changed, 467 insertions, 0 deletions
diff --git a/drivers/ide/at91_ide.c b/drivers/ide/at91_ide.c
new file mode 100644
index 000000000000..1bb50f46388d
--- /dev/null
+++ b/drivers/ide/at91_ide.c
@@ -0,0 +1,467 @@
1/*
2 * IDE host driver for AT91 (SAM9, CAP9, AT572D940HF) Static Memory Controller
3 * with Compact Flash True IDE logic
4 *
5 * Copyright (c) 2008, 2009 Kelvatek Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 *
21 */
22
23#include <linux/version.h>
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/clk.h>
27#include <linux/err.h>
28#include <linux/ide.h>
29#include <linux/platform_device.h>
30
31#include <mach/board.h>
32#include <mach/gpio.h>
33#include <mach/at91sam9263.h>
34#include <mach/at91sam9_smc.h>
35#include <mach/at91sam9263_matrix.h>
36
37#define DRV_NAME "at91_ide"
38
39#define perr(fmt, args...) pr_err(DRV_NAME ": " fmt, ##args)
40#define pdbg(fmt, args...) pr_debug("%s " fmt, __func__, ##args)
41
42/*
43 * Access to IDE device is possible through EBI Static Memory Controller
44 * with Compact Flash logic. For details see EBI and SMC datasheet sections
45 * of any microcontroller from AT91SAM9 family.
46 *
47 * Within SMC chip select address space, lines A[23:21] distinguish Compact
48 * Flash modes (I/O, common memory, attribute memory, True IDE). IDE modes are:
49 * 0x00c0000 - True IDE
50 * 0x00e0000 - Alternate True IDE (Alt Status Register)
51 *
52 * On True IDE mode Task File and Data Register are mapped at the same address.
53 * To distinguish access between these two different bus data width is used:
54 * 8Bit for Task File, 16Bit for Data I/O.
55 *
56 * After initialization we do 8/16 bit flipping (changes in SMC MODE register)
57 * only inside IDE callback routines which are serialized by IDE layer,
58 * so no additional locking needed.
59 */
60
61#define TASK_FILE 0x00c00000
62#define ALT_MODE 0x00e00000
63#define REGS_SIZE 8
64
65#define enter_16bit(cs, mode) do { \
66 mode = at91_sys_read(AT91_SMC_MODE(cs)); \
67 at91_sys_write(AT91_SMC_MODE(cs), mode | AT91_SMC_DBW_16); \
68} while (0)
69
70#define leave_16bit(cs, mode) at91_sys_write(AT91_SMC_MODE(cs), mode);
71
72static void set_smc_timings(const u8 chipselect, const u16 cycle,
73 const u16 setup, const u16 pulse,
74 const u16 data_float, int use_iordy)
75{
76 unsigned long mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
77 AT91_SMC_BAT_SELECT;
78
79 /* disable or enable waiting for IORDY signal */
80 if (use_iordy)
81 mode |= AT91_SMC_EXNWMODE_READY;
82
83 /* add data float cycles if needed */
84 if (data_float)
85 mode |= AT91_SMC_TDF_(data_float);
86
87 at91_sys_write(AT91_SMC_MODE(chipselect), mode);
88
89 /* setup timings in SMC */
90 at91_sys_write(AT91_SMC_SETUP(chipselect), AT91_SMC_NWESETUP_(setup) |
91 AT91_SMC_NCS_WRSETUP_(0) |
92 AT91_SMC_NRDSETUP_(setup) |
93 AT91_SMC_NCS_RDSETUP_(0));
94 at91_sys_write(AT91_SMC_PULSE(chipselect), AT91_SMC_NWEPULSE_(pulse) |
95 AT91_SMC_NCS_WRPULSE_(cycle) |
96 AT91_SMC_NRDPULSE_(pulse) |
97 AT91_SMC_NCS_RDPULSE_(cycle));
98 at91_sys_write(AT91_SMC_CYCLE(chipselect), AT91_SMC_NWECYCLE_(cycle) |
99 AT91_SMC_NRDCYCLE_(cycle));
100}
101
102static unsigned int calc_mck_cycles(unsigned int ns, unsigned int mck_hz)
103{
104 u64 tmp = ns;
105
106 tmp *= mck_hz;
107 tmp += 1000*1000*1000 - 1; /* round up */
108 do_div(tmp, 1000*1000*1000);
109 return (unsigned int) tmp;
110}
111
112static void apply_timings(const u8 chipselect, const u8 pio,
113 const struct ide_timing *timing, int use_iordy)
114{
115 unsigned int t0, t1, t2, t6z;
116 unsigned int cycle, setup, pulse, data_float;
117 unsigned int mck_hz;
118 struct clk *mck;
119
120 /* see table 22 of Compact Flash standard 4.1 for the meaning,
121 * we do not stretch active (t2) time, so setup (t1) + hold time (th)
122 * assure at least minimal recovery (t2i) time */
123 t0 = timing->cyc8b;
124 t1 = timing->setup;
125 t2 = timing->act8b;
126 t6z = (pio < 5) ? 30 : 20;
127
128 pdbg("t0=%u t1=%u t2=%u t6z=%u\n", t0, t1, t2, t6z);
129
130 mck = clk_get(NULL, "mck");
131 BUG_ON(IS_ERR(mck));
132 mck_hz = clk_get_rate(mck);
133 pdbg("mck_hz=%u\n", mck_hz);
134
135 cycle = calc_mck_cycles(t0, mck_hz);
136 setup = calc_mck_cycles(t1, mck_hz);
137 pulse = calc_mck_cycles(t2, mck_hz);
138 data_float = calc_mck_cycles(t6z, mck_hz);
139
140 pdbg("cycle=%u setup=%u pulse=%u data_float=%u\n",
141 cycle, setup, pulse, data_float);
142
143 set_smc_timings(chipselect, cycle, setup, pulse, data_float, use_iordy);
144}
145
146static void at91_ide_input_data(ide_drive_t *drive, struct request *rq,
147 void *buf, unsigned int len)
148{
149 ide_hwif_t *hwif = drive->hwif;
150 struct ide_io_ports *io_ports = &hwif->io_ports;
151 u8 chipselect = hwif->select_data;
152 unsigned long mode;
153
154 pdbg("cs %u buf %p len %d\n", chipselect, buf, len);
155
156 len++;
157
158 enter_16bit(chipselect, mode);
159 __ide_mm_insw((void __iomem *) io_ports->data_addr, buf, len / 2);
160 leave_16bit(chipselect, mode);
161}
162
163static void at91_ide_output_data(ide_drive_t *drive, struct request *rq,
164 void *buf, unsigned int len)
165{
166 ide_hwif_t *hwif = drive->hwif;
167 struct ide_io_ports *io_ports = &hwif->io_ports;
168 u8 chipselect = hwif->select_data;
169 unsigned long mode;
170
171 pdbg("cs %u buf %p len %d\n", chipselect, buf, len);
172
173 enter_16bit(chipselect, mode);
174 __ide_mm_outsw((void __iomem *) io_ports->data_addr, buf, len / 2);
175 leave_16bit(chipselect, mode);
176}
177
178static u8 ide_mm_inb(unsigned long port)
179{
180 return readb((void __iomem *) port);
181}
182
183static void ide_mm_outb(u8 value, unsigned long port)
184{
185 writeb(value, (void __iomem *) port);
186}
187
188static void at91_ide_tf_load(ide_drive_t *drive, ide_task_t *task)
189{
190 ide_hwif_t *hwif = drive->hwif;
191 struct ide_io_ports *io_ports = &hwif->io_ports;
192 struct ide_taskfile *tf = &task->tf;
193 u8 HIHI = (task->tf_flags & IDE_TFLAG_LBA48) ? 0xE0 : 0xEF;
194
195 if (task->tf_flags & IDE_TFLAG_FLAGGED)
196 HIHI = 0xFF;
197
198 if (task->tf_flags & IDE_TFLAG_OUT_DATA) {
199 u16 data = (tf->hob_data << 8) | tf->data;
200
201 at91_ide_output_data(drive, NULL, &data, 2);
202 }
203
204 if (task->tf_flags & IDE_TFLAG_OUT_HOB_FEATURE)
205 ide_mm_outb(tf->hob_feature, io_ports->feature_addr);
206 if (task->tf_flags & IDE_TFLAG_OUT_HOB_NSECT)
207 ide_mm_outb(tf->hob_nsect, io_ports->nsect_addr);
208 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAL)
209 ide_mm_outb(tf->hob_lbal, io_ports->lbal_addr);
210 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAM)
211 ide_mm_outb(tf->hob_lbam, io_ports->lbam_addr);
212 if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAH)
213 ide_mm_outb(tf->hob_lbah, io_ports->lbah_addr);
214
215 if (task->tf_flags & IDE_TFLAG_OUT_FEATURE)
216 ide_mm_outb(tf->feature, io_ports->feature_addr);
217 if (task->tf_flags & IDE_TFLAG_OUT_NSECT)
218 ide_mm_outb(tf->nsect, io_ports->nsect_addr);
219 if (task->tf_flags & IDE_TFLAG_OUT_LBAL)
220 ide_mm_outb(tf->lbal, io_ports->lbal_addr);
221 if (task->tf_flags & IDE_TFLAG_OUT_LBAM)
222 ide_mm_outb(tf->lbam, io_ports->lbam_addr);
223 if (task->tf_flags & IDE_TFLAG_OUT_LBAH)
224 ide_mm_outb(tf->lbah, io_ports->lbah_addr);
225
226 if (task->tf_flags & IDE_TFLAG_OUT_DEVICE)
227 ide_mm_outb((tf->device & HIHI) | drive->select, io_ports->device_addr);
228}
229
230static void at91_ide_tf_read(ide_drive_t *drive, ide_task_t *task)
231{
232 ide_hwif_t *hwif = drive->hwif;
233 struct ide_io_ports *io_ports = &hwif->io_ports;
234 struct ide_taskfile *tf = &task->tf;
235
236 if (task->tf_flags & IDE_TFLAG_IN_DATA) {
237 u16 data;
238
239 at91_ide_input_data(drive, NULL, &data, 2);
240 tf->data = data & 0xff;
241 tf->hob_data = (data >> 8) & 0xff;
242 }
243
244 /* be sure we're looking at the low order bits */
245 ide_mm_outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr);
246
247 if (task->tf_flags & IDE_TFLAG_IN_FEATURE)
248 tf->feature = ide_mm_inb(io_ports->feature_addr);
249 if (task->tf_flags & IDE_TFLAG_IN_NSECT)
250 tf->nsect = ide_mm_inb(io_ports->nsect_addr);
251 if (task->tf_flags & IDE_TFLAG_IN_LBAL)
252 tf->lbal = ide_mm_inb(io_ports->lbal_addr);
253 if (task->tf_flags & IDE_TFLAG_IN_LBAM)
254 tf->lbam = ide_mm_inb(io_ports->lbam_addr);
255 if (task->tf_flags & IDE_TFLAG_IN_LBAH)
256 tf->lbah = ide_mm_inb(io_ports->lbah_addr);
257 if (task->tf_flags & IDE_TFLAG_IN_DEVICE)
258 tf->device = ide_mm_inb(io_ports->device_addr);
259
260 if (task->tf_flags & IDE_TFLAG_LBA48) {
261 ide_mm_outb(ATA_DEVCTL_OBS | 0x80, io_ports->ctl_addr);
262
263 if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
264 tf->hob_feature = ide_mm_inb(io_ports->feature_addr);
265 if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
266 tf->hob_nsect = ide_mm_inb(io_ports->nsect_addr);
267 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
268 tf->hob_lbal = ide_mm_inb(io_ports->lbal_addr);
269 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
270 tf->hob_lbam = ide_mm_inb(io_ports->lbam_addr);
271 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
272 tf->hob_lbah = ide_mm_inb(io_ports->lbah_addr);
273 }
274}
275
276static void at91_ide_set_pio_mode(ide_drive_t *drive, const u8 pio)
277{
278 struct ide_timing *timing;
279 u8 chipselect = drive->hwif->select_data;
280 int use_iordy = 0;
281
282 pdbg("chipselect %u pio %u\n", chipselect, pio);
283
284 timing = ide_timing_find_mode(XFER_PIO_0 + pio);
285 BUG_ON(!timing);
286
287 if ((pio > 2 || ata_id_has_iordy(drive->id)) &&
288 !(ata_id_is_cfa(drive->id) && pio > 4))
289 use_iordy = 1;
290
291 apply_timings(chipselect, pio, timing, use_iordy);
292}
293
294static const struct ide_tp_ops at91_ide_tp_ops = {
295 .exec_command = ide_exec_command,
296 .read_status = ide_read_status,
297 .read_altstatus = ide_read_altstatus,
298 .set_irq = ide_set_irq,
299
300 .tf_load = at91_ide_tf_load,
301 .tf_read = at91_ide_tf_read,
302
303 .input_data = at91_ide_input_data,
304 .output_data = at91_ide_output_data,
305};
306
307static const struct ide_port_ops at91_ide_port_ops = {
308 .set_pio_mode = at91_ide_set_pio_mode,
309};
310
311static const struct ide_port_info at91_ide_port_info __initdata = {
312 .port_ops = &at91_ide_port_ops,
313 .tp_ops = &at91_ide_tp_ops,
314 .host_flags = IDE_HFLAG_MMIO | IDE_HFLAG_NO_DMA | IDE_HFLAG_SINGLE |
315 IDE_HFLAG_NO_IO_32BIT | IDE_HFLAG_UNMASK_IRQS,
316 .pio_mask = ATA_PIO5,
317};
318
319/*
320 * If interrupt is delivered through GPIO, IRQ are triggered on falling
321 * and rising edge of signal. Whereas IDE device request interrupt on high
322 * level (rising edge in our case). This mean we have fake interrupts, so
323 * we need to check interrupt pin and exit instantly from ISR when line
324 * is on low level.
325 */
326
327irqreturn_t at91_irq_handler(int irq, void *dev_id)
328{
329 int ntries = 8;
330 int pin_val1, pin_val2;
331
332 /* additional deglitch, line can be noisy in badly designed PCB */
333 do {
334 pin_val1 = at91_get_gpio_value(irq);
335 pin_val2 = at91_get_gpio_value(irq);
336 } while (pin_val1 != pin_val2 && --ntries > 0);
337
338 if (pin_val1 == 0 || ntries <= 0)
339 return IRQ_HANDLED;
340
341 return ide_intr(irq, dev_id);
342}
343
344static int __init at91_ide_probe(struct platform_device *pdev)
345{
346 int ret;
347 hw_regs_t hw;
348 hw_regs_t *hws[] = { &hw, NULL, NULL, NULL };
349 struct ide_host *host;
350 struct resource *res;
351 unsigned long tf_base = 0, ctl_base = 0;
352 struct at91_cf_data *board = pdev->dev.platform_data;
353
354 if (!board)
355 return -ENODEV;
356
357 if (board->det_pin && at91_get_gpio_value(board->det_pin) != 0) {
358 perr("no device detected\n");
359 return -ENODEV;
360 }
361
362 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
363 if (!res) {
364 perr("can't get memory resource\n");
365 return -ENODEV;
366 }
367
368 if (!devm_request_mem_region(&pdev->dev, res->start + TASK_FILE,
369 REGS_SIZE, "ide") ||
370 !devm_request_mem_region(&pdev->dev, res->start + ALT_MODE,
371 REGS_SIZE, "alt")) {
372 perr("memory resources in use\n");
373 return -EBUSY;
374 }
375
376 pdbg("chipselect %u irq %u res %08lx\n", board->chipselect,
377 board->irq_pin, (unsigned long) res->start);
378
379 tf_base = (unsigned long) devm_ioremap(&pdev->dev, res->start + TASK_FILE,
380 REGS_SIZE);
381 ctl_base = (unsigned long) devm_ioremap(&pdev->dev, res->start + ALT_MODE,
382 REGS_SIZE);
383 if (!tf_base || !ctl_base) {
384 perr("can't map memory regions\n");
385 return -EBUSY;
386 }
387
388 memset(&hw, 0, sizeof(hw));
389
390 if (board->flags & AT91_IDE_SWAP_A0_A2) {
391 /* workaround for stupid hardware bug */
392 hw.io_ports.data_addr = tf_base + 0;
393 hw.io_ports.error_addr = tf_base + 4;
394 hw.io_ports.nsect_addr = tf_base + 2;
395 hw.io_ports.lbal_addr = tf_base + 6;
396 hw.io_ports.lbam_addr = tf_base + 1;
397 hw.io_ports.lbah_addr = tf_base + 5;
398 hw.io_ports.device_addr = tf_base + 3;
399 hw.io_ports.command_addr = tf_base + 7;
400 hw.io_ports.ctl_addr = ctl_base + 3;
401 } else
402 ide_std_init_ports(&hw, tf_base, ctl_base + 6);
403
404 hw.irq = board->irq_pin;
405 hw.chipset = ide_generic;
406 hw.dev = &pdev->dev;
407
408 host = ide_host_alloc(&at91_ide_port_info, hws);
409 if (!host) {
410 perr("failed to allocate ide host\n");
411 return -ENOMEM;
412 }
413
414 /* setup Static Memory Controller - PIO 0 as default */
415 apply_timings(board->chipselect, 0, ide_timing_find_mode(XFER_PIO_0), 0);
416
417 /* with GPIO interrupt we have to do quirks in handler */
418 if (board->irq_pin >= PIN_BASE)
419 host->irq_handler = at91_irq_handler;
420
421 host->ports[0]->select_data = board->chipselect;
422
423 ret = ide_host_register(host, &at91_ide_port_info, hws);
424 if (ret) {
425 perr("failed to register ide host\n");
426 goto err_free_host;
427 }
428 platform_set_drvdata(pdev, host);
429 return 0;
430
431err_free_host:
432 ide_host_free(host);
433 return ret;
434}
435
436static int __exit at91_ide_remove(struct platform_device *pdev)
437{
438 struct ide_host *host = platform_get_drvdata(pdev);
439
440 ide_host_remove(host);
441 return 0;
442}
443
444static struct platform_driver at91_ide_driver = {
445 .driver = {
446 .name = DRV_NAME,
447 .owner = THIS_MODULE,
448 },
449 .remove = __exit_p(at91_ide_remove),
450};
451
452static int __init at91_ide_init(void)
453{
454 return platform_driver_probe(&at91_ide_driver, at91_ide_probe);
455}
456
457static void __exit at91_ide_exit(void)
458{
459 platform_driver_unregister(&at91_ide_driver);
460}
461
462module_init(at91_ide_init);
463module_exit(at91_ide_exit);
464
465MODULE_LICENSE("GPL");
466MODULE_AUTHOR("Stanislaw Gruszka <stf_xl@wp.pl>");
467