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authorWolfram Sang <wsa+renesas@sang-engineering.com>2014-05-28 03:44:39 -0400
committerWolfram Sang <wsa@the-dreams.de>2014-06-01 16:22:29 -0400
commitf2382249b27d1589a1ae495a1df84d890982a3e1 (patch)
treea51f0e3d8e53ddc22d430511c41639ad20c6a257 /drivers/i2c
parent4f443a8a611d0cb3c40e95e0d90e9d7e4740eda6 (diff)
i2c: rcar: refactor irq state machine
Remove the seperate functions and use designated constants. As readable but less overhead. Actually, this is even more readable since the old function used a mix of "=" and "|=". Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Diffstat (limited to 'drivers/i2c')
-rw-r--r--drivers/i2c/busses/i2c-rcar.c39
1 files changed, 7 insertions, 32 deletions
diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c
index eadaca0ef4be..f2cbb8a7d0ba 100644
--- a/drivers/i2c/busses/i2c-rcar.c
+++ b/drivers/i2c/busses/i2c-rcar.c
@@ -83,12 +83,9 @@
83#define RCAR_BUS_PHASE_DATA (MDBS | MIE) 83#define RCAR_BUS_PHASE_DATA (MDBS | MIE)
84#define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB) 84#define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB)
85 85
86enum { 86#define RCAR_IRQ_SEND (MNRE | MALE | MSTE | MATE | MDEE)
87 RCAR_IRQ_CLOSE, 87#define RCAR_IRQ_RECV (MNRE | MALE | MSTE | MATE | MDRE)
88 RCAR_IRQ_OPEN_FOR_SEND, 88#define RCAR_IRQ_STOP (MSTE)
89 RCAR_IRQ_OPEN_FOR_RECV,
90 RCAR_IRQ_OPEN_FOR_STOP,
91};
92 89
93/* 90/*
94 * flags 91 * flags
@@ -158,28 +155,6 @@ static void rcar_i2c_init(struct rcar_i2c_priv *priv)
158 rcar_i2c_write(priv, ICMAR, 0); 155 rcar_i2c_write(priv, ICMAR, 0);
159} 156}
160 157
161static void rcar_i2c_irq_mask(struct rcar_i2c_priv *priv, int open)
162{
163 u32 val = MNRE | MALE | MSTE | MATE; /* default */
164
165 switch (open) {
166 case RCAR_IRQ_OPEN_FOR_SEND:
167 val |= MDEE; /* default + send */
168 break;
169 case RCAR_IRQ_OPEN_FOR_RECV:
170 val |= MDRE; /* default + read */
171 break;
172 case RCAR_IRQ_OPEN_FOR_STOP:
173 val = MSTE; /* stop irq only */
174 break;
175 case RCAR_IRQ_CLOSE:
176 default:
177 val = 0; /* all close */
178 break;
179 }
180 rcar_i2c_write(priv, ICMIER, val);
181}
182
183static void rcar_i2c_set_addr(struct rcar_i2c_priv *priv, u32 recv) 158static void rcar_i2c_set_addr(struct rcar_i2c_priv *priv, u32 recv)
184{ 159{
185 rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | recv); 160 rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | recv);
@@ -312,7 +287,7 @@ static int rcar_i2c_recv(struct rcar_i2c_priv *priv)
312 rcar_i2c_set_addr(priv, 1); 287 rcar_i2c_set_addr(priv, 1);
313 rcar_i2c_status_clear(priv); 288 rcar_i2c_status_clear(priv);
314 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 289 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
315 rcar_i2c_irq_mask(priv, RCAR_IRQ_OPEN_FOR_RECV); 290 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_RECV);
316 291
317 return 0; 292 return 0;
318} 293}
@@ -331,7 +306,7 @@ static int rcar_i2c_send(struct rcar_i2c_priv *priv)
331 rcar_i2c_set_addr(priv, 0); 306 rcar_i2c_set_addr(priv, 0);
332 rcar_i2c_status_clear(priv); 307 rcar_i2c_status_clear(priv);
333 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START); 308 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
334 rcar_i2c_irq_mask(priv, RCAR_IRQ_OPEN_FOR_SEND); 309 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_SEND);
335 310
336 return 0; 311 return 0;
337} 312}
@@ -486,7 +461,7 @@ static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
486 461
487 /* go to stop phase */ 462 /* go to stop phase */
488 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP); 463 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
489 rcar_i2c_irq_mask(priv, RCAR_IRQ_OPEN_FOR_STOP); 464 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
490 rcar_i2c_flags_set(priv, ID_NACK); 465 rcar_i2c_flags_set(priv, ID_NACK);
491 goto out; 466 goto out;
492 } 467 }
@@ -501,7 +476,7 @@ static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
501 476
502out: 477out:
503 if (rcar_i2c_flags_has(priv, ID_DONE)) { 478 if (rcar_i2c_flags_has(priv, ID_DONE)) {
504 rcar_i2c_irq_mask(priv, RCAR_IRQ_CLOSE); 479 rcar_i2c_write(priv, ICMIER, 0);
505 rcar_i2c_status_clear(priv); 480 rcar_i2c_status_clear(priv);
506 wake_up(&priv->wait); 481 wake_up(&priv->wait);
507 } 482 }