diff options
author | Ben Dooks <ben-linux@fluff.org> | 2010-08-09 09:30:24 -0400 |
---|---|---|
committer | Ben Dooks <ben-linux@fluff.org> | 2010-08-09 09:30:24 -0400 |
commit | e126613e67873178f3c6f7c8674e70aa4327d8cd (patch) | |
tree | c996c49a41498cdc634064b11f5ca42f9112038f /drivers/i2c | |
parent | 45d7f32c7a43cbb9592886d38190e379e2eb2226 (diff) | |
parent | 8574faf9a5ae71fdd84c6413779a9b076138eb9e (diff) |
Merge branch 'davinci-i2c' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci into for-2636/i2c/davinci
Diffstat (limited to 'drivers/i2c')
-rw-r--r-- | drivers/i2c/busses/i2c-davinci.c | 314 |
1 files changed, 251 insertions, 63 deletions
diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davinci.c index 4523364e6722..2222c87876b9 100644 --- a/drivers/i2c/busses/i2c-davinci.c +++ b/drivers/i2c/busses/i2c-davinci.c | |||
@@ -36,14 +36,16 @@ | |||
36 | #include <linux/platform_device.h> | 36 | #include <linux/platform_device.h> |
37 | #include <linux/io.h> | 37 | #include <linux/io.h> |
38 | #include <linux/slab.h> | 38 | #include <linux/slab.h> |
39 | #include <linux/cpufreq.h> | ||
40 | #include <linux/gpio.h> | ||
39 | 41 | ||
40 | #include <mach/hardware.h> | 42 | #include <mach/hardware.h> |
41 | |||
42 | #include <mach/i2c.h> | 43 | #include <mach/i2c.h> |
43 | 44 | ||
44 | /* ----- global defines ----------------------------------------------- */ | 45 | /* ----- global defines ----------------------------------------------- */ |
45 | 46 | ||
46 | #define DAVINCI_I2C_TIMEOUT (1*HZ) | 47 | #define DAVINCI_I2C_TIMEOUT (1*HZ) |
48 | #define DAVINCI_I2C_MAX_TRIES 2 | ||
47 | #define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_AAS | \ | 49 | #define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_AAS | \ |
48 | DAVINCI_I2C_IMR_SCD | \ | 50 | DAVINCI_I2C_IMR_SCD | \ |
49 | DAVINCI_I2C_IMR_ARDY | \ | 51 | DAVINCI_I2C_IMR_ARDY | \ |
@@ -72,37 +74,29 @@ | |||
72 | #define DAVINCI_I2C_IVR_NACK 0x02 | 74 | #define DAVINCI_I2C_IVR_NACK 0x02 |
73 | #define DAVINCI_I2C_IVR_AL 0x01 | 75 | #define DAVINCI_I2C_IVR_AL 0x01 |
74 | 76 | ||
75 | #define DAVINCI_I2C_STR_BB (1 << 12) | 77 | #define DAVINCI_I2C_STR_BB BIT(12) |
76 | #define DAVINCI_I2C_STR_RSFULL (1 << 11) | 78 | #define DAVINCI_I2C_STR_RSFULL BIT(11) |
77 | #define DAVINCI_I2C_STR_SCD (1 << 5) | 79 | #define DAVINCI_I2C_STR_SCD BIT(5) |
78 | #define DAVINCI_I2C_STR_ARDY (1 << 2) | 80 | #define DAVINCI_I2C_STR_ARDY BIT(2) |
79 | #define DAVINCI_I2C_STR_NACK (1 << 1) | 81 | #define DAVINCI_I2C_STR_NACK BIT(1) |
80 | #define DAVINCI_I2C_STR_AL (1 << 0) | 82 | #define DAVINCI_I2C_STR_AL BIT(0) |
81 | 83 | ||
82 | #define DAVINCI_I2C_MDR_NACK (1 << 15) | 84 | #define DAVINCI_I2C_MDR_NACK BIT(15) |
83 | #define DAVINCI_I2C_MDR_STT (1 << 13) | 85 | #define DAVINCI_I2C_MDR_STT BIT(13) |
84 | #define DAVINCI_I2C_MDR_STP (1 << 11) | 86 | #define DAVINCI_I2C_MDR_STP BIT(11) |
85 | #define DAVINCI_I2C_MDR_MST (1 << 10) | 87 | #define DAVINCI_I2C_MDR_MST BIT(10) |
86 | #define DAVINCI_I2C_MDR_TRX (1 << 9) | 88 | #define DAVINCI_I2C_MDR_TRX BIT(9) |
87 | #define DAVINCI_I2C_MDR_XA (1 << 8) | 89 | #define DAVINCI_I2C_MDR_XA BIT(8) |
88 | #define DAVINCI_I2C_MDR_RM (1 << 7) | 90 | #define DAVINCI_I2C_MDR_RM BIT(7) |
89 | #define DAVINCI_I2C_MDR_IRS (1 << 5) | 91 | #define DAVINCI_I2C_MDR_IRS BIT(5) |
90 | 92 | ||
91 | #define DAVINCI_I2C_IMR_AAS (1 << 6) | 93 | #define DAVINCI_I2C_IMR_AAS BIT(6) |
92 | #define DAVINCI_I2C_IMR_SCD (1 << 5) | 94 | #define DAVINCI_I2C_IMR_SCD BIT(5) |
93 | #define DAVINCI_I2C_IMR_XRDY (1 << 4) | 95 | #define DAVINCI_I2C_IMR_XRDY BIT(4) |
94 | #define DAVINCI_I2C_IMR_RRDY (1 << 3) | 96 | #define DAVINCI_I2C_IMR_RRDY BIT(3) |
95 | #define DAVINCI_I2C_IMR_ARDY (1 << 2) | 97 | #define DAVINCI_I2C_IMR_ARDY BIT(2) |
96 | #define DAVINCI_I2C_IMR_NACK (1 << 1) | 98 | #define DAVINCI_I2C_IMR_NACK BIT(1) |
97 | #define DAVINCI_I2C_IMR_AL (1 << 0) | 99 | #define DAVINCI_I2C_IMR_AL BIT(0) |
98 | |||
99 | #define MOD_REG_BIT(val, mask, set) do { \ | ||
100 | if (set) { \ | ||
101 | val |= mask; \ | ||
102 | } else { \ | ||
103 | val &= ~mask; \ | ||
104 | } \ | ||
105 | } while (0) | ||
106 | 100 | ||
107 | struct davinci_i2c_dev { | 101 | struct davinci_i2c_dev { |
108 | struct device *dev; | 102 | struct device *dev; |
@@ -113,8 +107,13 @@ struct davinci_i2c_dev { | |||
113 | u8 *buf; | 107 | u8 *buf; |
114 | size_t buf_len; | 108 | size_t buf_len; |
115 | int irq; | 109 | int irq; |
110 | int stop; | ||
116 | u8 terminate; | 111 | u8 terminate; |
117 | struct i2c_adapter adapter; | 112 | struct i2c_adapter adapter; |
113 | #ifdef CONFIG_CPU_FREQ | ||
114 | struct completion xfr_complete; | ||
115 | struct notifier_block freq_transition; | ||
116 | #endif | ||
118 | }; | 117 | }; |
119 | 118 | ||
120 | /* default platform data to use if not supplied in the platform_device */ | 119 | /* default platform data to use if not supplied in the platform_device */ |
@@ -134,12 +133,59 @@ static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg) | |||
134 | return __raw_readw(i2c_dev->base + reg); | 133 | return __raw_readw(i2c_dev->base + reg); |
135 | } | 134 | } |
136 | 135 | ||
137 | /* | 136 | /* Generate a pulse on the i2c clock pin. */ |
138 | * This functions configures I2C and brings I2C out of reset. | 137 | static void generic_i2c_clock_pulse(unsigned int scl_pin) |
139 | * This function is called during I2C init function. This function | 138 | { |
140 | * also gets called if I2C encounters any errors. | 139 | u16 i; |
140 | |||
141 | if (scl_pin) { | ||
142 | /* Send high and low on the SCL line */ | ||
143 | for (i = 0; i < 9; i++) { | ||
144 | gpio_set_value(scl_pin, 0); | ||
145 | udelay(20); | ||
146 | gpio_set_value(scl_pin, 1); | ||
147 | udelay(20); | ||
148 | } | ||
149 | } | ||
150 | } | ||
151 | |||
152 | /* This routine does i2c bus recovery as specified in the | ||
153 | * i2c protocol Rev. 03 section 3.16 titled "Bus clear" | ||
141 | */ | 154 | */ |
142 | static int i2c_davinci_init(struct davinci_i2c_dev *dev) | 155 | static void i2c_recover_bus(struct davinci_i2c_dev *dev) |
156 | { | ||
157 | u32 flag = 0; | ||
158 | struct davinci_i2c_platform_data *pdata = dev->dev->platform_data; | ||
159 | |||
160 | dev_err(dev->dev, "initiating i2c bus recovery\n"); | ||
161 | /* Send NACK to the slave */ | ||
162 | flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); | ||
163 | flag |= DAVINCI_I2C_MDR_NACK; | ||
164 | /* write the data into mode register */ | ||
165 | davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); | ||
166 | if (pdata) | ||
167 | generic_i2c_clock_pulse(pdata->scl_pin); | ||
168 | /* Send STOP */ | ||
169 | flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); | ||
170 | flag |= DAVINCI_I2C_MDR_STP; | ||
171 | davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); | ||
172 | } | ||
173 | |||
174 | static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev, | ||
175 | int val) | ||
176 | { | ||
177 | u16 w; | ||
178 | |||
179 | w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG); | ||
180 | if (!val) /* put I2C into reset */ | ||
181 | w &= ~DAVINCI_I2C_MDR_IRS; | ||
182 | else /* take I2C out of reset */ | ||
183 | w |= DAVINCI_I2C_MDR_IRS; | ||
184 | |||
185 | davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w); | ||
186 | } | ||
187 | |||
188 | static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev) | ||
143 | { | 189 | { |
144 | struct davinci_i2c_platform_data *pdata = dev->dev->platform_data; | 190 | struct davinci_i2c_platform_data *pdata = dev->dev->platform_data; |
145 | u16 psc; | 191 | u16 psc; |
@@ -148,15 +194,6 @@ static int i2c_davinci_init(struct davinci_i2c_dev *dev) | |||
148 | u32 clkh; | 194 | u32 clkh; |
149 | u32 clkl; | 195 | u32 clkl; |
150 | u32 input_clock = clk_get_rate(dev->clk); | 196 | u32 input_clock = clk_get_rate(dev->clk); |
151 | u16 w; | ||
152 | |||
153 | if (!pdata) | ||
154 | pdata = &davinci_i2c_platform_data_default; | ||
155 | |||
156 | /* put I2C into reset */ | ||
157 | w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); | ||
158 | MOD_REG_BIT(w, DAVINCI_I2C_MDR_IRS, 0); | ||
159 | davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); | ||
160 | 197 | ||
161 | /* NOTE: I2C Clock divider programming info | 198 | /* NOTE: I2C Clock divider programming info |
162 | * As per I2C specs the following formulas provide prescaler | 199 | * As per I2C specs the following formulas provide prescaler |
@@ -188,12 +225,32 @@ static int i2c_davinci_init(struct davinci_i2c_dev *dev) | |||
188 | davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh); | 225 | davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh); |
189 | davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl); | 226 | davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl); |
190 | 227 | ||
228 | dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk); | ||
229 | } | ||
230 | |||
231 | /* | ||
232 | * This function configures I2C and brings I2C out of reset. | ||
233 | * This function is called during I2C init function. This function | ||
234 | * also gets called if I2C encounters any errors. | ||
235 | */ | ||
236 | static int i2c_davinci_init(struct davinci_i2c_dev *dev) | ||
237 | { | ||
238 | struct davinci_i2c_platform_data *pdata = dev->dev->platform_data; | ||
239 | |||
240 | if (!pdata) | ||
241 | pdata = &davinci_i2c_platform_data_default; | ||
242 | |||
243 | /* put I2C into reset */ | ||
244 | davinci_i2c_reset_ctrl(dev, 0); | ||
245 | |||
246 | /* compute clock dividers */ | ||
247 | i2c_davinci_calc_clk_dividers(dev); | ||
248 | |||
191 | /* Respond at reserved "SMBus Host" slave address" (and zero); | 249 | /* Respond at reserved "SMBus Host" slave address" (and zero); |
192 | * we seem to have no option to not respond... | 250 | * we seem to have no option to not respond... |
193 | */ | 251 | */ |
194 | davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, 0x08); | 252 | davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, 0x08); |
195 | 253 | ||
196 | dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk); | ||
197 | dev_dbg(dev->dev, "PSC = %d\n", | 254 | dev_dbg(dev->dev, "PSC = %d\n", |
198 | davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG)); | 255 | davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG)); |
199 | dev_dbg(dev->dev, "CLKL = %d\n", | 256 | dev_dbg(dev->dev, "CLKL = %d\n", |
@@ -204,9 +261,7 @@ static int i2c_davinci_init(struct davinci_i2c_dev *dev) | |||
204 | pdata->bus_freq, pdata->bus_delay); | 261 | pdata->bus_freq, pdata->bus_delay); |
205 | 262 | ||
206 | /* Take the I2C module out of reset: */ | 263 | /* Take the I2C module out of reset: */ |
207 | w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); | 264 | davinci_i2c_reset_ctrl(dev, 1); |
208 | MOD_REG_BIT(w, DAVINCI_I2C_MDR_IRS, 1); | ||
209 | davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); | ||
210 | 265 | ||
211 | /* Enable interrupts */ | 266 | /* Enable interrupts */ |
212 | davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL); | 267 | davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL); |
@@ -221,14 +276,22 @@ static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev, | |||
221 | char allow_sleep) | 276 | char allow_sleep) |
222 | { | 277 | { |
223 | unsigned long timeout; | 278 | unsigned long timeout; |
279 | static u16 to_cnt; | ||
224 | 280 | ||
225 | timeout = jiffies + dev->adapter.timeout; | 281 | timeout = jiffies + dev->adapter.timeout; |
226 | while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) | 282 | while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) |
227 | & DAVINCI_I2C_STR_BB) { | 283 | & DAVINCI_I2C_STR_BB) { |
228 | if (time_after(jiffies, timeout)) { | 284 | if (to_cnt <= DAVINCI_I2C_MAX_TRIES) { |
229 | dev_warn(dev->dev, | 285 | if (time_after(jiffies, timeout)) { |
230 | "timeout waiting for bus ready\n"); | 286 | dev_warn(dev->dev, |
231 | return -ETIMEDOUT; | 287 | "timeout waiting for bus ready\n"); |
288 | to_cnt++; | ||
289 | return -ETIMEDOUT; | ||
290 | } else { | ||
291 | to_cnt = 0; | ||
292 | i2c_recover_bus(dev); | ||
293 | i2c_davinci_init(dev); | ||
294 | } | ||
232 | } | 295 | } |
233 | if (allow_sleep) | 296 | if (allow_sleep) |
234 | schedule_timeout(1); | 297 | schedule_timeout(1); |
@@ -250,9 +313,6 @@ i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop) | |||
250 | u16 w; | 313 | u16 w; |
251 | int r; | 314 | int r; |
252 | 315 | ||
253 | if (msg->len == 0) | ||
254 | return -EINVAL; | ||
255 | |||
256 | if (!pdata) | 316 | if (!pdata) |
257 | pdata = &davinci_i2c_platform_data_default; | 317 | pdata = &davinci_i2c_platform_data_default; |
258 | /* Introduce a delay, required for some boards (e.g Davinci EVM) */ | 318 | /* Introduce a delay, required for some boards (e.g Davinci EVM) */ |
@@ -264,6 +324,7 @@ i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop) | |||
264 | 324 | ||
265 | dev->buf = msg->buf; | 325 | dev->buf = msg->buf; |
266 | dev->buf_len = msg->len; | 326 | dev->buf_len = msg->len; |
327 | dev->stop = stop; | ||
267 | 328 | ||
268 | davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len); | 329 | davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len); |
269 | 330 | ||
@@ -281,23 +342,40 @@ i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop) | |||
281 | flag |= DAVINCI_I2C_MDR_TRX; | 342 | flag |= DAVINCI_I2C_MDR_TRX; |
282 | if (stop) | 343 | if (stop) |
283 | flag |= DAVINCI_I2C_MDR_STP; | 344 | flag |= DAVINCI_I2C_MDR_STP; |
345 | if (msg->len == 0) { | ||
346 | flag |= DAVINCI_I2C_MDR_RM; | ||
347 | flag &= ~DAVINCI_I2C_MDR_STP; | ||
348 | } | ||
284 | 349 | ||
285 | /* Enable receive or transmit interrupts */ | 350 | /* Enable receive or transmit interrupts */ |
286 | w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG); | 351 | w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG); |
287 | if (msg->flags & I2C_M_RD) | 352 | if (msg->flags & I2C_M_RD) |
288 | MOD_REG_BIT(w, DAVINCI_I2C_IMR_RRDY, 1); | 353 | w |= DAVINCI_I2C_IMR_RRDY; |
289 | else | 354 | else |
290 | MOD_REG_BIT(w, DAVINCI_I2C_IMR_XRDY, 1); | 355 | w |= DAVINCI_I2C_IMR_XRDY; |
291 | davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w); | 356 | davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w); |
292 | 357 | ||
293 | dev->terminate = 0; | 358 | dev->terminate = 0; |
359 | |||
294 | /* write the data into mode register */ | 360 | /* write the data into mode register */ |
295 | davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); | 361 | davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); |
296 | 362 | ||
363 | /* | ||
364 | * First byte should be set here, not after interrupt, | ||
365 | * because transmit-data-ready interrupt can come before | ||
366 | * NACK-interrupt during sending of previous message and | ||
367 | * ICDXR may have wrong data | ||
368 | */ | ||
369 | if ((!(msg->flags & I2C_M_RD)) && dev->buf_len) { | ||
370 | davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++); | ||
371 | dev->buf_len--; | ||
372 | } | ||
373 | |||
297 | r = wait_for_completion_interruptible_timeout(&dev->cmd_complete, | 374 | r = wait_for_completion_interruptible_timeout(&dev->cmd_complete, |
298 | dev->adapter.timeout); | 375 | dev->adapter.timeout); |
299 | if (r == 0) { | 376 | if (r == 0) { |
300 | dev_err(dev->dev, "controller timed out\n"); | 377 | dev_err(dev->dev, "controller timed out\n"); |
378 | i2c_recover_bus(dev); | ||
301 | i2c_davinci_init(dev); | 379 | i2c_davinci_init(dev); |
302 | dev->buf_len = 0; | 380 | dev->buf_len = 0; |
303 | return -ETIMEDOUT; | 381 | return -ETIMEDOUT; |
@@ -334,7 +412,7 @@ i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop) | |||
334 | return msg->len; | 412 | return msg->len; |
335 | if (stop) { | 413 | if (stop) { |
336 | w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); | 414 | w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG); |
337 | MOD_REG_BIT(w, DAVINCI_I2C_MDR_STP, 1); | 415 | w |= DAVINCI_I2C_MDR_STP; |
338 | davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); | 416 | davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w); |
339 | } | 417 | } |
340 | return -EREMOTEIO; | 418 | return -EREMOTEIO; |
@@ -367,12 +445,17 @@ i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) | |||
367 | if (ret < 0) | 445 | if (ret < 0) |
368 | return ret; | 446 | return ret; |
369 | } | 447 | } |
448 | |||
449 | #ifdef CONFIG_CPU_FREQ | ||
450 | complete(&dev->xfr_complete); | ||
451 | #endif | ||
452 | |||
370 | return num; | 453 | return num; |
371 | } | 454 | } |
372 | 455 | ||
373 | static u32 i2c_davinci_func(struct i2c_adapter *adap) | 456 | static u32 i2c_davinci_func(struct i2c_adapter *adap) |
374 | { | 457 | { |
375 | return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); | 458 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; |
376 | } | 459 | } |
377 | 460 | ||
378 | static void terminate_read(struct davinci_i2c_dev *dev) | 461 | static void terminate_read(struct davinci_i2c_dev *dev) |
@@ -431,6 +514,14 @@ static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id) | |||
431 | case DAVINCI_I2C_IVR_ARDY: | 514 | case DAVINCI_I2C_IVR_ARDY: |
432 | davinci_i2c_write_reg(dev, | 515 | davinci_i2c_write_reg(dev, |
433 | DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY); | 516 | DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY); |
517 | if (((dev->buf_len == 0) && (dev->stop != 0)) || | ||
518 | (dev->cmd_err & DAVINCI_I2C_STR_NACK)) { | ||
519 | w = davinci_i2c_read_reg(dev, | ||
520 | DAVINCI_I2C_MDR_REG); | ||
521 | w |= DAVINCI_I2C_MDR_STP; | ||
522 | davinci_i2c_write_reg(dev, | ||
523 | DAVINCI_I2C_MDR_REG, w); | ||
524 | } | ||
434 | complete(&dev->cmd_complete); | 525 | complete(&dev->cmd_complete); |
435 | break; | 526 | break; |
436 | 527 | ||
@@ -462,7 +553,7 @@ static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id) | |||
462 | 553 | ||
463 | w = davinci_i2c_read_reg(dev, | 554 | w = davinci_i2c_read_reg(dev, |
464 | DAVINCI_I2C_IMR_REG); | 555 | DAVINCI_I2C_IMR_REG); |
465 | MOD_REG_BIT(w, DAVINCI_I2C_IMR_XRDY, 0); | 556 | w &= ~DAVINCI_I2C_IMR_XRDY; |
466 | davinci_i2c_write_reg(dev, | 557 | davinci_i2c_write_reg(dev, |
467 | DAVINCI_I2C_IMR_REG, | 558 | DAVINCI_I2C_IMR_REG, |
468 | w); | 559 | w); |
@@ -491,6 +582,48 @@ static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id) | |||
491 | return count ? IRQ_HANDLED : IRQ_NONE; | 582 | return count ? IRQ_HANDLED : IRQ_NONE; |
492 | } | 583 | } |
493 | 584 | ||
585 | #ifdef CONFIG_CPU_FREQ | ||
586 | static int i2c_davinci_cpufreq_transition(struct notifier_block *nb, | ||
587 | unsigned long val, void *data) | ||
588 | { | ||
589 | struct davinci_i2c_dev *dev; | ||
590 | |||
591 | dev = container_of(nb, struct davinci_i2c_dev, freq_transition); | ||
592 | if (val == CPUFREQ_PRECHANGE) { | ||
593 | wait_for_completion(&dev->xfr_complete); | ||
594 | davinci_i2c_reset_ctrl(dev, 0); | ||
595 | } else if (val == CPUFREQ_POSTCHANGE) { | ||
596 | i2c_davinci_calc_clk_dividers(dev); | ||
597 | davinci_i2c_reset_ctrl(dev, 1); | ||
598 | } | ||
599 | |||
600 | return 0; | ||
601 | } | ||
602 | |||
603 | static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev) | ||
604 | { | ||
605 | dev->freq_transition.notifier_call = i2c_davinci_cpufreq_transition; | ||
606 | |||
607 | return cpufreq_register_notifier(&dev->freq_transition, | ||
608 | CPUFREQ_TRANSITION_NOTIFIER); | ||
609 | } | ||
610 | |||
611 | static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev) | ||
612 | { | ||
613 | cpufreq_unregister_notifier(&dev->freq_transition, | ||
614 | CPUFREQ_TRANSITION_NOTIFIER); | ||
615 | } | ||
616 | #else | ||
617 | static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev) | ||
618 | { | ||
619 | return 0; | ||
620 | } | ||
621 | |||
622 | static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev) | ||
623 | { | ||
624 | } | ||
625 | #endif | ||
626 | |||
494 | static struct i2c_algorithm i2c_davinci_algo = { | 627 | static struct i2c_algorithm i2c_davinci_algo = { |
495 | .master_xfer = i2c_davinci_xfer, | 628 | .master_xfer = i2c_davinci_xfer, |
496 | .functionality = i2c_davinci_func, | 629 | .functionality = i2c_davinci_func, |
@@ -530,6 +663,9 @@ static int davinci_i2c_probe(struct platform_device *pdev) | |||
530 | } | 663 | } |
531 | 664 | ||
532 | init_completion(&dev->cmd_complete); | 665 | init_completion(&dev->cmd_complete); |
666 | #ifdef CONFIG_CPU_FREQ | ||
667 | init_completion(&dev->xfr_complete); | ||
668 | #endif | ||
533 | dev->dev = get_device(&pdev->dev); | 669 | dev->dev = get_device(&pdev->dev); |
534 | dev->irq = irq->start; | 670 | dev->irq = irq->start; |
535 | platform_set_drvdata(pdev, dev); | 671 | platform_set_drvdata(pdev, dev); |
@@ -541,7 +677,12 @@ static int davinci_i2c_probe(struct platform_device *pdev) | |||
541 | } | 677 | } |
542 | clk_enable(dev->clk); | 678 | clk_enable(dev->clk); |
543 | 679 | ||
544 | dev->base = (void __iomem *)IO_ADDRESS(mem->start); | 680 | dev->base = ioremap(mem->start, resource_size(mem)); |
681 | if (!dev->base) { | ||
682 | r = -EBUSY; | ||
683 | goto err_mem_ioremap; | ||
684 | } | ||
685 | |||
545 | i2c_davinci_init(dev); | 686 | i2c_davinci_init(dev); |
546 | 687 | ||
547 | r = request_irq(dev->irq, i2c_davinci_isr, 0, pdev->name, dev); | 688 | r = request_irq(dev->irq, i2c_davinci_isr, 0, pdev->name, dev); |
@@ -550,6 +691,12 @@ static int davinci_i2c_probe(struct platform_device *pdev) | |||
550 | goto err_unuse_clocks; | 691 | goto err_unuse_clocks; |
551 | } | 692 | } |
552 | 693 | ||
694 | r = i2c_davinci_cpufreq_register(dev); | ||
695 | if (r) { | ||
696 | dev_err(&pdev->dev, "failed to register cpufreq\n"); | ||
697 | goto err_free_irq; | ||
698 | } | ||
699 | |||
553 | adap = &dev->adapter; | 700 | adap = &dev->adapter; |
554 | i2c_set_adapdata(adap, dev); | 701 | i2c_set_adapdata(adap, dev); |
555 | adap->owner = THIS_MODULE; | 702 | adap->owner = THIS_MODULE; |
@@ -571,6 +718,8 @@ static int davinci_i2c_probe(struct platform_device *pdev) | |||
571 | err_free_irq: | 718 | err_free_irq: |
572 | free_irq(dev->irq, dev); | 719 | free_irq(dev->irq, dev); |
573 | err_unuse_clocks: | 720 | err_unuse_clocks: |
721 | iounmap(dev->base); | ||
722 | err_mem_ioremap: | ||
574 | clk_disable(dev->clk); | 723 | clk_disable(dev->clk); |
575 | clk_put(dev->clk); | 724 | clk_put(dev->clk); |
576 | dev->clk = NULL; | 725 | dev->clk = NULL; |
@@ -589,6 +738,8 @@ static int davinci_i2c_remove(struct platform_device *pdev) | |||
589 | struct davinci_i2c_dev *dev = platform_get_drvdata(pdev); | 738 | struct davinci_i2c_dev *dev = platform_get_drvdata(pdev); |
590 | struct resource *mem; | 739 | struct resource *mem; |
591 | 740 | ||
741 | i2c_davinci_cpufreq_deregister(dev); | ||
742 | |||
592 | platform_set_drvdata(pdev, NULL); | 743 | platform_set_drvdata(pdev, NULL); |
593 | i2c_del_adapter(&dev->adapter); | 744 | i2c_del_adapter(&dev->adapter); |
594 | put_device(&pdev->dev); | 745 | put_device(&pdev->dev); |
@@ -599,6 +750,7 @@ static int davinci_i2c_remove(struct platform_device *pdev) | |||
599 | 750 | ||
600 | davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0); | 751 | davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0); |
601 | free_irq(IRQ_I2C, dev); | 752 | free_irq(IRQ_I2C, dev); |
753 | iounmap(dev->base); | ||
602 | kfree(dev); | 754 | kfree(dev); |
603 | 755 | ||
604 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 756 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
@@ -606,6 +758,41 @@ static int davinci_i2c_remove(struct platform_device *pdev) | |||
606 | return 0; | 758 | return 0; |
607 | } | 759 | } |
608 | 760 | ||
761 | #ifdef CONFIG_PM | ||
762 | static int davinci_i2c_suspend(struct device *dev) | ||
763 | { | ||
764 | struct platform_device *pdev = to_platform_device(dev); | ||
765 | struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev); | ||
766 | |||
767 | /* put I2C into reset */ | ||
768 | davinci_i2c_reset_ctrl(i2c_dev, 0); | ||
769 | clk_disable(i2c_dev->clk); | ||
770 | |||
771 | return 0; | ||
772 | } | ||
773 | |||
774 | static int davinci_i2c_resume(struct device *dev) | ||
775 | { | ||
776 | struct platform_device *pdev = to_platform_device(dev); | ||
777 | struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev); | ||
778 | |||
779 | clk_enable(i2c_dev->clk); | ||
780 | /* take I2C out of reset */ | ||
781 | davinci_i2c_reset_ctrl(i2c_dev, 1); | ||
782 | |||
783 | return 0; | ||
784 | } | ||
785 | |||
786 | static const struct dev_pm_ops davinci_i2c_pm = { | ||
787 | .suspend = davinci_i2c_suspend, | ||
788 | .resume = davinci_i2c_resume, | ||
789 | }; | ||
790 | |||
791 | #define davinci_i2c_pm_ops (&davinci_i2c_pm) | ||
792 | #else | ||
793 | #define davinci_i2c_pm_ops NULL | ||
794 | #endif | ||
795 | |||
609 | /* work with hotplug and coldplug */ | 796 | /* work with hotplug and coldplug */ |
610 | MODULE_ALIAS("platform:i2c_davinci"); | 797 | MODULE_ALIAS("platform:i2c_davinci"); |
611 | 798 | ||
@@ -615,6 +802,7 @@ static struct platform_driver davinci_i2c_driver = { | |||
615 | .driver = { | 802 | .driver = { |
616 | .name = "i2c_davinci", | 803 | .name = "i2c_davinci", |
617 | .owner = THIS_MODULE, | 804 | .owner = THIS_MODULE, |
805 | .pm = davinci_i2c_pm_ops, | ||
618 | }, | 806 | }, |
619 | }; | 807 | }; |
620 | 808 | ||