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authorsrinidhi kasagar <srinidhi.kasagar@stericsson.com>2010-02-01 09:14:54 -0500
committerBen Dooks <ben-linux@fluff.org>2010-03-07 17:02:16 -0500
commit3f9900f17cdb0366d234c0487df80a6b0d18c852 (patch)
tree90626f0ae4d1f8fea1cd7bd259d2e25b2d1643fa /drivers/i2c
parent08b8499bdd26822df16f962db88215d02e40850a (diff)
i2c: Add support for Ux500/Nomadik I2C controller
This adds support for ST-Ericsson's I2C block found in Ux500 and Nomadik 8815 platforms. Signed-off-by: srinidhi kasagar <srinidhi.kasagar@stericsson.com> Acked-by: Andrea Gallo <andrea.gallo@stericsson.com> Acked-by: Linus Walleij <linus.walleij@stericsson.com> Reviewed-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'drivers/i2c')
-rw-r--r--drivers/i2c/busses/Kconfig7
-rw-r--r--drivers/i2c/busses/Makefile1
-rw-r--r--drivers/i2c/busses/i2c-nomadik.c959
3 files changed, 967 insertions, 0 deletions
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 4cc3807bd31c..10041813c6ed 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -440,6 +440,13 @@ config I2C_MV64XXX
440 This driver can also be built as a module. If so, the module 440 This driver can also be built as a module. If so, the module
441 will be called i2c-mv64xxx. 441 will be called i2c-mv64xxx.
442 442
443config I2C_NOMADIK
444 tristate "ST-Ericsson Nomadik/Ux500 I2C Controller"
445 depends on PLAT_NOMADIK
446 help
447 If you say yes to this option, support will be included for the
448 I2C interface from ST-Ericsson's Nomadik and Ux500 architectures.
449
443config I2C_OCORES 450config I2C_OCORES
444 tristate "OpenCores I2C Controller" 451 tristate "OpenCores I2C Controller"
445 depends on EXPERIMENTAL 452 depends on EXPERIMENTAL
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index c2c4ea1908d8..59abcf48e6a9 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o
42obj-$(CONFIG_I2C_IXP2000) += i2c-ixp2000.o 42obj-$(CONFIG_I2C_IXP2000) += i2c-ixp2000.o
43obj-$(CONFIG_I2C_MPC) += i2c-mpc.o 43obj-$(CONFIG_I2C_MPC) += i2c-mpc.o
44obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o 44obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o
45obj-$(CONFIG_I2C_NOMADIK) += i2c-nomadik.o
45obj-$(CONFIG_I2C_OCORES) += i2c-ocores.o 46obj-$(CONFIG_I2C_OCORES) += i2c-ocores.o
46obj-$(CONFIG_I2C_OMAP) += i2c-omap.o 47obj-$(CONFIG_I2C_OMAP) += i2c-omap.o
47obj-$(CONFIG_I2C_PASEMI) += i2c-pasemi.o 48obj-$(CONFIG_I2C_PASEMI) += i2c-pasemi.o
diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c
new file mode 100644
index 000000000000..a15f731fa451
--- /dev/null
+++ b/drivers/i2c/busses/i2c-nomadik.c
@@ -0,0 +1,959 @@
1/*
2 * Copyright (C) 2009 ST-Ericsson
3 * Copyright (C) 2009 STMicroelectronics
4 *
5 * I2C master mode controller driver, used in Nomadik 8815
6 * and Ux500 platforms.
7 *
8 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
9 * Author: Sachin Verma <sachin.verma@st.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2, as
13 * published by the Free Software Foundation.
14 */
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/platform_device.h>
18#include <linux/delay.h>
19#include <linux/interrupt.h>
20#include <linux/i2c.h>
21#include <linux/err.h>
22#include <linux/clk.h>
23#include <linux/io.h>
24
25#include <plat/i2c.h>
26
27#define DRIVER_NAME "nmk-i2c"
28
29/* I2C Controller register offsets */
30#define I2C_CR (0x000)
31#define I2C_SCR (0x004)
32#define I2C_HSMCR (0x008)
33#define I2C_MCR (0x00C)
34#define I2C_TFR (0x010)
35#define I2C_SR (0x014)
36#define I2C_RFR (0x018)
37#define I2C_TFTR (0x01C)
38#define I2C_RFTR (0x020)
39#define I2C_DMAR (0x024)
40#define I2C_BRCR (0x028)
41#define I2C_IMSCR (0x02C)
42#define I2C_RISR (0x030)
43#define I2C_MISR (0x034)
44#define I2C_ICR (0x038)
45
46/* Control registers */
47#define I2C_CR_PE (0x1 << 0) /* Peripheral Enable */
48#define I2C_CR_OM (0x3 << 1) /* Operating mode */
49#define I2C_CR_SAM (0x1 << 3) /* Slave addressing mode */
50#define I2C_CR_SM (0x3 << 4) /* Speed mode */
51#define I2C_CR_SGCM (0x1 << 6) /* Slave general call mode */
52#define I2C_CR_FTX (0x1 << 7) /* Flush Transmit */
53#define I2C_CR_FRX (0x1 << 8) /* Flush Receive */
54#define I2C_CR_DMA_TX_EN (0x1 << 9) /* DMA Tx enable */
55#define I2C_CR_DMA_RX_EN (0x1 << 10) /* DMA Rx Enable */
56#define I2C_CR_DMA_SLE (0x1 << 11) /* DMA sync. logic enable */
57#define I2C_CR_LM (0x1 << 12) /* Loopback mode */
58#define I2C_CR_FON (0x3 << 13) /* Filtering on */
59#define I2C_CR_FS (0x3 << 15) /* Force stop enable */
60
61/* Master controller (MCR) register */
62#define I2C_MCR_OP (0x1 << 0) /* Operation */
63#define I2C_MCR_A7 (0x7f << 1) /* 7-bit address */
64#define I2C_MCR_EA10 (0x7 << 8) /* 10-bit Extended address */
65#define I2C_MCR_SB (0x1 << 11) /* Extended address */
66#define I2C_MCR_AM (0x3 << 12) /* Address type */
67#define I2C_MCR_STOP (0x1 << 14) /* Stop condition */
68#define I2C_MCR_LENGTH (0x7ff << 15) /* Transaction length */
69
70/* Status register (SR) */
71#define I2C_SR_OP (0x3 << 0) /* Operation */
72#define I2C_SR_STATUS (0x3 << 2) /* controller status */
73#define I2C_SR_CAUSE (0x7 << 4) /* Abort cause */
74#define I2C_SR_TYPE (0x3 << 7) /* Receive type */
75#define I2C_SR_LENGTH (0x7ff << 9) /* Transfer length */
76
77/* Interrupt mask set/clear (IMSCR) bits */
78#define I2C_IT_TXFE (0x1 << 0)
79#define I2C_IT_TXFNE (0x1 << 1)
80#define I2C_IT_TXFF (0x1 << 2)
81#define I2C_IT_TXFOVR (0x1 << 3)
82#define I2C_IT_RXFE (0x1 << 4)
83#define I2C_IT_RXFNF (0x1 << 5)
84#define I2C_IT_RXFF (0x1 << 6)
85#define I2C_IT_RFSR (0x1 << 16)
86#define I2C_IT_RFSE (0x1 << 17)
87#define I2C_IT_WTSR (0x1 << 18)
88#define I2C_IT_MTD (0x1 << 19)
89#define I2C_IT_STD (0x1 << 20)
90#define I2C_IT_MAL (0x1 << 24)
91#define I2C_IT_BERR (0x1 << 25)
92#define I2C_IT_MTDWS (0x1 << 28)
93
94#define GEN_MASK(val, mask, sb) (((val) << (sb)) & (mask))
95
96/* some bits in ICR are reserved */
97#define I2C_CLEAR_ALL_INTS 0x131f007f
98
99/* first three msb bits are reserved */
100#define IRQ_MASK(mask) (mask & 0x1fffffff)
101
102/* maximum threshold value */
103#define MAX_I2C_FIFO_THRESHOLD 15
104
105enum i2c_status {
106 I2C_NOP,
107 I2C_ON_GOING,
108 I2C_OK,
109 I2C_ABORT
110};
111
112/* operation */
113enum i2c_operation {
114 I2C_NO_OPERATION = 0xff,
115 I2C_WRITE = 0x00,
116 I2C_READ = 0x01
117};
118
119/* controller response timeout in ms */
120#define I2C_TIMEOUT_MS 500
121
122/**
123 * struct i2c_nmk_client - client specific data
124 * @slave_adr: 7-bit slave address
125 * @count: no. bytes to be transfered
126 * @buffer: client data buffer
127 * @xfer_bytes: bytes transfered till now
128 * @operation: current I2C operation
129 */
130struct i2c_nmk_client {
131 unsigned short slave_adr;
132 unsigned long count;
133 unsigned char *buffer;
134 unsigned long xfer_bytes;
135 enum i2c_operation operation;
136};
137
138/**
139 * struct nmk_i2c_dev - private data structure of the controller
140 * @pdev: parent platform device
141 * @adap: corresponding I2C adapter
142 * @irq: interrupt line for the controller
143 * @virtbase: virtual io memory area
144 * @clk: hardware i2c block clock
145 * @cfg: machine provided controller configuration
146 * @cli: holder of client specific data
147 * @stop: stop condition
148 * @xfer_complete: acknowledge completion for a I2C message
149 * @result: controller propogated result
150 */
151struct nmk_i2c_dev {
152 struct platform_device *pdev;
153 struct i2c_adapter adap;
154 int irq;
155 void __iomem *virtbase;
156 struct clk *clk;
157 struct nmk_i2c_controller cfg;
158 struct i2c_nmk_client cli;
159 int stop;
160 struct completion xfer_complete;
161 int result;
162};
163
164/* controller's abort causes */
165static const char *abort_causes[] = {
166 "no ack received after address transmission",
167 "no ack received during data phase",
168 "ack received after xmission of master code",
169 "master lost arbitration",
170 "slave restarts",
171 "slave reset",
172 "overflow, maxsize is 2047 bytes",
173};
174
175static inline void i2c_set_bit(void __iomem *reg, u32 mask)
176{
177 writel(readl(reg) | mask, reg);
178}
179
180static inline void i2c_clr_bit(void __iomem *reg, u32 mask)
181{
182 writel(readl(reg) & ~mask, reg);
183}
184
185/**
186 * flush_i2c_fifo() - This function flushes the I2C FIFO
187 * @dev: private data of I2C Driver
188 *
189 * This function flushes the I2C Tx and Rx FIFOs. It returns
190 * 0 on successful flushing of FIFO
191 */
192static int flush_i2c_fifo(struct nmk_i2c_dev *dev)
193{
194#define LOOP_ATTEMPTS 10
195 int i;
196 unsigned long timeout;
197
198 /*
199 * flush the transmit and receive FIFO. The flushing
200 * operation takes several cycles before to be completed.
201 * On the completion, the I2C internal logic clears these
202 * bits, until then no one must access Tx, Rx FIFO and
203 * should poll on these bits waiting for the completion.
204 */
205 writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR);
206
207 for (i = 0; i < LOOP_ATTEMPTS; i++) {
208 timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT_MS);
209
210 while (!time_after(jiffies, timeout)) {
211 if ((readl(dev->virtbase + I2C_CR) &
212 (I2C_CR_FTX | I2C_CR_FRX)) == 0)
213 return 0;
214 }
215 }
216
217 dev_err(&dev->pdev->dev, "flushing operation timed out "
218 "giving up after %d attempts", LOOP_ATTEMPTS);
219
220 return -ETIMEDOUT;
221}
222
223/**
224 * disable_all_interrupts() - Disable all interrupts of this I2c Bus
225 * @dev: private data of I2C Driver
226 */
227static void disable_all_interrupts(struct nmk_i2c_dev *dev)
228{
229 u32 mask = IRQ_MASK(0);
230 writel(mask, dev->virtbase + I2C_IMSCR);
231}
232
233/**
234 * clear_all_interrupts() - Clear all interrupts of I2C Controller
235 * @dev: private data of I2C Driver
236 */
237static void clear_all_interrupts(struct nmk_i2c_dev *dev)
238{
239 u32 mask;
240 mask = IRQ_MASK(I2C_CLEAR_ALL_INTS);
241 writel(mask, dev->virtbase + I2C_ICR);
242}
243
244/**
245 * init_hw() - initialize the I2C hardware
246 * @dev: private data of I2C Driver
247 */
248static int init_hw(struct nmk_i2c_dev *dev)
249{
250 int stat;
251
252 stat = flush_i2c_fifo(dev);
253 if (stat)
254 return stat;
255
256 /* disable the controller */
257 i2c_clr_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
258
259 disable_all_interrupts(dev);
260
261 clear_all_interrupts(dev);
262
263 dev->cli.operation = I2C_NO_OPERATION;
264
265 return 0;
266}
267
268/* enable peripheral, master mode operation */
269#define DEFAULT_I2C_REG_CR ((1 << 1) | I2C_CR_PE)
270
271/**
272 * load_i2c_mcr_reg() - load the MCR register
273 * @dev: private data of controller
274 */
275static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev)
276{
277 u32 mcr = 0;
278
279 /* 7-bit address transaction */
280 mcr |= GEN_MASK(1, I2C_MCR_AM, 12);
281 mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1);
282
283 /* start byte procedure not applied */
284 mcr |= GEN_MASK(0, I2C_MCR_SB, 11);
285
286 /* check the operation, master read/write? */
287 if (dev->cli.operation == I2C_WRITE)
288 mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0);
289 else
290 mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0);
291
292 /* stop or repeated start? */
293 if (dev->stop)
294 mcr |= GEN_MASK(1, I2C_MCR_STOP, 14);
295 else
296 mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14));
297
298 mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15);
299
300 return mcr;
301}
302
303/**
304 * setup_i2c_controller() - setup the controller
305 * @dev: private data of controller
306 */
307static void setup_i2c_controller(struct nmk_i2c_dev *dev)
308{
309 u32 brcr1, brcr2;
310 u32 i2c_clk, div;
311
312 writel(0x0, dev->virtbase + I2C_CR);
313 writel(0x0, dev->virtbase + I2C_HSMCR);
314 writel(0x0, dev->virtbase + I2C_TFTR);
315 writel(0x0, dev->virtbase + I2C_RFTR);
316 writel(0x0, dev->virtbase + I2C_DMAR);
317
318 /*
319 * set the slsu:
320 *
321 * slsu defines the data setup time after SCL clock
322 * stretching in terms of i2c clk cycles. The
323 * needed setup time for the three modes are 250ns,
324 * 100ns, 10ns repectively thus leading to the values
325 * of 14, 6, 2 for a 48 MHz i2c clk.
326 */
327 writel(dev->cfg.slsu << 16, dev->virtbase + I2C_SCR);
328
329 i2c_clk = clk_get_rate(dev->clk);
330
331 /* fallback to std. mode if machine has not provided it */
332 if (dev->cfg.clk_freq == 0)
333 dev->cfg.clk_freq = 100000;
334
335 /*
336 * The spec says, in case of std. mode the divider is
337 * 2 whereas it is 3 for fast and fastplus mode of
338 * operation. TODO - high speed support.
339 */
340 div = (dev->cfg.clk_freq > 100000) ? 3 : 2;
341
342 /*
343 * generate the mask for baud rate counters. The controller
344 * has two baud rate counters. One is used for High speed
345 * operation, and the other is for std, fast mode, fast mode
346 * plus operation. Currently we do not supprt high speed mode
347 * so set brcr1 to 0.
348 */
349 brcr1 = 0 << 16;
350 brcr2 = (i2c_clk/(dev->cfg.clk_freq * div)) & 0xffff;
351
352 /* set the baud rate counter register */
353 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
354
355 /*
356 * set the speed mode. Currently we support
357 * only standard and fast mode of operation
358 * TODO - support for fast mode plus (upto 1Mb/s)
359 * and high speed (up to 3.4 Mb/s)
360 */
361 if (dev->cfg.sm > I2C_FREQ_MODE_FAST) {
362 dev_err(&dev->pdev->dev, "do not support this mode "
363 "defaulting to std. mode\n");
364 brcr2 = i2c_clk/(100000 * 2) & 0xffff;
365 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
366 writel(I2C_FREQ_MODE_STANDARD << 4,
367 dev->virtbase + I2C_CR);
368 }
369 writel(dev->cfg.sm << 4, dev->virtbase + I2C_CR);
370
371 /* set the Tx and Rx FIFO threshold */
372 writel(dev->cfg.tft, dev->virtbase + I2C_TFTR);
373 writel(dev->cfg.rft, dev->virtbase + I2C_RFTR);
374}
375
376/**
377 * read_i2c() - Read from I2C client device
378 * @dev: private data of I2C Driver
379 *
380 * This function reads from i2c client device when controller is in
381 * master mode. There is a completion timeout. If there is no transfer
382 * before timeout error is returned.
383 */
384static int read_i2c(struct nmk_i2c_dev *dev)
385{
386 u32 status = 0;
387 u32 mcr;
388 u32 irq_mask = 0;
389 int timeout;
390
391 mcr = load_i2c_mcr_reg(dev);
392 writel(mcr, dev->virtbase + I2C_MCR);
393
394 /* load the current CR value */
395 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
396 dev->virtbase + I2C_CR);
397
398 /* enable the controller */
399 i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
400
401 init_completion(&dev->xfer_complete);
402
403 /* enable interrupts by setting the mask */
404 irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF |
405 I2C_IT_MAL | I2C_IT_BERR);
406
407 if (dev->stop)
408 irq_mask |= I2C_IT_MTD;
409 else
410 irq_mask |= I2C_IT_MTDWS;
411
412 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
413
414 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
415 dev->virtbase + I2C_IMSCR);
416
417 timeout = wait_for_completion_interruptible_timeout(
418 &dev->xfer_complete, msecs_to_jiffies(I2C_TIMEOUT_MS));
419
420 if (timeout < 0) {
421 dev_err(&dev->pdev->dev,
422 "wait_for_completion_interruptible_timeout"
423 "returned %d waiting for event\n", timeout);
424 status = timeout;
425 }
426
427 if (timeout == 0) {
428 /* controler has timedout, re-init the h/w */
429 dev_err(&dev->pdev->dev, "controller timed out, re-init h/w\n");
430 (void) init_hw(dev);
431 status = -ETIMEDOUT;
432 }
433
434 return status;
435}
436
437/**
438 * write_i2c() - Write data to I2C client.
439 * @dev: private data of I2C Driver
440 *
441 * This function writes data to I2C client
442 */
443static int write_i2c(struct nmk_i2c_dev *dev)
444{
445 u32 status = 0;
446 u32 mcr;
447 u32 irq_mask = 0;
448 int timeout;
449
450 mcr = load_i2c_mcr_reg(dev);
451
452 writel(mcr, dev->virtbase + I2C_MCR);
453
454 /* load the current CR value */
455 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
456 dev->virtbase + I2C_CR);
457
458 /* enable the controller */
459 i2c_set_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
460
461 init_completion(&dev->xfer_complete);
462
463 /* enable interrupts by settings the masks */
464 irq_mask = (I2C_IT_TXFNE | I2C_IT_TXFOVR |
465 I2C_IT_MAL | I2C_IT_BERR);
466
467 /*
468 * check if we want to transfer a single or multiple bytes, if so
469 * set the MTDWS bit (Master Transaction Done Without Stop)
470 * to start repeated start operation
471 */
472 if (dev->stop)
473 irq_mask |= I2C_IT_MTD;
474 else
475 irq_mask |= I2C_IT_MTDWS;
476
477 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
478
479 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
480 dev->virtbase + I2C_IMSCR);
481
482 timeout = wait_for_completion_interruptible_timeout(
483 &dev->xfer_complete, msecs_to_jiffies(I2C_TIMEOUT_MS));
484
485 if (timeout < 0) {
486 dev_err(&dev->pdev->dev,
487 "wait_for_completion_interruptible_timeout"
488 "returned %d waiting for event\n", timeout);
489 status = timeout;
490 }
491
492 if (timeout == 0) {
493 /* controler has timedout, re-init the h/w */
494 dev_err(&dev->pdev->dev, "controller timed out, re-init h/w\n");
495 (void) init_hw(dev);
496 status = -ETIMEDOUT;
497 }
498
499 return status;
500}
501
502/**
503 * nmk_i2c_xfer() - I2C transfer function used by kernel framework
504 * @i2c_adap - Adapter pointer to the controller
505 * @msgs[] - Pointer to data to be written.
506 * @num_msgs - Number of messages to be executed
507 *
508 * This is the function called by the generic kernel i2c_transfer()
509 * or i2c_smbus...() API calls. Note that this code is protected by the
510 * semaphore set in the kernel i2c_transfer() function.
511 *
512 * NOTE:
513 * READ TRANSFER : We impose a restriction of the first message to be the
514 * index message for any read transaction.
515 * - a no index is coded as '0',
516 * - 2byte big endian index is coded as '3'
517 * !!! msg[0].buf holds the actual index.
518 * This is compatible with generic messages of smbus emulator
519 * that send a one byte index.
520 * eg. a I2C transation to read 2 bytes from index 0
521 * idx = 0;
522 * msg[0].addr = client->addr;
523 * msg[0].flags = 0x0;
524 * msg[0].len = 1;
525 * msg[0].buf = &idx;
526 *
527 * msg[1].addr = client->addr;
528 * msg[1].flags = I2C_M_RD;
529 * msg[1].len = 2;
530 * msg[1].buf = rd_buff
531 * i2c_transfer(adap, msg, 2);
532 *
533 * WRITE TRANSFER : The I2C standard interface interprets all data as payload.
534 * If you want to emulate an SMBUS write transaction put the
535 * index as first byte(or first and second) in the payload.
536 * eg. a I2C transation to write 2 bytes from index 1
537 * wr_buff[0] = 0x1;
538 * wr_buff[1] = 0x23;
539 * wr_buff[2] = 0x46;
540 * msg[0].flags = 0x0;
541 * msg[0].len = 3;
542 * msg[0].buf = wr_buff;
543 * i2c_transfer(adap, msg, 1);
544 *
545 * To read or write a block of data (multiple bytes) using SMBUS emulation
546 * please use the i2c_smbus_read_i2c_block_data()
547 * or i2c_smbus_write_i2c_block_data() API
548 */
549static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap,
550 struct i2c_msg msgs[], int num_msgs)
551{
552 int status;
553 int i;
554 u32 cause;
555 struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap);
556
557 status = init_hw(dev);
558 if (status)
559 return status;
560
561 /* setup the i2c controller */
562 setup_i2c_controller(dev);
563
564 for (i = 0; i < num_msgs; i++) {
565 if (unlikely(msgs[i].flags & I2C_M_TEN)) {
566 dev_err(&dev->pdev->dev, "10 bit addressing"
567 "not supported\n");
568 return -EINVAL;
569 }
570 dev->cli.slave_adr = msgs[i].addr;
571 dev->cli.buffer = msgs[i].buf;
572 dev->cli.count = msgs[i].len;
573 dev->stop = (i < (num_msgs - 1)) ? 0 : 1;
574 dev->result = 0;
575
576 if (msgs[i].flags & I2C_M_RD) {
577 /* it is a read operation */
578 dev->cli.operation = I2C_READ;
579 status = read_i2c(dev);
580 } else {
581 /* write operation */
582 dev->cli.operation = I2C_WRITE;
583 status = write_i2c(dev);
584 }
585 if (status || (dev->result)) {
586 /* get the abort cause */
587 cause = (readl(dev->virtbase + I2C_SR) >> 4) & 0x7;
588 dev_err(&dev->pdev->dev, "error during I2C"
589 "message xfer: %d\n", cause);
590 dev_err(&dev->pdev->dev, "%s\n",
591 cause >= ARRAY_SIZE(abort_causes)
592 ? "unknown reason" : abort_causes[cause]);
593 return status;
594 }
595 mdelay(1);
596 }
597 /* return the no. messages processed */
598 if (status)
599 return status;
600 else
601 return num_msgs;
602}
603
604/**
605 * disable_interrupts() - disable the interrupts
606 * @dev: private data of controller
607 */
608static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq)
609{
610 irq = IRQ_MASK(irq);
611 writel(readl(dev->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq),
612 dev->virtbase + I2C_IMSCR);
613 return 0;
614}
615
616/**
617 * i2c_irq_handler() - interrupt routine
618 * @irq: interrupt number
619 * @arg: data passed to the handler
620 *
621 * This is the interrupt handler for the i2c driver. Currently
622 * it handles the major interrupts like Rx & Tx FIFO management
623 * interrupts, master transaction interrupts, arbitration and
624 * bus error interrupts. The rest of the interrupts are treated as
625 * unhandled.
626 */
627static irqreturn_t i2c_irq_handler(int irq, void *arg)
628{
629 struct nmk_i2c_dev *dev = arg;
630 u32 tft, rft;
631 u32 count;
632 u32 misr;
633 u32 src = 0;
634
635 /* load Tx FIFO and Rx FIFO threshold values */
636 tft = readl(dev->virtbase + I2C_TFTR);
637 rft = readl(dev->virtbase + I2C_RFTR);
638
639 /* read interrupt status register */
640 misr = readl(dev->virtbase + I2C_MISR);
641
642 src = __ffs(misr);
643 switch ((1 << src)) {
644
645 /* Transmit FIFO nearly empty interrupt */
646 case I2C_IT_TXFNE:
647 {
648 if (dev->cli.operation == I2C_READ) {
649 /*
650 * in read operation why do we care for writing?
651 * so disable the Transmit FIFO interrupt
652 */
653 disable_interrupts(dev, I2C_IT_TXFNE);
654 } else {
655 for (count = (MAX_I2C_FIFO_THRESHOLD - tft - 2);
656 (count > 0) &&
657 (dev->cli.count != 0);
658 count--) {
659 /* write to the Tx FIFO */
660 writeb(*dev->cli.buffer,
661 dev->virtbase + I2C_TFR);
662 dev->cli.buffer++;
663 dev->cli.count--;
664 dev->cli.xfer_bytes++;
665 }
666 /*
667 * if done, close the transfer by disabling the
668 * corresponding TXFNE interrupt
669 */
670 if (dev->cli.count == 0)
671 disable_interrupts(dev, I2C_IT_TXFNE);
672 }
673 }
674 break;
675
676 /*
677 * Rx FIFO nearly full interrupt.
678 * This is set when the numer of entries in Rx FIFO is
679 * greater or equal than the threshold value programmed
680 * in RFT
681 */
682 case I2C_IT_RXFNF:
683 for (count = rft; count > 0; count--) {
684 /* Read the Rx FIFO */
685 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
686 dev->cli.buffer++;
687 }
688 dev->cli.count -= rft;
689 dev->cli.xfer_bytes += rft;
690 break;
691
692 /* Rx FIFO full */
693 case I2C_IT_RXFF:
694 for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) {
695 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
696 dev->cli.buffer++;
697 }
698 dev->cli.count -= MAX_I2C_FIFO_THRESHOLD;
699 dev->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD;
700 break;
701
702 /* Master Transaction Done with/without stop */
703 case I2C_IT_MTD:
704 case I2C_IT_MTDWS:
705 if (dev->cli.operation == I2C_READ) {
706 while (!readl(dev->virtbase + I2C_RISR) & I2C_IT_RXFE) {
707 if (dev->cli.count == 0)
708 break;
709 *dev->cli.buffer =
710 readb(dev->virtbase + I2C_RFR);
711 dev->cli.buffer++;
712 dev->cli.count--;
713 dev->cli.xfer_bytes++;
714 }
715 }
716
717 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MTD);
718 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MTDWS);
719
720 disable_interrupts(dev,
721 (I2C_IT_TXFNE | I2C_IT_TXFE | I2C_IT_TXFF
722 | I2C_IT_TXFOVR | I2C_IT_RXFNF
723 | I2C_IT_RXFF | I2C_IT_RXFE));
724
725 if (dev->cli.count) {
726 dev->result = -1;
727 dev_err(&dev->pdev->dev, "%lu bytes still remain to be"
728 "xfered\n", dev->cli.count);
729 (void) init_hw(dev);
730 }
731 complete(&dev->xfer_complete);
732
733 break;
734
735 /* Master Arbitration lost interrupt */
736 case I2C_IT_MAL:
737 dev->result = -1;
738 (void) init_hw(dev);
739
740 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL);
741 complete(&dev->xfer_complete);
742
743 break;
744
745 /*
746 * Bus Error interrupt.
747 * This happens when an unexpected start/stop condition occurs
748 * during the transaction.
749 */
750 case I2C_IT_BERR:
751 dev->result = -1;
752 /* get the status */
753 if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT)
754 (void) init_hw(dev);
755
756 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_BERR);
757 complete(&dev->xfer_complete);
758
759 break;
760
761 /*
762 * Tx FIFO overrun interrupt.
763 * This is set when a write operation in Tx FIFO is performed and
764 * the Tx FIFO is full.
765 */
766 case I2C_IT_TXFOVR:
767 dev->result = -1;
768 (void) init_hw(dev);
769
770 dev_err(&dev->pdev->dev, "Tx Fifo Over run\n");
771 complete(&dev->xfer_complete);
772
773 break;
774
775 /* unhandled interrupts by this driver - TODO*/
776 case I2C_IT_TXFE:
777 case I2C_IT_TXFF:
778 case I2C_IT_RXFE:
779 case I2C_IT_RFSR:
780 case I2C_IT_RFSE:
781 case I2C_IT_WTSR:
782 case I2C_IT_STD:
783 dev_err(&dev->pdev->dev, "unhandled Interrupt\n");
784 break;
785 default:
786 dev_err(&dev->pdev->dev, "spurious Interrupt..\n");
787 break;
788 }
789
790 return IRQ_HANDLED;
791}
792
793static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap)
794{
795 return I2C_FUNC_I2C
796 | I2C_FUNC_SMBUS_BYTE_DATA
797 | I2C_FUNC_SMBUS_WORD_DATA
798 | I2C_FUNC_SMBUS_I2C_BLOCK;
799}
800
801static const struct i2c_algorithm nmk_i2c_algo = {
802 .master_xfer = nmk_i2c_xfer,
803 .functionality = nmk_i2c_functionality
804};
805
806static int __devinit nmk_i2c_probe(struct platform_device *pdev)
807{
808 int ret = 0;
809 struct resource *res;
810 struct nmk_i2c_controller *pdata =
811 pdev->dev.platform_data;
812 struct nmk_i2c_dev *dev;
813 struct i2c_adapter *adap;
814
815 dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL);
816 if (!dev) {
817 dev_err(&pdev->dev, "cannot allocate memory\n");
818 ret = -ENOMEM;
819 goto err_no_mem;
820 }
821
822 dev->pdev = pdev;
823 platform_set_drvdata(pdev, dev);
824
825 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
826 if (!res) {
827 ret = -ENOENT;
828 goto err_no_resource;
829 }
830
831 if (request_mem_region(res->start, resource_size(res),
832 DRIVER_NAME "I/O region") == NULL) {
833 ret = -EBUSY;
834 goto err_no_region;
835 }
836
837 dev->virtbase = ioremap(res->start, resource_size(res));
838 if (!dev->virtbase) {
839 ret = -ENOMEM;
840 goto err_no_ioremap;
841 }
842
843 dev->irq = platform_get_irq(pdev, 0);
844 ret = request_irq(dev->irq, i2c_irq_handler, IRQF_DISABLED,
845 DRIVER_NAME, dev);
846 if (ret) {
847 dev_err(&pdev->dev, "cannot claim the irq %d\n", dev->irq);
848 goto err_irq;
849 }
850
851 dev->clk = clk_get(&pdev->dev, NULL);
852 if (IS_ERR(dev->clk)) {
853 dev_err(&pdev->dev, "could not get i2c clock\n");
854 ret = PTR_ERR(dev->clk);
855 goto err_no_clk;
856 }
857
858 clk_enable(dev->clk);
859
860 adap = &dev->adap;
861 adap->dev.parent = &pdev->dev;
862 adap->owner = THIS_MODULE;
863 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
864 adap->algo = &nmk_i2c_algo;
865
866 /* fetch the controller id */
867 adap->nr = pdev->id;
868
869 /* fetch the controller configuration from machine */
870 dev->cfg.clk_freq = pdata->clk_freq;
871 dev->cfg.slsu = pdata->slsu;
872 dev->cfg.tft = pdata->tft;
873 dev->cfg.rft = pdata->rft;
874 dev->cfg.sm = pdata->sm;
875
876 i2c_set_adapdata(adap, dev);
877
878 ret = init_hw(dev);
879 if (ret != 0) {
880 dev_err(&pdev->dev, "error in initializing i2c hardware\n");
881 goto err_init_hw;
882 }
883
884 dev_dbg(&pdev->dev, "initialize I2C%d bus on virtual "
885 "base %p\n", pdev->id, dev->virtbase);
886
887 ret = i2c_add_numbered_adapter(adap);
888 if (ret) {
889 dev_err(&pdev->dev, "failed to add adapter\n");
890 goto err_add_adap;
891 }
892
893 return 0;
894
895 err_init_hw:
896 clk_disable(dev->clk);
897 err_add_adap:
898 clk_put(dev->clk);
899 err_no_clk:
900 free_irq(dev->irq, dev);
901 err_irq:
902 iounmap(dev->virtbase);
903 err_no_ioremap:
904 release_mem_region(res->start, resource_size(res));
905 err_no_region:
906 platform_set_drvdata(pdev, NULL);
907 err_no_resource:
908 kfree(dev);
909 err_no_mem:
910
911 return ret;
912}
913
914static int __devexit nmk_i2c_remove(struct platform_device *pdev)
915{
916 struct nmk_i2c_dev *dev = platform_get_drvdata(pdev);
917
918 i2c_del_adapter(&dev->adap);
919 flush_i2c_fifo(dev);
920 disable_all_interrupts(dev);
921 clear_all_interrupts(dev);
922 /* disable the controller */
923 i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
924 free_irq(dev->irq, dev);
925 iounmap(dev->virtbase);
926 clk_disable(dev->clk);
927 clk_put(dev->clk);
928 platform_set_drvdata(pdev, NULL);
929 kfree(dev);
930
931 return 0;
932}
933
934static struct platform_driver nmk_i2c_driver = {
935 .driver = {
936 .owner = THIS_MODULE,
937 .name = DRIVER_NAME,
938 },
939 .probe = nmk_i2c_probe,
940 .remove = __devexit_p(nmk_i2c_remove),
941};
942
943static int __init nmk_i2c_init(void)
944{
945 return platform_driver_register(&nmk_i2c_driver);
946}
947
948static void __exit nmk_i2c_exit(void)
949{
950 platform_driver_unregister(&nmk_i2c_driver);
951}
952
953subsys_initcall(nmk_i2c_init);
954module_exit(nmk_i2c_exit);
955
956MODULE_AUTHOR("Sachin Verma, Srinidhi KASAGAR");
957MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver");
958MODULE_LICENSE("GPL");
959MODULE_ALIAS("platform:" DRIVER_NAME);