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authorShinya Kuribayashi <shinya.kuribayashi@necel.com>2009-11-06 07:48:55 -0500
committerBen Dooks <ben-linux@fluff.org>2009-12-08 19:19:11 -0500
commit81e798b73aec2d7ce06d18bd191b088c233e554f (patch)
tree4f3121a1708f0632cfec4d750dc064171e987dcf /drivers/i2c
parent21a89d4101ce338c2872401c82b66a7c155e24ab (diff)
i2c-designware: Divide i2c_dw_xfer_msg into two functions
We have some steps at the top of i2c_dw_xfer_msg() to set up a slave address and enable DW I2C core. And it's executed only when we don't have STATUS_WRITE_IN_PROGRESS. But we need to make sure that STATUS_WRITE_IN_PROGRESS only indicates that we have a pending i2c_msg to process. In other words, even if STATUS_WRITE_IN_PROGRESS is not set, that doesn't mean we're at initial state in the I2C transaction. Since i2c_dw_xfer_msg() will be invoked again and again during a transaction, those init steps have a possibility to be re-processed needlessly. For example, this issue easily takes place when processing a combined transaction with a certain condition (the number of tx bytes in the first i2c_msg, equals to the Tx FIFO depth). Consequently we should not use STATUS_WRITE_IN_PROGRESS to determine where we're at in an I2C transaction. It would be better to separate those initialization steps from i2c_dw_xfer_msg(). Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Acked-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'drivers/i2c')
-rw-r--r--drivers/i2c/busses/i2c-designware.c45
1 files changed, 25 insertions, 20 deletions
diff --git a/drivers/i2c/busses/i2c-designware.c b/drivers/i2c/busses/i2c-designware.c
index 940bbf31bc8c..da5612b21aff 100644
--- a/drivers/i2c/busses/i2c-designware.c
+++ b/drivers/i2c/busses/i2c-designware.c
@@ -326,6 +326,29 @@ static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
326 return 0; 326 return 0;
327} 327}
328 328
329static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
330{
331 struct i2c_msg *msgs = dev->msgs;
332 u32 ic_con;
333
334 /* Disable the adapter */
335 writel(0, dev->base + DW_IC_ENABLE);
336
337 /* set the slave (target) address */
338 writel(msgs[dev->msg_write_idx].addr, dev->base + DW_IC_TAR);
339
340 /* if the slave address is ten bit address, enable 10BITADDR */
341 ic_con = readl(dev->base + DW_IC_CON);
342 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN)
343 ic_con |= DW_IC_CON_10BITADDR_MASTER;
344 else
345 ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
346 writel(ic_con, dev->base + DW_IC_CON);
347
348 /* Enable the adapter */
349 writel(1, dev->base + DW_IC_ENABLE);
350}
351
329/* 352/*
330 * Initiate low level master read/write transaction. 353 * Initiate low level master read/write transaction.
331 * This function is called from i2c_dw_xfer when starting a transfer. 354 * This function is called from i2c_dw_xfer when starting a transfer.
@@ -336,7 +359,7 @@ static void
336i2c_dw_xfer_msg(struct dw_i2c_dev *dev) 359i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
337{ 360{
338 struct i2c_msg *msgs = dev->msgs; 361 struct i2c_msg *msgs = dev->msgs;
339 u32 ic_con, intr_mask; 362 u32 intr_mask;
340 int tx_limit = dev->tx_fifo_depth - readl(dev->base + DW_IC_TXFLR); 363 int tx_limit = dev->tx_fifo_depth - readl(dev->base + DW_IC_TXFLR);
341 int rx_limit = dev->rx_fifo_depth - readl(dev->base + DW_IC_RXFLR); 364 int rx_limit = dev->rx_fifo_depth - readl(dev->base + DW_IC_RXFLR);
342 u32 addr = msgs[dev->msg_write_idx].addr; 365 u32 addr = msgs[dev->msg_write_idx].addr;
@@ -344,25 +367,6 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
344 367
345 intr_mask = DW_IC_INTR_STOP_DET | DW_IC_INTR_TX_ABRT | DW_IC_INTR_RX_FULL; 368 intr_mask = DW_IC_INTR_STOP_DET | DW_IC_INTR_TX_ABRT | DW_IC_INTR_RX_FULL;
346 369
347 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
348 /* Disable the adapter */
349 writel(0, dev->base + DW_IC_ENABLE);
350
351 /* set the slave (target) address */
352 writel(msgs[dev->msg_write_idx].addr, dev->base + DW_IC_TAR);
353
354 /* if the slave address is ten bit address, enable 10BITADDR */
355 ic_con = readl(dev->base + DW_IC_CON);
356 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN)
357 ic_con |= DW_IC_CON_10BITADDR_MASTER;
358 else
359 ic_con &= ~DW_IC_CON_10BITADDR_MASTER;
360 writel(ic_con, dev->base + DW_IC_CON);
361
362 /* Enable the adapter */
363 writel(1, dev->base + DW_IC_ENABLE);
364 }
365
366 for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { 370 for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
367 /* if target address has changed, we need to 371 /* if target address has changed, we need to
368 * reprogram the target address in the i2c 372 * reprogram the target address in the i2c
@@ -474,6 +478,7 @@ i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
474 goto done; 478 goto done;
475 479
476 /* start the transfers */ 480 /* start the transfers */
481 i2c_dw_xfer_init(dev);
477 i2c_dw_xfer_msg(dev); 482 i2c_dw_xfer_msg(dev);
478 483
479 /* wait for tx to complete */ 484 /* wait for tx to complete */