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authorLinus Torvalds <torvalds@linux-foundation.org>2013-07-04 17:02:09 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-07-04 17:02:09 -0400
commit98f486f18d16e2214728d101ed8b6a12dce75539 (patch)
tree987e2fcbd6089a94a00e489cd62fec1b8b10cd02 /drivers/i2c
parent84cbd7222b2b00dcddef3103203986b3d59c836a (diff)
parent97191d734f6ac028e5e6dcd574378c1544a16c0b (diff)
Merge branch 'i2c/for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
Pull i2c updates from Wolfram Sang: - new drivers: Kontron PLD, Wondermedia VT - mv64xxx driver gained sun4i support and a bigger cleanup - duplicate driver 'intel-mid' removed - added generic device tree binding for sda holding time (and designware driver already uses it) - we tried to allow driver probing with only device tree and no i2c ids, but I had to revert it because of side effects. Needs some rethinking. - driver bugfixes, cleanups... * 'i2c/for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (34 commits) i2c-designware: use div_u64 to fix link i2c: Kontron PLD i2c bus driver i2c: iop3xxx: fix build failure after waitqueue changes i2c-designware: make SDA hold time configurable i2c: mv64xxx: Set bus frequency to 100kHz if clock-frequency is not provided i2c: imx: allow autoloading on dt ids i2c: mv64xxx: Fix transfer error code i2c: i801: SMBus patch for Intel Coleto Creek DeviceIDs i2c: omap: correct usage of the interrupt enable register i2c-pxa: prepare clock before use Revert "i2c: core: make it possible to match a pure device tree driver" i2c: nomadik: allocate adapter number dynamically i2c: nomadik: support elder Nomadiks i2c: mv64xxx: Add Allwinner sun4i compatible i2c: mv64xxx: make the registers offset configurable i2c: mv64xxx: Add macros to access parts of registers i2c: vt8500: Add support for I2C bus on Wondermedia SoCs i2c: designware: fix race between subsequent xfers i2c: bfin-twi: Read and write the FIFO in loop i2c: core: make it possible to match a pure device tree driver ...
Diffstat (limited to 'drivers/i2c')
-rw-r--r--drivers/i2c/busses/Kconfig34
-rw-r--r--drivers/i2c/busses/Makefile3
-rw-r--r--drivers/i2c/busses/i2c-bfin-twi.c47
-rw-r--r--drivers/i2c/busses/i2c-cpm.c4
-rw-r--r--drivers/i2c/busses/i2c-davinci.c8
-rw-r--r--drivers/i2c/busses/i2c-designware-core.c30
-rw-r--r--drivers/i2c/busses/i2c-designware-core.h1
-rw-r--r--drivers/i2c/busses/i2c-designware-platdrv.c19
-rw-r--r--drivers/i2c/busses/i2c-i801.c3
-rw-r--r--drivers/i2c/busses/i2c-ibm_iic.c4
-rw-r--r--drivers/i2c/busses/i2c-imx.c15
-rw-r--r--drivers/i2c/busses/i2c-intel-mid.c1121
-rw-r--r--drivers/i2c/busses/i2c-iop3xx.c2
-rw-r--r--drivers/i2c/busses/i2c-kempld.c410
-rw-r--r--drivers/i2c/busses/i2c-mpc.c4
-rw-r--r--drivers/i2c/busses/i2c-mv64xxx.c321
-rw-r--r--drivers/i2c/busses/i2c-mxs.c6
-rw-r--r--drivers/i2c/busses/i2c-nomadik.c52
-rw-r--r--drivers/i2c/busses/i2c-omap.c23
-rw-r--r--drivers/i2c/busses/i2c-pxa.c6
-rw-r--r--drivers/i2c/busses/i2c-rcar.c7
-rw-r--r--drivers/i2c/busses/i2c-wmt.c479
22 files changed, 1212 insertions, 1387 deletions
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 527503617ee2..fdc2ab4af315 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -108,6 +108,7 @@ config I2C_I801
108 Lynx Point-LP (PCH) 108 Lynx Point-LP (PCH)
109 Avoton (SOC) 109 Avoton (SOC)
110 Wellsburg (PCH) 110 Wellsburg (PCH)
111 Coleto Creek (PCH)
111 112
112 This driver can also be built as a module. If so, the module 113 This driver can also be built as a module. If so, the module
113 will be called i2c-i801. 114 will be called i2c-i801.
@@ -475,16 +476,6 @@ config I2C_IMX
475 This driver can also be built as a module. If so, the module 476 This driver can also be built as a module. If so, the module
476 will be called i2c-imx. 477 will be called i2c-imx.
477 478
478config I2C_INTEL_MID
479 tristate "Intel Moorestown/Medfield Platform I2C controller"
480 depends on PCI
481 help
482 Say Y here if you have an Intel Moorestown/Medfield platform I2C
483 controller.
484
485 This support is also available as a module. If so, the module
486 will be called i2c-intel-mid.
487
488config I2C_IOP3XX 479config I2C_IOP3XX
489 tristate "Intel IOPx3xx and IXP4xx on-chip I2C interface" 480 tristate "Intel IOPx3xx and IXP4xx on-chip I2C interface"
490 depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IXP4XX || ARCH_IOP13XX 481 depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IXP4XX || ARCH_IOP13XX
@@ -495,6 +486,16 @@ config I2C_IOP3XX
495 This driver can also be built as a module. If so, the module 486 This driver can also be built as a module. If so, the module
496 will be called i2c-iop3xx. 487 will be called i2c-iop3xx.
497 488
489config I2C_KEMPLD
490 tristate "Kontron COM I2C Controller"
491 depends on MFD_KEMPLD
492 help
493 This enables support for the I2C bus interface on some Kontron ETX
494 and COMexpress (ETXexpress) modules.
495
496 This driver can also be built as a module. If so, the module
497 will be called i2c-kempld.
498
498config I2C_MPC 499config I2C_MPC
499 tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx" 500 tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx"
500 depends on PPC 501 depends on PPC
@@ -508,10 +509,11 @@ config I2C_MPC
508 509
509config I2C_MV64XXX 510config I2C_MV64XXX
510 tristate "Marvell mv64xxx I2C Controller" 511 tristate "Marvell mv64xxx I2C Controller"
511 depends on (MV64X60 || PLAT_ORION) 512 depends on (MV64X60 || PLAT_ORION || ARCH_SUNXI)
512 help 513 help
513 If you say yes to this option, support will be included for the 514 If you say yes to this option, support will be included for the
514 built-in I2C interface on the Marvell 64xxx line of host bridges. 515 built-in I2C interface on the Marvell 64xxx line of host bridges.
516 This driver is also used for Allwinner SoCs I2C controllers.
515 517
516 This driver can also be built as a module. If so, the module 518 This driver can also be built as a module. If so, the module
517 will be called i2c-mv64xxx. 519 will be called i2c-mv64xxx.
@@ -725,6 +727,16 @@ config I2C_VERSATILE
725 This driver can also be built as a module. If so, the module 727 This driver can also be built as a module. If so, the module
726 will be called i2c-versatile. 728 will be called i2c-versatile.
727 729
730config I2C_WMT
731 tristate "Wondermedia WM8xxx SoC I2C bus support"
732 depends on ARCH_VT8500
733 help
734 Say yes if you want to support the I2C bus on Wondermedia 8xxx-series
735 SoCs.
736
737 This driver can also be built as a module. If so, the module will be
738 called i2c-wmt.
739
728config I2C_OCTEON 740config I2C_OCTEON
729 tristate "Cavium OCTEON I2C bus support" 741 tristate "Cavium OCTEON I2C bus support"
730 depends on CPU_CAVIUM_OCTEON 742 depends on CPU_CAVIUM_OCTEON
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 8f4fc23b85b1..d00997f3eb3b 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -46,8 +46,8 @@ obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o
46obj-$(CONFIG_I2C_HIGHLANDER) += i2c-highlander.o 46obj-$(CONFIG_I2C_HIGHLANDER) += i2c-highlander.o
47obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o 47obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o
48obj-$(CONFIG_I2C_IMX) += i2c-imx.o 48obj-$(CONFIG_I2C_IMX) += i2c-imx.o
49obj-$(CONFIG_I2C_INTEL_MID) += i2c-intel-mid.o
50obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o 49obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o
50obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o
51obj-$(CONFIG_I2C_MPC) += i2c-mpc.o 51obj-$(CONFIG_I2C_MPC) += i2c-mpc.o
52obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o 52obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o
53obj-$(CONFIG_I2C_MXS) += i2c-mxs.o 53obj-$(CONFIG_I2C_MXS) += i2c-mxs.o
@@ -71,6 +71,7 @@ obj-$(CONFIG_I2C_SIRF) += i2c-sirf.o
71obj-$(CONFIG_I2C_STU300) += i2c-stu300.o 71obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
72obj-$(CONFIG_I2C_TEGRA) += i2c-tegra.o 72obj-$(CONFIG_I2C_TEGRA) += i2c-tegra.o
73obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o 73obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
74obj-$(CONFIG_I2C_WMT) += i2c-wmt.o
74obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o 75obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
75obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o 76obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
76obj-$(CONFIG_I2C_XLR) += i2c-xlr.o 77obj-$(CONFIG_I2C_XLR) += i2c-xlr.o
diff --git a/drivers/i2c/busses/i2c-bfin-twi.c b/drivers/i2c/busses/i2c-bfin-twi.c
index 05080c449c6b..13ea1c29873d 100644
--- a/drivers/i2c/busses/i2c-bfin-twi.c
+++ b/drivers/i2c/busses/i2c-bfin-twi.c
@@ -39,33 +39,40 @@ static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface,
39 unsigned short mast_stat = read_MASTER_STAT(iface); 39 unsigned short mast_stat = read_MASTER_STAT(iface);
40 40
41 if (twi_int_status & XMTSERV) { 41 if (twi_int_status & XMTSERV) {
42 if (iface->writeNum <= 0) {
43 /* start receive immediately after complete sending in
44 * combine mode.
45 */
46 if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
47 write_MASTER_CTL(iface,
48 read_MASTER_CTL(iface) | MDIR);
49 else if (iface->manual_stop)
50 write_MASTER_CTL(iface,
51 read_MASTER_CTL(iface) | STOP);
52 else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
53 iface->cur_msg + 1 < iface->msg_num) {
54 if (iface->pmsg[iface->cur_msg + 1].flags &
55 I2C_M_RD)
56 write_MASTER_CTL(iface,
57 read_MASTER_CTL(iface) |
58 MDIR);
59 else
60 write_MASTER_CTL(iface,
61 read_MASTER_CTL(iface) &
62 ~MDIR);
63 }
64 }
42 /* Transmit next data */ 65 /* Transmit next data */
43 if (iface->writeNum > 0) { 66 while (iface->writeNum > 0 &&
67 (read_FIFO_STAT(iface) & XMTSTAT) != XMT_FULL) {
44 SSYNC(); 68 SSYNC();
45 write_XMT_DATA8(iface, *(iface->transPtr++)); 69 write_XMT_DATA8(iface, *(iface->transPtr++));
46 iface->writeNum--; 70 iface->writeNum--;
47 } 71 }
48 /* start receive immediately after complete sending in
49 * combine mode.
50 */
51 else if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
52 write_MASTER_CTL(iface,
53 read_MASTER_CTL(iface) | MDIR);
54 else if (iface->manual_stop)
55 write_MASTER_CTL(iface,
56 read_MASTER_CTL(iface) | STOP);
57 else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
58 iface->cur_msg + 1 < iface->msg_num) {
59 if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
60 write_MASTER_CTL(iface,
61 read_MASTER_CTL(iface) | MDIR);
62 else
63 write_MASTER_CTL(iface,
64 read_MASTER_CTL(iface) & ~MDIR);
65 }
66 } 72 }
67 if (twi_int_status & RCVSERV) { 73 if (twi_int_status & RCVSERV) {
68 if (iface->readNum > 0) { 74 while (iface->readNum > 0 &&
75 (read_FIFO_STAT(iface) & RCVSTAT)) {
69 /* Receive next data */ 76 /* Receive next data */
70 *(iface->transPtr) = read_RCV_DATA8(iface); 77 *(iface->transPtr) = read_RCV_DATA8(iface);
71 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) { 78 if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
diff --git a/drivers/i2c/busses/i2c-cpm.c b/drivers/i2c/busses/i2c-cpm.c
index 9e6002108720..2e1f7eb55bf4 100644
--- a/drivers/i2c/busses/i2c-cpm.c
+++ b/drivers/i2c/busses/i2c-cpm.c
@@ -654,7 +654,7 @@ static int cpm_i2c_probe(struct platform_device *ofdev)
654 654
655 cpm->ofdev = ofdev; 655 cpm->ofdev = ofdev;
656 656
657 dev_set_drvdata(&ofdev->dev, cpm); 657 platform_set_drvdata(ofdev, cpm);
658 658
659 cpm->adap = cpm_ops; 659 cpm->adap = cpm_ops;
660 i2c_set_adapdata(&cpm->adap, cpm); 660 i2c_set_adapdata(&cpm->adap, cpm);
@@ -697,7 +697,7 @@ out_free:
697 697
698static int cpm_i2c_remove(struct platform_device *ofdev) 698static int cpm_i2c_remove(struct platform_device *ofdev)
699{ 699{
700 struct cpm_i2c *cpm = dev_get_drvdata(&ofdev->dev); 700 struct cpm_i2c *cpm = platform_get_drvdata(ofdev);
701 701
702 i2c_del_adapter(&cpm->adap); 702 i2c_del_adapter(&cpm->adap);
703 703
diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davinci.c
index cf20e06a88e1..fa556057d224 100644
--- a/drivers/i2c/busses/i2c-davinci.c
+++ b/drivers/i2c/busses/i2c-davinci.c
@@ -646,13 +646,6 @@ static int davinci_i2c_probe(struct platform_device *pdev)
646 struct resource *mem, *irq; 646 struct resource *mem, *irq;
647 int r; 647 int r;
648 648
649 /* NOTE: driver uses the static register mapping */
650 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
651 if (!mem) {
652 dev_err(&pdev->dev, "no mem resource?\n");
653 return -ENODEV;
654 }
655
656 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 649 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
657 if (!irq) { 650 if (!irq) {
658 dev_err(&pdev->dev, "no irq resource?\n"); 651 dev_err(&pdev->dev, "no irq resource?\n");
@@ -697,6 +690,7 @@ static int davinci_i2c_probe(struct platform_device *pdev)
697 return -ENODEV; 690 return -ENODEV;
698 clk_prepare_enable(dev->clk); 691 clk_prepare_enable(dev->clk);
699 692
693 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
700 dev->base = devm_ioremap_resource(&pdev->dev, mem); 694 dev->base = devm_ioremap_resource(&pdev->dev, mem);
701 if (IS_ERR(dev->base)) { 695 if (IS_ERR(dev->base)) {
702 r = PTR_ERR(dev->base); 696 r = PTR_ERR(dev->base);
diff --git a/drivers/i2c/busses/i2c-designware-core.c b/drivers/i2c/busses/i2c-designware-core.c
index c41ca6354fc5..ad46616de29e 100644
--- a/drivers/i2c/busses/i2c-designware-core.c
+++ b/drivers/i2c/busses/i2c-designware-core.c
@@ -67,9 +67,12 @@
67#define DW_IC_STATUS 0x70 67#define DW_IC_STATUS 0x70
68#define DW_IC_TXFLR 0x74 68#define DW_IC_TXFLR 0x74
69#define DW_IC_RXFLR 0x78 69#define DW_IC_RXFLR 0x78
70#define DW_IC_SDA_HOLD 0x7c
70#define DW_IC_TX_ABRT_SOURCE 0x80 71#define DW_IC_TX_ABRT_SOURCE 0x80
71#define DW_IC_ENABLE_STATUS 0x9c 72#define DW_IC_ENABLE_STATUS 0x9c
72#define DW_IC_COMP_PARAM_1 0xf4 73#define DW_IC_COMP_PARAM_1 0xf4
74#define DW_IC_COMP_VERSION 0xf8
75#define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A
73#define DW_IC_COMP_TYPE 0xfc 76#define DW_IC_COMP_TYPE 0xfc
74#define DW_IC_COMP_TYPE_VALUE 0x44570140 77#define DW_IC_COMP_TYPE_VALUE 0x44570140
75 78
@@ -332,6 +335,16 @@ int i2c_dw_init(struct dw_i2c_dev *dev)
332 dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT); 335 dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT);
333 dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); 336 dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
334 337
338 /* Configure SDA Hold Time if required */
339 if (dev->sda_hold_time) {
340 reg = dw_readl(dev, DW_IC_COMP_VERSION);
341 if (reg >= DW_IC_SDA_HOLD_MIN_VERS)
342 dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD);
343 else
344 dev_warn(dev->dev,
345 "Hardware too old to adjust SDA hold time.");
346 }
347
335 /* Configure Tx/Rx FIFO threshold levels */ 348 /* Configure Tx/Rx FIFO threshold levels */
336 dw_writel(dev, dev->tx_fifo_depth - 1, DW_IC_TX_TL); 349 dw_writel(dev, dev->tx_fifo_depth - 1, DW_IC_TX_TL);
337 dw_writel(dev, 0, DW_IC_RX_TL); 350 dw_writel(dev, 0, DW_IC_RX_TL);
@@ -580,14 +593,23 @@ i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
580 i2c_dw_xfer_init(dev); 593 i2c_dw_xfer_init(dev);
581 594
582 /* wait for tx to complete */ 595 /* wait for tx to complete */
583 ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, HZ); 596 ret = wait_for_completion_timeout(&dev->cmd_complete, HZ);
584 if (ret == 0) { 597 if (ret == 0) {
585 dev_err(dev->dev, "controller timed out\n"); 598 dev_err(dev->dev, "controller timed out\n");
599 /* i2c_dw_init implicitly disables the adapter */
586 i2c_dw_init(dev); 600 i2c_dw_init(dev);
587 ret = -ETIMEDOUT; 601 ret = -ETIMEDOUT;
588 goto done; 602 goto done;
589 } else if (ret < 0) 603 }
590 goto done; 604
605 /*
606 * We must disable the adapter before unlocking the &dev->lock mutex
607 * below. Otherwise the hardware might continue generating interrupts
608 * which in turn causes a race condition with the following transfer.
609 * Needs some more investigation if the additional interrupts are
610 * a hardware bug or this driver doesn't handle them correctly yet.
611 */
612 __i2c_dw_enable(dev, false);
591 613
592 if (dev->msg_err) { 614 if (dev->msg_err) {
593 ret = dev->msg_err; 615 ret = dev->msg_err;
@@ -596,8 +618,6 @@ i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
596 618
597 /* no error */ 619 /* no error */
598 if (likely(!dev->cmd_err)) { 620 if (likely(!dev->cmd_err)) {
599 /* Disable the adapter */
600 __i2c_dw_enable(dev, false);
601 ret = num; 621 ret = num;
602 goto done; 622 goto done;
603 } 623 }
diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h
index e761ad18dd61..912aa2262866 100644
--- a/drivers/i2c/busses/i2c-designware-core.h
+++ b/drivers/i2c/busses/i2c-designware-core.h
@@ -90,6 +90,7 @@ struct dw_i2c_dev {
90 unsigned int tx_fifo_depth; 90 unsigned int tx_fifo_depth;
91 unsigned int rx_fifo_depth; 91 unsigned int rx_fifo_depth;
92 int rx_outstanding; 92 int rx_outstanding;
93 u32 sda_hold_time;
93}; 94};
94 95
95#define ACCESS_SWAP 0x00000001 96#define ACCESS_SWAP 0x00000001
diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c
index 35b70a1edf57..4c5fadabe49d 100644
--- a/drivers/i2c/busses/i2c-designware-platdrv.c
+++ b/drivers/i2c/busses/i2c-designware-platdrv.c
@@ -34,6 +34,7 @@
34#include <linux/sched.h> 34#include <linux/sched.h>
35#include <linux/err.h> 35#include <linux/err.h>
36#include <linux/interrupt.h> 36#include <linux/interrupt.h>
37#include <linux/of.h>
37#include <linux/of_i2c.h> 38#include <linux/of_i2c.h>
38#include <linux/platform_device.h> 39#include <linux/platform_device.h>
39#include <linux/pm.h> 40#include <linux/pm.h>
@@ -87,13 +88,6 @@ static int dw_i2c_probe(struct platform_device *pdev)
87 struct resource *mem; 88 struct resource *mem;
88 int irq, r; 89 int irq, r;
89 90
90 /* NOTE: driver uses the static register mapping */
91 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
92 if (!mem) {
93 dev_err(&pdev->dev, "no mem resource?\n");
94 return -EINVAL;
95 }
96
97 irq = platform_get_irq(pdev, 0); 91 irq = platform_get_irq(pdev, 0);
98 if (irq < 0) { 92 if (irq < 0) {
99 dev_err(&pdev->dev, "no irq resource?\n"); 93 dev_err(&pdev->dev, "no irq resource?\n");
@@ -104,6 +98,7 @@ static int dw_i2c_probe(struct platform_device *pdev)
104 if (!dev) 98 if (!dev)
105 return -ENOMEM; 99 return -ENOMEM;
106 100
101 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
107 dev->base = devm_ioremap_resource(&pdev->dev, mem); 102 dev->base = devm_ioremap_resource(&pdev->dev, mem);
108 if (IS_ERR(dev->base)) 103 if (IS_ERR(dev->base))
109 return PTR_ERR(dev->base); 104 return PTR_ERR(dev->base);
@@ -121,6 +116,16 @@ static int dw_i2c_probe(struct platform_device *pdev)
121 return PTR_ERR(dev->clk); 116 return PTR_ERR(dev->clk);
122 clk_prepare_enable(dev->clk); 117 clk_prepare_enable(dev->clk);
123 118
119 if (pdev->dev.of_node) {
120 u32 ht = 0;
121 u32 ic_clk = dev->get_clk_rate_khz(dev);
122
123 of_property_read_u32(pdev->dev.of_node,
124 "i2c-sda-hold-time-ns", &ht);
125 dev->sda_hold_time = div_u64((u64)ic_clk * ht + 500000,
126 1000000);
127 }
128
124 dev->functionality = 129 dev->functionality =
125 I2C_FUNC_I2C | 130 I2C_FUNC_I2C |
126 I2C_FUNC_10BIT_ADDR | 131 I2C_FUNC_10BIT_ADDR |
diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
index 3a6903f63913..4ebceed6bc66 100644
--- a/drivers/i2c/busses/i2c-i801.c
+++ b/drivers/i2c/busses/i2c-i801.c
@@ -58,6 +58,7 @@
58 Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes 58 Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
59 Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes 59 Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
60 Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes 60 Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
61 Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
61 62
62 Features supported by this driver: 63 Features supported by this driver:
63 Software PEC no 64 Software PEC no
@@ -169,6 +170,7 @@
169#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 170#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
170#define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c 171#define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
171#define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 172#define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
173#define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
172#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 174#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
173#define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 175#define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
174#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 176#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
@@ -817,6 +819,7 @@ static DEFINE_PCI_DEVICE_TABLE(i801_ids) = {
817 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) }, 819 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
818 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) }, 820 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
819 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) }, 821 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
822 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
820 { 0, } 823 { 0, }
821}; 824};
822 825
diff --git a/drivers/i2c/busses/i2c-ibm_iic.c b/drivers/i2c/busses/i2c-ibm_iic.c
index 405a2e240454..973f51688276 100644
--- a/drivers/i2c/busses/i2c-ibm_iic.c
+++ b/drivers/i2c/busses/i2c-ibm_iic.c
@@ -705,7 +705,7 @@ static int iic_probe(struct platform_device *ofdev)
705 return -ENOMEM; 705 return -ENOMEM;
706 } 706 }
707 707
708 dev_set_drvdata(&ofdev->dev, dev); 708 platform_set_drvdata(ofdev, dev);
709 709
710 dev->vaddr = of_iomap(np, 0); 710 dev->vaddr = of_iomap(np, 0);
711 if (dev->vaddr == NULL) { 711 if (dev->vaddr == NULL) {
@@ -782,7 +782,7 @@ error_cleanup:
782 */ 782 */
783static int iic_remove(struct platform_device *ofdev) 783static int iic_remove(struct platform_device *ofdev)
784{ 784{
785 struct ibm_iic_private *dev = dev_get_drvdata(&ofdev->dev); 785 struct ibm_iic_private *dev = platform_get_drvdata(ofdev);
786 786
787 i2c_del_adapter(&dev->adap); 787 i2c_del_adapter(&dev->adap);
788 788
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index 82f20c60bb7b..e24279725d36 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -51,7 +51,6 @@
51#include <linux/of.h> 51#include <linux/of.h>
52#include <linux/of_device.h> 52#include <linux/of_device.h>
53#include <linux/of_i2c.h> 53#include <linux/of_i2c.h>
54#include <linux/pinctrl/consumer.h>
55#include <linux/platform_data/i2c-imx.h> 54#include <linux/platform_data/i2c-imx.h>
56 55
57/** Defines ******************************************************************** 56/** Defines ********************************************************************
@@ -148,6 +147,7 @@ static const struct of_device_id i2c_imx_dt_ids[] = {
148 { .compatible = "fsl,imx21-i2c", .data = &imx_i2c_devtype[IMX21_I2C], }, 147 { .compatible = "fsl,imx21-i2c", .data = &imx_i2c_devtype[IMX21_I2C], },
149 { /* sentinel */ } 148 { /* sentinel */ }
150}; 149};
150MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids);
151 151
152static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx) 152static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx)
153{ 153{
@@ -493,24 +493,19 @@ static int __init i2c_imx_probe(struct platform_device *pdev)
493 struct imx_i2c_struct *i2c_imx; 493 struct imx_i2c_struct *i2c_imx;
494 struct resource *res; 494 struct resource *res;
495 struct imxi2c_platform_data *pdata = pdev->dev.platform_data; 495 struct imxi2c_platform_data *pdata = pdev->dev.platform_data;
496 struct pinctrl *pinctrl;
497 void __iomem *base; 496 void __iomem *base;
498 int irq, ret; 497 int irq, ret;
499 u32 bitrate; 498 u32 bitrate;
500 499
501 dev_dbg(&pdev->dev, "<%s>\n", __func__); 500 dev_dbg(&pdev->dev, "<%s>\n", __func__);
502 501
503 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
504 if (!res) {
505 dev_err(&pdev->dev, "can't get device resources\n");
506 return -ENOENT;
507 }
508 irq = platform_get_irq(pdev, 0); 502 irq = platform_get_irq(pdev, 0);
509 if (irq < 0) { 503 if (irq < 0) {
510 dev_err(&pdev->dev, "can't get irq number\n"); 504 dev_err(&pdev->dev, "can't get irq number\n");
511 return -ENOENT; 505 return -ENOENT;
512 } 506 }
513 507
508 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
514 base = devm_ioremap_resource(&pdev->dev, res); 509 base = devm_ioremap_resource(&pdev->dev, res);
515 if (IS_ERR(base)) 510 if (IS_ERR(base))
516 return PTR_ERR(base); 511 return PTR_ERR(base);
@@ -535,12 +530,6 @@ static int __init i2c_imx_probe(struct platform_device *pdev)
535 i2c_imx->adapter.dev.of_node = pdev->dev.of_node; 530 i2c_imx->adapter.dev.of_node = pdev->dev.of_node;
536 i2c_imx->base = base; 531 i2c_imx->base = base;
537 532
538 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
539 if (IS_ERR(pinctrl)) {
540 dev_err(&pdev->dev, "can't get/select pinctrl\n");
541 return PTR_ERR(pinctrl);
542 }
543
544 /* Get I2C clock */ 533 /* Get I2C clock */
545 i2c_imx->clk = devm_clk_get(&pdev->dev, NULL); 534 i2c_imx->clk = devm_clk_get(&pdev->dev, NULL);
546 if (IS_ERR(i2c_imx->clk)) { 535 if (IS_ERR(i2c_imx->clk)) {
diff --git a/drivers/i2c/busses/i2c-intel-mid.c b/drivers/i2c/busses/i2c-intel-mid.c
deleted file mode 100644
index 0fb659726ffc..000000000000
--- a/drivers/i2c/busses/i2c-intel-mid.c
+++ /dev/null
@@ -1,1121 +0,0 @@
1/*
2 * Support for Moorestown/Medfield I2C chip
3 *
4 * Copyright (c) 2009 Intel Corporation.
5 * Copyright (c) 2009 Synopsys. Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License, version
9 * 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT ANY
12 * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
13 * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
14 * details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc., 51
18 * Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/err.h>
25#include <linux/slab.h>
26#include <linux/stat.h>
27#include <linux/delay.h>
28#include <linux/i2c.h>
29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/interrupt.h>
32#include <linux/pm_runtime.h>
33#include <linux/io.h>
34
35#define DRIVER_NAME "i2c-intel-mid"
36#define VERSION "Version 0.5ac2"
37#define PLATFORM "Moorestown/Medfield"
38
39/* Tables use: 0 Moorestown, 1 Medfield */
40#define NUM_PLATFORMS 2
41enum platform_enum {
42 MOORESTOWN = 0,
43 MEDFIELD = 1,
44};
45
46enum mid_i2c_status {
47 STATUS_IDLE = 0,
48 STATUS_READ_START,
49 STATUS_READ_IN_PROGRESS,
50 STATUS_READ_SUCCESS,
51 STATUS_WRITE_START,
52 STATUS_WRITE_SUCCESS,
53 STATUS_XFER_ABORT,
54 STATUS_STANDBY
55};
56
57/**
58 * struct intel_mid_i2c_private - per device I²C context
59 * @adap: core i2c layer adapter information
60 * @dev: device reference for power management
61 * @base: register base
62 * @speed: speed mode for this port
63 * @complete: completion object for transaction wait
64 * @abort: reason for last abort
65 * @rx_buf: pointer into working receive buffer
66 * @rx_buf_len: receive buffer length
67 * @status: adapter state machine
68 * @msg: the message we are currently processing
69 * @platform: the MID device type we are part of
70 * @lock: transaction serialization
71 *
72 * We allocate one of these per device we discover, it holds the core
73 * i2c layer objects and the data we need to track privately.
74 */
75struct intel_mid_i2c_private {
76 struct i2c_adapter adap;
77 struct device *dev;
78 void __iomem *base;
79 int speed;
80 struct completion complete;
81 int abort;
82 u8 *rx_buf;
83 int rx_buf_len;
84 enum mid_i2c_status status;
85 struct i2c_msg *msg;
86 enum platform_enum platform;
87 struct mutex lock;
88};
89
90#define NUM_SPEEDS 3
91
92#define ACTIVE 0
93#define STANDBY 1
94
95
96/* Control register */
97#define IC_CON 0x00
98#define SLV_DIS (1 << 6) /* Disable slave mode */
99#define RESTART (1 << 5) /* Send a Restart condition */
100#define ADDR_10BIT (1 << 4) /* 10-bit addressing */
101#define STANDARD_MODE (1 << 1) /* standard mode */
102#define FAST_MODE (2 << 1) /* fast mode */
103#define HIGH_MODE (3 << 1) /* high speed mode */
104#define MASTER_EN (1 << 0) /* Master mode */
105
106/* Target address register */
107#define IC_TAR 0x04
108#define IC_TAR_10BIT_ADDR (1 << 12) /* 10-bit addressing */
109#define IC_TAR_SPECIAL (1 << 11) /* Perform special I2C cmd */
110#define IC_TAR_GC_OR_START (1 << 10) /* 0: Gerneral Call Address */
111 /* 1: START BYTE */
112/* Slave Address Register */
113#define IC_SAR 0x08 /* Not used in Master mode */
114
115/* High Speed Master Mode Code Address Register */
116#define IC_HS_MADDR 0x0c
117
118/* Rx/Tx Data Buffer and Command Register */
119#define IC_DATA_CMD 0x10
120#define IC_RD (1 << 8) /* 1: Read 0: Write */
121
122/* Standard Speed Clock SCL High Count Register */
123#define IC_SS_SCL_HCNT 0x14
124
125/* Standard Speed Clock SCL Low Count Register */
126#define IC_SS_SCL_LCNT 0x18
127
128/* Fast Speed Clock SCL High Count Register */
129#define IC_FS_SCL_HCNT 0x1c
130
131/* Fast Spedd Clock SCL Low Count Register */
132#define IC_FS_SCL_LCNT 0x20
133
134/* High Speed Clock SCL High Count Register */
135#define IC_HS_SCL_HCNT 0x24
136
137/* High Speed Clock SCL Low Count Register */
138#define IC_HS_SCL_LCNT 0x28
139
140/* Interrupt Status Register */
141#define IC_INTR_STAT 0x2c /* Read only */
142#define R_GEN_CALL (1 << 11)
143#define R_START_DET (1 << 10)
144#define R_STOP_DET (1 << 9)
145#define R_ACTIVITY (1 << 8)
146#define R_RX_DONE (1 << 7)
147#define R_TX_ABRT (1 << 6)
148#define R_RD_REQ (1 << 5)
149#define R_TX_EMPTY (1 << 4)
150#define R_TX_OVER (1 << 3)
151#define R_RX_FULL (1 << 2)
152#define R_RX_OVER (1 << 1)
153#define R_RX_UNDER (1 << 0)
154
155/* Interrupt Mask Register */
156#define IC_INTR_MASK 0x30 /* Read and Write */
157#define M_GEN_CALL (1 << 11)
158#define M_START_DET (1 << 10)
159#define M_STOP_DET (1 << 9)
160#define M_ACTIVITY (1 << 8)
161#define M_RX_DONE (1 << 7)
162#define M_TX_ABRT (1 << 6)
163#define M_RD_REQ (1 << 5)
164#define M_TX_EMPTY (1 << 4)
165#define M_TX_OVER (1 << 3)
166#define M_RX_FULL (1 << 2)
167#define M_RX_OVER (1 << 1)
168#define M_RX_UNDER (1 << 0)
169
170/* Raw Interrupt Status Register */
171#define IC_RAW_INTR_STAT 0x34 /* Read Only */
172#define GEN_CALL (1 << 11) /* General call */
173#define START_DET (1 << 10) /* (RE)START occurred */
174#define STOP_DET (1 << 9) /* STOP occurred */
175#define ACTIVITY (1 << 8) /* Bus busy */
176#define RX_DONE (1 << 7) /* Not used in Master mode */
177#define TX_ABRT (1 << 6) /* Transmit Abort */
178#define RD_REQ (1 << 5) /* Not used in Master mode */
179#define TX_EMPTY (1 << 4) /* TX FIFO <= threshold */
180#define TX_OVER (1 << 3) /* TX FIFO overflow */
181#define RX_FULL (1 << 2) /* RX FIFO >= threshold */
182#define RX_OVER (1 << 1) /* RX FIFO overflow */
183#define RX_UNDER (1 << 0) /* RX FIFO empty */
184
185/* Receive FIFO Threshold Register */
186#define IC_RX_TL 0x38
187
188/* Transmit FIFO Treshold Register */
189#define IC_TX_TL 0x3c
190
191/* Clear Combined and Individual Interrupt Register */
192#define IC_CLR_INTR 0x40
193#define CLR_INTR (1 << 0)
194
195/* Clear RX_UNDER Interrupt Register */
196#define IC_CLR_RX_UNDER 0x44
197#define CLR_RX_UNDER (1 << 0)
198
199/* Clear RX_OVER Interrupt Register */
200#define IC_CLR_RX_OVER 0x48
201#define CLR_RX_OVER (1 << 0)
202
203/* Clear TX_OVER Interrupt Register */
204#define IC_CLR_TX_OVER 0x4c
205#define CLR_TX_OVER (1 << 0)
206
207#define IC_CLR_RD_REQ 0x50
208
209/* Clear TX_ABRT Interrupt Register */
210#define IC_CLR_TX_ABRT 0x54
211#define CLR_TX_ABRT (1 << 0)
212#define IC_CLR_RX_DONE 0x58
213
214/* Clear ACTIVITY Interrupt Register */
215#define IC_CLR_ACTIVITY 0x5c
216#define CLR_ACTIVITY (1 << 0)
217
218/* Clear STOP_DET Interrupt Register */
219#define IC_CLR_STOP_DET 0x60
220#define CLR_STOP_DET (1 << 0)
221
222/* Clear START_DET Interrupt Register */
223#define IC_CLR_START_DET 0x64
224#define CLR_START_DET (1 << 0)
225
226/* Clear GEN_CALL Interrupt Register */
227#define IC_CLR_GEN_CALL 0x68
228#define CLR_GEN_CALL (1 << 0)
229
230/* Enable Register */
231#define IC_ENABLE 0x6c
232#define ENABLE (1 << 0)
233
234/* Status Register */
235#define IC_STATUS 0x70 /* Read Only */
236#define STAT_SLV_ACTIVITY (1 << 6) /* Slave not in idle */
237#define STAT_MST_ACTIVITY (1 << 5) /* Master not in idle */
238#define STAT_RFF (1 << 4) /* RX FIFO Full */
239#define STAT_RFNE (1 << 3) /* RX FIFO Not Empty */
240#define STAT_TFE (1 << 2) /* TX FIFO Empty */
241#define STAT_TFNF (1 << 1) /* TX FIFO Not Full */
242#define STAT_ACTIVITY (1 << 0) /* Activity Status */
243
244/* Transmit FIFO Level Register */
245#define IC_TXFLR 0x74 /* Read Only */
246#define TXFLR (1 << 0) /* TX FIFO level */
247
248/* Receive FIFO Level Register */
249#define IC_RXFLR 0x78 /* Read Only */
250#define RXFLR (1 << 0) /* RX FIFO level */
251
252/* Transmit Abort Source Register */
253#define IC_TX_ABRT_SOURCE 0x80
254#define ABRT_SLVRD_INTX (1 << 15)
255#define ABRT_SLV_ARBLOST (1 << 14)
256#define ABRT_SLVFLUSH_TXFIFO (1 << 13)
257#define ARB_LOST (1 << 12)
258#define ABRT_MASTER_DIS (1 << 11)
259#define ABRT_10B_RD_NORSTRT (1 << 10)
260#define ABRT_SBYTE_NORSTRT (1 << 9)
261#define ABRT_HS_NORSTRT (1 << 8)
262#define ABRT_SBYTE_ACKDET (1 << 7)
263#define ABRT_HS_ACKDET (1 << 6)
264#define ABRT_GCALL_READ (1 << 5)
265#define ABRT_GCALL_NOACK (1 << 4)
266#define ABRT_TXDATA_NOACK (1 << 3)
267#define ABRT_10ADDR2_NOACK (1 << 2)
268#define ABRT_10ADDR1_NOACK (1 << 1)
269#define ABRT_7B_ADDR_NOACK (1 << 0)
270
271/* Enable Status Register */
272#define IC_ENABLE_STATUS 0x9c
273#define IC_EN (1 << 0) /* I2C in an enabled state */
274
275/* Component Parameter Register 1*/
276#define IC_COMP_PARAM_1 0xf4
277#define APB_DATA_WIDTH (0x3 << 0)
278
279/* added by xiaolin --begin */
280#define SS_MIN_SCL_HIGH 4000
281#define SS_MIN_SCL_LOW 4700
282#define FS_MIN_SCL_HIGH 600
283#define FS_MIN_SCL_LOW 1300
284#define HS_MIN_SCL_HIGH_100PF 60
285#define HS_MIN_SCL_LOW_100PF 120
286
287#define STANDARD 0
288#define FAST 1
289#define HIGH 2
290
291#define NUM_SPEEDS 3
292
293static int speed_mode[6] = {
294 FAST,
295 FAST,
296 FAST,
297 STANDARD,
298 FAST,
299 FAST
300};
301
302static int ctl_num = 6;
303module_param_array(speed_mode, int, &ctl_num, S_IRUGO);
304MODULE_PARM_DESC(speed_mode, "Set the speed of the i2c interface (0-2)");
305
306/**
307 * intel_mid_i2c_disable - Disable I2C controller
308 * @adap: struct pointer to i2c_adapter
309 *
310 * Return Value:
311 * 0 success
312 * -EBUSY if device is busy
313 * -ETIMEDOUT if i2c cannot be disabled within the given time
314 *
315 * I2C bus state should be checked prior to disabling the hardware. If bus is
316 * not in idle state, an errno is returned. Write "0" to IC_ENABLE to disable
317 * I2C controller.
318 */
319static int intel_mid_i2c_disable(struct i2c_adapter *adap)
320{
321 struct intel_mid_i2c_private *i2c = i2c_get_adapdata(adap);
322 int err = 0;
323 int count = 0;
324 int ret1, ret2;
325 static const u16 delay[NUM_SPEEDS] = {100, 25, 3};
326
327 /* Set IC_ENABLE to 0 */
328 writel(0, i2c->base + IC_ENABLE);
329
330 /* Check if device is busy */
331 dev_dbg(&adap->dev, "mrst i2c disable\n");
332 while ((ret1 = readl(i2c->base + IC_ENABLE_STATUS) & 0x1)
333 || (ret2 = readl(i2c->base + IC_STATUS) & 0x1)) {
334 udelay(delay[i2c->speed]);
335 writel(0, i2c->base + IC_ENABLE);
336 dev_dbg(&adap->dev, "i2c is busy, count is %d speed %d\n",
337 count, i2c->speed);
338 if (count++ > 10) {
339 err = -ETIMEDOUT;
340 break;
341 }
342 }
343
344 /* Clear all interrupts */
345 readl(i2c->base + IC_CLR_INTR);
346 readl(i2c->base + IC_CLR_STOP_DET);
347 readl(i2c->base + IC_CLR_START_DET);
348 readl(i2c->base + IC_CLR_ACTIVITY);
349 readl(i2c->base + IC_CLR_TX_ABRT);
350 readl(i2c->base + IC_CLR_RX_OVER);
351 readl(i2c->base + IC_CLR_RX_UNDER);
352 readl(i2c->base + IC_CLR_TX_OVER);
353 readl(i2c->base + IC_CLR_RX_DONE);
354 readl(i2c->base + IC_CLR_GEN_CALL);
355
356 /* Disable all interupts */
357 writel(0x0000, i2c->base + IC_INTR_MASK);
358
359 return err;
360}
361
362/**
363 * intel_mid_i2c_hwinit - Initialize the I2C hardware registers
364 * @dev: pci device struct pointer
365 *
366 * This function will be called in intel_mid_i2c_probe() before device
367 * registration.
368 *
369 * Return Values:
370 * 0 success
371 * -EBUSY i2c cannot be disabled
372 * -ETIMEDOUT i2c cannot be disabled
373 * -EFAULT If APB data width is not 32-bit wide
374 *
375 * I2C should be disabled prior to other register operation. If failed, an
376 * errno is returned. Mask and Clear all interrpts, this should be done at
377 * first. Set common registers which will not be modified during normal
378 * transfers, including: control register, FIFO threshold and clock freq.
379 * Check APB data width at last.
380 */
381static int intel_mid_i2c_hwinit(struct intel_mid_i2c_private *i2c)
382{
383 int err;
384
385 static const u16 hcnt[NUM_PLATFORMS][NUM_SPEEDS] = {
386 { 0x75, 0x15, 0x07 },
387 { 0x04c, 0x10, 0x06 }
388 };
389 static const u16 lcnt[NUM_PLATFORMS][NUM_SPEEDS] = {
390 { 0x7C, 0x21, 0x0E },
391 { 0x053, 0x19, 0x0F }
392 };
393
394 /* Disable i2c first */
395 err = intel_mid_i2c_disable(&i2c->adap);
396 if (err)
397 return err;
398
399 /*
400 * Setup clock frequency and speed mode
401 * Enable restart condition,
402 * enable master FSM, disable slave FSM,
403 * use target address when initiating transfer
404 */
405
406 writel((i2c->speed + 1) << 1 | SLV_DIS | RESTART | MASTER_EN,
407 i2c->base + IC_CON);
408 writel(hcnt[i2c->platform][i2c->speed],
409 i2c->base + (IC_SS_SCL_HCNT + (i2c->speed << 3)));
410 writel(lcnt[i2c->platform][i2c->speed],
411 i2c->base + (IC_SS_SCL_LCNT + (i2c->speed << 3)));
412
413 /* Set tranmit & receive FIFO threshold to zero */
414 writel(0x0, i2c->base + IC_RX_TL);
415 writel(0x0, i2c->base + IC_TX_TL);
416
417 return 0;
418}
419
420/**
421 * intel_mid_i2c_func - Return the supported three I2C operations.
422 * @adapter: i2c_adapter struct pointer
423 */
424static u32 intel_mid_i2c_func(struct i2c_adapter *adapter)
425{
426 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
427}
428
429/**
430 * intel_mid_i2c_address_neq - To check if the addresses for different i2c messages
431 * are equal.
432 * @p1: first i2c_msg
433 * @p2: second i2c_msg
434 *
435 * Return Values:
436 * 0 if addresses are equal
437 * 1 if not equal
438 *
439 * Within a single transfer, the I2C client may need to send its address more
440 * than once. So a check if the addresses match is needed.
441 */
442static inline bool intel_mid_i2c_address_neq(const struct i2c_msg *p1,
443 const struct i2c_msg *p2)
444{
445 if (p1->addr != p2->addr)
446 return 1;
447 if ((p1->flags ^ p2->flags) & I2C_M_TEN)
448 return 1;
449 return 0;
450}
451
452/**
453 * intel_mid_i2c_abort - To handle transfer abortions and print error messages.
454 * @adap: i2c_adapter struct pointer
455 *
456 * By reading register IC_TX_ABRT_SOURCE, various transfer errors can be
457 * distingushed. At present, no circumstances have been found out that
458 * multiple errors would be occurred simutaneously, so we simply use the
459 * register value directly.
460 *
461 * At last the error bits are cleared. (Note clear ABRT_SBYTE_NORSTRT bit need
462 * a few extra steps)
463 */
464static void intel_mid_i2c_abort(struct intel_mid_i2c_private *i2c)
465{
466 /* Read about source register */
467 int abort = i2c->abort;
468 struct i2c_adapter *adap = &i2c->adap;
469
470 /* Single transfer error check:
471 * According to databook, TX/RX FIFOs would be flushed when
472 * the abort interrupt occurred.
473 */
474 if (abort & ABRT_MASTER_DIS)
475 dev_err(&adap->dev,
476 "initiate master operation with master mode disabled.\n");
477 if (abort & ABRT_10B_RD_NORSTRT)
478 dev_err(&adap->dev,
479 "RESTART disabled and master sent READ cmd in 10-bit addressing.\n");
480
481 if (abort & ABRT_SBYTE_NORSTRT) {
482 dev_err(&adap->dev,
483 "RESTART disabled and user is trying to send START byte.\n");
484 writel(~ABRT_SBYTE_NORSTRT, i2c->base + IC_TX_ABRT_SOURCE);
485 writel(RESTART, i2c->base + IC_CON);
486 writel(~IC_TAR_SPECIAL, i2c->base + IC_TAR);
487 }
488
489 if (abort & ABRT_SBYTE_ACKDET)
490 dev_err(&adap->dev,
491 "START byte was not acknowledged.\n");
492 if (abort & ABRT_TXDATA_NOACK)
493 dev_dbg(&adap->dev,
494 "No acknowledgement received from slave.\n");
495 if (abort & ABRT_10ADDR2_NOACK)
496 dev_dbg(&adap->dev,
497 "The 2nd address byte of the 10-bit address was not acknowledged.\n");
498 if (abort & ABRT_10ADDR1_NOACK)
499 dev_dbg(&adap->dev,
500 "The 1st address byte of 10-bit address was not acknowledged.\n");
501 if (abort & ABRT_7B_ADDR_NOACK)
502 dev_dbg(&adap->dev,
503 "I2C slave device not acknowledged.\n");
504
505 /* Clear TX_ABRT bit */
506 readl(i2c->base + IC_CLR_TX_ABRT);
507 i2c->status = STATUS_XFER_ABORT;
508}
509
510/**
511 * xfer_read - Internal function to implement master read transfer.
512 * @adap: i2c_adapter struct pointer
513 * @buf: buffer in i2c_msg
514 * @length: number of bytes to be read
515 *
516 * Return Values:
517 * 0 if the read transfer succeeds
518 * -ETIMEDOUT if cannot read the "raw" interrupt register
519 * -EINVAL if a transfer abort occurred
520 *
521 * For every byte, a "READ" command will be loaded into IC_DATA_CMD prior to
522 * data transfer. The actual "read" operation will be performed if an RX_FULL
523 * interrupt occurred.
524 *
525 * Note there may be two interrupt signals captured, one should read
526 * IC_RAW_INTR_STAT to separate between errors and actual data.
527 */
528static int xfer_read(struct i2c_adapter *adap, unsigned char *buf, int length)
529{
530 struct intel_mid_i2c_private *i2c = i2c_get_adapdata(adap);
531 int i = length;
532 int err;
533
534 if (length >= 256) {
535 dev_err(&adap->dev,
536 "I2C FIFO cannot support larger than 256 bytes\n");
537 return -EMSGSIZE;
538 }
539
540 INIT_COMPLETION(i2c->complete);
541
542 readl(i2c->base + IC_CLR_INTR);
543 writel(0x0044, i2c->base + IC_INTR_MASK);
544
545 i2c->status = STATUS_READ_START;
546
547 while (i--)
548 writel(IC_RD, i2c->base + IC_DATA_CMD);
549
550 i2c->status = STATUS_READ_START;
551 err = wait_for_completion_interruptible_timeout(&i2c->complete, HZ);
552 if (!err) {
553 dev_err(&adap->dev, "Timeout for ACK from I2C slave device\n");
554 intel_mid_i2c_hwinit(i2c);
555 return -ETIMEDOUT;
556 }
557 if (i2c->status == STATUS_READ_SUCCESS)
558 return 0;
559 else
560 return -EIO;
561}
562
563/**
564 * xfer_write - Internal function to implement master write transfer.
565 * @adap: i2c_adapter struct pointer
566 * @buf: buffer in i2c_msg
567 * @length: number of bytes to be read
568 *
569 * Return Values:
570 * 0 if the read transfer succeeds
571 * -ETIMEDOUT if we cannot read the "raw" interrupt register
572 * -EINVAL if a transfer abort occurred
573 *
574 * For every byte, a "WRITE" command will be loaded into IC_DATA_CMD prior to
575 * data transfer. The actual "write" operation will be performed when the
576 * RX_FULL interrupt signal occurs.
577 *
578 * Note there may be two interrupt signals captured, one should read
579 * IC_RAW_INTR_STAT to separate between errors and actual data.
580 */
581static int xfer_write(struct i2c_adapter *adap,
582 unsigned char *buf, int length)
583{
584 struct intel_mid_i2c_private *i2c = i2c_get_adapdata(adap);
585 int i, err;
586
587 if (length >= 256) {
588 dev_err(&adap->dev,
589 "I2C FIFO cannot support larger than 256 bytes\n");
590 return -EMSGSIZE;
591 }
592
593 INIT_COMPLETION(i2c->complete);
594
595 readl(i2c->base + IC_CLR_INTR);
596 writel(0x0050, i2c->base + IC_INTR_MASK);
597
598 i2c->status = STATUS_WRITE_START;
599 for (i = 0; i < length; i++)
600 writel((u16)(*(buf + i)), i2c->base + IC_DATA_CMD);
601
602 i2c->status = STATUS_WRITE_START;
603 err = wait_for_completion_interruptible_timeout(&i2c->complete, HZ);
604 if (!err) {
605 dev_err(&adap->dev, "Timeout for ACK from I2C slave device\n");
606 intel_mid_i2c_hwinit(i2c);
607 return -ETIMEDOUT;
608 } else {
609 if (i2c->status == STATUS_WRITE_SUCCESS)
610 return 0;
611 else
612 return -EIO;
613 }
614}
615
616static int intel_mid_i2c_setup(struct i2c_adapter *adap, struct i2c_msg *pmsg)
617{
618 struct intel_mid_i2c_private *i2c = i2c_get_adapdata(adap);
619 int err;
620 u32 reg;
621 u32 bit_mask;
622 u32 mode;
623
624 /* Disable device first */
625 err = intel_mid_i2c_disable(adap);
626 if (err) {
627 dev_err(&adap->dev,
628 "Cannot disable i2c controller, timeout\n");
629 return err;
630 }
631
632 mode = (1 + i2c->speed) << 1;
633 /* set the speed mode */
634 reg = readl(i2c->base + IC_CON);
635 if ((reg & 0x06) != mode) {
636 dev_dbg(&adap->dev, "set mode %d\n", i2c->speed);
637 writel((reg & ~0x6) | mode, i2c->base + IC_CON);
638 }
639
640 reg = readl(i2c->base + IC_CON);
641 /* use 7-bit addressing */
642 if (pmsg->flags & I2C_M_TEN) {
643 if ((reg & ADDR_10BIT) != ADDR_10BIT) {
644 dev_dbg(&adap->dev, "set i2c 10 bit address mode\n");
645 writel(reg | ADDR_10BIT, i2c->base + IC_CON);
646 }
647 } else {
648 if ((reg & ADDR_10BIT) != 0x0) {
649 dev_dbg(&adap->dev, "set i2c 7 bit address mode\n");
650 writel(reg & ~ADDR_10BIT, i2c->base + IC_CON);
651 }
652 }
653 /* enable restart conditions */
654 reg = readl(i2c->base + IC_CON);
655 if ((reg & RESTART) != RESTART) {
656 dev_dbg(&adap->dev, "enable restart conditions\n");
657 writel(reg | RESTART, i2c->base + IC_CON);
658 }
659
660 /* enable master FSM */
661 reg = readl(i2c->base + IC_CON);
662 dev_dbg(&adap->dev, "ic_con reg is 0x%x\n", reg);
663 writel(reg | MASTER_EN, i2c->base + IC_CON);
664 if ((reg & SLV_DIS) != SLV_DIS) {
665 dev_dbg(&adap->dev, "enable master FSM\n");
666 writel(reg | SLV_DIS, i2c->base + IC_CON);
667 dev_dbg(&adap->dev, "ic_con reg is 0x%x\n", reg);
668 }
669
670 /* use target address when initiating transfer */
671 reg = readl(i2c->base + IC_TAR);
672 bit_mask = IC_TAR_SPECIAL | IC_TAR_GC_OR_START;
673
674 if ((reg & bit_mask) != 0x0) {
675 dev_dbg(&adap->dev,
676 "WR: use target address when intiating transfer, i2c_tx_target\n");
677 writel(reg & ~bit_mask, i2c->base + IC_TAR);
678 }
679
680 /* set target address to the I2C slave address */
681 dev_dbg(&adap->dev,
682 "set target address to the I2C slave address, addr is %x\n",
683 pmsg->addr);
684 writel(pmsg->addr | (pmsg->flags & I2C_M_TEN ? IC_TAR_10BIT_ADDR : 0),
685 i2c->base + IC_TAR);
686
687 /* Enable I2C controller */
688 writel(ENABLE, i2c->base + IC_ENABLE);
689
690 return 0;
691}
692
693/**
694 * intel_mid_i2c_xfer - Main master transfer routine.
695 * @adap: i2c_adapter struct pointer
696 * @pmsg: i2c_msg struct pointer
697 * @num: number of i2c_msg
698 *
699 * Return Values:
700 * + number of messages transferred
701 * -ETIMEDOUT If cannot disable I2C controller or read IC_STATUS
702 * -EINVAL If the address in i2c_msg is invalid
703 *
704 * This function will be registered in i2c-core and exposed to external
705 * I2C clients.
706 * 1. Disable I2C controller
707 * 2. Unmask three interrupts: RX_FULL, TX_EMPTY, TX_ABRT
708 * 3. Check if address in i2c_msg is valid
709 * 4. Enable I2C controller
710 * 5. Perform real transfer (call xfer_read or xfer_write)
711 * 6. Wait until the current transfer is finished (check bus state)
712 * 7. Mask and clear all interrupts
713 */
714static int intel_mid_i2c_xfer(struct i2c_adapter *adap,
715 struct i2c_msg *pmsg,
716 int num)
717{
718 struct intel_mid_i2c_private *i2c = i2c_get_adapdata(adap);
719 int i, err = 0;
720
721 /* if number of messages equal 0*/
722 if (num == 0)
723 return 0;
724
725 pm_runtime_get(i2c->dev);
726
727 mutex_lock(&i2c->lock);
728 dev_dbg(&adap->dev, "intel_mid_i2c_xfer, process %d msg(s)\n", num);
729 dev_dbg(&adap->dev, "slave address is %x\n", pmsg->addr);
730
731
732 if (i2c->status != STATUS_IDLE) {
733 dev_err(&adap->dev, "Adapter %d in transfer/standby\n",
734 adap->nr);
735 mutex_unlock(&i2c->lock);
736 pm_runtime_put(i2c->dev);
737 return -1;
738 }
739
740
741 for (i = 1; i < num; i++) {
742 /* Message address equal? */
743 if (unlikely(intel_mid_i2c_address_neq(&pmsg[0], &pmsg[i]))) {
744 dev_err(&adap->dev, "Invalid address in msg[%d]\n", i);
745 mutex_unlock(&i2c->lock);
746 pm_runtime_put(i2c->dev);
747 return -EINVAL;
748 }
749 }
750
751 if (intel_mid_i2c_setup(adap, pmsg)) {
752 mutex_unlock(&i2c->lock);
753 pm_runtime_put(i2c->dev);
754 return -EINVAL;
755 }
756
757 for (i = 0; i < num; i++) {
758 i2c->msg = pmsg;
759 i2c->status = STATUS_IDLE;
760 /* Read or Write */
761 if (pmsg->flags & I2C_M_RD) {
762 dev_dbg(&adap->dev, "I2C_M_RD\n");
763 err = xfer_read(adap, pmsg->buf, pmsg->len);
764 } else {
765 dev_dbg(&adap->dev, "I2C_M_WR\n");
766 err = xfer_write(adap, pmsg->buf, pmsg->len);
767 }
768 if (err < 0)
769 break;
770 dev_dbg(&adap->dev, "msg[%d] transfer complete\n", i);
771 pmsg++; /* next message */
772 }
773
774 /* Mask interrupts */
775 writel(0x0000, i2c->base + IC_INTR_MASK);
776 /* Clear all interrupts */
777 readl(i2c->base + IC_CLR_INTR);
778
779 i2c->status = STATUS_IDLE;
780 mutex_unlock(&i2c->lock);
781 pm_runtime_put(i2c->dev);
782
783 return err;
784}
785
786static int intel_mid_i2c_runtime_suspend(struct device *dev)
787{
788 struct pci_dev *pdev = to_pci_dev(dev);
789 struct intel_mid_i2c_private *i2c = pci_get_drvdata(pdev);
790 struct i2c_adapter *adap = to_i2c_adapter(dev);
791 int err;
792
793 if (i2c->status != STATUS_IDLE)
794 return -1;
795
796 intel_mid_i2c_disable(adap);
797
798 err = pci_save_state(pdev);
799 if (err) {
800 dev_err(dev, "pci_save_state failed\n");
801 return err;
802 }
803
804 err = pci_set_power_state(pdev, PCI_D3hot);
805 if (err) {
806 dev_err(dev, "pci_set_power_state failed\n");
807 return err;
808 }
809 i2c->status = STATUS_STANDBY;
810
811 return 0;
812}
813
814static int intel_mid_i2c_runtime_resume(struct device *dev)
815{
816 struct pci_dev *pdev = to_pci_dev(dev);
817 struct intel_mid_i2c_private *i2c = pci_get_drvdata(pdev);
818 int err;
819
820 if (i2c->status != STATUS_STANDBY)
821 return 0;
822
823 pci_set_power_state(pdev, PCI_D0);
824 pci_restore_state(pdev);
825 err = pci_enable_device(pdev);
826 if (err) {
827 dev_err(dev, "pci_enable_device failed\n");
828 return err;
829 }
830
831 i2c->status = STATUS_IDLE;
832
833 intel_mid_i2c_hwinit(i2c);
834 return err;
835}
836
837static void i2c_isr_read(struct intel_mid_i2c_private *i2c)
838{
839 struct i2c_msg *msg = i2c->msg;
840 int rx_num;
841 u32 len;
842 u8 *buf;
843
844 if (!(msg->flags & I2C_M_RD))
845 return;
846
847 if (i2c->status != STATUS_READ_IN_PROGRESS) {
848 len = msg->len;
849 buf = msg->buf;
850 } else {
851 len = i2c->rx_buf_len;
852 buf = i2c->rx_buf;
853 }
854
855 rx_num = readl(i2c->base + IC_RXFLR);
856
857 for (; len > 0 && rx_num > 0; len--, rx_num--)
858 *buf++ = readl(i2c->base + IC_DATA_CMD);
859
860 if (len > 0) {
861 i2c->status = STATUS_READ_IN_PROGRESS;
862 i2c->rx_buf_len = len;
863 i2c->rx_buf = buf;
864 } else
865 i2c->status = STATUS_READ_SUCCESS;
866
867 return;
868}
869
870static irqreturn_t intel_mid_i2c_isr(int this_irq, void *dev)
871{
872 struct intel_mid_i2c_private *i2c = dev;
873 u32 stat = readl(i2c->base + IC_INTR_STAT);
874
875 if (!stat)
876 return IRQ_NONE;
877
878 dev_dbg(&i2c->adap.dev, "%s, stat = 0x%x\n", __func__, stat);
879 stat &= 0x54;
880
881 if (i2c->status != STATUS_WRITE_START &&
882 i2c->status != STATUS_READ_START &&
883 i2c->status != STATUS_READ_IN_PROGRESS)
884 goto err;
885
886 if (stat & TX_ABRT)
887 i2c->abort = readl(i2c->base + IC_TX_ABRT_SOURCE);
888
889 readl(i2c->base + IC_CLR_INTR);
890
891 if (stat & TX_ABRT) {
892 intel_mid_i2c_abort(i2c);
893 goto exit;
894 }
895
896 if (stat & RX_FULL) {
897 i2c_isr_read(i2c);
898 goto exit;
899 }
900
901 if (stat & TX_EMPTY) {
902 if (readl(i2c->base + IC_STATUS) & 0x4)
903 i2c->status = STATUS_WRITE_SUCCESS;
904 }
905
906exit:
907 if (i2c->status == STATUS_READ_SUCCESS ||
908 i2c->status == STATUS_WRITE_SUCCESS ||
909 i2c->status == STATUS_XFER_ABORT) {
910 /* Clear all interrupts */
911 readl(i2c->base + IC_CLR_INTR);
912 /* Mask interrupts */
913 writel(0, i2c->base + IC_INTR_MASK);
914 complete(&i2c->complete);
915 }
916err:
917 return IRQ_HANDLED;
918}
919
920static struct i2c_algorithm intel_mid_i2c_algorithm = {
921 .master_xfer = intel_mid_i2c_xfer,
922 .functionality = intel_mid_i2c_func,
923};
924
925
926static const struct dev_pm_ops intel_mid_i2c_pm_ops = {
927 .runtime_suspend = intel_mid_i2c_runtime_suspend,
928 .runtime_resume = intel_mid_i2c_runtime_resume,
929};
930
931/**
932 * intel_mid_i2c_probe - I2C controller initialization routine
933 * @dev: pci device
934 * @id: device id
935 *
936 * Return Values:
937 * 0 success
938 * -ENODEV If cannot allocate pci resource
939 * -ENOMEM If the register base remapping failed, or
940 * if kzalloc failed
941 *
942 * Initialization steps:
943 * 1. Request for PCI resource
944 * 2. Remap the start address of PCI resource to register base
945 * 3. Request for device memory region
946 * 4. Fill in the struct members of intel_mid_i2c_private
947 * 5. Call intel_mid_i2c_hwinit() for hardware initialization
948 * 6. Register I2C adapter in i2c-core
949 */
950static int intel_mid_i2c_probe(struct pci_dev *dev,
951 const struct pci_device_id *id)
952{
953 struct intel_mid_i2c_private *mrst;
954 unsigned long start, len;
955 int err, busnum;
956 void __iomem *base = NULL;
957
958 dev_dbg(&dev->dev, "Get into probe function for I2C\n");
959 err = pci_enable_device(dev);
960 if (err) {
961 dev_err(&dev->dev, "Failed to enable I2C PCI device (%d)\n",
962 err);
963 goto exit;
964 }
965
966 /* Determine the address of the I2C area */
967 start = pci_resource_start(dev, 0);
968 len = pci_resource_len(dev, 0);
969 if (!start || len == 0) {
970 dev_err(&dev->dev, "base address not set\n");
971 err = -ENODEV;
972 goto exit;
973 }
974 dev_dbg(&dev->dev, "%s i2c resource start 0x%lx, len=%ld\n",
975 PLATFORM, start, len);
976
977 err = pci_request_region(dev, 0, DRIVER_NAME);
978 if (err) {
979 dev_err(&dev->dev, "failed to request I2C region "
980 "0x%lx-0x%lx\n", start,
981 (unsigned long)pci_resource_end(dev, 0));
982 goto exit;
983 }
984
985 base = ioremap_nocache(start, len);
986 if (!base) {
987 dev_err(&dev->dev, "I/O memory remapping failed\n");
988 err = -ENOMEM;
989 goto fail0;
990 }
991
992 /* Allocate the per-device data structure, intel_mid_i2c_private */
993 mrst = kzalloc(sizeof(struct intel_mid_i2c_private), GFP_KERNEL);
994 if (mrst == NULL) {
995 dev_err(&dev->dev, "can't allocate interface\n");
996 err = -ENOMEM;
997 goto fail1;
998 }
999
1000 /* Initialize struct members */
1001 snprintf(mrst->adap.name, sizeof(mrst->adap.name),
1002 "Intel MID I2C at %lx", start);
1003 mrst->adap.owner = THIS_MODULE;
1004 mrst->adap.algo = &intel_mid_i2c_algorithm;
1005 mrst->adap.dev.parent = &dev->dev;
1006 mrst->dev = &dev->dev;
1007 mrst->base = base;
1008 mrst->speed = STANDARD;
1009 mrst->abort = 0;
1010 mrst->rx_buf_len = 0;
1011 mrst->status = STATUS_IDLE;
1012
1013 pci_set_drvdata(dev, mrst);
1014 i2c_set_adapdata(&mrst->adap, mrst);
1015
1016 mrst->adap.nr = busnum = id->driver_data;
1017 if (dev->device <= 0x0804)
1018 mrst->platform = MOORESTOWN;
1019 else
1020 mrst->platform = MEDFIELD;
1021
1022 dev_dbg(&dev->dev, "I2C%d\n", busnum);
1023
1024 if (ctl_num > busnum) {
1025 if (speed_mode[busnum] < 0 || speed_mode[busnum] >= NUM_SPEEDS)
1026 dev_warn(&dev->dev, "invalid speed %d ignored.\n",
1027 speed_mode[busnum]);
1028 else
1029 mrst->speed = speed_mode[busnum];
1030 }
1031
1032 /* Initialize i2c controller */
1033 err = intel_mid_i2c_hwinit(mrst);
1034 if (err < 0) {
1035 dev_err(&dev->dev, "I2C interface initialization failed\n");
1036 goto fail2;
1037 }
1038
1039 mutex_init(&mrst->lock);
1040 init_completion(&mrst->complete);
1041
1042 /* Clear all interrupts */
1043 readl(mrst->base + IC_CLR_INTR);
1044 writel(0x0000, mrst->base + IC_INTR_MASK);
1045
1046 err = request_irq(dev->irq, intel_mid_i2c_isr, IRQF_SHARED,
1047 mrst->adap.name, mrst);
1048 if (err) {
1049 dev_err(&dev->dev, "Failed to request IRQ for I2C controller: "
1050 "%s", mrst->adap.name);
1051 goto fail2;
1052 }
1053
1054 /* Adapter registration */
1055 err = i2c_add_numbered_adapter(&mrst->adap);
1056 if (err) {
1057 dev_err(&dev->dev, "Adapter %s registration failed\n",
1058 mrst->adap.name);
1059 goto fail3;
1060 }
1061
1062 dev_dbg(&dev->dev, "%s I2C bus %d driver bind success.\n",
1063 (mrst->platform == MOORESTOWN) ? "Moorestown" : "Medfield",
1064 busnum);
1065
1066 pm_runtime_enable(&dev->dev);
1067 return 0;
1068
1069fail3:
1070 free_irq(dev->irq, mrst);
1071fail2:
1072 kfree(mrst);
1073fail1:
1074 iounmap(base);
1075fail0:
1076 pci_release_region(dev, 0);
1077exit:
1078 return err;
1079}
1080
1081static void intel_mid_i2c_remove(struct pci_dev *dev)
1082{
1083 struct intel_mid_i2c_private *mrst = pci_get_drvdata(dev);
1084 intel_mid_i2c_disable(&mrst->adap);
1085 i2c_del_adapter(&mrst->adap);
1086
1087 free_irq(dev->irq, mrst);
1088 iounmap(mrst->base);
1089 kfree(mrst);
1090 pci_release_region(dev, 0);
1091}
1092
1093static DEFINE_PCI_DEVICE_TABLE(intel_mid_i2c_ids) = {
1094 /* Moorestown */
1095 { PCI_VDEVICE(INTEL, 0x0802), 0 },
1096 { PCI_VDEVICE(INTEL, 0x0803), 1 },
1097 { PCI_VDEVICE(INTEL, 0x0804), 2 },
1098 /* Medfield */
1099 { PCI_VDEVICE(INTEL, 0x0817), 3,},
1100 { PCI_VDEVICE(INTEL, 0x0818), 4 },
1101 { PCI_VDEVICE(INTEL, 0x0819), 5 },
1102 { PCI_VDEVICE(INTEL, 0x082C), 0 },
1103 { PCI_VDEVICE(INTEL, 0x082D), 1 },
1104 { PCI_VDEVICE(INTEL, 0x082E), 2 },
1105 { 0,}
1106};
1107MODULE_DEVICE_TABLE(pci, intel_mid_i2c_ids);
1108
1109static struct pci_driver intel_mid_i2c_driver = {
1110 .name = DRIVER_NAME,
1111 .id_table = intel_mid_i2c_ids,
1112 .probe = intel_mid_i2c_probe,
1113 .remove = intel_mid_i2c_remove,
1114};
1115
1116module_pci_driver(intel_mid_i2c_driver);
1117
1118MODULE_AUTHOR("Ba Zheng <zheng.ba@intel.com>");
1119MODULE_DESCRIPTION("I2C driver for Moorestown Platform");
1120MODULE_LICENSE("GPL");
1121MODULE_VERSION(VERSION);
diff --git a/drivers/i2c/busses/i2c-iop3xx.c b/drivers/i2c/busses/i2c-iop3xx.c
index bc993331c695..dd24aa0424a9 100644
--- a/drivers/i2c/busses/i2c-iop3xx.c
+++ b/drivers/i2c/busses/i2c-iop3xx.c
@@ -176,7 +176,7 @@ iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap,
176 interrupted = wait_event_interruptible_timeout ( 176 interrupted = wait_event_interruptible_timeout (
177 iop3xx_adap->waitq, 177 iop3xx_adap->waitq,
178 (done = compare( sr = iop3xx_i2c_get_srstat(iop3xx_adap) ,flags )), 178 (done = compare( sr = iop3xx_i2c_get_srstat(iop3xx_adap) ,flags )),
179 1 * HZ; 179 1 * HZ
180 ); 180 );
181 if ((rc = iop3xx_i2c_error(sr)) < 0) { 181 if ((rc = iop3xx_i2c_error(sr)) < 0) {
182 *status = sr; 182 *status = sr;
diff --git a/drivers/i2c/busses/i2c-kempld.c b/drivers/i2c/busses/i2c-kempld.c
new file mode 100644
index 000000000000..ccec916bc3eb
--- /dev/null
+++ b/drivers/i2c/busses/i2c-kempld.c
@@ -0,0 +1,410 @@
1/*
2 * I2C bus driver for Kontron COM modules
3 *
4 * Copyright (c) 2010-2013 Kontron Europe GmbH
5 * Author: Michael Brunner <michael.brunner@kontron.com>
6 *
7 * The driver is based on the i2c-ocores driver by Peter Korsgaard.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License 2 as published
11 * by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/module.h>
20#include <linux/platform_device.h>
21#include <linux/i2c.h>
22#include <linux/delay.h>
23#include <linux/mfd/kempld.h>
24
25#define KEMPLD_I2C_PRELOW 0x0b
26#define KEMPLD_I2C_PREHIGH 0x0c
27#define KEMPLD_I2C_DATA 0x0e
28
29#define KEMPLD_I2C_CTRL 0x0d
30#define I2C_CTRL_IEN 0x40
31#define I2C_CTRL_EN 0x80
32
33#define KEMPLD_I2C_STAT 0x0f
34#define I2C_STAT_IF 0x01
35#define I2C_STAT_TIP 0x02
36#define I2C_STAT_ARBLOST 0x20
37#define I2C_STAT_BUSY 0x40
38#define I2C_STAT_NACK 0x80
39
40#define KEMPLD_I2C_CMD 0x0f
41#define I2C_CMD_START 0x91
42#define I2C_CMD_STOP 0x41
43#define I2C_CMD_READ 0x21
44#define I2C_CMD_WRITE 0x11
45#define I2C_CMD_READ_ACK 0x21
46#define I2C_CMD_READ_NACK 0x29
47#define I2C_CMD_IACK 0x01
48
49#define KEMPLD_I2C_FREQ_MAX 2700 /* 2.7 mHz */
50#define KEMPLD_I2C_FREQ_STD 100 /* 100 kHz */
51
52enum {
53 STATE_DONE = 0,
54 STATE_INIT,
55 STATE_ADDR,
56 STATE_ADDR10,
57 STATE_START,
58 STATE_WRITE,
59 STATE_READ,
60 STATE_ERROR,
61};
62
63struct kempld_i2c_data {
64 struct device *dev;
65 struct kempld_device_data *pld;
66 struct i2c_adapter adap;
67 struct i2c_msg *msg;
68 int pos;
69 int nmsgs;
70 int state;
71 bool was_active;
72};
73
74static unsigned int bus_frequency = KEMPLD_I2C_FREQ_STD;
75module_param(bus_frequency, uint, 0);
76MODULE_PARM_DESC(bus_frequency, "Set I2C bus frequency in kHz (default="
77 __MODULE_STRING(KEMPLD_I2C_FREQ_STD)")");
78
79static int i2c_bus = -1;
80module_param(i2c_bus, int, 0);
81MODULE_PARM_DESC(i2c_bus, "Set I2C bus number (default=-1 for dynamic assignment)");
82
83static bool i2c_gpio_mux;
84module_param(i2c_gpio_mux, bool, 0);
85MODULE_PARM_DESC(i2c_gpio_mux, "Enable I2C port on GPIO out (default=false)");
86
87/*
88 * kempld_get_mutex must be called prior to calling this function.
89 */
90static int kempld_i2c_process(struct kempld_i2c_data *i2c)
91{
92 struct kempld_device_data *pld = i2c->pld;
93 u8 stat = kempld_read8(pld, KEMPLD_I2C_STAT);
94 struct i2c_msg *msg = i2c->msg;
95 u8 addr;
96
97 /* Ready? */
98 if (stat & I2C_STAT_TIP)
99 return -EBUSY;
100
101 if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) {
102 /* Stop has been sent */
103 kempld_write8(pld, KEMPLD_I2C_CMD, I2C_CMD_IACK);
104 if (i2c->state == STATE_ERROR)
105 return -EIO;
106 return 0;
107 }
108
109 /* Error? */
110 if (stat & I2C_STAT_ARBLOST) {
111 i2c->state = STATE_ERROR;
112 kempld_write8(pld, KEMPLD_I2C_CMD, I2C_CMD_STOP);
113 return -EAGAIN;
114 }
115
116 if (i2c->state == STATE_INIT) {
117 if (stat & I2C_STAT_BUSY)
118 return -EBUSY;
119
120 i2c->state = STATE_ADDR;
121 }
122
123 if (i2c->state == STATE_ADDR) {
124 /* 10 bit address? */
125 if (i2c->msg->flags & I2C_M_TEN) {
126 addr = 0xf0 | ((i2c->msg->addr >> 7) & 0x6);
127 i2c->state = STATE_ADDR10;
128 } else {
129 addr = (i2c->msg->addr << 1);
130 i2c->state = STATE_START;
131 }
132
133 /* Set read bit if necessary */
134 addr |= (i2c->msg->flags & I2C_M_RD) ? 1 : 0;
135
136 kempld_write8(pld, KEMPLD_I2C_DATA, addr);
137 kempld_write8(pld, KEMPLD_I2C_CMD, I2C_CMD_START);
138
139 return 0;
140 }
141
142 /* Second part of 10 bit addressing */
143 if (i2c->state == STATE_ADDR10) {
144 kempld_write8(pld, KEMPLD_I2C_DATA, i2c->msg->addr & 0xff);
145 kempld_write8(pld, KEMPLD_I2C_CMD, I2C_CMD_WRITE);
146
147 i2c->state = STATE_START;
148 return 0;
149 }
150
151 if (i2c->state == STATE_START || i2c->state == STATE_WRITE) {
152 i2c->state = (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
153
154 if (stat & I2C_STAT_NACK) {
155 i2c->state = STATE_ERROR;
156 kempld_write8(pld, KEMPLD_I2C_CMD, I2C_CMD_STOP);
157 return -ENXIO;
158 }
159 } else {
160 msg->buf[i2c->pos++] = kempld_read8(pld, KEMPLD_I2C_DATA);
161 }
162
163 if (i2c->pos >= msg->len) {
164 i2c->nmsgs--;
165 i2c->msg++;
166 i2c->pos = 0;
167 msg = i2c->msg;
168
169 if (i2c->nmsgs) {
170 if (!(msg->flags & I2C_M_NOSTART)) {
171 i2c->state = STATE_ADDR;
172 return 0;
173 } else {
174 i2c->state = (msg->flags & I2C_M_RD)
175 ? STATE_READ : STATE_WRITE;
176 }
177 } else {
178 i2c->state = STATE_DONE;
179 kempld_write8(pld, KEMPLD_I2C_CMD, I2C_CMD_STOP);
180 return 0;
181 }
182 }
183
184 if (i2c->state == STATE_READ) {
185 kempld_write8(pld, KEMPLD_I2C_CMD, i2c->pos == (msg->len - 1) ?
186 I2C_CMD_READ_NACK : I2C_CMD_READ_ACK);
187 } else {
188 kempld_write8(pld, KEMPLD_I2C_DATA, msg->buf[i2c->pos++]);
189 kempld_write8(pld, KEMPLD_I2C_CMD, I2C_CMD_WRITE);
190 }
191
192 return 0;
193}
194
195static int kempld_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
196 int num)
197{
198 struct kempld_i2c_data *i2c = i2c_get_adapdata(adap);
199 struct kempld_device_data *pld = i2c->pld;
200 unsigned long timeout = jiffies + HZ;
201 int ret;
202
203 i2c->msg = msgs;
204 i2c->pos = 0;
205 i2c->nmsgs = num;
206 i2c->state = STATE_INIT;
207
208 /* Handle the transfer */
209 while (time_before(jiffies, timeout)) {
210 kempld_get_mutex(pld);
211 ret = kempld_i2c_process(i2c);
212 kempld_release_mutex(pld);
213
214 if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR)
215 return (i2c->state == STATE_DONE) ? num : ret;
216
217 if (ret == 0)
218 timeout = jiffies + HZ;
219
220 usleep_range(5, 15);
221 }
222
223 i2c->state = STATE_ERROR;
224
225 return -ETIMEDOUT;
226}
227
228/*
229 * kempld_get_mutex must be called prior to calling this function.
230 */
231static void kempld_i2c_device_init(struct kempld_i2c_data *i2c)
232{
233 struct kempld_device_data *pld = i2c->pld;
234 u16 prescale_corr;
235 long prescale;
236 u8 ctrl;
237 u8 stat;
238 u8 cfg;
239
240 /* Make sure the device is disabled */
241 ctrl = kempld_read8(pld, KEMPLD_I2C_CTRL);
242 ctrl &= ~(I2C_CTRL_EN | I2C_CTRL_IEN);
243 kempld_write8(pld, KEMPLD_I2C_CTRL, ctrl);
244
245 if (bus_frequency > KEMPLD_I2C_FREQ_MAX)
246 bus_frequency = KEMPLD_I2C_FREQ_MAX;
247
248 if (pld->info.spec_major == 1)
249 prescale = pld->pld_clock / bus_frequency * 5 - 1000;
250 else
251 prescale = pld->pld_clock / bus_frequency * 4 - 3000;
252
253 if (prescale < 0)
254 prescale = 0;
255
256 /* Round to the best matching value */
257 prescale_corr = prescale / 1000;
258 if (prescale % 1000 >= 500)
259 prescale_corr++;
260
261 kempld_write8(pld, KEMPLD_I2C_PRELOW, prescale_corr & 0xff);
262 kempld_write8(pld, KEMPLD_I2C_PREHIGH, prescale_corr >> 8);
263
264 /* Activate I2C bus output on GPIO pins */
265 cfg = kempld_read8(pld, KEMPLD_CFG);
266 if (i2c_gpio_mux)
267 cfg |= KEMPLD_CFG_GPIO_I2C_MUX;
268 else
269 cfg &= ~KEMPLD_CFG_GPIO_I2C_MUX;
270 kempld_write8(pld, KEMPLD_CFG, cfg);
271
272 /* Enable the device */
273 kempld_write8(pld, KEMPLD_I2C_CMD, I2C_CMD_IACK);
274 ctrl |= I2C_CTRL_EN;
275 kempld_write8(pld, KEMPLD_I2C_CTRL, ctrl);
276
277 stat = kempld_read8(pld, KEMPLD_I2C_STAT);
278 if (stat & I2C_STAT_BUSY)
279 kempld_write8(pld, KEMPLD_I2C_CMD, I2C_CMD_STOP);
280}
281
282static u32 kempld_i2c_func(struct i2c_adapter *adap)
283{
284 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
285}
286
287static const struct i2c_algorithm kempld_i2c_algorithm = {
288 .master_xfer = kempld_i2c_xfer,
289 .functionality = kempld_i2c_func,
290};
291
292static struct i2c_adapter kempld_i2c_adapter = {
293 .owner = THIS_MODULE,
294 .name = "i2c-kempld",
295 .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
296 .algo = &kempld_i2c_algorithm,
297};
298
299static int kempld_i2c_probe(struct platform_device *pdev)
300{
301 struct kempld_device_data *pld = dev_get_drvdata(pdev->dev.parent);
302 struct kempld_i2c_data *i2c;
303 int ret;
304 u8 ctrl;
305
306 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
307 if (!i2c)
308 return -ENOMEM;
309
310 i2c->pld = pld;
311 i2c->dev = &pdev->dev;
312 i2c->adap = kempld_i2c_adapter;
313 i2c->adap.dev.parent = i2c->dev;
314 i2c_set_adapdata(&i2c->adap, i2c);
315 platform_set_drvdata(pdev, i2c);
316
317 kempld_get_mutex(pld);
318 ctrl = kempld_read8(pld, KEMPLD_I2C_CTRL);
319
320 if (ctrl & I2C_CTRL_EN)
321 i2c->was_active = true;
322
323 kempld_i2c_device_init(i2c);
324 kempld_release_mutex(pld);
325
326 /* Add I2C adapter to I2C tree */
327 if (i2c_bus >= -1)
328 i2c->adap.nr = i2c_bus;
329 ret = i2c_add_numbered_adapter(&i2c->adap);
330 if (ret)
331 return ret;
332
333 dev_info(i2c->dev, "I2C bus initialized at %dkHz\n",
334 bus_frequency);
335
336 return 0;
337}
338
339static int kempld_i2c_remove(struct platform_device *pdev)
340{
341 struct kempld_i2c_data *i2c = platform_get_drvdata(pdev);
342 struct kempld_device_data *pld = i2c->pld;
343 u8 ctrl;
344
345 kempld_get_mutex(pld);
346 /*
347 * Disable I2C logic if it was not activated before the
348 * driver loaded
349 */
350 if (!i2c->was_active) {
351 ctrl = kempld_read8(pld, KEMPLD_I2C_CTRL);
352 ctrl &= ~I2C_CTRL_EN;
353 kempld_write8(pld, KEMPLD_I2C_CTRL, ctrl);
354 }
355 kempld_release_mutex(pld);
356
357 i2c_del_adapter(&i2c->adap);
358
359 return 0;
360}
361
362#ifdef CONFIG_PM
363static int kempld_i2c_suspend(struct platform_device *pdev, pm_message_t state)
364{
365 struct kempld_i2c_data *i2c = platform_get_drvdata(pdev);
366 struct kempld_device_data *pld = i2c->pld;
367 u8 ctrl;
368
369 kempld_get_mutex(pld);
370 ctrl = kempld_read8(pld, KEMPLD_I2C_CTRL);
371 ctrl &= ~I2C_CTRL_EN;
372 kempld_write8(pld, KEMPLD_I2C_CTRL, ctrl);
373 kempld_release_mutex(pld);
374
375 return 0;
376}
377
378static int kempld_i2c_resume(struct platform_device *pdev)
379{
380 struct kempld_i2c_data *i2c = platform_get_drvdata(pdev);
381 struct kempld_device_data *pld = i2c->pld;
382
383 kempld_get_mutex(pld);
384 kempld_i2c_device_init(i2c);
385 kempld_release_mutex(pld);
386
387 return 0;
388}
389#else
390#define kempld_i2c_suspend NULL
391#define kempld_i2c_resume NULL
392#endif
393
394static struct platform_driver kempld_i2c_driver = {
395 .driver = {
396 .name = "kempld-i2c",
397 .owner = THIS_MODULE,
398 },
399 .probe = kempld_i2c_probe,
400 .remove = kempld_i2c_remove,
401 .suspend = kempld_i2c_suspend,
402 .resume = kempld_i2c_resume,
403};
404
405module_platform_driver(kempld_i2c_driver);
406
407MODULE_DESCRIPTION("KEM PLD I2C Driver");
408MODULE_AUTHOR("Michael Brunner <michael.brunner@kontron.com>");
409MODULE_LICENSE("GPL");
410MODULE_ALIAS("platform:kempld_i2c");
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
index 5e705ee02f4a..7607dc061918 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -679,7 +679,7 @@ static int fsl_i2c_probe(struct platform_device *op)
679 } 679 }
680 dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ); 680 dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ);
681 681
682 dev_set_drvdata(&op->dev, i2c); 682 platform_set_drvdata(op, i2c);
683 683
684 i2c->adap = mpc_ops; 684 i2c->adap = mpc_ops;
685 i2c_set_adapdata(&i2c->adap, i2c); 685 i2c_set_adapdata(&i2c->adap, i2c);
@@ -707,7 +707,7 @@ static int fsl_i2c_probe(struct platform_device *op)
707 707
708static int fsl_i2c_remove(struct platform_device *op) 708static int fsl_i2c_remove(struct platform_device *op)
709{ 709{
710 struct mpc_i2c *i2c = dev_get_drvdata(&op->dev); 710 struct mpc_i2c *i2c = platform_get_drvdata(op);
711 711
712 i2c_del_adapter(&i2c->adap); 712 i2c_del_adapter(&i2c->adap);
713 713
diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c
index 1a3abd6a0bfc..b1f42bf40963 100644
--- a/drivers/i2c/busses/i2c-mv64xxx.c
+++ b/drivers/i2c/busses/i2c-mv64xxx.c
@@ -19,19 +19,15 @@
19#include <linux/platform_device.h> 19#include <linux/platform_device.h>
20#include <linux/io.h> 20#include <linux/io.h>
21#include <linux/of.h> 21#include <linux/of.h>
22#include <linux/of_device.h>
22#include <linux/of_irq.h> 23#include <linux/of_irq.h>
23#include <linux/of_i2c.h> 24#include <linux/of_i2c.h>
24#include <linux/clk.h> 25#include <linux/clk.h>
25#include <linux/err.h> 26#include <linux/err.h>
26 27
27/* Register defines */ 28#define MV64XXX_I2C_ADDR_ADDR(val) ((val & 0x7f) << 1)
28#define MV64XXX_I2C_REG_SLAVE_ADDR 0x00 29#define MV64XXX_I2C_BAUD_DIV_N(val) (val & 0x7)
29#define MV64XXX_I2C_REG_DATA 0x04 30#define MV64XXX_I2C_BAUD_DIV_M(val) ((val & 0xf) << 3)
30#define MV64XXX_I2C_REG_CONTROL 0x08
31#define MV64XXX_I2C_REG_STATUS 0x0c
32#define MV64XXX_I2C_REG_BAUD 0x0c
33#define MV64XXX_I2C_REG_EXT_SLAVE_ADDR 0x10
34#define MV64XXX_I2C_REG_SOFT_RESET 0x1c
35 31
36#define MV64XXX_I2C_REG_CONTROL_ACK 0x00000004 32#define MV64XXX_I2C_REG_CONTROL_ACK 0x00000004
37#define MV64XXX_I2C_REG_CONTROL_IFLG 0x00000008 33#define MV64XXX_I2C_REG_CONTROL_IFLG 0x00000008
@@ -85,15 +81,26 @@ enum {
85 MV64XXX_I2C_ACTION_SEND_STOP, 81 MV64XXX_I2C_ACTION_SEND_STOP,
86}; 82};
87 83
84struct mv64xxx_i2c_regs {
85 u8 addr;
86 u8 ext_addr;
87 u8 data;
88 u8 control;
89 u8 status;
90 u8 clock;
91 u8 soft_reset;
92};
93
88struct mv64xxx_i2c_data { 94struct mv64xxx_i2c_data {
95 struct i2c_msg *msgs;
96 int num_msgs;
89 int irq; 97 int irq;
90 u32 state; 98 u32 state;
91 u32 action; 99 u32 action;
92 u32 aborting; 100 u32 aborting;
93 u32 cntl_bits; 101 u32 cntl_bits;
94 void __iomem *reg_base; 102 void __iomem *reg_base;
95 u32 reg_base_p; 103 struct mv64xxx_i2c_regs reg_offsets;
96 u32 reg_size;
97 u32 addr1; 104 u32 addr1;
98 u32 addr2; 105 u32 addr2;
99 u32 bytes_left; 106 u32 bytes_left;
@@ -112,6 +119,52 @@ struct mv64xxx_i2c_data {
112 struct i2c_adapter adapter; 119 struct i2c_adapter adapter;
113}; 120};
114 121
122static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx = {
123 .addr = 0x00,
124 .ext_addr = 0x10,
125 .data = 0x04,
126 .control = 0x08,
127 .status = 0x0c,
128 .clock = 0x0c,
129 .soft_reset = 0x1c,
130};
131
132static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_sun4i = {
133 .addr = 0x00,
134 .ext_addr = 0x04,
135 .data = 0x08,
136 .control = 0x0c,
137 .status = 0x10,
138 .clock = 0x14,
139 .soft_reset = 0x18,
140};
141
142static void
143mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
144 struct i2c_msg *msg)
145{
146 u32 dir = 0;
147
148 drv_data->msg = msg;
149 drv_data->byte_posn = 0;
150 drv_data->bytes_left = msg->len;
151 drv_data->aborting = 0;
152 drv_data->rc = 0;
153 drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK |
154 MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN;
155
156 if (msg->flags & I2C_M_RD)
157 dir = 1;
158
159 if (msg->flags & I2C_M_TEN) {
160 drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
161 drv_data->addr2 = (u32)msg->addr & 0xff;
162 } else {
163 drv_data->addr1 = MV64XXX_I2C_ADDR_ADDR((u32)msg->addr) | dir;
164 drv_data->addr2 = 0;
165 }
166}
167
115/* 168/*
116 ***************************************************************************** 169 *****************************************************************************
117 * 170 *
@@ -124,13 +177,13 @@ struct mv64xxx_i2c_data {
124static void 177static void
125mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data) 178mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
126{ 179{
127 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SOFT_RESET); 180 writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset);
128 writel((((drv_data->freq_m & 0xf) << 3) | (drv_data->freq_n & 0x7)), 181 writel(MV64XXX_I2C_BAUD_DIV_M(drv_data->freq_m) | MV64XXX_I2C_BAUD_DIV_N(drv_data->freq_n),
129 drv_data->reg_base + MV64XXX_I2C_REG_BAUD); 182 drv_data->reg_base + drv_data->reg_offsets.clock);
130 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SLAVE_ADDR); 183 writel(0, drv_data->reg_base + drv_data->reg_offsets.addr);
131 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_EXT_SLAVE_ADDR); 184 writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr);
132 writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP, 185 writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP,
133 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 186 drv_data->reg_base + drv_data->reg_offsets.control);
134 drv_data->state = MV64XXX_I2C_STATE_IDLE; 187 drv_data->state = MV64XXX_I2C_STATE_IDLE;
135} 188}
136 189
@@ -170,7 +223,7 @@ mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
170 if ((drv_data->bytes_left == 0) 223 if ((drv_data->bytes_left == 0)
171 || (drv_data->aborting 224 || (drv_data->aborting
172 && (drv_data->byte_posn != 0))) { 225 && (drv_data->byte_posn != 0))) {
173 if (drv_data->send_stop) { 226 if (drv_data->send_stop || drv_data->aborting) {
174 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; 227 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
175 drv_data->state = MV64XXX_I2C_STATE_IDLE; 228 drv_data->state = MV64XXX_I2C_STATE_IDLE;
176 } else { 229 } else {
@@ -227,7 +280,7 @@ mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
227 /* Doesn't seem to be a device at other end */ 280 /* Doesn't seem to be a device at other end */
228 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; 281 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
229 drv_data->state = MV64XXX_I2C_STATE_IDLE; 282 drv_data->state = MV64XXX_I2C_STATE_IDLE;
230 drv_data->rc = -ENODEV; 283 drv_data->rc = -ENXIO;
231 break; 284 break;
232 285
233 default: 286 default:
@@ -247,58 +300,71 @@ mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
247{ 300{
248 switch(drv_data->action) { 301 switch(drv_data->action) {
249 case MV64XXX_I2C_ACTION_SEND_RESTART: 302 case MV64XXX_I2C_ACTION_SEND_RESTART:
303 /* We should only get here if we have further messages */
304 BUG_ON(drv_data->num_msgs == 0);
305
250 drv_data->cntl_bits |= MV64XXX_I2C_REG_CONTROL_START; 306 drv_data->cntl_bits |= MV64XXX_I2C_REG_CONTROL_START;
251 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
252 writel(drv_data->cntl_bits, 307 writel(drv_data->cntl_bits,
253 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 308 drv_data->reg_base + drv_data->reg_offsets.control);
254 drv_data->block = 0; 309
255 wake_up(&drv_data->waitq); 310 drv_data->msgs++;
311 drv_data->num_msgs--;
312
313 /* Setup for the next message */
314 mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs);
315
316 /*
317 * We're never at the start of the message here, and by this
318 * time it's already too late to do any protocol mangling.
319 * Thankfully, do not advertise support for that feature.
320 */
321 drv_data->send_stop = drv_data->num_msgs == 1;
256 break; 322 break;
257 323
258 case MV64XXX_I2C_ACTION_CONTINUE: 324 case MV64XXX_I2C_ACTION_CONTINUE:
259 writel(drv_data->cntl_bits, 325 writel(drv_data->cntl_bits,
260 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 326 drv_data->reg_base + drv_data->reg_offsets.control);
261 break; 327 break;
262 328
263 case MV64XXX_I2C_ACTION_SEND_START: 329 case MV64XXX_I2C_ACTION_SEND_START:
264 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START, 330 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
265 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 331 drv_data->reg_base + drv_data->reg_offsets.control);
266 break; 332 break;
267 333
268 case MV64XXX_I2C_ACTION_SEND_ADDR_1: 334 case MV64XXX_I2C_ACTION_SEND_ADDR_1:
269 writel(drv_data->addr1, 335 writel(drv_data->addr1,
270 drv_data->reg_base + MV64XXX_I2C_REG_DATA); 336 drv_data->reg_base + drv_data->reg_offsets.data);
271 writel(drv_data->cntl_bits, 337 writel(drv_data->cntl_bits,
272 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 338 drv_data->reg_base + drv_data->reg_offsets.control);
273 break; 339 break;
274 340
275 case MV64XXX_I2C_ACTION_SEND_ADDR_2: 341 case MV64XXX_I2C_ACTION_SEND_ADDR_2:
276 writel(drv_data->addr2, 342 writel(drv_data->addr2,
277 drv_data->reg_base + MV64XXX_I2C_REG_DATA); 343 drv_data->reg_base + drv_data->reg_offsets.data);
278 writel(drv_data->cntl_bits, 344 writel(drv_data->cntl_bits,
279 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 345 drv_data->reg_base + drv_data->reg_offsets.control);
280 break; 346 break;
281 347
282 case MV64XXX_I2C_ACTION_SEND_DATA: 348 case MV64XXX_I2C_ACTION_SEND_DATA:
283 writel(drv_data->msg->buf[drv_data->byte_posn++], 349 writel(drv_data->msg->buf[drv_data->byte_posn++],
284 drv_data->reg_base + MV64XXX_I2C_REG_DATA); 350 drv_data->reg_base + drv_data->reg_offsets.data);
285 writel(drv_data->cntl_bits, 351 writel(drv_data->cntl_bits,
286 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 352 drv_data->reg_base + drv_data->reg_offsets.control);
287 break; 353 break;
288 354
289 case MV64XXX_I2C_ACTION_RCV_DATA: 355 case MV64XXX_I2C_ACTION_RCV_DATA:
290 drv_data->msg->buf[drv_data->byte_posn++] = 356 drv_data->msg->buf[drv_data->byte_posn++] =
291 readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA); 357 readl(drv_data->reg_base + drv_data->reg_offsets.data);
292 writel(drv_data->cntl_bits, 358 writel(drv_data->cntl_bits,
293 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 359 drv_data->reg_base + drv_data->reg_offsets.control);
294 break; 360 break;
295 361
296 case MV64XXX_I2C_ACTION_RCV_DATA_STOP: 362 case MV64XXX_I2C_ACTION_RCV_DATA_STOP:
297 drv_data->msg->buf[drv_data->byte_posn++] = 363 drv_data->msg->buf[drv_data->byte_posn++] =
298 readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA); 364 readl(drv_data->reg_base + drv_data->reg_offsets.data);
299 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN; 365 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
300 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP, 366 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
301 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 367 drv_data->reg_base + drv_data->reg_offsets.control);
302 drv_data->block = 0; 368 drv_data->block = 0;
303 wake_up(&drv_data->waitq); 369 wake_up(&drv_data->waitq);
304 break; 370 break;
@@ -313,7 +379,7 @@ mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
313 case MV64XXX_I2C_ACTION_SEND_STOP: 379 case MV64XXX_I2C_ACTION_SEND_STOP:
314 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN; 380 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
315 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP, 381 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
316 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 382 drv_data->reg_base + drv_data->reg_offsets.control);
317 drv_data->block = 0; 383 drv_data->block = 0;
318 wake_up(&drv_data->waitq); 384 wake_up(&drv_data->waitq);
319 break; 385 break;
@@ -329,9 +395,9 @@ mv64xxx_i2c_intr(int irq, void *dev_id)
329 irqreturn_t rc = IRQ_NONE; 395 irqreturn_t rc = IRQ_NONE;
330 396
331 spin_lock_irqsave(&drv_data->lock, flags); 397 spin_lock_irqsave(&drv_data->lock, flags);
332 while (readl(drv_data->reg_base + MV64XXX_I2C_REG_CONTROL) & 398 while (readl(drv_data->reg_base + drv_data->reg_offsets.control) &
333 MV64XXX_I2C_REG_CONTROL_IFLG) { 399 MV64XXX_I2C_REG_CONTROL_IFLG) {
334 status = readl(drv_data->reg_base + MV64XXX_I2C_REG_STATUS); 400 status = readl(drv_data->reg_base + drv_data->reg_offsets.status);
335 mv64xxx_i2c_fsm(drv_data, status); 401 mv64xxx_i2c_fsm(drv_data, status);
336 mv64xxx_i2c_do_action(drv_data); 402 mv64xxx_i2c_do_action(drv_data);
337 rc = IRQ_HANDLED; 403 rc = IRQ_HANDLED;
@@ -349,32 +415,6 @@ mv64xxx_i2c_intr(int irq, void *dev_id)
349 ***************************************************************************** 415 *****************************************************************************
350 */ 416 */
351static void 417static void
352mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
353 struct i2c_msg *msg)
354{
355 u32 dir = 0;
356
357 drv_data->msg = msg;
358 drv_data->byte_posn = 0;
359 drv_data->bytes_left = msg->len;
360 drv_data->aborting = 0;
361 drv_data->rc = 0;
362 drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK |
363 MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN;
364
365 if (msg->flags & I2C_M_RD)
366 dir = 1;
367
368 if (msg->flags & I2C_M_TEN) {
369 drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
370 drv_data->addr2 = (u32)msg->addr & 0xff;
371 } else {
372 drv_data->addr1 = ((u32)msg->addr & 0x7f) << 1 | dir;
373 drv_data->addr2 = 0;
374 }
375}
376
377static void
378mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data) 418mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
379{ 419{
380 long time_left; 420 long time_left;
@@ -414,36 +454,15 @@ mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
414 454
415static int 455static int
416mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg, 456mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg,
417 int is_first, int is_last) 457 int is_last)
418{ 458{
419 unsigned long flags; 459 unsigned long flags;
420 460
421 spin_lock_irqsave(&drv_data->lock, flags); 461 spin_lock_irqsave(&drv_data->lock, flags);
422 mv64xxx_i2c_prepare_for_io(drv_data, msg); 462 mv64xxx_i2c_prepare_for_io(drv_data, msg);
423 463
424 if (unlikely(msg->flags & I2C_M_NOSTART)) { /* Skip start/addr phases */ 464 drv_data->action = MV64XXX_I2C_ACTION_SEND_START;
425 if (drv_data->msg->flags & I2C_M_RD) { 465 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
426 /* No action to do, wait for slave to send a byte */
427 drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
428 drv_data->state =
429 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
430 } else {
431 drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
432 drv_data->state =
433 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
434 drv_data->bytes_left--;
435 }
436 } else {
437 if (is_first) {
438 drv_data->action = MV64XXX_I2C_ACTION_SEND_START;
439 drv_data->state =
440 MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
441 } else {
442 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
443 drv_data->state =
444 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
445 }
446 }
447 466
448 drv_data->send_stop = is_last; 467 drv_data->send_stop = is_last;
449 drv_data->block = 1; 468 drv_data->block = 1;
@@ -471,16 +490,20 @@ static int
471mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 490mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
472{ 491{
473 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap); 492 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
474 int i, rc; 493 int rc, ret = num;
475 494
476 for (i = 0; i < num; i++) { 495 BUG_ON(drv_data->msgs != NULL);
477 rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[i], 496 drv_data->msgs = msgs;
478 i == 0, i + 1 == num); 497 drv_data->num_msgs = num;
479 if (rc < 0) 498
480 return rc; 499 rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[0], num == 1);
481 } 500 if (rc < 0)
501 ret = rc;
502
503 drv_data->num_msgs = 0;
504 drv_data->msgs = NULL;
482 505
483 return num; 506 return ret;
484} 507}
485 508
486static const struct i2c_algorithm mv64xxx_i2c_algo = { 509static const struct i2c_algorithm mv64xxx_i2c_algo = {
@@ -495,39 +518,12 @@ static const struct i2c_algorithm mv64xxx_i2c_algo = {
495 * 518 *
496 ***************************************************************************** 519 *****************************************************************************
497 */ 520 */
498static int 521static const struct of_device_id mv64xxx_i2c_of_match_table[] = {
499mv64xxx_i2c_map_regs(struct platform_device *pd, 522 { .compatible = "allwinner,sun4i-i2c", .data = &mv64xxx_i2c_regs_sun4i},
500 struct mv64xxx_i2c_data *drv_data) 523 { .compatible = "marvell,mv64xxx-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
501{ 524 {}
502 int size; 525};
503 struct resource *r = platform_get_resource(pd, IORESOURCE_MEM, 0); 526MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table);
504
505 if (!r)
506 return -ENODEV;
507
508 size = resource_size(r);
509
510 if (!request_mem_region(r->start, size, drv_data->adapter.name))
511 return -EBUSY;
512
513 drv_data->reg_base = ioremap(r->start, size);
514 drv_data->reg_base_p = r->start;
515 drv_data->reg_size = size;
516
517 return 0;
518}
519
520static void
521mv64xxx_i2c_unmap_regs(struct mv64xxx_i2c_data *drv_data)
522{
523 if (drv_data->reg_base) {
524 iounmap(drv_data->reg_base);
525 release_mem_region(drv_data->reg_base_p, drv_data->reg_size);
526 }
527
528 drv_data->reg_base = NULL;
529 drv_data->reg_base_p = 0;
530}
531 527
532#ifdef CONFIG_OF 528#ifdef CONFIG_OF
533static int 529static int
@@ -562,8 +558,10 @@ mv64xxx_find_baud_factors(const u32 req_freq, const u32 tclk, u32 *best_n,
562 558
563static int 559static int
564mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data, 560mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
565 struct device_node *np) 561 struct device *dev)
566{ 562{
563 const struct of_device_id *device;
564 struct device_node *np = dev->of_node;
567 u32 bus_freq, tclk; 565 u32 bus_freq, tclk;
568 int rc = 0; 566 int rc = 0;
569 567
@@ -580,7 +578,11 @@ mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
580 goto out; 578 goto out;
581 } 579 }
582 tclk = clk_get_rate(drv_data->clk); 580 tclk = clk_get_rate(drv_data->clk);
583 of_property_read_u32(np, "clock-frequency", &bus_freq); 581
582 rc = of_property_read_u32(np, "clock-frequency", &bus_freq);
583 if (rc)
584 bus_freq = 100000; /* 100kHz by default */
585
584 if (!mv64xxx_find_baud_factors(bus_freq, tclk, 586 if (!mv64xxx_find_baud_factors(bus_freq, tclk,
585 &drv_data->freq_n, &drv_data->freq_m)) { 587 &drv_data->freq_n, &drv_data->freq_m)) {
586 rc = -EINVAL; 588 rc = -EINVAL;
@@ -592,6 +594,13 @@ mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
592 * So hard code the value to 1 second. 594 * So hard code the value to 1 second.
593 */ 595 */
594 drv_data->adapter.timeout = HZ; 596 drv_data->adapter.timeout = HZ;
597
598 device = of_match_device(mv64xxx_i2c_of_match_table, dev);
599 if (!device)
600 return -ENODEV;
601
602 memcpy(&drv_data->reg_offsets, device->data, sizeof(drv_data->reg_offsets));
603
595out: 604out:
596 return rc; 605 return rc;
597#endif 606#endif
@@ -599,7 +608,7 @@ out:
599#else /* CONFIG_OF */ 608#else /* CONFIG_OF */
600static int 609static int
601mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data, 610mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
602 struct device_node *np) 611 struct device *dev)
603{ 612{
604 return -ENODEV; 613 return -ENODEV;
605} 614}
@@ -610,19 +619,21 @@ mv64xxx_i2c_probe(struct platform_device *pd)
610{ 619{
611 struct mv64xxx_i2c_data *drv_data; 620 struct mv64xxx_i2c_data *drv_data;
612 struct mv64xxx_i2c_pdata *pdata = pd->dev.platform_data; 621 struct mv64xxx_i2c_pdata *pdata = pd->dev.platform_data;
622 struct resource *r;
613 int rc; 623 int rc;
614 624
615 if ((!pdata && !pd->dev.of_node)) 625 if ((!pdata && !pd->dev.of_node))
616 return -ENODEV; 626 return -ENODEV;
617 627
618 drv_data = kzalloc(sizeof(struct mv64xxx_i2c_data), GFP_KERNEL); 628 drv_data = devm_kzalloc(&pd->dev, sizeof(struct mv64xxx_i2c_data),
629 GFP_KERNEL);
619 if (!drv_data) 630 if (!drv_data)
620 return -ENOMEM; 631 return -ENOMEM;
621 632
622 if (mv64xxx_i2c_map_regs(pd, drv_data)) { 633 r = platform_get_resource(pd, IORESOURCE_MEM, 0);
623 rc = -ENODEV; 634 drv_data->reg_base = devm_ioremap_resource(&pd->dev, r);
624 goto exit_kfree; 635 if (IS_ERR(drv_data->reg_base))
625 } 636 return PTR_ERR(drv_data->reg_base);
626 637
627 strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter", 638 strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
628 sizeof(drv_data->adapter.name)); 639 sizeof(drv_data->adapter.name));
@@ -632,7 +643,7 @@ mv64xxx_i2c_probe(struct platform_device *pd)
632 643
633#if defined(CONFIG_HAVE_CLK) 644#if defined(CONFIG_HAVE_CLK)
634 /* Not all platforms have a clk */ 645 /* Not all platforms have a clk */
635 drv_data->clk = clk_get(&pd->dev, NULL); 646 drv_data->clk = devm_clk_get(&pd->dev, NULL);
636 if (!IS_ERR(drv_data->clk)) { 647 if (!IS_ERR(drv_data->clk)) {
637 clk_prepare(drv_data->clk); 648 clk_prepare(drv_data->clk);
638 clk_enable(drv_data->clk); 649 clk_enable(drv_data->clk);
@@ -643,14 +654,15 @@ mv64xxx_i2c_probe(struct platform_device *pd)
643 drv_data->freq_n = pdata->freq_n; 654 drv_data->freq_n = pdata->freq_n;
644 drv_data->irq = platform_get_irq(pd, 0); 655 drv_data->irq = platform_get_irq(pd, 0);
645 drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout); 656 drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout);
657 memcpy(&drv_data->reg_offsets, &mv64xxx_i2c_regs_mv64xxx, sizeof(drv_data->reg_offsets));
646 } else if (pd->dev.of_node) { 658 } else if (pd->dev.of_node) {
647 rc = mv64xxx_of_config(drv_data, pd->dev.of_node); 659 rc = mv64xxx_of_config(drv_data, &pd->dev);
648 if (rc) 660 if (rc)
649 goto exit_unmap_regs; 661 goto exit_clk;
650 } 662 }
651 if (drv_data->irq < 0) { 663 if (drv_data->irq < 0) {
652 rc = -ENXIO; 664 rc = -ENXIO;
653 goto exit_unmap_regs; 665 goto exit_clk;
654 } 666 }
655 667
656 drv_data->adapter.dev.parent = &pd->dev; 668 drv_data->adapter.dev.parent = &pd->dev;
@@ -664,13 +676,13 @@ mv64xxx_i2c_probe(struct platform_device *pd)
664 676
665 mv64xxx_i2c_hw_init(drv_data); 677 mv64xxx_i2c_hw_init(drv_data);
666 678
667 if (request_irq(drv_data->irq, mv64xxx_i2c_intr, 0, 679 rc = request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
668 MV64XXX_I2C_CTLR_NAME, drv_data)) { 680 MV64XXX_I2C_CTLR_NAME, drv_data);
681 if (rc) {
669 dev_err(&drv_data->adapter.dev, 682 dev_err(&drv_data->adapter.dev,
670 "mv64xxx: Can't register intr handler irq: %d\n", 683 "mv64xxx: Can't register intr handler irq%d: %d\n",
671 drv_data->irq); 684 drv_data->irq, rc);
672 rc = -EINVAL; 685 goto exit_clk;
673 goto exit_unmap_regs;
674 } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) { 686 } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) {
675 dev_err(&drv_data->adapter.dev, 687 dev_err(&drv_data->adapter.dev,
676 "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc); 688 "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc);
@@ -681,9 +693,9 @@ mv64xxx_i2c_probe(struct platform_device *pd)
681 693
682 return 0; 694 return 0;
683 695
684 exit_free_irq: 696exit_free_irq:
685 free_irq(drv_data->irq, drv_data); 697 free_irq(drv_data->irq, drv_data);
686 exit_unmap_regs: 698exit_clk:
687#if defined(CONFIG_HAVE_CLK) 699#if defined(CONFIG_HAVE_CLK)
688 /* Not all platforms have a clk */ 700 /* Not all platforms have a clk */
689 if (!IS_ERR(drv_data->clk)) { 701 if (!IS_ERR(drv_data->clk)) {
@@ -691,9 +703,6 @@ mv64xxx_i2c_probe(struct platform_device *pd)
691 clk_unprepare(drv_data->clk); 703 clk_unprepare(drv_data->clk);
692 } 704 }
693#endif 705#endif
694 mv64xxx_i2c_unmap_regs(drv_data);
695 exit_kfree:
696 kfree(drv_data);
697 return rc; 706 return rc;
698} 707}
699 708
@@ -704,7 +713,6 @@ mv64xxx_i2c_remove(struct platform_device *dev)
704 713
705 i2c_del_adapter(&drv_data->adapter); 714 i2c_del_adapter(&drv_data->adapter);
706 free_irq(drv_data->irq, drv_data); 715 free_irq(drv_data->irq, drv_data);
707 mv64xxx_i2c_unmap_regs(drv_data);
708#if defined(CONFIG_HAVE_CLK) 716#if defined(CONFIG_HAVE_CLK)
709 /* Not all platforms have a clk */ 717 /* Not all platforms have a clk */
710 if (!IS_ERR(drv_data->clk)) { 718 if (!IS_ERR(drv_data->clk)) {
@@ -712,17 +720,10 @@ mv64xxx_i2c_remove(struct platform_device *dev)
712 clk_unprepare(drv_data->clk); 720 clk_unprepare(drv_data->clk);
713 } 721 }
714#endif 722#endif
715 kfree(drv_data);
716 723
717 return 0; 724 return 0;
718} 725}
719 726
720static const struct of_device_id mv64xxx_i2c_of_match_table[] = {
721 { .compatible = "marvell,mv64xxx-i2c", },
722 {}
723};
724MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table);
725
726static struct platform_driver mv64xxx_i2c_driver = { 727static struct platform_driver mv64xxx_i2c_driver = {
727 .probe = mv64xxx_i2c_probe, 728 .probe = mv64xxx_i2c_probe,
728 .remove = mv64xxx_i2c_remove, 729 .remove = mv64xxx_i2c_remove,
diff --git a/drivers/i2c/busses/i2c-mxs.c b/drivers/i2c/busses/i2c-mxs.c
index 2039f230482d..df8ff5aea5b5 100644
--- a/drivers/i2c/busses/i2c-mxs.c
+++ b/drivers/i2c/busses/i2c-mxs.c
@@ -24,7 +24,6 @@
24#include <linux/platform_device.h> 24#include <linux/platform_device.h>
25#include <linux/jiffies.h> 25#include <linux/jiffies.h>
26#include <linux/io.h> 26#include <linux/io.h>
27#include <linux/pinctrl/consumer.h>
28#include <linux/stmp_device.h> 27#include <linux/stmp_device.h>
29#include <linux/of.h> 28#include <linux/of.h>
30#include <linux/of_device.h> 29#include <linux/of_device.h>
@@ -638,15 +637,10 @@ static int mxs_i2c_probe(struct platform_device *pdev)
638 struct device *dev = &pdev->dev; 637 struct device *dev = &pdev->dev;
639 struct mxs_i2c_dev *i2c; 638 struct mxs_i2c_dev *i2c;
640 struct i2c_adapter *adap; 639 struct i2c_adapter *adap;
641 struct pinctrl *pinctrl;
642 struct resource *res; 640 struct resource *res;
643 resource_size_t res_size; 641 resource_size_t res_size;
644 int err, irq; 642 int err, irq;
645 643
646 pinctrl = devm_pinctrl_get_select_default(dev);
647 if (IS_ERR(pinctrl))
648 return PTR_ERR(pinctrl);
649
650 i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL); 644 i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL);
651 if (!i2c) 645 if (!i2c)
652 return -ENOMEM; 646 return -ENOMEM;
diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c
index c7e3b0c1a1ca..512dfe609706 100644
--- a/drivers/i2c/busses/i2c-nomadik.c
+++ b/drivers/i2c/busses/i2c-nomadik.c
@@ -15,7 +15,6 @@
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/module.h> 16#include <linux/module.h>
17#include <linux/amba/bus.h> 17#include <linux/amba/bus.h>
18#include <linux/atomic.h>
19#include <linux/slab.h> 18#include <linux/slab.h>
20#include <linux/interrupt.h> 19#include <linux/interrupt.h>
21#include <linux/i2c.h> 20#include <linux/i2c.h>
@@ -106,6 +105,16 @@
106/* maximum threshold value */ 105/* maximum threshold value */
107#define MAX_I2C_FIFO_THRESHOLD 15 106#define MAX_I2C_FIFO_THRESHOLD 15
108 107
108/**
109 * struct i2c_vendor_data - per-vendor variations
110 * @has_mtdws: variant has the MTDWS bit
111 * @fifodepth: variant FIFO depth
112 */
113struct i2c_vendor_data {
114 bool has_mtdws;
115 u32 fifodepth;
116};
117
109enum i2c_status { 118enum i2c_status {
110 I2C_NOP, 119 I2C_NOP,
111 I2C_ON_GOING, 120 I2C_ON_GOING,
@@ -138,6 +147,7 @@ struct i2c_nmk_client {
138 147
139/** 148/**
140 * struct nmk_i2c_dev - private data structure of the controller. 149 * struct nmk_i2c_dev - private data structure of the controller.
150 * @vendor: vendor data for this variant.
141 * @adev: parent amba device. 151 * @adev: parent amba device.
142 * @adap: corresponding I2C adapter. 152 * @adap: corresponding I2C adapter.
143 * @irq: interrupt line for the controller. 153 * @irq: interrupt line for the controller.
@@ -151,6 +161,7 @@ struct i2c_nmk_client {
151 * @busy: Busy doing transfer. 161 * @busy: Busy doing transfer.
152 */ 162 */
153struct nmk_i2c_dev { 163struct nmk_i2c_dev {
164 struct i2c_vendor_data *vendor;
154 struct amba_device *adev; 165 struct amba_device *adev;
155 struct i2c_adapter adap; 166 struct i2c_adapter adap;
156 int irq; 167 int irq;
@@ -422,7 +433,7 @@ static int read_i2c(struct nmk_i2c_dev *dev, u16 flags)
422 irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF | 433 irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF |
423 I2C_IT_MAL | I2C_IT_BERR); 434 I2C_IT_MAL | I2C_IT_BERR);
424 435
425 if (dev->stop) 436 if (dev->stop || !dev->vendor->has_mtdws)
426 irq_mask |= I2C_IT_MTD; 437 irq_mask |= I2C_IT_MTD;
427 else 438 else
428 irq_mask |= I2C_IT_MTDWS; 439 irq_mask |= I2C_IT_MTDWS;
@@ -502,7 +513,7 @@ static int write_i2c(struct nmk_i2c_dev *dev, u16 flags)
502 * set the MTDWS bit (Master Transaction Done Without Stop) 513 * set the MTDWS bit (Master Transaction Done Without Stop)
503 * to start repeated start operation 514 * to start repeated start operation
504 */ 515 */
505 if (dev->stop) 516 if (dev->stop || !dev->vendor->has_mtdws)
506 irq_mask |= I2C_IT_MTD; 517 irq_mask |= I2C_IT_MTD;
507 else 518 else
508 irq_mask |= I2C_IT_MTDWS; 519 irq_mask |= I2C_IT_MTDWS;
@@ -929,8 +940,6 @@ static void nmk_i2c_of_probe(struct device_node *np,
929 pdata->sm = I2C_FREQ_MODE_FAST; 940 pdata->sm = I2C_FREQ_MODE_FAST;
930} 941}
931 942
932static atomic_t adapter_id = ATOMIC_INIT(0);
933
934static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id) 943static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id)
935{ 944{
936 int ret = 0; 945 int ret = 0;
@@ -938,6 +947,8 @@ static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id)
938 struct device_node *np = adev->dev.of_node; 947 struct device_node *np = adev->dev.of_node;
939 struct nmk_i2c_dev *dev; 948 struct nmk_i2c_dev *dev;
940 struct i2c_adapter *adap; 949 struct i2c_adapter *adap;
950 struct i2c_vendor_data *vendor = id->data;
951 u32 max_fifo_threshold = (vendor->fifodepth / 2) - 1;
941 952
942 if (!pdata) { 953 if (!pdata) {
943 if (np) { 954 if (np) {
@@ -954,12 +965,25 @@ static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id)
954 pdata = &u8500_i2c; 965 pdata = &u8500_i2c;
955 } 966 }
956 967
968 if (pdata->tft > max_fifo_threshold) {
969 dev_warn(&adev->dev, "requested TX FIFO threshold %u, adjusted down to %u\n",
970 pdata->tft, max_fifo_threshold);
971 pdata->tft = max_fifo_threshold;
972 }
973
974 if (pdata->rft > max_fifo_threshold) {
975 dev_warn(&adev->dev, "requested RX FIFO threshold %u, adjusted down to %u\n",
976 pdata->rft, max_fifo_threshold);
977 pdata->rft = max_fifo_threshold;
978 }
979
957 dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL); 980 dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL);
958 if (!dev) { 981 if (!dev) {
959 dev_err(&adev->dev, "cannot allocate memory\n"); 982 dev_err(&adev->dev, "cannot allocate memory\n");
960 ret = -ENOMEM; 983 ret = -ENOMEM;
961 goto err_no_mem; 984 goto err_no_mem;
962 } 985 }
986 dev->vendor = vendor;
963 dev->busy = false; 987 dev->busy = false;
964 dev->adev = adev; 988 dev->adev = adev;
965 amba_set_drvdata(adev, dev); 989 amba_set_drvdata(adev, dev);
@@ -999,10 +1023,8 @@ static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id)
999 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 1023 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1000 adap->algo = &nmk_i2c_algo; 1024 adap->algo = &nmk_i2c_algo;
1001 adap->timeout = msecs_to_jiffies(pdata->timeout); 1025 adap->timeout = msecs_to_jiffies(pdata->timeout);
1002 adap->nr = atomic_read(&adapter_id);
1003 snprintf(adap->name, sizeof(adap->name), 1026 snprintf(adap->name, sizeof(adap->name),
1004 "Nomadik I2C%d at %pR", adap->nr, &adev->res); 1027 "Nomadik I2C at %pR", &adev->res);
1005 atomic_inc(&adapter_id);
1006 1028
1007 /* fetch the controller configuration from machine */ 1029 /* fetch the controller configuration from machine */
1008 dev->cfg.clk_freq = pdata->clk_freq; 1030 dev->cfg.clk_freq = pdata->clk_freq;
@@ -1017,7 +1039,7 @@ static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id)
1017 "initialize %s on virtual base %p\n", 1039 "initialize %s on virtual base %p\n",
1018 adap->name, dev->virtbase); 1040 adap->name, dev->virtbase);
1019 1041
1020 ret = i2c_add_numbered_adapter(adap); 1042 ret = i2c_add_adapter(adap);
1021 if (ret) { 1043 if (ret) {
1022 dev_err(&adev->dev, "failed to add adapter\n"); 1044 dev_err(&adev->dev, "failed to add adapter\n");
1023 goto err_add_adap; 1045 goto err_add_adap;
@@ -1064,14 +1086,26 @@ static int nmk_i2c_remove(struct amba_device *adev)
1064 return 0; 1086 return 0;
1065} 1087}
1066 1088
1089static struct i2c_vendor_data vendor_stn8815 = {
1090 .has_mtdws = false,
1091 .fifodepth = 16, /* Guessed from TFTR/RFTR = 7 */
1092};
1093
1094static struct i2c_vendor_data vendor_db8500 = {
1095 .has_mtdws = true,
1096 .fifodepth = 32, /* Guessed from TFTR/RFTR = 15 */
1097};
1098
1067static struct amba_id nmk_i2c_ids[] = { 1099static struct amba_id nmk_i2c_ids[] = {
1068 { 1100 {
1069 .id = 0x00180024, 1101 .id = 0x00180024,
1070 .mask = 0x00ffffff, 1102 .mask = 0x00ffffff,
1103 .data = &vendor_stn8815,
1071 }, 1104 },
1072 { 1105 {
1073 .id = 0x00380024, 1106 .id = 0x00380024,
1074 .mask = 0x00ffffff, 1107 .mask = 0x00ffffff,
1108 .data = &vendor_db8500,
1075 }, 1109 },
1076 {}, 1110 {},
1077}; 1111};
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index e02f9e36a7b2..142b694d1c60 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -180,6 +180,8 @@ enum {
180#define I2C_OMAP_ERRATA_I207 (1 << 0) 180#define I2C_OMAP_ERRATA_I207 (1 << 0)
181#define I2C_OMAP_ERRATA_I462 (1 << 1) 181#define I2C_OMAP_ERRATA_I462 (1 << 1)
182 182
183#define OMAP_I2C_IP_V2_INTERRUPTS_MASK 0x6FFF
184
183struct omap_i2c_dev { 185struct omap_i2c_dev {
184 spinlock_t lock; /* IRQ synchronization */ 186 spinlock_t lock; /* IRQ synchronization */
185 struct device *dev; 187 struct device *dev;
@@ -193,6 +195,7 @@ struct omap_i2c_dev {
193 long latency); 195 long latency);
194 u32 speed; /* Speed of bus in kHz */ 196 u32 speed; /* Speed of bus in kHz */
195 u32 flags; 197 u32 flags;
198 u16 scheme;
196 u16 cmd_err; 199 u16 cmd_err;
197 u8 *buf; 200 u8 *buf;
198 u8 *regs; 201 u8 *regs;
@@ -1082,14 +1085,7 @@ omap_i2c_probe(struct platform_device *pdev)
1082 int irq; 1085 int irq;
1083 int r; 1086 int r;
1084 u32 rev; 1087 u32 rev;
1085 u16 minor, major, scheme; 1088 u16 minor, major;
1086
1087 /* NOTE: driver uses the static register mapping */
1088 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1089 if (!mem) {
1090 dev_err(&pdev->dev, "no mem resource?\n");
1091 return -ENODEV;
1092 }
1093 1089
1094 irq = platform_get_irq(pdev, 0); 1090 irq = platform_get_irq(pdev, 0);
1095 if (irq < 0) { 1091 if (irq < 0) {
@@ -1103,6 +1099,7 @@ omap_i2c_probe(struct platform_device *pdev)
1103 return -ENOMEM; 1099 return -ENOMEM;
1104 } 1100 }
1105 1101
1102 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1106 dev->base = devm_ioremap_resource(&pdev->dev, mem); 1103 dev->base = devm_ioremap_resource(&pdev->dev, mem);
1107 if (IS_ERR(dev->base)) 1104 if (IS_ERR(dev->base))
1108 return PTR_ERR(dev->base); 1105 return PTR_ERR(dev->base);
@@ -1159,8 +1156,8 @@ omap_i2c_probe(struct platform_device *pdev)
1159 */ 1156 */
1160 rev = __raw_readw(dev->base + 0x04); 1157 rev = __raw_readw(dev->base + 0x04);
1161 1158
1162 scheme = OMAP_I2C_SCHEME(rev); 1159 dev->scheme = OMAP_I2C_SCHEME(rev);
1163 switch (scheme) { 1160 switch (dev->scheme) {
1164 case OMAP_I2C_SCHEME_0: 1161 case OMAP_I2C_SCHEME_0:
1165 dev->regs = (u8 *)reg_map_ip_v1; 1162 dev->regs = (u8 *)reg_map_ip_v1;
1166 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG); 1163 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG);
@@ -1289,7 +1286,11 @@ static int omap_i2c_runtime_suspend(struct device *dev)
1289 1286
1290 _dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG); 1287 _dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG);
1291 1288
1292 omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0); 1289 if (_dev->scheme == OMAP_I2C_SCHEME_0)
1290 omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0);
1291 else
1292 omap_i2c_write_reg(_dev, OMAP_I2C_IP_V2_IRQENABLE_CLR,
1293 OMAP_I2C_IP_V2_INTERRUPTS_MASK);
1293 1294
1294 if (_dev->rev < OMAP_I2C_OMAP1_REV_2) { 1295 if (_dev->rev < OMAP_I2C_OMAP1_REV_2) {
1295 omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */ 1296 omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */
diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c
index ea6d45d1dcd6..fbafed29fb81 100644
--- a/drivers/i2c/busses/i2c-pxa.c
+++ b/drivers/i2c/busses/i2c-pxa.c
@@ -1160,7 +1160,7 @@ static int i2c_pxa_probe(struct platform_device *dev)
1160 i2c->adap.class = plat->class; 1160 i2c->adap.class = plat->class;
1161 } 1161 }
1162 1162
1163 clk_enable(i2c->clk); 1163 clk_prepare_enable(i2c->clk);
1164 1164
1165 if (i2c->use_pio) { 1165 if (i2c->use_pio) {
1166 i2c->adap.algo = &i2c_pxa_pio_algorithm; 1166 i2c->adap.algo = &i2c_pxa_pio_algorithm;
@@ -1202,7 +1202,7 @@ eadapt:
1202 if (!i2c->use_pio) 1202 if (!i2c->use_pio)
1203 free_irq(irq, i2c); 1203 free_irq(irq, i2c);
1204ereqirq: 1204ereqirq:
1205 clk_disable(i2c->clk); 1205 clk_disable_unprepare(i2c->clk);
1206 iounmap(i2c->reg_base); 1206 iounmap(i2c->reg_base);
1207eremap: 1207eremap:
1208 clk_put(i2c->clk); 1208 clk_put(i2c->clk);
@@ -1221,7 +1221,7 @@ static int i2c_pxa_remove(struct platform_device *dev)
1221 if (!i2c->use_pio) 1221 if (!i2c->use_pio)
1222 free_irq(i2c->irq, i2c); 1222 free_irq(i2c->irq, i2c);
1223 1223
1224 clk_disable(i2c->clk); 1224 clk_disable_unprepare(i2c->clk);
1225 clk_put(i2c->clk); 1225 clk_put(i2c->clk);
1226 1226
1227 iounmap(i2c->reg_base); 1227 iounmap(i2c->reg_base);
diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c
index 4ba4a95b6b26..0fc585861610 100644
--- a/drivers/i2c/busses/i2c-rcar.c
+++ b/drivers/i2c/busses/i2c-rcar.c
@@ -623,12 +623,6 @@ static int rcar_i2c_probe(struct platform_device *pdev)
623 u32 bus_speed; 623 u32 bus_speed;
624 int ret; 624 int ret;
625 625
626 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
627 if (!res) {
628 dev_err(dev, "no mmio resources\n");
629 return -ENODEV;
630 }
631
632 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL); 626 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
633 if (!priv) { 627 if (!priv) {
634 dev_err(dev, "no mem for private data\n"); 628 dev_err(dev, "no mem for private data\n");
@@ -642,6 +636,7 @@ static int rcar_i2c_probe(struct platform_device *pdev)
642 if (ret < 0) 636 if (ret < 0)
643 return ret; 637 return ret;
644 638
639 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
645 priv->io = devm_ioremap_resource(dev, res); 640 priv->io = devm_ioremap_resource(dev, res);
646 if (IS_ERR(priv->io)) 641 if (IS_ERR(priv->io))
647 return PTR_ERR(priv->io); 642 return PTR_ERR(priv->io);
diff --git a/drivers/i2c/busses/i2c-wmt.c b/drivers/i2c/busses/i2c-wmt.c
new file mode 100644
index 000000000000..baaa7d15b73e
--- /dev/null
+++ b/drivers/i2c/busses/i2c-wmt.c
@@ -0,0 +1,479 @@
1/*
2 * Wondermedia I2C Master Mode Driver
3 *
4 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5 *
6 * Derived from GPLv2+ licensed source:
7 * - Copyright (C) 2008 WonderMedia Technologies, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2, or
11 * (at your option) any later version. as published by the Free Software
12 * Foundation
13 */
14
15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/err.h>
18#include <linux/i2c.h>
19#include <linux/interrupt.h>
20#include <linux/io.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/of_address.h>
24#include <linux/of_i2c.h>
25#include <linux/of_irq.h>
26#include <linux/platform_device.h>
27
28#define REG_CR 0x00
29#define REG_TCR 0x02
30#define REG_CSR 0x04
31#define REG_ISR 0x06
32#define REG_IMR 0x08
33#define REG_CDR 0x0A
34#define REG_TR 0x0C
35#define REG_MCR 0x0E
36#define REG_SLAVE_CR 0x10
37#define REG_SLAVE_SR 0x12
38#define REG_SLAVE_ISR 0x14
39#define REG_SLAVE_IMR 0x16
40#define REG_SLAVE_DR 0x18
41#define REG_SLAVE_TR 0x1A
42
43/* REG_CR Bit fields */
44#define CR_TX_NEXT_ACK 0x0000
45#define CR_ENABLE 0x0001
46#define CR_TX_NEXT_NO_ACK 0x0002
47#define CR_TX_END 0x0004
48#define CR_CPU_RDY 0x0008
49#define SLAV_MODE_SEL 0x8000
50
51/* REG_TCR Bit fields */
52#define TCR_STANDARD_MODE 0x0000
53#define TCR_MASTER_WRITE 0x0000
54#define TCR_HS_MODE 0x2000
55#define TCR_MASTER_READ 0x4000
56#define TCR_FAST_MODE 0x8000
57#define TCR_SLAVE_ADDR_MASK 0x007F
58
59/* REG_ISR Bit fields */
60#define ISR_NACK_ADDR 0x0001
61#define ISR_BYTE_END 0x0002
62#define ISR_SCL_TIMEOUT 0x0004
63#define ISR_WRITE_ALL 0x0007
64
65/* REG_IMR Bit fields */
66#define IMR_ENABLE_ALL 0x0007
67
68/* REG_CSR Bit fields */
69#define CSR_RCV_NOT_ACK 0x0001
70#define CSR_RCV_ACK_MASK 0x0001
71#define CSR_READY_MASK 0x0002
72
73/* REG_TR */
74#define SCL_TIMEOUT(x) (((x) & 0xFF) << 8)
75#define TR_STD 0x0064
76#define TR_HS 0x0019
77
78/* REG_MCR */
79#define MCR_APB_96M 7
80#define MCR_APB_166M 12
81
82#define I2C_MODE_STANDARD 0
83#define I2C_MODE_FAST 1
84
85#define WMT_I2C_TIMEOUT (msecs_to_jiffies(1000))
86
87struct wmt_i2c_dev {
88 struct i2c_adapter adapter;
89 struct completion complete;
90 struct device *dev;
91 void __iomem *base;
92 struct clk *clk;
93 int mode;
94 int irq;
95 u16 cmd_status;
96};
97
98static int wmt_i2c_wait_bus_not_busy(struct wmt_i2c_dev *i2c_dev)
99{
100 unsigned long timeout;
101
102 timeout = jiffies + WMT_I2C_TIMEOUT;
103 while (!(readw(i2c_dev->base + REG_CSR) & CSR_READY_MASK)) {
104 if (time_after(jiffies, timeout)) {
105 dev_warn(i2c_dev->dev, "timeout waiting for bus ready\n");
106 return -EBUSY;
107 }
108 msleep(20);
109 }
110
111 return 0;
112}
113
114static int wmt_check_status(struct wmt_i2c_dev *i2c_dev)
115{
116 int ret = 0;
117
118 if (i2c_dev->cmd_status & ISR_NACK_ADDR)
119 ret = -EIO;
120
121 if (i2c_dev->cmd_status & ISR_SCL_TIMEOUT)
122 ret = -ETIMEDOUT;
123
124 return ret;
125}
126
127static int wmt_i2c_write(struct i2c_adapter *adap, struct i2c_msg *pmsg,
128 int last)
129{
130 struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
131 u16 val, tcr_val;
132 int ret, wait_result;
133 int xfer_len = 0;
134
135 if (!(pmsg->flags & I2C_M_NOSTART)) {
136 ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
137 if (ret < 0)
138 return ret;
139 }
140
141 if (pmsg->len == 0) {
142 /*
143 * We still need to run through the while (..) once, so
144 * start at -1 and break out early from the loop
145 */
146 xfer_len = -1;
147 writew(0, i2c_dev->base + REG_CDR);
148 } else {
149 writew(pmsg->buf[0] & 0xFF, i2c_dev->base + REG_CDR);
150 }
151
152 if (!(pmsg->flags & I2C_M_NOSTART)) {
153 val = readw(i2c_dev->base + REG_CR);
154 val &= ~CR_TX_END;
155 writew(val, i2c_dev->base + REG_CR);
156
157 val = readw(i2c_dev->base + REG_CR);
158 val |= CR_CPU_RDY;
159 writew(val, i2c_dev->base + REG_CR);
160 }
161
162 INIT_COMPLETION(i2c_dev->complete);
163
164 if (i2c_dev->mode == I2C_MODE_STANDARD)
165 tcr_val = TCR_STANDARD_MODE;
166 else
167 tcr_val = TCR_FAST_MODE;
168
169 tcr_val |= (TCR_MASTER_WRITE | (pmsg->addr & TCR_SLAVE_ADDR_MASK));
170
171 writew(tcr_val, i2c_dev->base + REG_TCR);
172
173 if (pmsg->flags & I2C_M_NOSTART) {
174 val = readw(i2c_dev->base + REG_CR);
175 val |= CR_CPU_RDY;
176 writew(val, i2c_dev->base + REG_CR);
177 }
178
179 while (xfer_len < pmsg->len) {
180 wait_result = wait_for_completion_timeout(&i2c_dev->complete,
181 500 * HZ / 1000);
182
183 if (wait_result == 0)
184 return -ETIMEDOUT;
185
186 ret = wmt_check_status(i2c_dev);
187 if (ret)
188 return ret;
189
190 xfer_len++;
191
192 val = readw(i2c_dev->base + REG_CSR);
193 if ((val & CSR_RCV_ACK_MASK) == CSR_RCV_NOT_ACK) {
194 dev_dbg(i2c_dev->dev, "write RCV NACK error\n");
195 return -EIO;
196 }
197
198 if (pmsg->len == 0) {
199 val = CR_TX_END | CR_CPU_RDY | CR_ENABLE;
200 writew(val, i2c_dev->base + REG_CR);
201 break;
202 }
203
204 if (xfer_len == pmsg->len) {
205 if (last != 1)
206 writew(CR_ENABLE, i2c_dev->base + REG_CR);
207 } else {
208 writew(pmsg->buf[xfer_len] & 0xFF, i2c_dev->base +
209 REG_CDR);
210 writew(CR_CPU_RDY | CR_ENABLE, i2c_dev->base + REG_CR);
211 }
212 }
213
214 return 0;
215}
216
217static int wmt_i2c_read(struct i2c_adapter *adap, struct i2c_msg *pmsg,
218 int last)
219{
220 struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
221 u16 val, tcr_val;
222 int ret, wait_result;
223 u32 xfer_len = 0;
224
225 if (!(pmsg->flags & I2C_M_NOSTART)) {
226 ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
227 if (ret < 0)
228 return ret;
229 }
230
231 val = readw(i2c_dev->base + REG_CR);
232 val &= ~CR_TX_END;
233 writew(val, i2c_dev->base + REG_CR);
234
235 val = readw(i2c_dev->base + REG_CR);
236 val &= ~CR_TX_NEXT_NO_ACK;
237 writew(val, i2c_dev->base + REG_CR);
238
239 if (!(pmsg->flags & I2C_M_NOSTART)) {
240 val = readw(i2c_dev->base + REG_CR);
241 val |= CR_CPU_RDY;
242 writew(val, i2c_dev->base + REG_CR);
243 }
244
245 if (pmsg->len == 1) {
246 val = readw(i2c_dev->base + REG_CR);
247 val |= CR_TX_NEXT_NO_ACK;
248 writew(val, i2c_dev->base + REG_CR);
249 }
250
251 INIT_COMPLETION(i2c_dev->complete);
252
253 if (i2c_dev->mode == I2C_MODE_STANDARD)
254 tcr_val = TCR_STANDARD_MODE;
255 else
256 tcr_val = TCR_FAST_MODE;
257
258 tcr_val |= TCR_MASTER_READ | (pmsg->addr & TCR_SLAVE_ADDR_MASK);
259
260 writew(tcr_val, i2c_dev->base + REG_TCR);
261
262 if (pmsg->flags & I2C_M_NOSTART) {
263 val = readw(i2c_dev->base + REG_CR);
264 val |= CR_CPU_RDY;
265 writew(val, i2c_dev->base + REG_CR);
266 }
267
268 while (xfer_len < pmsg->len) {
269 wait_result = wait_for_completion_timeout(&i2c_dev->complete,
270 500 * HZ / 1000);
271
272 if (!wait_result)
273 return -ETIMEDOUT;
274
275 ret = wmt_check_status(i2c_dev);
276 if (ret)
277 return ret;
278
279 pmsg->buf[xfer_len] = readw(i2c_dev->base + REG_CDR) >> 8;
280 xfer_len++;
281
282 if (xfer_len == pmsg->len - 1) {
283 val = readw(i2c_dev->base + REG_CR);
284 val |= (CR_TX_NEXT_NO_ACK | CR_CPU_RDY);
285 writew(val, i2c_dev->base + REG_CR);
286 } else {
287 val = readw(i2c_dev->base + REG_CR);
288 val |= CR_CPU_RDY;
289 writew(val, i2c_dev->base + REG_CR);
290 }
291 }
292
293 return 0;
294}
295
296static int wmt_i2c_xfer(struct i2c_adapter *adap,
297 struct i2c_msg msgs[],
298 int num)
299{
300 struct i2c_msg *pmsg;
301 int i, is_last;
302 int ret = 0;
303
304 for (i = 0; ret >= 0 && i < num; i++) {
305 is_last = ((i + 1) == num);
306
307 pmsg = &msgs[i];
308 if (pmsg->flags & I2C_M_RD)
309 ret = wmt_i2c_read(adap, pmsg, is_last);
310 else
311 ret = wmt_i2c_write(adap, pmsg, is_last);
312 }
313
314 return (ret < 0) ? ret : i;
315}
316
317static u32 wmt_i2c_func(struct i2c_adapter *adap)
318{
319 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART;
320}
321
322static const struct i2c_algorithm wmt_i2c_algo = {
323 .master_xfer = wmt_i2c_xfer,
324 .functionality = wmt_i2c_func,
325};
326
327static irqreturn_t wmt_i2c_isr(int irq, void *data)
328{
329 struct wmt_i2c_dev *i2c_dev = data;
330
331 /* save the status and write-clear it */
332 i2c_dev->cmd_status = readw(i2c_dev->base + REG_ISR);
333 writew(i2c_dev->cmd_status, i2c_dev->base + REG_ISR);
334
335 complete(&i2c_dev->complete);
336
337 return IRQ_HANDLED;
338}
339
340static int wmt_i2c_reset_hardware(struct wmt_i2c_dev *i2c_dev)
341{
342 int err;
343
344 err = clk_prepare_enable(i2c_dev->clk);
345 if (err) {
346 dev_err(i2c_dev->dev, "failed to enable clock\n");
347 return err;
348 }
349
350 err = clk_set_rate(i2c_dev->clk, 20000000);
351 if (err) {
352 dev_err(i2c_dev->dev, "failed to set clock = 20Mhz\n");
353 return err;
354 }
355
356 writew(0, i2c_dev->base + REG_CR);
357 writew(MCR_APB_166M, i2c_dev->base + REG_MCR);
358 writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
359 writew(IMR_ENABLE_ALL, i2c_dev->base + REG_IMR);
360 writew(CR_ENABLE, i2c_dev->base + REG_CR);
361 readw(i2c_dev->base + REG_CSR); /* read clear */
362 writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
363
364 if (i2c_dev->mode == I2C_MODE_STANDARD)
365 writew(SCL_TIMEOUT(128) | TR_STD, i2c_dev->base + REG_TR);
366 else
367 writew(SCL_TIMEOUT(128) | TR_HS, i2c_dev->base + REG_TR);
368
369 return 0;
370}
371
372static int wmt_i2c_probe(struct platform_device *pdev)
373{
374 struct device_node *np = pdev->dev.of_node;
375 struct wmt_i2c_dev *i2c_dev;
376 struct i2c_adapter *adap;
377 struct resource *res;
378 int err;
379 u32 clk_rate;
380
381 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
382 if (!i2c_dev) {
383 dev_err(&pdev->dev, "device memory allocation failed\n");
384 return -ENOMEM;
385 }
386
387 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
388 i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
389 if (IS_ERR(i2c_dev->base))
390 return PTR_ERR(i2c_dev->base);
391
392 i2c_dev->irq = irq_of_parse_and_map(np, 0);
393 if (!i2c_dev->irq) {
394 dev_err(&pdev->dev, "irq missing or invalid\n");
395 return -EINVAL;
396 }
397
398 i2c_dev->clk = of_clk_get(np, 0);
399 if (IS_ERR(i2c_dev->clk)) {
400 dev_err(&pdev->dev, "unable to request clock\n");
401 return PTR_ERR(i2c_dev->clk);
402 }
403
404 i2c_dev->mode = I2C_MODE_STANDARD;
405 err = of_property_read_u32(np, "clock-frequency", &clk_rate);
406 if ((!err) && (clk_rate == 400000))
407 i2c_dev->mode = I2C_MODE_FAST;
408
409 i2c_dev->dev = &pdev->dev;
410
411 err = devm_request_irq(&pdev->dev, i2c_dev->irq, wmt_i2c_isr, 0,
412 "i2c", i2c_dev);
413 if (err) {
414 dev_err(&pdev->dev, "failed to request irq %i\n", i2c_dev->irq);
415 return err;
416 }
417
418 adap = &i2c_dev->adapter;
419 i2c_set_adapdata(adap, i2c_dev);
420 strlcpy(adap->name, "WMT I2C adapter", sizeof(adap->name));
421 adap->owner = THIS_MODULE;
422 adap->algo = &wmt_i2c_algo;
423 adap->dev.parent = &pdev->dev;
424 adap->dev.of_node = pdev->dev.of_node;
425
426 init_completion(&i2c_dev->complete);
427
428 err = wmt_i2c_reset_hardware(i2c_dev);
429 if (err) {
430 dev_err(&pdev->dev, "error initializing hardware\n");
431 return err;
432 }
433
434 err = i2c_add_adapter(adap);
435 if (err) {
436 dev_err(&pdev->dev, "failed to add adapter\n");
437 return err;
438 }
439
440 platform_set_drvdata(pdev, i2c_dev);
441
442 of_i2c_register_devices(adap);
443
444 return 0;
445}
446
447static int wmt_i2c_remove(struct platform_device *pdev)
448{
449 struct wmt_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
450
451 /* Disable interrupts, clock and delete adapter */
452 writew(0, i2c_dev->base + REG_IMR);
453 clk_disable_unprepare(i2c_dev->clk);
454 i2c_del_adapter(&i2c_dev->adapter);
455
456 return 0;
457}
458
459static struct of_device_id wmt_i2c_dt_ids[] = {
460 { .compatible = "wm,wm8505-i2c" },
461 { /* Sentinel */ },
462};
463
464static struct platform_driver wmt_i2c_driver = {
465 .probe = wmt_i2c_probe,
466 .remove = wmt_i2c_remove,
467 .driver = {
468 .name = "wmt-i2c",
469 .owner = THIS_MODULE,
470 .of_match_table = wmt_i2c_dt_ids,
471 },
472};
473
474module_platform_driver(wmt_i2c_driver);
475
476MODULE_DESCRIPTION("Wondermedia I2C master-mode bus adapter");
477MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
478MODULE_LICENSE("GPL");
479MODULE_DEVICE_TABLE(of, wmt_i2c_dt_ids);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-12 12:11:49 -0500