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authorAndreas Larsson <andreas@gaisler.com>2012-11-19 07:17:48 -0500
committerWolfram Sang <w.sang@pengutronix.de>2012-11-22 16:34:35 -0500
commitc5d5474425c4e7e291a98e739ea65f8acd0d8d5c (patch)
tree113d89b36e91c14b2405e1c3f4e38c52b608cfa1 /drivers/i2c
parent658122fe5e3a72940631ceda3efcb841054d91dc (diff)
i2c: ocores: Move grlib set/get functions into #ifdef CONFIG_OF block
This moves the grlib set and get functions into the #ifdef CONFIG_OF block to avoid warnings of unimplemented functions when compiling with -Wunused-function when CONFIG_OF is not defined. Signed-off-by: Andreas Larsson <andreas@gaisler.com> Acked-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Diffstat (limited to 'drivers/i2c')
-rw-r--r--drivers/i2c/busses/i2c-ocores.c68
1 files changed, 34 insertions, 34 deletions
diff --git a/drivers/i2c/busses/i2c-ocores.c b/drivers/i2c/busses/i2c-ocores.c
index 0ea84199b507..df69598ed28e 100644
--- a/drivers/i2c/busses/i2c-ocores.c
+++ b/drivers/i2c/busses/i2c-ocores.c
@@ -109,40 +109,6 @@ static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg)
109 return ioread32(i2c->base + (reg << i2c->reg_shift)); 109 return ioread32(i2c->base + (reg << i2c->reg_shift));
110} 110}
111 111
112/* Read and write functions for the GRLIB port of the controller. Registers are
113 * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
114 * register. The subsequent registers has their offset decreased accordingly. */
115static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
116{
117 u32 rd;
118 int rreg = reg;
119 if (reg != OCI2C_PRELOW)
120 rreg--;
121 rd = ioread32be(i2c->base + (rreg << i2c->reg_shift));
122 if (reg == OCI2C_PREHIGH)
123 return (u8)(rd >> 8);
124 else
125 return (u8)rd;
126}
127
128static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
129{
130 u32 curr, wr;
131 int rreg = reg;
132 if (reg != OCI2C_PRELOW)
133 rreg--;
134 if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) {
135 curr = ioread32be(i2c->base + (rreg << i2c->reg_shift));
136 if (reg == OCI2C_PRELOW)
137 wr = (curr & 0xff00) | value;
138 else
139 wr = (((u32)value) << 8) | (curr & 0xff);
140 } else {
141 wr = value;
142 }
143 iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift));
144}
145
146static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value) 112static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
147{ 113{
148 i2c->setreg(i2c, reg, value); 114 i2c->setreg(i2c, reg, value);
@@ -303,6 +269,40 @@ static struct of_device_id ocores_i2c_match[] = {
303MODULE_DEVICE_TABLE(of, ocores_i2c_match); 269MODULE_DEVICE_TABLE(of, ocores_i2c_match);
304 270
305#ifdef CONFIG_OF 271#ifdef CONFIG_OF
272/* Read and write functions for the GRLIB port of the controller. Registers are
273 * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
274 * register. The subsequent registers has their offset decreased accordingly. */
275static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
276{
277 u32 rd;
278 int rreg = reg;
279 if (reg != OCI2C_PRELOW)
280 rreg--;
281 rd = ioread32be(i2c->base + (rreg << i2c->reg_shift));
282 if (reg == OCI2C_PREHIGH)
283 return (u8)(rd >> 8);
284 else
285 return (u8)rd;
286}
287
288static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
289{
290 u32 curr, wr;
291 int rreg = reg;
292 if (reg != OCI2C_PRELOW)
293 rreg--;
294 if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) {
295 curr = ioread32be(i2c->base + (rreg << i2c->reg_shift));
296 if (reg == OCI2C_PRELOW)
297 wr = (curr & 0xff00) | value;
298 else
299 wr = (((u32)value) << 8) | (curr & 0xff);
300 } else {
301 wr = value;
302 }
303 iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift));
304}
305
306static int ocores_i2c_of_probe(struct platform_device *pdev, 306static int ocores_i2c_of_probe(struct platform_device *pdev,
307 struct ocores_i2c *i2c) 307 struct ocores_i2c *i2c)
308{ 308{