aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/i2c
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@g5.osdl.org>2005-09-08 18:43:09 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2005-09-08 18:43:09 -0400
commitc0d6f9663b30a09ed725229b2d50391268c8538e (patch)
tree7ba471cf9632097682ab55689cd64c9a68e11235 /drivers/i2c
parent0db7443b2bd0b92da4e8afa46f8123a7076136c6 (diff)
parent6fd60fa97b706e52abba7c9f810b148aa230817f (diff)
Merge master.kernel.org:/home/rmk/linux-2.6-i2c manually
Old tree, so the automatic merge had some problems.
Diffstat (limited to 'drivers/i2c')
-rw-r--r--drivers/i2c/busses/Kconfig16
-rw-r--r--drivers/i2c/busses/Makefile1
-rw-r--r--drivers/i2c/busses/i2c-pxa.c1022
3 files changed, 1039 insertions, 0 deletions
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 6e9da1372225..8334496a7e0a 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -144,6 +144,22 @@ config I2C_I810
144 This driver can also be built as a module. If so, the module 144 This driver can also be built as a module. If so, the module
145 will be called i2c-i810. 145 will be called i2c-i810.
146 146
147config I2C_PXA
148 tristate "Intel PXA2XX I2C adapter (EXPERIMENTAL)"
149 depends on I2C && EXPERIMENTAL && ARCH_PXA
150 help
151 If you have devices in the PXA I2C bus, say yes to this option.
152 This driver can also be built as a module. If so, the module
153 will be called i2c-pxa.
154
155config I2C_PXA_SLAVE
156 bool "Intel PXA2XX I2C Slave comms support"
157 depends on I2C_PXA
158 help
159 Support I2C slave mode communications on the PXA I2C bus. This
160 is necessary for systems where the PXA may be a target on the
161 I2C bus.
162
147config I2C_PIIX4 163config I2C_PIIX4
148 tristate "Intel PIIX4" 164 tristate "Intel PIIX4"
149 depends on I2C && PCI 165 depends on I2C && PCI
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 42d6d814da72..980b3e983670 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_I2C_PARPORT_LIGHT) += i2c-parport-light.o
28obj-$(CONFIG_I2C_PCA_ISA) += i2c-pca-isa.o 28obj-$(CONFIG_I2C_PCA_ISA) += i2c-pca-isa.o
29obj-$(CONFIG_I2C_PIIX4) += i2c-piix4.o 29obj-$(CONFIG_I2C_PIIX4) += i2c-piix4.o
30obj-$(CONFIG_I2C_PROSAVAGE) += i2c-prosavage.o 30obj-$(CONFIG_I2C_PROSAVAGE) += i2c-prosavage.o
31obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
31obj-$(CONFIG_I2C_RPXLITE) += i2c-rpx.o 32obj-$(CONFIG_I2C_RPXLITE) += i2c-rpx.o
32obj-$(CONFIG_I2C_S3C2410) += i2c-s3c2410.o 33obj-$(CONFIG_I2C_S3C2410) += i2c-s3c2410.o
33obj-$(CONFIG_I2C_SAVAGE4) += i2c-savage4.o 34obj-$(CONFIG_I2C_SAVAGE4) += i2c-savage4.o
diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c
new file mode 100644
index 000000000000..fdf53ce04248
--- /dev/null
+++ b/drivers/i2c/busses/i2c-pxa.c
@@ -0,0 +1,1022 @@
1/*
2 * i2c_adap_pxa.c
3 *
4 * I2C adapter for the PXA I2C bus access.
5 *
6 * Copyright (C) 2002 Intrinsyc Software Inc.
7 * Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * History:
14 * Apr 2002: Initial version [CS]
15 * Jun 2002: Properly seperated algo/adap [FB]
16 * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
17 * Jan 2003: added limited signal handling [Kai-Uwe Bloem]
18 * Sep 2004: Major rework to ensure efficient bus handling [RMK]
19 * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
20 * Feb 2005: Rework slave mode handling [RMK]
21 */
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/i2c.h>
25#include <linux/i2c-id.h>
26#include <linux/init.h>
27#include <linux/time.h>
28#include <linux/sched.h>
29#include <linux/delay.h>
30#include <linux/errno.h>
31#include <linux/interrupt.h>
32#include <linux/i2c-pxa.h>
33
34#include <asm/hardware.h>
35#include <asm/irq.h>
36#include <asm/arch/i2c.h>
37#include <asm/arch/pxa-regs.h>
38
39struct pxa_i2c {
40 spinlock_t lock;
41 wait_queue_head_t wait;
42 struct i2c_msg *msg;
43 unsigned int msg_num;
44 unsigned int msg_idx;
45 unsigned int msg_ptr;
46 unsigned int slave_addr;
47
48 struct i2c_adapter adap;
49#ifdef CONFIG_I2C_PXA_SLAVE
50 struct i2c_slave_client *slave;
51#endif
52
53 unsigned int irqlogidx;
54 u32 isrlog[32];
55 u32 icrlog[32];
56};
57
58/*
59 * I2C Slave mode address
60 */
61#define I2C_PXA_SLAVE_ADDR 0x1
62
63#ifdef DEBUG
64
65struct bits {
66 u32 mask;
67 const char *set;
68 const char *unset;
69};
70#define BIT(m, s, u) { .mask = m, .set = s, .unset = u }
71
72static inline void
73decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
74{
75 printk("%s %08x: ", prefix, val);
76 while (num--) {
77 const char *str = val & bits->mask ? bits->set : bits->unset;
78 if (str)
79 printk("%s ", str);
80 bits++;
81 }
82}
83
84static const struct bits isr_bits[] = {
85 BIT(ISR_RWM, "RX", "TX"),
86 BIT(ISR_ACKNAK, "NAK", "ACK"),
87 BIT(ISR_UB, "Bsy", "Rdy"),
88 BIT(ISR_IBB, "BusBsy", "BusRdy"),
89 BIT(ISR_SSD, "SlaveStop", NULL),
90 BIT(ISR_ALD, "ALD", NULL),
91 BIT(ISR_ITE, "TxEmpty", NULL),
92 BIT(ISR_IRF, "RxFull", NULL),
93 BIT(ISR_GCAD, "GenCall", NULL),
94 BIT(ISR_SAD, "SlaveAddr", NULL),
95 BIT(ISR_BED, "BusErr", NULL),
96};
97
98static void decode_ISR(unsigned int val)
99{
100 decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
101 printk("\n");
102}
103
104static const struct bits icr_bits[] = {
105 BIT(ICR_START, "START", NULL),
106 BIT(ICR_STOP, "STOP", NULL),
107 BIT(ICR_ACKNAK, "ACKNAK", NULL),
108 BIT(ICR_TB, "TB", NULL),
109 BIT(ICR_MA, "MA", NULL),
110 BIT(ICR_SCLE, "SCLE", "scle"),
111 BIT(ICR_IUE, "IUE", "iue"),
112 BIT(ICR_GCD, "GCD", NULL),
113 BIT(ICR_ITEIE, "ITEIE", NULL),
114 BIT(ICR_IRFIE, "IRFIE", NULL),
115 BIT(ICR_BEIE, "BEIE", NULL),
116 BIT(ICR_SSDIE, "SSDIE", NULL),
117 BIT(ICR_ALDIE, "ALDIE", NULL),
118 BIT(ICR_SADIE, "SADIE", NULL),
119 BIT(ICR_UR, "UR", "ur"),
120};
121
122static void decode_ICR(unsigned int val)
123{
124 decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
125 printk("\n");
126}
127
128static unsigned int i2c_debug = DEBUG;
129
130static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
131{
132 dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno, ISR, ICR, IBMR);
133}
134
135#define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __FUNCTION__)
136#else
137#define i2c_debug 0
138
139#define show_state(i2c) do { } while (0)
140#define decode_ISR(val) do { } while (0)
141#define decode_ICR(val) do { } while (0)
142#endif
143
144#define eedbg(lvl, x...) do { if ((lvl) < 1) { printk(KERN_DEBUG "" x); } } while(0)
145
146static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
147
148static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
149{
150 unsigned int i;
151 printk("i2c: error: %s\n", why);
152 printk("i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n",
153 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
154 printk("i2c: ICR: %08x ISR: %08x\n"
155 "i2c: log: ", ICR, ISR);
156 for (i = 0; i < i2c->irqlogidx; i++)
157 printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
158 printk("\n");
159}
160
161static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
162{
163 return !(ICR & ICR_SCLE);
164}
165
166static void i2c_pxa_abort(struct pxa_i2c *i2c)
167{
168 unsigned long timeout = jiffies + HZ/4;
169
170 if (i2c_pxa_is_slavemode(i2c)) {
171 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
172 return;
173 }
174
175 while (time_before(jiffies, timeout) && (IBMR & 0x1) == 0) {
176 unsigned long icr = ICR;
177
178 icr &= ~ICR_START;
179 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
180
181 ICR = icr;
182
183 show_state(i2c);
184
185 msleep(1);
186 }
187
188 ICR &= ~(ICR_MA | ICR_START | ICR_STOP);
189}
190
191static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
192{
193 int timeout = DEF_TIMEOUT;
194
195 while (timeout-- && ISR & (ISR_IBB | ISR_UB)) {
196 if ((ISR & ISR_SAD) != 0)
197 timeout += 4;
198
199 msleep(2);
200 show_state(i2c);
201 }
202
203 if (timeout <= 0)
204 show_state(i2c);
205
206 return timeout <= 0 ? I2C_RETRY : 0;
207}
208
209static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
210{
211 unsigned long timeout = jiffies + HZ*4;
212
213 while (time_before(jiffies, timeout)) {
214 if (i2c_debug > 1)
215 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
216 __func__, (long)jiffies, ISR, ICR, IBMR);
217
218 if (ISR & ISR_SAD) {
219 if (i2c_debug > 0)
220 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
221 goto out;
222 }
223
224 /* wait for unit and bus being not busy, and we also do a
225 * quick check of the i2c lines themselves to ensure they've
226 * gone high...
227 */
228 if ((ISR & (ISR_UB | ISR_IBB)) == 0 && IBMR == 3) {
229 if (i2c_debug > 0)
230 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
231 return 1;
232 }
233
234 msleep(1);
235 }
236
237 if (i2c_debug > 0)
238 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
239 out:
240 return 0;
241}
242
243static int i2c_pxa_set_master(struct pxa_i2c *i2c)
244{
245 if (i2c_debug)
246 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
247
248 if ((ISR & (ISR_UB | ISR_IBB)) != 0) {
249 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
250 if (!i2c_pxa_wait_master(i2c)) {
251 dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
252 return I2C_RETRY;
253 }
254 }
255
256 ICR |= ICR_SCLE;
257 return 0;
258}
259
260#ifdef CONFIG_I2C_PXA_SLAVE
261static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
262{
263 unsigned long timeout = jiffies + HZ*1;
264
265 /* wait for stop */
266
267 show_state(i2c);
268
269 while (time_before(jiffies, timeout)) {
270 if (i2c_debug > 1)
271 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
272 __func__, (long)jiffies, ISR, ICR, IBMR);
273
274 if ((ISR & (ISR_UB|ISR_IBB|ISR_SAD)) == ISR_SAD ||
275 (ICR & ICR_SCLE) == 0) {
276 if (i2c_debug > 1)
277 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
278 return 1;
279 }
280
281 msleep(1);
282 }
283
284 if (i2c_debug > 0)
285 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
286 return 0;
287}
288
289/*
290 * clear the hold on the bus, and take of anything else
291 * that has been configured
292 */
293static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
294{
295 show_state(i2c);
296
297 if (errcode < 0) {
298 udelay(100); /* simple delay */
299 } else {
300 /* we need to wait for the stop condition to end */
301
302 /* if we where in stop, then clear... */
303 if (ICR & ICR_STOP) {
304 udelay(100);
305 ICR &= ~ICR_STOP;
306 }
307
308 if (!i2c_pxa_wait_slave(i2c)) {
309 dev_err(&i2c->adap.dev, "%s: wait timedout\n",
310 __func__);
311 return;
312 }
313 }
314
315 ICR &= ~(ICR_STOP|ICR_ACKNAK|ICR_MA);
316 ICR &= ~ICR_SCLE;
317
318 if (i2c_debug) {
319 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", ICR, ISR);
320 decode_ICR(ICR);
321 }
322}
323#else
324#define i2c_pxa_set_slave(i2c, err) do { } while (0)
325#endif
326
327static void i2c_pxa_reset(struct pxa_i2c *i2c)
328{
329 pr_debug("Resetting I2C Controller Unit\n");
330
331 /* abort any transfer currently under way */
332 i2c_pxa_abort(i2c);
333
334 /* reset according to 9.8 */
335 ICR = ICR_UR;
336 ISR = I2C_ISR_INIT;
337 ICR &= ~ICR_UR;
338
339 ISAR = i2c->slave_addr;
340
341 /* set control register values */
342 ICR = I2C_ICR_INIT;
343
344#ifdef CONFIG_I2C_PXA_SLAVE
345 dev_info(&i2c->adap.dev, "Enabling slave mode\n");
346 ICR |= ICR_SADIE | ICR_ALDIE | ICR_SSDIE;
347#endif
348
349 i2c_pxa_set_slave(i2c, 0);
350
351 /* enable unit */
352 ICR |= ICR_IUE;
353 udelay(100);
354}
355
356
357#ifdef CONFIG_I2C_PXA_SLAVE
358/*
359 * I2C EEPROM emulation.
360 */
361static struct i2c_eeprom_emu eeprom = {
362 .size = I2C_EEPROM_EMU_SIZE,
363 .watch = LIST_HEAD_INIT(eeprom.watch),
364};
365
366struct i2c_eeprom_emu *i2c_pxa_get_eeprom(void)
367{
368 return &eeprom;
369}
370
371int i2c_eeprom_emu_addwatcher(struct i2c_eeprom_emu *emu, void *data,
372 unsigned int addr, unsigned int size,
373 struct i2c_eeprom_emu_watcher *watcher)
374{
375 struct i2c_eeprom_emu_watch *watch;
376 unsigned long flags;
377
378 if (addr + size > emu->size)
379 return -EINVAL;
380
381 watch = kmalloc(sizeof(struct i2c_eeprom_emu_watch), GFP_KERNEL);
382 if (watch) {
383 watch->start = addr;
384 watch->end = addr + size - 1;
385 watch->ops = watcher;
386 watch->data = data;
387
388 local_irq_save(flags);
389 list_add(&watch->node, &emu->watch);
390 local_irq_restore(flags);
391 }
392
393 return watch ? 0 : -ENOMEM;
394}
395
396void i2c_eeprom_emu_delwatcher(struct i2c_eeprom_emu *emu, void *data,
397 struct i2c_eeprom_emu_watcher *watcher)
398{
399 struct i2c_eeprom_emu_watch *watch, *n;
400 unsigned long flags;
401
402 list_for_each_entry_safe(watch, n, &emu->watch, node) {
403 if (watch->ops == watcher && watch->data == data) {
404 local_irq_save(flags);
405 list_del(&watch->node);
406 local_irq_restore(flags);
407 kfree(watch);
408 }
409 }
410}
411
412static void i2c_eeprom_emu_event(void *ptr, i2c_slave_event_t event)
413{
414 struct i2c_eeprom_emu *emu = ptr;
415
416 eedbg(3, "i2c_eeprom_emu_event: %d\n", event);
417
418 switch (event) {
419 case I2C_SLAVE_EVENT_START_WRITE:
420 emu->seen_start = 1;
421 eedbg(2, "i2c_eeprom: write initiated\n");
422 break;
423
424 case I2C_SLAVE_EVENT_START_READ:
425 emu->seen_start = 0;
426 eedbg(2, "i2c_eeprom: read initiated\n");
427 break;
428
429 case I2C_SLAVE_EVENT_STOP:
430 emu->seen_start = 0;
431 eedbg(2, "i2c_eeprom: received stop\n");
432 break;
433
434 default:
435 eedbg(0, "i2c_eeprom: unhandled event\n");
436 break;
437 }
438}
439
440static int i2c_eeprom_emu_read(void *ptr)
441{
442 struct i2c_eeprom_emu *emu = ptr;
443 int ret;
444
445 ret = emu->bytes[emu->ptr];
446 emu->ptr = (emu->ptr + 1) % emu->size;
447
448 return ret;
449}
450
451static void i2c_eeprom_emu_write(void *ptr, unsigned int val)
452{
453 struct i2c_eeprom_emu *emu = ptr;
454 struct i2c_eeprom_emu_watch *watch;
455
456 if (emu->seen_start != 0) {
457 eedbg(2, "i2c_eeprom_emu_write: setting ptr %02x\n", val);
458 emu->ptr = val;
459 emu->seen_start = 0;
460 return;
461 }
462
463 emu->bytes[emu->ptr] = val;
464
465 eedbg(1, "i2c_eeprom_emu_write: ptr=0x%02x, val=0x%02x\n",
466 emu->ptr, val);
467
468 list_for_each_entry(watch, &emu->watch, node) {
469 if (!watch->ops || !watch->ops->write)
470 continue;
471 if (watch->start <= emu->ptr && watch->end >= emu->ptr)
472 watch->ops->write(watch->data, emu->ptr, val);
473 }
474
475 emu->ptr = (emu->ptr + 1) % emu->size;
476}
477
478struct i2c_slave_client eeprom_client = {
479 .data = &eeprom,
480 .event = i2c_eeprom_emu_event,
481 .read = i2c_eeprom_emu_read,
482 .write = i2c_eeprom_emu_write
483};
484
485/*
486 * PXA I2C Slave mode
487 */
488
489static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
490{
491 if (isr & ISR_BED) {
492 /* what should we do here? */
493 } else {
494 int ret = i2c->slave->read(i2c->slave->data);
495
496 IDBR = ret;
497 ICR |= ICR_TB; /* allow next byte */
498 }
499}
500
501static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
502{
503 unsigned int byte = IDBR;
504
505 if (i2c->slave != NULL)
506 i2c->slave->write(i2c->slave->data, byte);
507
508 ICR |= ICR_TB;
509}
510
511static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
512{
513 int timeout;
514
515 if (i2c_debug > 0)
516 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
517 (isr & ISR_RWM) ? 'r' : 't');
518
519 if (i2c->slave != NULL)
520 i2c->slave->event(i2c->slave->data,
521 (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE);
522
523 /*
524 * slave could interrupt in the middle of us generating a
525 * start condition... if this happens, we'd better back off
526 * and stop holding the poor thing up
527 */
528 ICR &= ~(ICR_START|ICR_STOP);
529 ICR |= ICR_TB;
530
531 timeout = 0x10000;
532
533 while (1) {
534 if ((IBMR & 2) == 2)
535 break;
536
537 timeout--;
538
539 if (timeout <= 0) {
540 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
541 break;
542 }
543 }
544
545 ICR &= ~ICR_SCLE;
546}
547
548static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
549{
550 if (i2c_debug > 2)
551 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
552
553 if (i2c->slave != NULL)
554 i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP);
555
556 if (i2c_debug > 2)
557 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
558
559 /*
560 * If we have a master-mode message waiting,
561 * kick it off now that the slave has completed.
562 */
563 if (i2c->msg)
564 i2c_pxa_master_complete(i2c, I2C_RETRY);
565}
566#else
567static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
568{
569 if (isr & ISR_BED) {
570 /* what should we do here? */
571 } else {
572 IDBR = 0;
573 ICR |= ICR_TB;
574 }
575}
576
577static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
578{
579 ICR |= ICR_TB | ICR_ACKNAK;
580}
581
582static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
583{
584 int timeout;
585
586 /*
587 * slave could interrupt in the middle of us generating a
588 * start condition... if this happens, we'd better back off
589 * and stop holding the poor thing up
590 */
591 ICR &= ~(ICR_START|ICR_STOP);
592 ICR |= ICR_TB | ICR_ACKNAK;
593
594 timeout = 0x10000;
595
596 while (1) {
597 if ((IBMR & 2) == 2)
598 break;
599
600 timeout--;
601
602 if (timeout <= 0) {
603 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
604 break;
605 }
606 }
607
608 ICR &= ~ICR_SCLE;
609}
610
611static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
612{
613 if (i2c->msg)
614 i2c_pxa_master_complete(i2c, I2C_RETRY);
615}
616#endif
617
618/*
619 * PXA I2C Master mode
620 */
621
622static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg)
623{
624 unsigned int addr = (msg->addr & 0x7f) << 1;
625
626 if (msg->flags & I2C_M_RD)
627 addr |= 1;
628
629 return addr;
630}
631
632static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
633{
634 u32 icr;
635
636 /*
637 * Step 1: target slave address into IDBR
638 */
639 IDBR = i2c_pxa_addr_byte(i2c->msg);
640
641 /*
642 * Step 2: initiate the write.
643 */
644 icr = ICR & ~(ICR_STOP | ICR_ALDIE);
645 ICR = icr | ICR_START | ICR_TB;
646}
647
648/*
649 * We are protected by the adapter bus semaphore.
650 */
651static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
652{
653 long timeout;
654 int ret;
655
656 /*
657 * Wait for the bus to become free.
658 */
659 ret = i2c_pxa_wait_bus_not_busy(i2c);
660 if (ret) {
661 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
662 goto out;
663 }
664
665 /*
666 * Set master mode.
667 */
668 ret = i2c_pxa_set_master(i2c);
669 if (ret) {
670 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
671 goto out;
672 }
673
674 spin_lock_irq(&i2c->lock);
675
676 i2c->msg = msg;
677 i2c->msg_num = num;
678 i2c->msg_idx = 0;
679 i2c->msg_ptr = 0;
680 i2c->irqlogidx = 0;
681
682 i2c_pxa_start_message(i2c);
683
684 spin_unlock_irq(&i2c->lock);
685
686 /*
687 * The rest of the processing occurs in the interrupt handler.
688 */
689 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
690
691 /*
692 * We place the return code in i2c->msg_idx.
693 */
694 ret = i2c->msg_idx;
695
696 if (timeout == 0)
697 i2c_pxa_scream_blue_murder(i2c, "timeout");
698
699 out:
700 return ret;
701}
702
703/*
704 * i2c_pxa_master_complete - complete the message and wake up.
705 */
706static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
707{
708 i2c->msg_ptr = 0;
709 i2c->msg = NULL;
710 i2c->msg_idx ++;
711 i2c->msg_num = 0;
712 if (ret)
713 i2c->msg_idx = ret;
714 wake_up(&i2c->wait);
715}
716
717static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
718{
719 u32 icr = ICR & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
720
721 again:
722 /*
723 * If ISR_ALD is set, we lost arbitration.
724 */
725 if (isr & ISR_ALD) {
726 /*
727 * Do we need to do anything here? The PXA docs
728 * are vague about what happens.
729 */
730 i2c_pxa_scream_blue_murder(i2c, "ALD set");
731
732 /*
733 * We ignore this error. We seem to see spurious ALDs
734 * for seemingly no reason. If we handle them as I think
735 * they should, we end up causing an I2C error, which
736 * is painful for some systems.
737 */
738 return; /* ignore */
739 }
740
741 if (isr & ISR_BED) {
742 int ret = BUS_ERROR;
743
744 /*
745 * I2C bus error - either the device NAK'd us, or
746 * something more serious happened. If we were NAK'd
747 * on the initial address phase, we can retry.
748 */
749 if (isr & ISR_ACKNAK) {
750 if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
751 ret = I2C_RETRY;
752 else
753 ret = XFER_NAKED;
754 }
755 i2c_pxa_master_complete(i2c, ret);
756 } else if (isr & ISR_RWM) {
757 /*
758 * Read mode. We have just sent the address byte, and
759 * now we must initiate the transfer.
760 */
761 if (i2c->msg_ptr == i2c->msg->len - 1 &&
762 i2c->msg_idx == i2c->msg_num - 1)
763 icr |= ICR_STOP | ICR_ACKNAK;
764
765 icr |= ICR_ALDIE | ICR_TB;
766 } else if (i2c->msg_ptr < i2c->msg->len) {
767 /*
768 * Write mode. Write the next data byte.
769 */
770 IDBR = i2c->msg->buf[i2c->msg_ptr++];
771
772 icr |= ICR_ALDIE | ICR_TB;
773
774 /*
775 * If this is the last byte of the last message, send
776 * a STOP.
777 */
778 if (i2c->msg_ptr == i2c->msg->len &&
779 i2c->msg_idx == i2c->msg_num - 1)
780 icr |= ICR_STOP;
781 } else if (i2c->msg_idx < i2c->msg_num - 1) {
782 /*
783 * Next segment of the message.
784 */
785 i2c->msg_ptr = 0;
786 i2c->msg_idx ++;
787 i2c->msg++;
788
789 /*
790 * If we aren't doing a repeated start and address,
791 * go back and try to send the next byte. Note that
792 * we do not support switching the R/W direction here.
793 */
794 if (i2c->msg->flags & I2C_M_NOSTART)
795 goto again;
796
797 /*
798 * Write the next address.
799 */
800 IDBR = i2c_pxa_addr_byte(i2c->msg);
801
802 /*
803 * And trigger a repeated start, and send the byte.
804 */
805 icr &= ~ICR_ALDIE;
806 icr |= ICR_START | ICR_TB;
807 } else {
808 if (i2c->msg->len == 0) {
809 /*
810 * Device probes have a message length of zero
811 * and need the bus to be reset before it can
812 * be used again.
813 */
814 i2c_pxa_reset(i2c);
815 }
816 i2c_pxa_master_complete(i2c, 0);
817 }
818
819 i2c->icrlog[i2c->irqlogidx-1] = icr;
820
821 ICR = icr;
822 show_state(i2c);
823}
824
825static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
826{
827 u32 icr = ICR & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
828
829 /*
830 * Read the byte.
831 */
832 i2c->msg->buf[i2c->msg_ptr++] = IDBR;
833
834 if (i2c->msg_ptr < i2c->msg->len) {
835 /*
836 * If this is the last byte of the last
837 * message, send a STOP.
838 */
839 if (i2c->msg_ptr == i2c->msg->len - 1)
840 icr |= ICR_STOP | ICR_ACKNAK;
841
842 icr |= ICR_ALDIE | ICR_TB;
843 } else {
844 i2c_pxa_master_complete(i2c, 0);
845 }
846
847 i2c->icrlog[i2c->irqlogidx-1] = icr;
848
849 ICR = icr;
850}
851
852static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id, struct pt_regs *regs)
853{
854 struct pxa_i2c *i2c = dev_id;
855 u32 isr = ISR;
856
857 if (i2c_debug > 2 && 0) {
858 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
859 __func__, isr, ICR, IBMR);
860 decode_ISR(isr);
861 }
862
863 if (i2c->irqlogidx < sizeof(i2c->isrlog)/sizeof(u32))
864 i2c->isrlog[i2c->irqlogidx++] = isr;
865
866 show_state(i2c);
867
868 /*
869 * Always clear all pending IRQs.
870 */
871 ISR = isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED);
872
873 if (isr & ISR_SAD)
874 i2c_pxa_slave_start(i2c, isr);
875 if (isr & ISR_SSD)
876 i2c_pxa_slave_stop(i2c);
877
878 if (i2c_pxa_is_slavemode(i2c)) {
879 if (isr & ISR_ITE)
880 i2c_pxa_slave_txempty(i2c, isr);
881 if (isr & ISR_IRF)
882 i2c_pxa_slave_rxfull(i2c, isr);
883 } else if (i2c->msg) {
884 if (isr & ISR_ITE)
885 i2c_pxa_irq_txempty(i2c, isr);
886 if (isr & ISR_IRF)
887 i2c_pxa_irq_rxfull(i2c, isr);
888 } else {
889 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
890 }
891
892 return IRQ_HANDLED;
893}
894
895
896static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
897{
898 struct pxa_i2c *i2c = adap->algo_data;
899 int ret, i;
900
901 for (i = adap->retries; i >= 0; i--) {
902 ret = i2c_pxa_do_xfer(i2c, msgs, num);
903 if (ret != I2C_RETRY)
904 goto out;
905
906 if (i2c_debug)
907 dev_dbg(&adap->dev, "Retrying transmission\n");
908 udelay(100);
909 }
910 i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
911 ret = -EREMOTEIO;
912 out:
913 i2c_pxa_set_slave(i2c, ret);
914 return ret;
915}
916
917static struct i2c_algorithm i2c_pxa_algorithm = {
918 .name = "PXA-I2C-Algorithm",
919 .id = I2C_ALGO_PXA,
920 .master_xfer = i2c_pxa_xfer,
921};
922
923static struct pxa_i2c i2c_pxa = {
924 .lock = SPIN_LOCK_UNLOCKED,
925 .wait = __WAIT_QUEUE_HEAD_INITIALIZER(i2c_pxa.wait),
926 .adap = {
927 .name = "pxa2xx-i2c",
928 .id = I2C_ALGO_PXA,
929 .algo = &i2c_pxa_algorithm,
930 .retries = 5,
931 },
932};
933
934static int i2c_pxa_probe(struct device *dev)
935{
936 struct pxa_i2c *i2c = &i2c_pxa;
937 struct i2c_pxa_platform_data *plat = dev->platform_data;
938 int ret;
939
940#ifdef CONFIG_PXA27x
941 pxa_gpio_mode(GPIO117_I2CSCL_MD);
942 pxa_gpio_mode(GPIO118_I2CSDA_MD);
943 udelay(100);
944#endif
945
946 i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
947
948#ifdef CONFIG_I2C_PXA_SLAVE
949 i2c->slave = &eeprom_client;
950 if (plat) {
951 i2c->slave_addr = plat->slave_addr;
952 if (plat->slave)
953 i2c->slave = plat->slave;
954 }
955#endif
956
957 pxa_set_cken(CKEN14_I2C, 1);
958 ret = request_irq(IRQ_I2C, i2c_pxa_handler, SA_INTERRUPT,
959 "pxa2xx-i2c", i2c);
960 if (ret)
961 goto out;
962
963 i2c_pxa_reset(i2c);
964
965 i2c->adap.algo_data = i2c;
966 i2c->adap.dev.parent = dev;
967
968 ret = i2c_add_adapter(&i2c->adap);
969 if (ret < 0) {
970 printk(KERN_INFO "I2C: Failed to add bus\n");
971 goto err_irq;
972 }
973
974 dev_set_drvdata(dev, i2c);
975
976#ifdef CONFIG_I2C_PXA_SLAVE
977 printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n",
978 i2c->adap.dev.bus_id, i2c->slave_addr);
979#else
980 printk(KERN_INFO "I2C: %s: PXA I2C adapter\n",
981 i2c->adap.dev.bus_id);
982#endif
983 return 0;
984
985 err_irq:
986 free_irq(IRQ_I2C, i2c);
987 out:
988 return ret;
989}
990
991static int i2c_pxa_remove(struct device *dev)
992{
993 struct pxa_i2c *i2c = dev_get_drvdata(dev);
994
995 dev_set_drvdata(dev, NULL);
996
997 i2c_del_adapter(&i2c->adap);
998 free_irq(IRQ_I2C, i2c);
999 pxa_set_cken(CKEN14_I2C, 0);
1000
1001 return 0;
1002}
1003
1004static struct device_driver i2c_pxa_driver = {
1005 .name = "pxa2xx-i2c",
1006 .bus = &platform_bus_type,
1007 .probe = i2c_pxa_probe,
1008 .remove = i2c_pxa_remove,
1009};
1010
1011static int __init i2c_adap_pxa_init(void)
1012{
1013 return driver_register(&i2c_pxa_driver);
1014}
1015
1016static void i2c_adap_pxa_exit(void)
1017{
1018 return driver_unregister(&i2c_pxa_driver);
1019}
1020
1021module_init(i2c_adap_pxa_init);
1022module_exit(i2c_adap_pxa_exit);