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authorRussell King <rmk+kernel@arm.linux.org.uk>2010-03-08 15:21:04 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-03-08 15:21:04 -0500
commit988addf82e4c03739375279de73929580a2d4a6a (patch)
tree989ae1cd4e264bbad80c65f04480486246e7b9f3 /drivers/i2c
parent004c1c7096659d352b83047a7593e91d8a30e3c5 (diff)
parent25cf84cf377c0aae5dbcf937ea89bc7893db5176 (diff)
Merge branch 'origin' into devel-stable
Conflicts: arch/arm/mach-mx2/devices.c arch/arm/mach-mx2/devices.h sound/soc/pxa/pxa-ssp.c
Diffstat (limited to 'drivers/i2c')
-rw-r--r--drivers/i2c/Kconfig10
-rw-r--r--drivers/i2c/Makefile1
-rw-r--r--drivers/i2c/algos/i2c-algo-pca.c2
-rw-r--r--drivers/i2c/busses/Kconfig43
-rw-r--r--drivers/i2c/busses/Makefile3
-rw-r--r--drivers/i2c/busses/i2c-ali1535.c2
-rw-r--r--drivers/i2c/busses/i2c-ali1563.c2
-rw-r--r--drivers/i2c/busses/i2c-ali15x3.c2
-rw-r--r--drivers/i2c/busses/i2c-amd756.c2
-rw-r--r--drivers/i2c/busses/i2c-amd8111.c2
-rw-r--r--drivers/i2c/busses/i2c-designware.c4
-rw-r--r--drivers/i2c/busses/i2c-hydra.c2
-rw-r--r--drivers/i2c/busses/i2c-i801.c7
-rw-r--r--drivers/i2c/busses/i2c-imx.c1
-rw-r--r--drivers/i2c/busses/i2c-isch.c68
-rw-r--r--drivers/i2c/busses/i2c-mpc.c194
-rw-r--r--drivers/i2c/busses/i2c-nforce2.c2
-rw-r--r--drivers/i2c/busses/i2c-nomadik.c959
-rw-r--r--drivers/i2c/busses/i2c-octeon.c651
-rw-r--r--drivers/i2c/busses/i2c-omap.c44
-rw-r--r--drivers/i2c/busses/i2c-parport-light.c48
-rw-r--r--drivers/i2c/busses/i2c-parport.c43
-rw-r--r--drivers/i2c/busses/i2c-parport.h4
-rw-r--r--drivers/i2c/busses/i2c-pasemi.c2
-rw-r--r--drivers/i2c/busses/i2c-piix4.c2
-rw-r--r--drivers/i2c/busses/i2c-pnx.c296
-rw-r--r--drivers/i2c/busses/i2c-sis5595.c2
-rw-r--r--drivers/i2c/busses/i2c-sis630.c2
-rw-r--r--drivers/i2c/busses/i2c-sis96x.c2
-rw-r--r--drivers/i2c/busses/i2c-tiny-usb.c10
-rw-r--r--drivers/i2c/busses/i2c-via.c2
-rw-r--r--drivers/i2c/busses/i2c-viapro.c2
-rw-r--r--drivers/i2c/busses/i2c-xiic.c824
-rw-r--r--drivers/i2c/i2c-core.c54
-rw-r--r--drivers/i2c/i2c-smbus.c263
35 files changed, 3242 insertions, 315 deletions
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 8d8a00e5a30e..02ce9cff5fcf 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -61,6 +61,16 @@ config I2C_HELPER_AUTO
61 61
62 In doubt, say Y. 62 In doubt, say Y.
63 63
64config I2C_SMBUS
65 tristate "SMBus-specific protocols" if !I2C_HELPER_AUTO
66 help
67 Say Y here if you want support for SMBus extensions to the I2C
68 specification. At the moment, the only supported extension is
69 the SMBus alert protocol.
70
71 This support is also available as a module. If so, the module
72 will be called i2c-smbus.
73
64source drivers/i2c/algos/Kconfig 74source drivers/i2c/algos/Kconfig
65source drivers/i2c/busses/Kconfig 75source drivers/i2c/busses/Kconfig
66source drivers/i2c/chips/Kconfig 76source drivers/i2c/chips/Kconfig
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index ba26e6cbe74e..acd0250c16a0 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -4,6 +4,7 @@
4 4
5obj-$(CONFIG_I2C_BOARDINFO) += i2c-boardinfo.o 5obj-$(CONFIG_I2C_BOARDINFO) += i2c-boardinfo.o
6obj-$(CONFIG_I2C) += i2c-core.o 6obj-$(CONFIG_I2C) += i2c-core.o
7obj-$(CONFIG_I2C_SMBUS) += i2c-smbus.o
7obj-$(CONFIG_I2C_CHARDEV) += i2c-dev.o 8obj-$(CONFIG_I2C_CHARDEV) += i2c-dev.o
8obj-y += busses/ chips/ algos/ 9obj-y += busses/ chips/ algos/
9 10
diff --git a/drivers/i2c/algos/i2c-algo-pca.c b/drivers/i2c/algos/i2c-algo-pca.c
index 78d42aae0089..dcdaf8e675bf 100644
--- a/drivers/i2c/algos/i2c-algo-pca.c
+++ b/drivers/i2c/algos/i2c-algo-pca.c
@@ -453,8 +453,6 @@ static int pca_init(struct i2c_adapter *adap)
453 */ 453 */
454 int raise_fall_time; 454 int raise_fall_time;
455 455
456 struct i2c_algo_pca_data *pca_data = adap->algo_data;
457
458 /* Ignore the reset function from the module, 456 /* Ignore the reset function from the module,
459 * we can use the parallel bus reset 457 * we can use the parallel bus reset
460 */ 458 */
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 5f318ce29770..9c6170cd9aac 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -77,7 +77,7 @@ config I2C_AMD8111
77 will be called i2c-amd8111. 77 will be called i2c-amd8111.
78 78
79config I2C_I801 79config I2C_I801
80 tristate "Intel 82801 (ICH)" 80 tristate "Intel 82801 (ICH/PCH)"
81 depends on PCI 81 depends on PCI
82 help 82 help
83 If you say yes to this option, support will be included for the Intel 83 If you say yes to this option, support will be included for the Intel
@@ -97,7 +97,8 @@ config I2C_I801
97 ICH9 97 ICH9
98 Tolapai 98 Tolapai
99 ICH10 99 ICH10
100 PCH 100 3400/5 Series (PCH)
101 Cougar Point (PCH)
101 102
102 This driver can also be built as a module. If so, the module 103 This driver can also be built as a module. If so, the module
103 will be called i2c-i801. 104 will be called i2c-i801.
@@ -105,6 +106,8 @@ config I2C_I801
105config I2C_ISCH 106config I2C_ISCH
106 tristate "Intel SCH SMBus 1.0" 107 tristate "Intel SCH SMBus 1.0"
107 depends on PCI 108 depends on PCI
109 select MFD_CORE
110 select LPC_SCH
108 help 111 help
109 Say Y here if you want to use SMBus controller on the Intel SCH 112 Say Y here if you want to use SMBus controller on the Intel SCH
110 based systems. 113 based systems.
@@ -418,13 +421,12 @@ config I2C_IXP2000
418 instead. 421 instead.
419 422
420config I2C_MPC 423config I2C_MPC
421 tristate "MPC107/824x/85xx/52xx/86xx" 424 tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx"
422 depends on PPC32 425 depends on PPC32
423 help 426 help
424 If you say yes to this option, support will be included for the 427 If you say yes to this option, support will be included for the
425 built-in I2C interface on the MPC107/Tsi107/MPC8240/MPC8245 and 428 built-in I2C interface on the MPC107, Tsi107, MPC512x, MPC52xx,
426 MPC85xx/MPC8641 family processors. The driver may also work on 52xx 429 MPC8240, MPC8245, MPC83xx, MPC85xx and MPC8641 family processors.
427 family processors, though interrupts are known not to work.
428 430
429 This driver can also be built as a module. If so, the module 431 This driver can also be built as a module. If so, the module
430 will be called i2c-mpc. 432 will be called i2c-mpc.
@@ -439,6 +441,13 @@ config I2C_MV64XXX
439 This driver can also be built as a module. If so, the module 441 This driver can also be built as a module. If so, the module
440 will be called i2c-mv64xxx. 442 will be called i2c-mv64xxx.
441 443
444config I2C_NOMADIK
445 tristate "ST-Ericsson Nomadik/Ux500 I2C Controller"
446 depends on PLAT_NOMADIK
447 help
448 If you say yes to this option, support will be included for the
449 I2C interface from ST-Ericsson's Nomadik and Ux500 architectures.
450
442config I2C_OCORES 451config I2C_OCORES
443 tristate "OpenCores I2C Controller" 452 tristate "OpenCores I2C Controller"
444 depends on EXPERIMENTAL 453 depends on EXPERIMENTAL
@@ -564,12 +573,33 @@ config I2C_VERSATILE
564 This driver can also be built as a module. If so, the module 573 This driver can also be built as a module. If so, the module
565 will be called i2c-versatile. 574 will be called i2c-versatile.
566 575
576config I2C_OCTEON
577 tristate "Cavium OCTEON I2C bus support"
578 depends on CPU_CAVIUM_OCTEON
579 help
580 Say yes if you want to support the I2C serial bus on Cavium
581 OCTEON SOC.
582
583 This driver can also be built as a module. If so, the module
584 will be called i2c-octeon.
585
586config I2C_XILINX
587 tristate "Xilinx I2C Controller"
588 depends on EXPERIMENTAL && HAS_IOMEM
589 help
590 If you say yes to this option, support will be included for the
591 Xilinx I2C controller.
592
593 This driver can also be built as a module. If so, the module
594 will be called xilinx_i2c.
595
567comment "External I2C/SMBus adapter drivers" 596comment "External I2C/SMBus adapter drivers"
568 597
569config I2C_PARPORT 598config I2C_PARPORT
570 tristate "Parallel port adapter" 599 tristate "Parallel port adapter"
571 depends on PARPORT 600 depends on PARPORT
572 select I2C_ALGOBIT 601 select I2C_ALGOBIT
602 select I2C_SMBUS
573 help 603 help
574 This supports parallel port I2C adapters such as the ones made by 604 This supports parallel port I2C adapters such as the ones made by
575 Philips or Velleman, Analog Devices evaluation boards, and more. 605 Philips or Velleman, Analog Devices evaluation boards, and more.
@@ -593,6 +623,7 @@ config I2C_PARPORT
593config I2C_PARPORT_LIGHT 623config I2C_PARPORT_LIGHT
594 tristate "Parallel port adapter (light)" 624 tristate "Parallel port adapter (light)"
595 select I2C_ALGOBIT 625 select I2C_ALGOBIT
626 select I2C_SMBUS
596 help 627 help
597 This supports parallel port I2C adapters such as the ones made by 628 This supports parallel port I2C adapters such as the ones made by
598 Philips or Velleman, Analog Devices evaluation boards, and more. 629 Philips or Velleman, Analog Devices evaluation boards, and more.
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 302c551977bb..097236f631e8 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o
42obj-$(CONFIG_I2C_IXP2000) += i2c-ixp2000.o 42obj-$(CONFIG_I2C_IXP2000) += i2c-ixp2000.o
43obj-$(CONFIG_I2C_MPC) += i2c-mpc.o 43obj-$(CONFIG_I2C_MPC) += i2c-mpc.o
44obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o 44obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o
45obj-$(CONFIG_I2C_NOMADIK) += i2c-nomadik.o
45obj-$(CONFIG_I2C_OCORES) += i2c-ocores.o 46obj-$(CONFIG_I2C_OCORES) += i2c-ocores.o
46obj-$(CONFIG_I2C_OMAP) += i2c-omap.o 47obj-$(CONFIG_I2C_OMAP) += i2c-omap.o
47obj-$(CONFIG_I2C_PASEMI) += i2c-pasemi.o 48obj-$(CONFIG_I2C_PASEMI) += i2c-pasemi.o
@@ -54,6 +55,8 @@ obj-$(CONFIG_I2C_SH_MOBILE) += i2c-sh_mobile.o
54obj-$(CONFIG_I2C_SIMTEC) += i2c-simtec.o 55obj-$(CONFIG_I2C_SIMTEC) += i2c-simtec.o
55obj-$(CONFIG_I2C_STU300) += i2c-stu300.o 56obj-$(CONFIG_I2C_STU300) += i2c-stu300.o
56obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o 57obj-$(CONFIG_I2C_VERSATILE) += i2c-versatile.o
58obj-$(CONFIG_I2C_OCTEON) += i2c-octeon.o
59obj-$(CONFIG_I2C_XILINX) += i2c-xiic.o
57 60
58# External I2C/SMBus adapter drivers 61# External I2C/SMBus adapter drivers
59obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o 62obj-$(CONFIG_I2C_PARPORT) += i2c-parport.o
diff --git a/drivers/i2c/busses/i2c-ali1535.c b/drivers/i2c/busses/i2c-ali1535.c
index 8de7d7b87bb0..bd8f1e4d9e6c 100644
--- a/drivers/i2c/busses/i2c-ali1535.c
+++ b/drivers/i2c/busses/i2c-ali1535.c
@@ -480,7 +480,7 @@ static struct i2c_adapter ali1535_adapter = {
480 .algo = &smbus_algorithm, 480 .algo = &smbus_algorithm,
481}; 481};
482 482
483static struct pci_device_id ali1535_ids[] = { 483static const struct pci_device_id ali1535_ids[] = {
484 { PCI_DEVICE(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101) }, 484 { PCI_DEVICE(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101) },
485 { }, 485 { },
486}; 486};
diff --git a/drivers/i2c/busses/i2c-ali1563.c b/drivers/i2c/busses/i2c-ali1563.c
index 4687af40dd50..a409cfcf0629 100644
--- a/drivers/i2c/busses/i2c-ali1563.c
+++ b/drivers/i2c/busses/i2c-ali1563.c
@@ -417,7 +417,7 @@ static void __devexit ali1563_remove(struct pci_dev * dev)
417 ali1563_shutdown(dev); 417 ali1563_shutdown(dev);
418} 418}
419 419
420static struct pci_device_id __devinitdata ali1563_id_table[] = { 420static const struct pci_device_id ali1563_id_table[] __devinitconst = {
421 { PCI_DEVICE(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1563) }, 421 { PCI_DEVICE(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1563) },
422 {}, 422 {},
423}; 423};
diff --git a/drivers/i2c/busses/i2c-ali15x3.c b/drivers/i2c/busses/i2c-ali15x3.c
index e7e3205f1286..659f63f5e4af 100644
--- a/drivers/i2c/busses/i2c-ali15x3.c
+++ b/drivers/i2c/busses/i2c-ali15x3.c
@@ -477,7 +477,7 @@ static struct i2c_adapter ali15x3_adapter = {
477 .algo = &smbus_algorithm, 477 .algo = &smbus_algorithm,
478}; 478};
479 479
480static struct pci_device_id ali15x3_ids[] = { 480static const struct pci_device_id ali15x3_ids[] = {
481 { PCI_DEVICE(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101) }, 481 { PCI_DEVICE(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101) },
482 { 0, } 482 { 0, }
483}; 483};
diff --git a/drivers/i2c/busses/i2c-amd756.c b/drivers/i2c/busses/i2c-amd756.c
index 8f0b90ef8c76..c5a9fa488e7f 100644
--- a/drivers/i2c/busses/i2c-amd756.c
+++ b/drivers/i2c/busses/i2c-amd756.c
@@ -308,7 +308,7 @@ static const char* chipname[] = {
308 "nVidia nForce", "AMD8111", 308 "nVidia nForce", "AMD8111",
309}; 309};
310 310
311static struct pci_device_id amd756_ids[] = { 311static const struct pci_device_id amd756_ids[] = {
312 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_740B), 312 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_740B),
313 .driver_data = AMD756 }, 313 .driver_data = AMD756 },
314 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7413), 314 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7413),
diff --git a/drivers/i2c/busses/i2c-amd8111.c b/drivers/i2c/busses/i2c-amd8111.c
index 5b4ad86ca166..d0dc970d7370 100644
--- a/drivers/i2c/busses/i2c-amd8111.c
+++ b/drivers/i2c/busses/i2c-amd8111.c
@@ -351,7 +351,7 @@ static const struct i2c_algorithm smbus_algorithm = {
351}; 351};
352 352
353 353
354static struct pci_device_id amd8111_ids[] = { 354static const struct pci_device_id amd8111_ids[] = {
355 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS2) }, 355 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS2) },
356 { 0, } 356 { 0, }
357}; 357};
diff --git a/drivers/i2c/busses/i2c-designware.c b/drivers/i2c/busses/i2c-designware.c
index 9e18ef97f156..3e72b69aa7f8 100644
--- a/drivers/i2c/busses/i2c-designware.c
+++ b/drivers/i2c/busses/i2c-designware.c
@@ -497,13 +497,13 @@ static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
497 int i; 497 int i;
498 498
499 if (abort_source & DW_IC_TX_ABRT_NOACK) { 499 if (abort_source & DW_IC_TX_ABRT_NOACK) {
500 for_each_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) 500 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
501 dev_dbg(dev->dev, 501 dev_dbg(dev->dev,
502 "%s: %s\n", __func__, abort_sources[i]); 502 "%s: %s\n", __func__, abort_sources[i]);
503 return -EREMOTEIO; 503 return -EREMOTEIO;
504 } 504 }
505 505
506 for_each_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) 506 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
507 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]); 507 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
508 508
509 if (abort_source & DW_IC_TX_ARB_LOST) 509 if (abort_source & DW_IC_TX_ARB_LOST)
diff --git a/drivers/i2c/busses/i2c-hydra.c b/drivers/i2c/busses/i2c-hydra.c
index bec9b845dd16..c767295ad1fb 100644
--- a/drivers/i2c/busses/i2c-hydra.c
+++ b/drivers/i2c/busses/i2c-hydra.c
@@ -105,7 +105,7 @@ static struct i2c_adapter hydra_adap = {
105 .algo_data = &hydra_bit_data, 105 .algo_data = &hydra_bit_data,
106}; 106};
107 107
108static struct pci_device_id hydra_ids[] = { 108static const struct pci_device_id hydra_ids[] = {
109 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_HYDRA) }, 109 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_HYDRA) },
110 { 0, } 110 { 0, }
111}; 111};
diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
index df6ab553f975..9da5b05cdb52 100644
--- a/drivers/i2c/busses/i2c-i801.c
+++ b/drivers/i2c/busses/i2c-i801.c
@@ -41,7 +41,8 @@
41 Tolapai 0x5032 32 hard yes yes yes 41 Tolapai 0x5032 32 hard yes yes yes
42 ICH10 0x3a30 32 hard yes yes yes 42 ICH10 0x3a30 32 hard yes yes yes
43 ICH10 0x3a60 32 hard yes yes yes 43 ICH10 0x3a60 32 hard yes yes yes
44 PCH 0x3b30 32 hard yes yes yes 44 3400/5 Series (PCH) 0x3b30 32 hard yes yes yes
45 Cougar Point (PCH) 0x1c22 32 hard yes yes yes
45 46
46 Features supported by this driver: 47 Features supported by this driver:
47 Software PEC no 48 Software PEC no
@@ -561,7 +562,7 @@ static struct i2c_adapter i801_adapter = {
561 .algo = &smbus_algorithm, 562 .algo = &smbus_algorithm,
562}; 563};
563 564
564static struct pci_device_id i801_ids[] = { 565static const struct pci_device_id i801_ids[] = {
565 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, 566 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
566 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, 567 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
567 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, 568 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
@@ -578,6 +579,7 @@ static struct pci_device_id i801_ids[] = {
578 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, 579 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
579 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, 580 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
580 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PCH_SMBUS) }, 581 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PCH_SMBUS) },
582 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CPT_SMBUS) },
581 { 0, } 583 { 0, }
582}; 584};
583 585
@@ -707,6 +709,7 @@ static int __devinit i801_probe(struct pci_dev *dev, const struct pci_device_id
707 case PCI_DEVICE_ID_INTEL_ICH10_4: 709 case PCI_DEVICE_ID_INTEL_ICH10_4:
708 case PCI_DEVICE_ID_INTEL_ICH10_5: 710 case PCI_DEVICE_ID_INTEL_ICH10_5:
709 case PCI_DEVICE_ID_INTEL_PCH_SMBUS: 711 case PCI_DEVICE_ID_INTEL_PCH_SMBUS:
712 case PCI_DEVICE_ID_INTEL_CPT_SMBUS:
710 i801_features |= FEATURE_I2C_BLOCK_READ; 713 i801_features |= FEATURE_I2C_BLOCK_READ;
711 /* fall through */ 714 /* fall through */
712 case PCI_DEVICE_ID_INTEL_82801DB_3: 715 case PCI_DEVICE_ID_INTEL_82801DB_3:
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index 75bf820e7ccb..32375bddae7d 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -627,7 +627,6 @@ static int __exit i2c_imx_remove(struct platform_device *pdev)
627} 627}
628 628
629static struct platform_driver i2c_imx_driver = { 629static struct platform_driver i2c_imx_driver = {
630 .probe = i2c_imx_probe,
631 .remove = __exit_p(i2c_imx_remove), 630 .remove = __exit_p(i2c_imx_remove),
632 .driver = { 631 .driver = {
633 .name = DRIVER_NAME, 632 .name = DRIVER_NAME,
diff --git a/drivers/i2c/busses/i2c-isch.c b/drivers/i2c/busses/i2c-isch.c
index dba6eb053e2f..ddc258edb34f 100644
--- a/drivers/i2c/busses/i2c-isch.c
+++ b/drivers/i2c/busses/i2c-isch.c
@@ -27,7 +27,7 @@
27*/ 27*/
28 28
29#include <linux/module.h> 29#include <linux/module.h>
30#include <linux/pci.h> 30#include <linux/platform_device.h>
31#include <linux/kernel.h> 31#include <linux/kernel.h>
32#include <linux/delay.h> 32#include <linux/delay.h>
33#include <linux/stddef.h> 33#include <linux/stddef.h>
@@ -46,12 +46,6 @@
46#define SMBHSTDAT1 (7 + sch_smba) 46#define SMBHSTDAT1 (7 + sch_smba)
47#define SMBBLKDAT (0x20 + sch_smba) 47#define SMBBLKDAT (0x20 + sch_smba)
48 48
49/* count for request_region */
50#define SMBIOSIZE 64
51
52/* PCI Address Constants */
53#define SMBBA_SCH 0x40
54
55/* Other settings */ 49/* Other settings */
56#define MAX_TIMEOUT 500 50#define MAX_TIMEOUT 500
57 51
@@ -63,7 +57,6 @@
63#define SCH_BLOCK_DATA 0x05 57#define SCH_BLOCK_DATA 0x05
64 58
65static unsigned short sch_smba; 59static unsigned short sch_smba;
66static struct pci_driver sch_driver;
67static struct i2c_adapter sch_adapter; 60static struct i2c_adapter sch_adapter;
68 61
69/* 62/*
@@ -256,37 +249,23 @@ static struct i2c_adapter sch_adapter = {
256 .algo = &smbus_algorithm, 249 .algo = &smbus_algorithm,
257}; 250};
258 251
259static struct pci_device_id sch_ids[] = { 252static int __devinit smbus_sch_probe(struct platform_device *dev)
260 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_LPC) },
261 { 0, }
262};
263
264MODULE_DEVICE_TABLE(pci, sch_ids);
265
266static int __devinit sch_probe(struct pci_dev *dev,
267 const struct pci_device_id *id)
268{ 253{
254 struct resource *res;
269 int retval; 255 int retval;
270 unsigned int smba;
271 256
272 pci_read_config_dword(dev, SMBBA_SCH, &smba); 257 res = platform_get_resource(dev, IORESOURCE_IO, 0);
273 if (!(smba & (1 << 31))) { 258 if (!res)
274 dev_err(&dev->dev, "SMBus I/O space disabled!\n"); 259 return -EBUSY;
275 return -ENODEV;
276 }
277 260
278 sch_smba = (unsigned short)smba; 261 if (!request_region(res->start, resource_size(res), dev->name)) {
279 if (sch_smba == 0) {
280 dev_err(&dev->dev, "SMBus base address uninitialized!\n");
281 return -ENODEV;
282 }
283 if (acpi_check_region(sch_smba, SMBIOSIZE, sch_driver.name))
284 return -ENODEV;
285 if (!request_region(sch_smba, SMBIOSIZE, sch_driver.name)) {
286 dev_err(&dev->dev, "SMBus region 0x%x already in use!\n", 262 dev_err(&dev->dev, "SMBus region 0x%x already in use!\n",
287 sch_smba); 263 sch_smba);
288 return -EBUSY; 264 return -EBUSY;
289 } 265 }
266
267 sch_smba = res->start;
268
290 dev_dbg(&dev->dev, "SMBA = 0x%X\n", sch_smba); 269 dev_dbg(&dev->dev, "SMBA = 0x%X\n", sch_smba);
291 270
292 /* set up the sysfs linkage to our parent device */ 271 /* set up the sysfs linkage to our parent device */
@@ -298,37 +277,43 @@ static int __devinit sch_probe(struct pci_dev *dev,
298 retval = i2c_add_adapter(&sch_adapter); 277 retval = i2c_add_adapter(&sch_adapter);
299 if (retval) { 278 if (retval) {
300 dev_err(&dev->dev, "Couldn't register adapter!\n"); 279 dev_err(&dev->dev, "Couldn't register adapter!\n");
301 release_region(sch_smba, SMBIOSIZE); 280 release_region(res->start, resource_size(res));
302 sch_smba = 0; 281 sch_smba = 0;
303 } 282 }
304 283
305 return retval; 284 return retval;
306} 285}
307 286
308static void __devexit sch_remove(struct pci_dev *dev) 287static int __devexit smbus_sch_remove(struct platform_device *pdev)
309{ 288{
289 struct resource *res;
310 if (sch_smba) { 290 if (sch_smba) {
311 i2c_del_adapter(&sch_adapter); 291 i2c_del_adapter(&sch_adapter);
312 release_region(sch_smba, SMBIOSIZE); 292 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
293 release_region(res->start, resource_size(res));
313 sch_smba = 0; 294 sch_smba = 0;
314 } 295 }
296
297 return 0;
315} 298}
316 299
317static struct pci_driver sch_driver = { 300static struct platform_driver smbus_sch_driver = {
318 .name = "isch_smbus", 301 .driver = {
319 .id_table = sch_ids, 302 .name = "isch_smbus",
320 .probe = sch_probe, 303 .owner = THIS_MODULE,
321 .remove = __devexit_p(sch_remove), 304 },
305 .probe = smbus_sch_probe,
306 .remove = __devexit_p(smbus_sch_remove),
322}; 307};
323 308
324static int __init i2c_sch_init(void) 309static int __init i2c_sch_init(void)
325{ 310{
326 return pci_register_driver(&sch_driver); 311 return platform_driver_register(&smbus_sch_driver);
327} 312}
328 313
329static void __exit i2c_sch_exit(void) 314static void __exit i2c_sch_exit(void)
330{ 315{
331 pci_unregister_driver(&sch_driver); 316 platform_driver_unregister(&smbus_sch_driver);
332} 317}
333 318
334MODULE_AUTHOR("Jacob Pan <jacob.jun.pan@intel.com>"); 319MODULE_AUTHOR("Jacob Pan <jacob.jun.pan@intel.com>");
@@ -337,3 +322,4 @@ MODULE_LICENSE("GPL");
337 322
338module_init(i2c_sch_init); 323module_init(i2c_sch_init);
339module_exit(i2c_sch_exit); 324module_exit(i2c_sch_exit);
325MODULE_ALIAS("platform:isch_smbus");
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
index f627001108b8..78a15af32942 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -31,6 +31,9 @@
31 31
32#define DRV_NAME "mpc-i2c" 32#define DRV_NAME "mpc-i2c"
33 33
34#define MPC_I2C_CLOCK_LEGACY 0
35#define MPC_I2C_CLOCK_PRESERVE (~0U)
36
34#define MPC_I2C_FDR 0x04 37#define MPC_I2C_FDR 0x04
35#define MPC_I2C_CR 0x08 38#define MPC_I2C_CR 0x08
36#define MPC_I2C_SR 0x0c 39#define MPC_I2C_SR 0x0c
@@ -66,10 +69,9 @@ struct mpc_i2c_divider {
66 u16 fdr; /* including dfsrr */ 69 u16 fdr; /* including dfsrr */
67}; 70};
68 71
69struct mpc_i2c_match_data { 72struct mpc_i2c_data {
70 void (*setclock)(struct device_node *node, 73 void (*setup)(struct device_node *node, struct mpc_i2c *i2c,
71 struct mpc_i2c *i2c, 74 u32 clock, u32 prescaler);
72 u32 clock, u32 prescaler);
73 u32 prescaler; 75 u32 prescaler;
74}; 76};
75 77
@@ -164,8 +166,8 @@ static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
164 return 0; 166 return 0;
165} 167}
166 168
167#ifdef CONFIG_PPC_MPC52xx 169#if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
168static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = { 170static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] __devinitconst = {
169 {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23}, 171 {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
170 {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02}, 172 {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
171 {36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28}, 173 {36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28},
@@ -186,14 +188,15 @@ static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
186 {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f} 188 {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f}
187}; 189};
188 190
189int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescaler) 191static int __devinit mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock,
192 int prescaler)
190{ 193{
191 const struct mpc_i2c_divider *div = NULL; 194 const struct mpc_i2c_divider *div = NULL;
192 unsigned int pvr = mfspr(SPRN_PVR); 195 unsigned int pvr = mfspr(SPRN_PVR);
193 u32 divider; 196 u32 divider;
194 int i; 197 int i;
195 198
196 if (!clock) 199 if (clock == MPC_I2C_CLOCK_LEGACY)
197 return -EINVAL; 200 return -EINVAL;
198 201
199 /* Determine divider value */ 202 /* Determine divider value */
@@ -215,12 +218,18 @@ int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescaler)
215 return div ? (int)div->fdr : -EINVAL; 218 return div ? (int)div->fdr : -EINVAL;
216} 219}
217 220
218static void mpc_i2c_setclock_52xx(struct device_node *node, 221static void __devinit mpc_i2c_setup_52xx(struct device_node *node,
219 struct mpc_i2c *i2c, 222 struct mpc_i2c *i2c,
220 u32 clock, u32 prescaler) 223 u32 clock, u32 prescaler)
221{ 224{
222 int ret, fdr; 225 int ret, fdr;
223 226
227 if (clock == MPC_I2C_CLOCK_PRESERVE) {
228 dev_dbg(i2c->dev, "using fdr %d\n",
229 readb(i2c->base + MPC_I2C_FDR));
230 return;
231 }
232
224 ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler); 233 ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler);
225 fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */ 234 fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */
226 235
@@ -229,16 +238,52 @@ static void mpc_i2c_setclock_52xx(struct device_node *node,
229 if (ret >= 0) 238 if (ret >= 0)
230 dev_info(i2c->dev, "clock %d Hz (fdr=%d)\n", clock, fdr); 239 dev_info(i2c->dev, "clock %d Hz (fdr=%d)\n", clock, fdr);
231} 240}
232#else /* !CONFIG_PPC_MPC52xx */ 241#else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */
233static void mpc_i2c_setclock_52xx(struct device_node *node, 242static void __devinit mpc_i2c_setup_52xx(struct device_node *node,
234 struct mpc_i2c *i2c, 243 struct mpc_i2c *i2c,
235 u32 clock, u32 prescaler) 244 u32 clock, u32 prescaler)
245{
246}
247#endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */
248
249#ifdef CONFIG_PPC_MPC512x
250static void __devinit mpc_i2c_setup_512x(struct device_node *node,
251 struct mpc_i2c *i2c,
252 u32 clock, u32 prescaler)
253{
254 struct device_node *node_ctrl;
255 void __iomem *ctrl;
256 const u32 *pval;
257 u32 idx;
258
259 /* Enable I2C interrupts for mpc5121 */
260 node_ctrl = of_find_compatible_node(NULL, NULL,
261 "fsl,mpc5121-i2c-ctrl");
262 if (node_ctrl) {
263 ctrl = of_iomap(node_ctrl, 0);
264 if (ctrl) {
265 /* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */
266 pval = of_get_property(node, "reg", NULL);
267 idx = (*pval & 0xff) / 0x20;
268 setbits32(ctrl, 1 << (24 + idx * 2));
269 iounmap(ctrl);
270 }
271 of_node_put(node_ctrl);
272 }
273
274 /* The clock setup for the 52xx works also fine for the 512x */
275 mpc_i2c_setup_52xx(node, i2c, clock, prescaler);
276}
277#else /* CONFIG_PPC_MPC512x */
278static void __devinit mpc_i2c_setup_512x(struct device_node *node,
279 struct mpc_i2c *i2c,
280 u32 clock, u32 prescaler)
236{ 281{
237} 282}
238#endif /* CONFIG_PPC_MPC52xx*/ 283#endif /* CONFIG_PPC_MPC512x */
239 284
240#ifdef CONFIG_FSL_SOC 285#ifdef CONFIG_FSL_SOC
241static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = { 286static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] __devinitconst = {
242 {160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123}, 287 {160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123},
243 {288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102}, 288 {288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102},
244 {416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127}, 289 {416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127},
@@ -258,7 +303,7 @@ static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = {
258 {49152, 0x011e}, {61440, 0x011f} 303 {49152, 0x011e}, {61440, 0x011f}
259}; 304};
260 305
261u32 mpc_i2c_get_sec_cfg_8xxx(void) 306static u32 __devinit mpc_i2c_get_sec_cfg_8xxx(void)
262{ 307{
263 struct device_node *node = NULL; 308 struct device_node *node = NULL;
264 u32 __iomem *reg; 309 u32 __iomem *reg;
@@ -287,13 +332,14 @@ u32 mpc_i2c_get_sec_cfg_8xxx(void)
287 return val; 332 return val;
288} 333}
289 334
290int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock, u32 prescaler) 335static int __devinit mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
336 u32 prescaler)
291{ 337{
292 const struct mpc_i2c_divider *div = NULL; 338 const struct mpc_i2c_divider *div = NULL;
293 u32 divider; 339 u32 divider;
294 int i; 340 int i;
295 341
296 if (!clock) 342 if (clock == MPC_I2C_CLOCK_LEGACY)
297 return -EINVAL; 343 return -EINVAL;
298 344
299 /* Determine proper divider value */ 345 /* Determine proper divider value */
@@ -320,12 +366,19 @@ int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock, u32 prescaler)
320 return div ? (int)div->fdr : -EINVAL; 366 return div ? (int)div->fdr : -EINVAL;
321} 367}
322 368
323static void mpc_i2c_setclock_8xxx(struct device_node *node, 369static void __devinit mpc_i2c_setup_8xxx(struct device_node *node,
324 struct mpc_i2c *i2c, 370 struct mpc_i2c *i2c,
325 u32 clock, u32 prescaler) 371 u32 clock, u32 prescaler)
326{ 372{
327 int ret, fdr; 373 int ret, fdr;
328 374
375 if (clock == MPC_I2C_CLOCK_PRESERVE) {
376 dev_dbg(i2c->dev, "using dfsrr %d, fdr %d\n",
377 readb(i2c->base + MPC_I2C_DFSRR),
378 readb(i2c->base + MPC_I2C_FDR));
379 return;
380 }
381
329 ret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler); 382 ret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler);
330 fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */ 383 fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */
331 384
@@ -338,9 +391,9 @@ static void mpc_i2c_setclock_8xxx(struct device_node *node,
338} 391}
339 392
340#else /* !CONFIG_FSL_SOC */ 393#else /* !CONFIG_FSL_SOC */
341static void mpc_i2c_setclock_8xxx(struct device_node *node, 394static void __devinit mpc_i2c_setup_8xxx(struct device_node *node,
342 struct mpc_i2c *i2c, 395 struct mpc_i2c *i2c,
343 u32 clock, u32 prescaler) 396 u32 clock, u32 prescaler)
344{ 397{
345} 398}
346#endif /* CONFIG_FSL_SOC */ 399#endif /* CONFIG_FSL_SOC */
@@ -494,7 +547,7 @@ static int __devinit fsl_i2c_probe(struct of_device *op,
494{ 547{
495 struct mpc_i2c *i2c; 548 struct mpc_i2c *i2c;
496 const u32 *prop; 549 const u32 *prop;
497 u32 clock = 0; 550 u32 clock = MPC_I2C_CLOCK_LEGACY;
498 int result = 0; 551 int result = 0;
499 int plen; 552 int plen;
500 553
@@ -523,21 +576,21 @@ static int __devinit fsl_i2c_probe(struct of_device *op,
523 } 576 }
524 } 577 }
525 578
526 if (!of_get_property(op->node, "fsl,preserve-clocking", NULL)) { 579 if (of_get_property(op->node, "fsl,preserve-clocking", NULL)) {
580 clock = MPC_I2C_CLOCK_PRESERVE;
581 } else {
527 prop = of_get_property(op->node, "clock-frequency", &plen); 582 prop = of_get_property(op->node, "clock-frequency", &plen);
528 if (prop && plen == sizeof(u32)) 583 if (prop && plen == sizeof(u32))
529 clock = *prop; 584 clock = *prop;
585 }
530 586
531 if (match->data) { 587 if (match->data) {
532 struct mpc_i2c_match_data *data = 588 struct mpc_i2c_data *data = match->data;
533 (struct mpc_i2c_match_data *)match->data; 589 data->setup(op->node, i2c, clock, data->prescaler);
534 data->setclock(op->node, i2c, clock, data->prescaler); 590 } else {
535 } else { 591 /* Backwards compatibility */
536 /* Backwards compatibility */ 592 if (of_get_property(op->node, "dfsrr", NULL))
537 if (of_get_property(op->node, "dfsrr", NULL)) 593 mpc_i2c_setup_8xxx(op->node, i2c, clock, 0);
538 mpc_i2c_setclock_8xxx(op->node, i2c,
539 clock, 0);
540 }
541 } 594 }
542 595
543 dev_set_drvdata(&op->dev, i2c); 596 dev_set_drvdata(&op->dev, i2c);
@@ -582,47 +635,42 @@ static int __devexit fsl_i2c_remove(struct of_device *op)
582 return 0; 635 return 0;
583}; 636};
584 637
638static struct mpc_i2c_data mpc_i2c_data_512x __devinitdata = {
639 .setup = mpc_i2c_setup_512x,
640};
641
642static struct mpc_i2c_data mpc_i2c_data_52xx __devinitdata = {
643 .setup = mpc_i2c_setup_52xx,
644};
645
646static struct mpc_i2c_data mpc_i2c_data_8313 __devinitdata = {
647 .setup = mpc_i2c_setup_8xxx,
648};
649
650static struct mpc_i2c_data mpc_i2c_data_8543 __devinitdata = {
651 .setup = mpc_i2c_setup_8xxx,
652 .prescaler = 2,
653};
654
655static struct mpc_i2c_data mpc_i2c_data_8544 __devinitdata = {
656 .setup = mpc_i2c_setup_8xxx,
657 .prescaler = 3,
658};
659
585static const struct of_device_id mpc_i2c_of_match[] = { 660static const struct of_device_id mpc_i2c_of_match[] = {
586 {.compatible = "mpc5200-i2c", 661 {.compatible = "mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
587 .data = &(struct mpc_i2c_match_data) { 662 {.compatible = "fsl,mpc5200b-i2c", .data = &mpc_i2c_data_52xx, },
588 .setclock = mpc_i2c_setclock_52xx, 663 {.compatible = "fsl,mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
589 }, 664 {.compatible = "fsl,mpc5121-i2c", .data = &mpc_i2c_data_512x, },
590 }, 665 {.compatible = "fsl,mpc8313-i2c", .data = &mpc_i2c_data_8313, },
591 {.compatible = "fsl,mpc5200b-i2c", 666 {.compatible = "fsl,mpc8543-i2c", .data = &mpc_i2c_data_8543, },
592 .data = &(struct mpc_i2c_match_data) { 667 {.compatible = "fsl,mpc8544-i2c", .data = &mpc_i2c_data_8544, },
593 .setclock = mpc_i2c_setclock_52xx,
594 },
595 },
596 {.compatible = "fsl,mpc5200-i2c",
597 .data = &(struct mpc_i2c_match_data) {
598 .setclock = mpc_i2c_setclock_52xx,
599 },
600 },
601 {.compatible = "fsl,mpc8313-i2c",
602 .data = &(struct mpc_i2c_match_data) {
603 .setclock = mpc_i2c_setclock_8xxx,
604 },
605 },
606 {.compatible = "fsl,mpc8543-i2c",
607 .data = &(struct mpc_i2c_match_data) {
608 .setclock = mpc_i2c_setclock_8xxx,
609 .prescaler = 2,
610 },
611 },
612 {.compatible = "fsl,mpc8544-i2c",
613 .data = &(struct mpc_i2c_match_data) {
614 .setclock = mpc_i2c_setclock_8xxx,
615 .prescaler = 3,
616 },
617 /* Backward compatibility */ 668 /* Backward compatibility */
618 },
619 {.compatible = "fsl-i2c", }, 669 {.compatible = "fsl-i2c", },
620 {}, 670 {},
621}; 671};
622
623MODULE_DEVICE_TABLE(of, mpc_i2c_of_match); 672MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
624 673
625
626/* Structure for a device driver */ 674/* Structure for a device driver */
627static struct of_platform_driver mpc_i2c_driver = { 675static struct of_platform_driver mpc_i2c_driver = {
628 .match_table = mpc_i2c_of_match, 676 .match_table = mpc_i2c_of_match,
@@ -655,5 +703,5 @@ module_exit(fsl_i2c_exit);
655 703
656MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>"); 704MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
657MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and " 705MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and "
658 "MPC824x/85xx/52xx processors"); 706 "MPC824x/83xx/85xx/86xx/512x/52xx processors");
659MODULE_LICENSE("GPL"); 707MODULE_LICENSE("GPL");
diff --git a/drivers/i2c/busses/i2c-nforce2.c b/drivers/i2c/busses/i2c-nforce2.c
index ec11d1c4e77b..4a700587ef18 100644
--- a/drivers/i2c/busses/i2c-nforce2.c
+++ b/drivers/i2c/busses/i2c-nforce2.c
@@ -308,7 +308,7 @@ static struct i2c_algorithm smbus_algorithm = {
308}; 308};
309 309
310 310
311static struct pci_device_id nforce2_ids[] = { 311static const struct pci_device_id nforce2_ids[] = {
312 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_SMBUS) }, 312 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_SMBUS) },
313 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SMBUS) }, 313 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SMBUS) },
314 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_SMBUS) }, 314 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_SMBUS) },
diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c
new file mode 100644
index 000000000000..a15f731fa451
--- /dev/null
+++ b/drivers/i2c/busses/i2c-nomadik.c
@@ -0,0 +1,959 @@
1/*
2 * Copyright (C) 2009 ST-Ericsson
3 * Copyright (C) 2009 STMicroelectronics
4 *
5 * I2C master mode controller driver, used in Nomadik 8815
6 * and Ux500 platforms.
7 *
8 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
9 * Author: Sachin Verma <sachin.verma@st.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2, as
13 * published by the Free Software Foundation.
14 */
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/platform_device.h>
18#include <linux/delay.h>
19#include <linux/interrupt.h>
20#include <linux/i2c.h>
21#include <linux/err.h>
22#include <linux/clk.h>
23#include <linux/io.h>
24
25#include <plat/i2c.h>
26
27#define DRIVER_NAME "nmk-i2c"
28
29/* I2C Controller register offsets */
30#define I2C_CR (0x000)
31#define I2C_SCR (0x004)
32#define I2C_HSMCR (0x008)
33#define I2C_MCR (0x00C)
34#define I2C_TFR (0x010)
35#define I2C_SR (0x014)
36#define I2C_RFR (0x018)
37#define I2C_TFTR (0x01C)
38#define I2C_RFTR (0x020)
39#define I2C_DMAR (0x024)
40#define I2C_BRCR (0x028)
41#define I2C_IMSCR (0x02C)
42#define I2C_RISR (0x030)
43#define I2C_MISR (0x034)
44#define I2C_ICR (0x038)
45
46/* Control registers */
47#define I2C_CR_PE (0x1 << 0) /* Peripheral Enable */
48#define I2C_CR_OM (0x3 << 1) /* Operating mode */
49#define I2C_CR_SAM (0x1 << 3) /* Slave addressing mode */
50#define I2C_CR_SM (0x3 << 4) /* Speed mode */
51#define I2C_CR_SGCM (0x1 << 6) /* Slave general call mode */
52#define I2C_CR_FTX (0x1 << 7) /* Flush Transmit */
53#define I2C_CR_FRX (0x1 << 8) /* Flush Receive */
54#define I2C_CR_DMA_TX_EN (0x1 << 9) /* DMA Tx enable */
55#define I2C_CR_DMA_RX_EN (0x1 << 10) /* DMA Rx Enable */
56#define I2C_CR_DMA_SLE (0x1 << 11) /* DMA sync. logic enable */
57#define I2C_CR_LM (0x1 << 12) /* Loopback mode */
58#define I2C_CR_FON (0x3 << 13) /* Filtering on */
59#define I2C_CR_FS (0x3 << 15) /* Force stop enable */
60
61/* Master controller (MCR) register */
62#define I2C_MCR_OP (0x1 << 0) /* Operation */
63#define I2C_MCR_A7 (0x7f << 1) /* 7-bit address */
64#define I2C_MCR_EA10 (0x7 << 8) /* 10-bit Extended address */
65#define I2C_MCR_SB (0x1 << 11) /* Extended address */
66#define I2C_MCR_AM (0x3 << 12) /* Address type */
67#define I2C_MCR_STOP (0x1 << 14) /* Stop condition */
68#define I2C_MCR_LENGTH (0x7ff << 15) /* Transaction length */
69
70/* Status register (SR) */
71#define I2C_SR_OP (0x3 << 0) /* Operation */
72#define I2C_SR_STATUS (0x3 << 2) /* controller status */
73#define I2C_SR_CAUSE (0x7 << 4) /* Abort cause */
74#define I2C_SR_TYPE (0x3 << 7) /* Receive type */
75#define I2C_SR_LENGTH (0x7ff << 9) /* Transfer length */
76
77/* Interrupt mask set/clear (IMSCR) bits */
78#define I2C_IT_TXFE (0x1 << 0)
79#define I2C_IT_TXFNE (0x1 << 1)
80#define I2C_IT_TXFF (0x1 << 2)
81#define I2C_IT_TXFOVR (0x1 << 3)
82#define I2C_IT_RXFE (0x1 << 4)
83#define I2C_IT_RXFNF (0x1 << 5)
84#define I2C_IT_RXFF (0x1 << 6)
85#define I2C_IT_RFSR (0x1 << 16)
86#define I2C_IT_RFSE (0x1 << 17)
87#define I2C_IT_WTSR (0x1 << 18)
88#define I2C_IT_MTD (0x1 << 19)
89#define I2C_IT_STD (0x1 << 20)
90#define I2C_IT_MAL (0x1 << 24)
91#define I2C_IT_BERR (0x1 << 25)
92#define I2C_IT_MTDWS (0x1 << 28)
93
94#define GEN_MASK(val, mask, sb) (((val) << (sb)) & (mask))
95
96/* some bits in ICR are reserved */
97#define I2C_CLEAR_ALL_INTS 0x131f007f
98
99/* first three msb bits are reserved */
100#define IRQ_MASK(mask) (mask & 0x1fffffff)
101
102/* maximum threshold value */
103#define MAX_I2C_FIFO_THRESHOLD 15
104
105enum i2c_status {
106 I2C_NOP,
107 I2C_ON_GOING,
108 I2C_OK,
109 I2C_ABORT
110};
111
112/* operation */
113enum i2c_operation {
114 I2C_NO_OPERATION = 0xff,
115 I2C_WRITE = 0x00,
116 I2C_READ = 0x01
117};
118
119/* controller response timeout in ms */
120#define I2C_TIMEOUT_MS 500
121
122/**
123 * struct i2c_nmk_client - client specific data
124 * @slave_adr: 7-bit slave address
125 * @count: no. bytes to be transfered
126 * @buffer: client data buffer
127 * @xfer_bytes: bytes transfered till now
128 * @operation: current I2C operation
129 */
130struct i2c_nmk_client {
131 unsigned short slave_adr;
132 unsigned long count;
133 unsigned char *buffer;
134 unsigned long xfer_bytes;
135 enum i2c_operation operation;
136};
137
138/**
139 * struct nmk_i2c_dev - private data structure of the controller
140 * @pdev: parent platform device
141 * @adap: corresponding I2C adapter
142 * @irq: interrupt line for the controller
143 * @virtbase: virtual io memory area
144 * @clk: hardware i2c block clock
145 * @cfg: machine provided controller configuration
146 * @cli: holder of client specific data
147 * @stop: stop condition
148 * @xfer_complete: acknowledge completion for a I2C message
149 * @result: controller propogated result
150 */
151struct nmk_i2c_dev {
152 struct platform_device *pdev;
153 struct i2c_adapter adap;
154 int irq;
155 void __iomem *virtbase;
156 struct clk *clk;
157 struct nmk_i2c_controller cfg;
158 struct i2c_nmk_client cli;
159 int stop;
160 struct completion xfer_complete;
161 int result;
162};
163
164/* controller's abort causes */
165static const char *abort_causes[] = {
166 "no ack received after address transmission",
167 "no ack received during data phase",
168 "ack received after xmission of master code",
169 "master lost arbitration",
170 "slave restarts",
171 "slave reset",
172 "overflow, maxsize is 2047 bytes",
173};
174
175static inline void i2c_set_bit(void __iomem *reg, u32 mask)
176{
177 writel(readl(reg) | mask, reg);
178}
179
180static inline void i2c_clr_bit(void __iomem *reg, u32 mask)
181{
182 writel(readl(reg) & ~mask, reg);
183}
184
185/**
186 * flush_i2c_fifo() - This function flushes the I2C FIFO
187 * @dev: private data of I2C Driver
188 *
189 * This function flushes the I2C Tx and Rx FIFOs. It returns
190 * 0 on successful flushing of FIFO
191 */
192static int flush_i2c_fifo(struct nmk_i2c_dev *dev)
193{
194#define LOOP_ATTEMPTS 10
195 int i;
196 unsigned long timeout;
197
198 /*
199 * flush the transmit and receive FIFO. The flushing
200 * operation takes several cycles before to be completed.
201 * On the completion, the I2C internal logic clears these
202 * bits, until then no one must access Tx, Rx FIFO and
203 * should poll on these bits waiting for the completion.
204 */
205 writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR);
206
207 for (i = 0; i < LOOP_ATTEMPTS; i++) {
208 timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT_MS);
209
210 while (!time_after(jiffies, timeout)) {
211 if ((readl(dev->virtbase + I2C_CR) &
212 (I2C_CR_FTX | I2C_CR_FRX)) == 0)
213 return 0;
214 }
215 }
216
217 dev_err(&dev->pdev->dev, "flushing operation timed out "
218 "giving up after %d attempts", LOOP_ATTEMPTS);
219
220 return -ETIMEDOUT;
221}
222
223/**
224 * disable_all_interrupts() - Disable all interrupts of this I2c Bus
225 * @dev: private data of I2C Driver
226 */
227static void disable_all_interrupts(struct nmk_i2c_dev *dev)
228{
229 u32 mask = IRQ_MASK(0);
230 writel(mask, dev->virtbase + I2C_IMSCR);
231}
232
233/**
234 * clear_all_interrupts() - Clear all interrupts of I2C Controller
235 * @dev: private data of I2C Driver
236 */
237static void clear_all_interrupts(struct nmk_i2c_dev *dev)
238{
239 u32 mask;
240 mask = IRQ_MASK(I2C_CLEAR_ALL_INTS);
241 writel(mask, dev->virtbase + I2C_ICR);
242}
243
244/**
245 * init_hw() - initialize the I2C hardware
246 * @dev: private data of I2C Driver
247 */
248static int init_hw(struct nmk_i2c_dev *dev)
249{
250 int stat;
251
252 stat = flush_i2c_fifo(dev);
253 if (stat)
254 return stat;
255
256 /* disable the controller */
257 i2c_clr_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
258
259 disable_all_interrupts(dev);
260
261 clear_all_interrupts(dev);
262
263 dev->cli.operation = I2C_NO_OPERATION;
264
265 return 0;
266}
267
268/* enable peripheral, master mode operation */
269#define DEFAULT_I2C_REG_CR ((1 << 1) | I2C_CR_PE)
270
271/**
272 * load_i2c_mcr_reg() - load the MCR register
273 * @dev: private data of controller
274 */
275static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *dev)
276{
277 u32 mcr = 0;
278
279 /* 7-bit address transaction */
280 mcr |= GEN_MASK(1, I2C_MCR_AM, 12);
281 mcr |= GEN_MASK(dev->cli.slave_adr, I2C_MCR_A7, 1);
282
283 /* start byte procedure not applied */
284 mcr |= GEN_MASK(0, I2C_MCR_SB, 11);
285
286 /* check the operation, master read/write? */
287 if (dev->cli.operation == I2C_WRITE)
288 mcr |= GEN_MASK(I2C_WRITE, I2C_MCR_OP, 0);
289 else
290 mcr |= GEN_MASK(I2C_READ, I2C_MCR_OP, 0);
291
292 /* stop or repeated start? */
293 if (dev->stop)
294 mcr |= GEN_MASK(1, I2C_MCR_STOP, 14);
295 else
296 mcr &= ~(GEN_MASK(1, I2C_MCR_STOP, 14));
297
298 mcr |= GEN_MASK(dev->cli.count, I2C_MCR_LENGTH, 15);
299
300 return mcr;
301}
302
303/**
304 * setup_i2c_controller() - setup the controller
305 * @dev: private data of controller
306 */
307static void setup_i2c_controller(struct nmk_i2c_dev *dev)
308{
309 u32 brcr1, brcr2;
310 u32 i2c_clk, div;
311
312 writel(0x0, dev->virtbase + I2C_CR);
313 writel(0x0, dev->virtbase + I2C_HSMCR);
314 writel(0x0, dev->virtbase + I2C_TFTR);
315 writel(0x0, dev->virtbase + I2C_RFTR);
316 writel(0x0, dev->virtbase + I2C_DMAR);
317
318 /*
319 * set the slsu:
320 *
321 * slsu defines the data setup time after SCL clock
322 * stretching in terms of i2c clk cycles. The
323 * needed setup time for the three modes are 250ns,
324 * 100ns, 10ns repectively thus leading to the values
325 * of 14, 6, 2 for a 48 MHz i2c clk.
326 */
327 writel(dev->cfg.slsu << 16, dev->virtbase + I2C_SCR);
328
329 i2c_clk = clk_get_rate(dev->clk);
330
331 /* fallback to std. mode if machine has not provided it */
332 if (dev->cfg.clk_freq == 0)
333 dev->cfg.clk_freq = 100000;
334
335 /*
336 * The spec says, in case of std. mode the divider is
337 * 2 whereas it is 3 for fast and fastplus mode of
338 * operation. TODO - high speed support.
339 */
340 div = (dev->cfg.clk_freq > 100000) ? 3 : 2;
341
342 /*
343 * generate the mask for baud rate counters. The controller
344 * has two baud rate counters. One is used for High speed
345 * operation, and the other is for std, fast mode, fast mode
346 * plus operation. Currently we do not supprt high speed mode
347 * so set brcr1 to 0.
348 */
349 brcr1 = 0 << 16;
350 brcr2 = (i2c_clk/(dev->cfg.clk_freq * div)) & 0xffff;
351
352 /* set the baud rate counter register */
353 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
354
355 /*
356 * set the speed mode. Currently we support
357 * only standard and fast mode of operation
358 * TODO - support for fast mode plus (upto 1Mb/s)
359 * and high speed (up to 3.4 Mb/s)
360 */
361 if (dev->cfg.sm > I2C_FREQ_MODE_FAST) {
362 dev_err(&dev->pdev->dev, "do not support this mode "
363 "defaulting to std. mode\n");
364 brcr2 = i2c_clk/(100000 * 2) & 0xffff;
365 writel((brcr1 | brcr2), dev->virtbase + I2C_BRCR);
366 writel(I2C_FREQ_MODE_STANDARD << 4,
367 dev->virtbase + I2C_CR);
368 }
369 writel(dev->cfg.sm << 4, dev->virtbase + I2C_CR);
370
371 /* set the Tx and Rx FIFO threshold */
372 writel(dev->cfg.tft, dev->virtbase + I2C_TFTR);
373 writel(dev->cfg.rft, dev->virtbase + I2C_RFTR);
374}
375
376/**
377 * read_i2c() - Read from I2C client device
378 * @dev: private data of I2C Driver
379 *
380 * This function reads from i2c client device when controller is in
381 * master mode. There is a completion timeout. If there is no transfer
382 * before timeout error is returned.
383 */
384static int read_i2c(struct nmk_i2c_dev *dev)
385{
386 u32 status = 0;
387 u32 mcr;
388 u32 irq_mask = 0;
389 int timeout;
390
391 mcr = load_i2c_mcr_reg(dev);
392 writel(mcr, dev->virtbase + I2C_MCR);
393
394 /* load the current CR value */
395 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
396 dev->virtbase + I2C_CR);
397
398 /* enable the controller */
399 i2c_set_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
400
401 init_completion(&dev->xfer_complete);
402
403 /* enable interrupts by setting the mask */
404 irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF |
405 I2C_IT_MAL | I2C_IT_BERR);
406
407 if (dev->stop)
408 irq_mask |= I2C_IT_MTD;
409 else
410 irq_mask |= I2C_IT_MTDWS;
411
412 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
413
414 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
415 dev->virtbase + I2C_IMSCR);
416
417 timeout = wait_for_completion_interruptible_timeout(
418 &dev->xfer_complete, msecs_to_jiffies(I2C_TIMEOUT_MS));
419
420 if (timeout < 0) {
421 dev_err(&dev->pdev->dev,
422 "wait_for_completion_interruptible_timeout"
423 "returned %d waiting for event\n", timeout);
424 status = timeout;
425 }
426
427 if (timeout == 0) {
428 /* controler has timedout, re-init the h/w */
429 dev_err(&dev->pdev->dev, "controller timed out, re-init h/w\n");
430 (void) init_hw(dev);
431 status = -ETIMEDOUT;
432 }
433
434 return status;
435}
436
437/**
438 * write_i2c() - Write data to I2C client.
439 * @dev: private data of I2C Driver
440 *
441 * This function writes data to I2C client
442 */
443static int write_i2c(struct nmk_i2c_dev *dev)
444{
445 u32 status = 0;
446 u32 mcr;
447 u32 irq_mask = 0;
448 int timeout;
449
450 mcr = load_i2c_mcr_reg(dev);
451
452 writel(mcr, dev->virtbase + I2C_MCR);
453
454 /* load the current CR value */
455 writel(readl(dev->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
456 dev->virtbase + I2C_CR);
457
458 /* enable the controller */
459 i2c_set_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
460
461 init_completion(&dev->xfer_complete);
462
463 /* enable interrupts by settings the masks */
464 irq_mask = (I2C_IT_TXFNE | I2C_IT_TXFOVR |
465 I2C_IT_MAL | I2C_IT_BERR);
466
467 /*
468 * check if we want to transfer a single or multiple bytes, if so
469 * set the MTDWS bit (Master Transaction Done Without Stop)
470 * to start repeated start operation
471 */
472 if (dev->stop)
473 irq_mask |= I2C_IT_MTD;
474 else
475 irq_mask |= I2C_IT_MTDWS;
476
477 irq_mask = I2C_CLEAR_ALL_INTS & IRQ_MASK(irq_mask);
478
479 writel(readl(dev->virtbase + I2C_IMSCR) | irq_mask,
480 dev->virtbase + I2C_IMSCR);
481
482 timeout = wait_for_completion_interruptible_timeout(
483 &dev->xfer_complete, msecs_to_jiffies(I2C_TIMEOUT_MS));
484
485 if (timeout < 0) {
486 dev_err(&dev->pdev->dev,
487 "wait_for_completion_interruptible_timeout"
488 "returned %d waiting for event\n", timeout);
489 status = timeout;
490 }
491
492 if (timeout == 0) {
493 /* controler has timedout, re-init the h/w */
494 dev_err(&dev->pdev->dev, "controller timed out, re-init h/w\n");
495 (void) init_hw(dev);
496 status = -ETIMEDOUT;
497 }
498
499 return status;
500}
501
502/**
503 * nmk_i2c_xfer() - I2C transfer function used by kernel framework
504 * @i2c_adap - Adapter pointer to the controller
505 * @msgs[] - Pointer to data to be written.
506 * @num_msgs - Number of messages to be executed
507 *
508 * This is the function called by the generic kernel i2c_transfer()
509 * or i2c_smbus...() API calls. Note that this code is protected by the
510 * semaphore set in the kernel i2c_transfer() function.
511 *
512 * NOTE:
513 * READ TRANSFER : We impose a restriction of the first message to be the
514 * index message for any read transaction.
515 * - a no index is coded as '0',
516 * - 2byte big endian index is coded as '3'
517 * !!! msg[0].buf holds the actual index.
518 * This is compatible with generic messages of smbus emulator
519 * that send a one byte index.
520 * eg. a I2C transation to read 2 bytes from index 0
521 * idx = 0;
522 * msg[0].addr = client->addr;
523 * msg[0].flags = 0x0;
524 * msg[0].len = 1;
525 * msg[0].buf = &idx;
526 *
527 * msg[1].addr = client->addr;
528 * msg[1].flags = I2C_M_RD;
529 * msg[1].len = 2;
530 * msg[1].buf = rd_buff
531 * i2c_transfer(adap, msg, 2);
532 *
533 * WRITE TRANSFER : The I2C standard interface interprets all data as payload.
534 * If you want to emulate an SMBUS write transaction put the
535 * index as first byte(or first and second) in the payload.
536 * eg. a I2C transation to write 2 bytes from index 1
537 * wr_buff[0] = 0x1;
538 * wr_buff[1] = 0x23;
539 * wr_buff[2] = 0x46;
540 * msg[0].flags = 0x0;
541 * msg[0].len = 3;
542 * msg[0].buf = wr_buff;
543 * i2c_transfer(adap, msg, 1);
544 *
545 * To read or write a block of data (multiple bytes) using SMBUS emulation
546 * please use the i2c_smbus_read_i2c_block_data()
547 * or i2c_smbus_write_i2c_block_data() API
548 */
549static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap,
550 struct i2c_msg msgs[], int num_msgs)
551{
552 int status;
553 int i;
554 u32 cause;
555 struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap);
556
557 status = init_hw(dev);
558 if (status)
559 return status;
560
561 /* setup the i2c controller */
562 setup_i2c_controller(dev);
563
564 for (i = 0; i < num_msgs; i++) {
565 if (unlikely(msgs[i].flags & I2C_M_TEN)) {
566 dev_err(&dev->pdev->dev, "10 bit addressing"
567 "not supported\n");
568 return -EINVAL;
569 }
570 dev->cli.slave_adr = msgs[i].addr;
571 dev->cli.buffer = msgs[i].buf;
572 dev->cli.count = msgs[i].len;
573 dev->stop = (i < (num_msgs - 1)) ? 0 : 1;
574 dev->result = 0;
575
576 if (msgs[i].flags & I2C_M_RD) {
577 /* it is a read operation */
578 dev->cli.operation = I2C_READ;
579 status = read_i2c(dev);
580 } else {
581 /* write operation */
582 dev->cli.operation = I2C_WRITE;
583 status = write_i2c(dev);
584 }
585 if (status || (dev->result)) {
586 /* get the abort cause */
587 cause = (readl(dev->virtbase + I2C_SR) >> 4) & 0x7;
588 dev_err(&dev->pdev->dev, "error during I2C"
589 "message xfer: %d\n", cause);
590 dev_err(&dev->pdev->dev, "%s\n",
591 cause >= ARRAY_SIZE(abort_causes)
592 ? "unknown reason" : abort_causes[cause]);
593 return status;
594 }
595 mdelay(1);
596 }
597 /* return the no. messages processed */
598 if (status)
599 return status;
600 else
601 return num_msgs;
602}
603
604/**
605 * disable_interrupts() - disable the interrupts
606 * @dev: private data of controller
607 */
608static int disable_interrupts(struct nmk_i2c_dev *dev, u32 irq)
609{
610 irq = IRQ_MASK(irq);
611 writel(readl(dev->virtbase + I2C_IMSCR) & ~(I2C_CLEAR_ALL_INTS & irq),
612 dev->virtbase + I2C_IMSCR);
613 return 0;
614}
615
616/**
617 * i2c_irq_handler() - interrupt routine
618 * @irq: interrupt number
619 * @arg: data passed to the handler
620 *
621 * This is the interrupt handler for the i2c driver. Currently
622 * it handles the major interrupts like Rx & Tx FIFO management
623 * interrupts, master transaction interrupts, arbitration and
624 * bus error interrupts. The rest of the interrupts are treated as
625 * unhandled.
626 */
627static irqreturn_t i2c_irq_handler(int irq, void *arg)
628{
629 struct nmk_i2c_dev *dev = arg;
630 u32 tft, rft;
631 u32 count;
632 u32 misr;
633 u32 src = 0;
634
635 /* load Tx FIFO and Rx FIFO threshold values */
636 tft = readl(dev->virtbase + I2C_TFTR);
637 rft = readl(dev->virtbase + I2C_RFTR);
638
639 /* read interrupt status register */
640 misr = readl(dev->virtbase + I2C_MISR);
641
642 src = __ffs(misr);
643 switch ((1 << src)) {
644
645 /* Transmit FIFO nearly empty interrupt */
646 case I2C_IT_TXFNE:
647 {
648 if (dev->cli.operation == I2C_READ) {
649 /*
650 * in read operation why do we care for writing?
651 * so disable the Transmit FIFO interrupt
652 */
653 disable_interrupts(dev, I2C_IT_TXFNE);
654 } else {
655 for (count = (MAX_I2C_FIFO_THRESHOLD - tft - 2);
656 (count > 0) &&
657 (dev->cli.count != 0);
658 count--) {
659 /* write to the Tx FIFO */
660 writeb(*dev->cli.buffer,
661 dev->virtbase + I2C_TFR);
662 dev->cli.buffer++;
663 dev->cli.count--;
664 dev->cli.xfer_bytes++;
665 }
666 /*
667 * if done, close the transfer by disabling the
668 * corresponding TXFNE interrupt
669 */
670 if (dev->cli.count == 0)
671 disable_interrupts(dev, I2C_IT_TXFNE);
672 }
673 }
674 break;
675
676 /*
677 * Rx FIFO nearly full interrupt.
678 * This is set when the numer of entries in Rx FIFO is
679 * greater or equal than the threshold value programmed
680 * in RFT
681 */
682 case I2C_IT_RXFNF:
683 for (count = rft; count > 0; count--) {
684 /* Read the Rx FIFO */
685 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
686 dev->cli.buffer++;
687 }
688 dev->cli.count -= rft;
689 dev->cli.xfer_bytes += rft;
690 break;
691
692 /* Rx FIFO full */
693 case I2C_IT_RXFF:
694 for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) {
695 *dev->cli.buffer = readb(dev->virtbase + I2C_RFR);
696 dev->cli.buffer++;
697 }
698 dev->cli.count -= MAX_I2C_FIFO_THRESHOLD;
699 dev->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD;
700 break;
701
702 /* Master Transaction Done with/without stop */
703 case I2C_IT_MTD:
704 case I2C_IT_MTDWS:
705 if (dev->cli.operation == I2C_READ) {
706 while (!readl(dev->virtbase + I2C_RISR) & I2C_IT_RXFE) {
707 if (dev->cli.count == 0)
708 break;
709 *dev->cli.buffer =
710 readb(dev->virtbase + I2C_RFR);
711 dev->cli.buffer++;
712 dev->cli.count--;
713 dev->cli.xfer_bytes++;
714 }
715 }
716
717 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MTD);
718 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MTDWS);
719
720 disable_interrupts(dev,
721 (I2C_IT_TXFNE | I2C_IT_TXFE | I2C_IT_TXFF
722 | I2C_IT_TXFOVR | I2C_IT_RXFNF
723 | I2C_IT_RXFF | I2C_IT_RXFE));
724
725 if (dev->cli.count) {
726 dev->result = -1;
727 dev_err(&dev->pdev->dev, "%lu bytes still remain to be"
728 "xfered\n", dev->cli.count);
729 (void) init_hw(dev);
730 }
731 complete(&dev->xfer_complete);
732
733 break;
734
735 /* Master Arbitration lost interrupt */
736 case I2C_IT_MAL:
737 dev->result = -1;
738 (void) init_hw(dev);
739
740 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL);
741 complete(&dev->xfer_complete);
742
743 break;
744
745 /*
746 * Bus Error interrupt.
747 * This happens when an unexpected start/stop condition occurs
748 * during the transaction.
749 */
750 case I2C_IT_BERR:
751 dev->result = -1;
752 /* get the status */
753 if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT)
754 (void) init_hw(dev);
755
756 i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_BERR);
757 complete(&dev->xfer_complete);
758
759 break;
760
761 /*
762 * Tx FIFO overrun interrupt.
763 * This is set when a write operation in Tx FIFO is performed and
764 * the Tx FIFO is full.
765 */
766 case I2C_IT_TXFOVR:
767 dev->result = -1;
768 (void) init_hw(dev);
769
770 dev_err(&dev->pdev->dev, "Tx Fifo Over run\n");
771 complete(&dev->xfer_complete);
772
773 break;
774
775 /* unhandled interrupts by this driver - TODO*/
776 case I2C_IT_TXFE:
777 case I2C_IT_TXFF:
778 case I2C_IT_RXFE:
779 case I2C_IT_RFSR:
780 case I2C_IT_RFSE:
781 case I2C_IT_WTSR:
782 case I2C_IT_STD:
783 dev_err(&dev->pdev->dev, "unhandled Interrupt\n");
784 break;
785 default:
786 dev_err(&dev->pdev->dev, "spurious Interrupt..\n");
787 break;
788 }
789
790 return IRQ_HANDLED;
791}
792
793static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap)
794{
795 return I2C_FUNC_I2C
796 | I2C_FUNC_SMBUS_BYTE_DATA
797 | I2C_FUNC_SMBUS_WORD_DATA
798 | I2C_FUNC_SMBUS_I2C_BLOCK;
799}
800
801static const struct i2c_algorithm nmk_i2c_algo = {
802 .master_xfer = nmk_i2c_xfer,
803 .functionality = nmk_i2c_functionality
804};
805
806static int __devinit nmk_i2c_probe(struct platform_device *pdev)
807{
808 int ret = 0;
809 struct resource *res;
810 struct nmk_i2c_controller *pdata =
811 pdev->dev.platform_data;
812 struct nmk_i2c_dev *dev;
813 struct i2c_adapter *adap;
814
815 dev = kzalloc(sizeof(struct nmk_i2c_dev), GFP_KERNEL);
816 if (!dev) {
817 dev_err(&pdev->dev, "cannot allocate memory\n");
818 ret = -ENOMEM;
819 goto err_no_mem;
820 }
821
822 dev->pdev = pdev;
823 platform_set_drvdata(pdev, dev);
824
825 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
826 if (!res) {
827 ret = -ENOENT;
828 goto err_no_resource;
829 }
830
831 if (request_mem_region(res->start, resource_size(res),
832 DRIVER_NAME "I/O region") == NULL) {
833 ret = -EBUSY;
834 goto err_no_region;
835 }
836
837 dev->virtbase = ioremap(res->start, resource_size(res));
838 if (!dev->virtbase) {
839 ret = -ENOMEM;
840 goto err_no_ioremap;
841 }
842
843 dev->irq = platform_get_irq(pdev, 0);
844 ret = request_irq(dev->irq, i2c_irq_handler, IRQF_DISABLED,
845 DRIVER_NAME, dev);
846 if (ret) {
847 dev_err(&pdev->dev, "cannot claim the irq %d\n", dev->irq);
848 goto err_irq;
849 }
850
851 dev->clk = clk_get(&pdev->dev, NULL);
852 if (IS_ERR(dev->clk)) {
853 dev_err(&pdev->dev, "could not get i2c clock\n");
854 ret = PTR_ERR(dev->clk);
855 goto err_no_clk;
856 }
857
858 clk_enable(dev->clk);
859
860 adap = &dev->adap;
861 adap->dev.parent = &pdev->dev;
862 adap->owner = THIS_MODULE;
863 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
864 adap->algo = &nmk_i2c_algo;
865
866 /* fetch the controller id */
867 adap->nr = pdev->id;
868
869 /* fetch the controller configuration from machine */
870 dev->cfg.clk_freq = pdata->clk_freq;
871 dev->cfg.slsu = pdata->slsu;
872 dev->cfg.tft = pdata->tft;
873 dev->cfg.rft = pdata->rft;
874 dev->cfg.sm = pdata->sm;
875
876 i2c_set_adapdata(adap, dev);
877
878 ret = init_hw(dev);
879 if (ret != 0) {
880 dev_err(&pdev->dev, "error in initializing i2c hardware\n");
881 goto err_init_hw;
882 }
883
884 dev_dbg(&pdev->dev, "initialize I2C%d bus on virtual "
885 "base %p\n", pdev->id, dev->virtbase);
886
887 ret = i2c_add_numbered_adapter(adap);
888 if (ret) {
889 dev_err(&pdev->dev, "failed to add adapter\n");
890 goto err_add_adap;
891 }
892
893 return 0;
894
895 err_init_hw:
896 clk_disable(dev->clk);
897 err_add_adap:
898 clk_put(dev->clk);
899 err_no_clk:
900 free_irq(dev->irq, dev);
901 err_irq:
902 iounmap(dev->virtbase);
903 err_no_ioremap:
904 release_mem_region(res->start, resource_size(res));
905 err_no_region:
906 platform_set_drvdata(pdev, NULL);
907 err_no_resource:
908 kfree(dev);
909 err_no_mem:
910
911 return ret;
912}
913
914static int __devexit nmk_i2c_remove(struct platform_device *pdev)
915{
916 struct nmk_i2c_dev *dev = platform_get_drvdata(pdev);
917
918 i2c_del_adapter(&dev->adap);
919 flush_i2c_fifo(dev);
920 disable_all_interrupts(dev);
921 clear_all_interrupts(dev);
922 /* disable the controller */
923 i2c_clr_bit(dev->virtbase + I2C_CR, I2C_CR_PE);
924 free_irq(dev->irq, dev);
925 iounmap(dev->virtbase);
926 clk_disable(dev->clk);
927 clk_put(dev->clk);
928 platform_set_drvdata(pdev, NULL);
929 kfree(dev);
930
931 return 0;
932}
933
934static struct platform_driver nmk_i2c_driver = {
935 .driver = {
936 .owner = THIS_MODULE,
937 .name = DRIVER_NAME,
938 },
939 .probe = nmk_i2c_probe,
940 .remove = __devexit_p(nmk_i2c_remove),
941};
942
943static int __init nmk_i2c_init(void)
944{
945 return platform_driver_register(&nmk_i2c_driver);
946}
947
948static void __exit nmk_i2c_exit(void)
949{
950 platform_driver_unregister(&nmk_i2c_driver);
951}
952
953subsys_initcall(nmk_i2c_init);
954module_exit(nmk_i2c_exit);
955
956MODULE_AUTHOR("Sachin Verma, Srinidhi KASAGAR");
957MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver");
958MODULE_LICENSE("GPL");
959MODULE_ALIAS("platform:" DRIVER_NAME);
diff --git a/drivers/i2c/busses/i2c-octeon.c b/drivers/i2c/busses/i2c-octeon.c
new file mode 100644
index 000000000000..60375504fa49
--- /dev/null
+++ b/drivers/i2c/busses/i2c-octeon.c
@@ -0,0 +1,651 @@
1/*
2 * (C) Copyright 2009-2010
3 * Nokia Siemens Networks, michael.lawnick.ext@nsn.com
4 *
5 * Portions Copyright (C) 2010 Cavium Networks, Inc.
6 *
7 * This is a driver for the i2c adapter in Cavium Networks' OCTEON processors.
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/sched.h>
17#include <linux/init.h>
18
19#include <linux/io.h>
20#include <linux/i2c.h>
21#include <linux/interrupt.h>
22#include <linux/delay.h>
23#include <linux/platform_device.h>
24
25#include <asm/octeon/octeon.h>
26
27#define DRV_NAME "i2c-octeon"
28
29/* The previous out-of-tree version was implicitly version 1.0. */
30#define DRV_VERSION "2.0"
31
32/* register offsets */
33#define SW_TWSI 0x00
34#define TWSI_INT 0x10
35
36/* Controller command patterns */
37#define SW_TWSI_V 0x8000000000000000ull
38#define SW_TWSI_EOP_TWSI_DATA 0x0C00000100000000ull
39#define SW_TWSI_EOP_TWSI_CTL 0x0C00000200000000ull
40#define SW_TWSI_EOP_TWSI_CLKCTL 0x0C00000300000000ull
41#define SW_TWSI_EOP_TWSI_STAT 0x0C00000300000000ull
42#define SW_TWSI_EOP_TWSI_RST 0x0C00000700000000ull
43#define SW_TWSI_OP_TWSI_CLK 0x0800000000000000ull
44#define SW_TWSI_R 0x0100000000000000ull
45
46/* Controller command and status bits */
47#define TWSI_CTL_CE 0x80
48#define TWSI_CTL_ENAB 0x40
49#define TWSI_CTL_STA 0x20
50#define TWSI_CTL_STP 0x10
51#define TWSI_CTL_IFLG 0x08
52#define TWSI_CTL_AAK 0x04
53
54/* Some status values */
55#define STAT_START 0x08
56#define STAT_RSTART 0x10
57#define STAT_TXADDR_ACK 0x18
58#define STAT_TXDATA_ACK 0x28
59#define STAT_RXADDR_ACK 0x40
60#define STAT_RXDATA_ACK 0x50
61#define STAT_IDLE 0xF8
62
63struct octeon_i2c {
64 wait_queue_head_t queue;
65 struct i2c_adapter adap;
66 int irq;
67 int twsi_freq;
68 int sys_freq;
69 resource_size_t twsi_phys;
70 void __iomem *twsi_base;
71 resource_size_t regsize;
72 struct device *dev;
73};
74
75/**
76 * octeon_i2c_write_sw - write an I2C core register.
77 * @i2c: The struct octeon_i2c.
78 * @eop_reg: Register selector.
79 * @data: Value to be written.
80 *
81 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
82 */
83static void octeon_i2c_write_sw(struct octeon_i2c *i2c,
84 u64 eop_reg,
85 u8 data)
86{
87 u64 tmp;
88
89 __raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + SW_TWSI);
90 do {
91 tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
92 } while ((tmp & SW_TWSI_V) != 0);
93}
94
95/**
96 * octeon_i2c_read_sw - write an I2C core register.
97 * @i2c: The struct octeon_i2c.
98 * @eop_reg: Register selector.
99 *
100 * Returns the data.
101 *
102 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
103 */
104static u8 octeon_i2c_read_sw(struct octeon_i2c *i2c, u64 eop_reg)
105{
106 u64 tmp;
107
108 __raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + SW_TWSI);
109 do {
110 tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
111 } while ((tmp & SW_TWSI_V) != 0);
112
113 return tmp & 0xFF;
114}
115
116/**
117 * octeon_i2c_write_int - write the TWSI_INT register
118 * @i2c: The struct octeon_i2c.
119 * @data: Value to be written.
120 */
121static void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)
122{
123 u64 tmp;
124
125 __raw_writeq(data, i2c->twsi_base + TWSI_INT);
126 tmp = __raw_readq(i2c->twsi_base + TWSI_INT);
127}
128
129/**
130 * octeon_i2c_int_enable - enable the TS interrupt.
131 * @i2c: The struct octeon_i2c.
132 *
133 * The interrupt will be asserted when there is non-STAT_IDLE state in
134 * the SW_TWSI_EOP_TWSI_STAT register.
135 */
136static void octeon_i2c_int_enable(struct octeon_i2c *i2c)
137{
138 octeon_i2c_write_int(i2c, 0x40);
139}
140
141/**
142 * octeon_i2c_int_disable - disable the TS interrupt.
143 * @i2c: The struct octeon_i2c.
144 */
145static void octeon_i2c_int_disable(struct octeon_i2c *i2c)
146{
147 octeon_i2c_write_int(i2c, 0);
148}
149
150/**
151 * octeon_i2c_unblock - unblock the bus.
152 * @i2c: The struct octeon_i2c.
153 *
154 * If there was a reset while a device was driving 0 to bus,
155 * bus is blocked. We toggle it free manually by some clock
156 * cycles and send a stop.
157 */
158static void octeon_i2c_unblock(struct octeon_i2c *i2c)
159{
160 int i;
161
162 dev_dbg(i2c->dev, "%s\n", __func__);
163 for (i = 0; i < 9; i++) {
164 octeon_i2c_write_int(i2c, 0x0);
165 udelay(5);
166 octeon_i2c_write_int(i2c, 0x200);
167 udelay(5);
168 }
169 octeon_i2c_write_int(i2c, 0x300);
170 udelay(5);
171 octeon_i2c_write_int(i2c, 0x100);
172 udelay(5);
173 octeon_i2c_write_int(i2c, 0x0);
174}
175
176/**
177 * octeon_i2c_isr - the interrupt service routine.
178 * @int: The irq, unused.
179 * @dev_id: Our struct octeon_i2c.
180 */
181static irqreturn_t octeon_i2c_isr(int irq, void *dev_id)
182{
183 struct octeon_i2c *i2c = dev_id;
184
185 octeon_i2c_int_disable(i2c);
186 wake_up_interruptible(&i2c->queue);
187
188 return IRQ_HANDLED;
189}
190
191
192static int octeon_i2c_test_iflg(struct octeon_i2c *i2c)
193{
194 return (octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_CTL) & TWSI_CTL_IFLG) != 0;
195}
196
197/**
198 * octeon_i2c_wait - wait for the IFLG to be set.
199 * @i2c: The struct octeon_i2c.
200 *
201 * Returns 0 on success, otherwise a negative errno.
202 */
203static int octeon_i2c_wait(struct octeon_i2c *i2c)
204{
205 int result;
206
207 octeon_i2c_int_enable(i2c);
208
209 result = wait_event_interruptible_timeout(i2c->queue,
210 octeon_i2c_test_iflg(i2c),
211 i2c->adap.timeout);
212
213 octeon_i2c_int_disable(i2c);
214
215 if (result < 0) {
216 dev_dbg(i2c->dev, "%s: wait interrupted\n", __func__);
217 return result;
218 } else if (result == 0) {
219 dev_dbg(i2c->dev, "%s: timeout\n", __func__);
220 result = -ETIMEDOUT;
221 }
222
223 return 0;
224}
225
226/**
227 * octeon_i2c_start - send START to the bus.
228 * @i2c: The struct octeon_i2c.
229 *
230 * Returns 0 on success, otherwise a negative errno.
231 */
232static int octeon_i2c_start(struct octeon_i2c *i2c)
233{
234 u8 data;
235 int result;
236
237 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
238 TWSI_CTL_ENAB | TWSI_CTL_STA);
239
240 result = octeon_i2c_wait(i2c);
241 if (result) {
242 if (octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT) == STAT_IDLE) {
243 /*
244 * Controller refused to send start flag May
245 * be a client is holding SDA low - let's try
246 * to free it.
247 */
248 octeon_i2c_unblock(i2c);
249 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
250 TWSI_CTL_ENAB | TWSI_CTL_STA);
251
252 result = octeon_i2c_wait(i2c);
253 }
254 if (result)
255 return result;
256 }
257
258 data = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
259 if ((data != STAT_START) && (data != STAT_RSTART)) {
260 dev_err(i2c->dev, "%s: bad status (0x%x)\n", __func__, data);
261 return -EIO;
262 }
263
264 return 0;
265}
266
267/**
268 * octeon_i2c_stop - send STOP to the bus.
269 * @i2c: The struct octeon_i2c.
270 *
271 * Returns 0 on success, otherwise a negative errno.
272 */
273static int octeon_i2c_stop(struct octeon_i2c *i2c)
274{
275 u8 data;
276
277 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
278 TWSI_CTL_ENAB | TWSI_CTL_STP);
279
280 data = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
281
282 if (data != STAT_IDLE) {
283 dev_err(i2c->dev, "%s: bad status(0x%x)\n", __func__, data);
284 return -EIO;
285 }
286 return 0;
287}
288
289/**
290 * octeon_i2c_write - send data to the bus.
291 * @i2c: The struct octeon_i2c.
292 * @target: Target address.
293 * @data: Pointer to the data to be sent.
294 * @length: Length of the data.
295 *
296 * The address is sent over the bus, then the data.
297 *
298 * Returns 0 on success, otherwise a negative errno.
299 */
300static int octeon_i2c_write(struct octeon_i2c *i2c, int target,
301 const u8 *data, int length)
302{
303 int i, result;
304 u8 tmp;
305
306 result = octeon_i2c_start(i2c);
307 if (result)
308 return result;
309
310 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, target << 1);
311 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
312
313 result = octeon_i2c_wait(i2c);
314 if (result)
315 return result;
316
317 for (i = 0; i < length; i++) {
318 tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
319 if ((tmp != STAT_TXADDR_ACK) && (tmp != STAT_TXDATA_ACK)) {
320 dev_err(i2c->dev,
321 "%s: bad status before write (0x%x)\n",
322 __func__, tmp);
323 return -EIO;
324 }
325
326 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, data[i]);
327 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
328
329 result = octeon_i2c_wait(i2c);
330 if (result)
331 return result;
332 }
333
334 return 0;
335}
336
337/**
338 * octeon_i2c_read - receive data from the bus.
339 * @i2c: The struct octeon_i2c.
340 * @target: Target address.
341 * @data: Pointer to the location to store the datae .
342 * @length: Length of the data.
343 *
344 * The address is sent over the bus, then the data is read.
345 *
346 * Returns 0 on success, otherwise a negative errno.
347 */
348static int octeon_i2c_read(struct octeon_i2c *i2c, int target,
349 u8 *data, int length)
350{
351 int i, result;
352 u8 tmp;
353
354 if (length < 1)
355 return -EINVAL;
356
357 result = octeon_i2c_start(i2c);
358 if (result)
359 return result;
360
361 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, (target<<1) | 1);
362 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
363
364 result = octeon_i2c_wait(i2c);
365 if (result)
366 return result;
367
368 for (i = 0; i < length; i++) {
369 tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
370 if ((tmp != STAT_RXDATA_ACK) && (tmp != STAT_RXADDR_ACK)) {
371 dev_err(i2c->dev,
372 "%s: bad status before read (0x%x)\n",
373 __func__, tmp);
374 return -EIO;
375 }
376
377 if (i+1 < length)
378 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
379 TWSI_CTL_ENAB | TWSI_CTL_AAK);
380 else
381 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
382 TWSI_CTL_ENAB);
383
384 result = octeon_i2c_wait(i2c);
385 if (result)
386 return result;
387
388 data[i] = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_DATA);
389 }
390 return 0;
391}
392
393/**
394 * octeon_i2c_xfer - The driver's master_xfer function.
395 * @adap: Pointer to the i2c_adapter structure.
396 * @msgs: Pointer to the messages to be processed.
397 * @num: Length of the MSGS array.
398 *
399 * Returns the number of messages processed, or a negative errno on
400 * failure.
401 */
402static int octeon_i2c_xfer(struct i2c_adapter *adap,
403 struct i2c_msg *msgs,
404 int num)
405{
406 struct i2c_msg *pmsg;
407 int i;
408 int ret = 0;
409 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
410
411 for (i = 0; ret == 0 && i < num; i++) {
412 pmsg = &msgs[i];
413 dev_dbg(i2c->dev,
414 "Doing %s %d byte(s) to/from 0x%02x - %d of %d messages\n",
415 pmsg->flags & I2C_M_RD ? "read" : "write",
416 pmsg->len, pmsg->addr, i + 1, num);
417 if (pmsg->flags & I2C_M_RD)
418 ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf,
419 pmsg->len);
420 else
421 ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf,
422 pmsg->len);
423 }
424 octeon_i2c_stop(i2c);
425
426 return (ret != 0) ? ret : num;
427}
428
429static u32 octeon_i2c_functionality(struct i2c_adapter *adap)
430{
431 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
432}
433
434static const struct i2c_algorithm octeon_i2c_algo = {
435 .master_xfer = octeon_i2c_xfer,
436 .functionality = octeon_i2c_functionality,
437};
438
439static struct i2c_adapter octeon_i2c_ops = {
440 .owner = THIS_MODULE,
441 .name = "OCTEON adapter",
442 .algo = &octeon_i2c_algo,
443 .timeout = 2,
444};
445
446/**
447 * octeon_i2c_setclock - Calculate and set clock divisors.
448 */
449static int __init octeon_i2c_setclock(struct octeon_i2c *i2c)
450{
451 int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff;
452 int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000;
453
454 for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) {
455 /*
456 * An mdiv value of less than 2 seems to not work well
457 * with ds1337 RTCs, so we constrain it to larger
458 * values.
459 */
460 for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) {
461 /*
462 * For given ndiv and mdiv values check the
463 * two closest thp values.
464 */
465 tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10;
466 tclk *= (1 << ndiv_idx);
467 thp_base = (i2c->sys_freq / (tclk * 2)) - 1;
468 for (inc = 0; inc <= 1; inc++) {
469 thp_idx = thp_base + inc;
470 if (thp_idx < 5 || thp_idx > 0xff)
471 continue;
472
473 foscl = i2c->sys_freq / (2 * (thp_idx + 1));
474 foscl = foscl / (1 << ndiv_idx);
475 foscl = foscl / (mdiv_idx + 1) / 10;
476 diff = abs(foscl - i2c->twsi_freq);
477 if (diff < delta_hz) {
478 delta_hz = diff;
479 thp = thp_idx;
480 mdiv = mdiv_idx;
481 ndiv = ndiv_idx;
482 }
483 }
484 }
485 }
486 octeon_i2c_write_sw(i2c, SW_TWSI_OP_TWSI_CLK, thp);
487 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);
488
489 return 0;
490}
491
492static int __init octeon_i2c_initlowlevel(struct octeon_i2c *i2c)
493{
494 u8 status;
495 int tries;
496
497 /* disable high level controller, enable bus access */
498 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
499
500 /* reset controller */
501 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_RST, 0);
502
503 for (tries = 10; tries; tries--) {
504 udelay(1);
505 status = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
506 if (status == STAT_IDLE)
507 return 0;
508 }
509 dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n", __func__, status);
510 return -EIO;
511}
512
513static int __devinit octeon_i2c_probe(struct platform_device *pdev)
514{
515 int irq, result = 0;
516 struct octeon_i2c *i2c;
517 struct octeon_i2c_data *i2c_data;
518 struct resource *res_mem;
519
520 /* All adaptors have an irq. */
521 irq = platform_get_irq(pdev, 0);
522 if (irq < 0)
523 return irq;
524
525 i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
526 if (!i2c) {
527 dev_err(&pdev->dev, "kzalloc failed\n");
528 result = -ENOMEM;
529 goto out;
530 }
531 i2c->dev = &pdev->dev;
532 i2c_data = pdev->dev.platform_data;
533
534 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
535
536 if (res_mem == NULL) {
537 dev_err(i2c->dev, "found no memory resource\n");
538 result = -ENXIO;
539 goto fail_region;
540 }
541
542 if (i2c_data == NULL) {
543 dev_err(i2c->dev, "no I2C frequency data\n");
544 result = -ENXIO;
545 goto fail_region;
546 }
547
548 i2c->twsi_phys = res_mem->start;
549 i2c->regsize = resource_size(res_mem);
550 i2c->twsi_freq = i2c_data->i2c_freq;
551 i2c->sys_freq = i2c_data->sys_freq;
552
553 if (!request_mem_region(i2c->twsi_phys, i2c->regsize, res_mem->name)) {
554 dev_err(i2c->dev, "request_mem_region failed\n");
555 goto fail_region;
556 }
557 i2c->twsi_base = ioremap(i2c->twsi_phys, i2c->regsize);
558
559 init_waitqueue_head(&i2c->queue);
560
561 i2c->irq = irq;
562
563 result = request_irq(i2c->irq, octeon_i2c_isr, 0, DRV_NAME, i2c);
564 if (result < 0) {
565 dev_err(i2c->dev, "failed to attach interrupt\n");
566 goto fail_irq;
567 }
568
569 result = octeon_i2c_initlowlevel(i2c);
570 if (result) {
571 dev_err(i2c->dev, "init low level failed\n");
572 goto fail_add;
573 }
574
575 result = octeon_i2c_setclock(i2c);
576 if (result) {
577 dev_err(i2c->dev, "clock init failed\n");
578 goto fail_add;
579 }
580
581 i2c->adap = octeon_i2c_ops;
582 i2c->adap.dev.parent = &pdev->dev;
583 i2c->adap.nr = pdev->id >= 0 ? pdev->id : 0;
584 i2c_set_adapdata(&i2c->adap, i2c);
585 platform_set_drvdata(pdev, i2c);
586
587 result = i2c_add_numbered_adapter(&i2c->adap);
588 if (result < 0) {
589 dev_err(i2c->dev, "failed to add adapter\n");
590 goto fail_add;
591 }
592
593 dev_info(i2c->dev, "version %s\n", DRV_VERSION);
594
595 return result;
596
597fail_add:
598 platform_set_drvdata(pdev, NULL);
599 free_irq(i2c->irq, i2c);
600fail_irq:
601 iounmap(i2c->twsi_base);
602 release_mem_region(i2c->twsi_phys, i2c->regsize);
603fail_region:
604 kfree(i2c);
605out:
606 return result;
607};
608
609static int __devexit octeon_i2c_remove(struct platform_device *pdev)
610{
611 struct octeon_i2c *i2c = platform_get_drvdata(pdev);
612
613 i2c_del_adapter(&i2c->adap);
614 platform_set_drvdata(pdev, NULL);
615 free_irq(i2c->irq, i2c);
616 iounmap(i2c->twsi_base);
617 release_mem_region(i2c->twsi_phys, i2c->regsize);
618 kfree(i2c);
619 return 0;
620};
621
622static struct platform_driver octeon_i2c_driver = {
623 .probe = octeon_i2c_probe,
624 .remove = __devexit_p(octeon_i2c_remove),
625 .driver = {
626 .owner = THIS_MODULE,
627 .name = DRV_NAME,
628 },
629};
630
631static int __init octeon_i2c_init(void)
632{
633 int rv;
634
635 rv = platform_driver_register(&octeon_i2c_driver);
636 return rv;
637}
638
639static void __exit octeon_i2c_exit(void)
640{
641 platform_driver_unregister(&octeon_i2c_driver);
642}
643
644MODULE_AUTHOR("Michael Lawnick <michael.lawnick.ext@nsn.com>");
645MODULE_DESCRIPTION("I2C-Bus adapter for Cavium OCTEON processors");
646MODULE_LICENSE("GPL");
647MODULE_VERSION(DRV_VERSION);
648MODULE_ALIAS("platform:" DRV_NAME);
649
650module_init(octeon_i2c_init);
651module_exit(octeon_i2c_exit);
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 0037e31076ba..913abd7c172f 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -49,24 +49,24 @@
49#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000)) 49#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
50 50
51#define OMAP_I2C_REV_REG 0x00 51#define OMAP_I2C_REV_REG 0x00
52#define OMAP_I2C_IE_REG 0x04 52#define OMAP_I2C_IE_REG 0x01
53#define OMAP_I2C_STAT_REG 0x08 53#define OMAP_I2C_STAT_REG 0x02
54#define OMAP_I2C_IV_REG 0x0c 54#define OMAP_I2C_IV_REG 0x03
55/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */ 55/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
56#define OMAP_I2C_WE_REG 0x0c 56#define OMAP_I2C_WE_REG 0x03
57#define OMAP_I2C_SYSS_REG 0x10 57#define OMAP_I2C_SYSS_REG 0x04
58#define OMAP_I2C_BUF_REG 0x14 58#define OMAP_I2C_BUF_REG 0x05
59#define OMAP_I2C_CNT_REG 0x18 59#define OMAP_I2C_CNT_REG 0x06
60#define OMAP_I2C_DATA_REG 0x1c 60#define OMAP_I2C_DATA_REG 0x07
61#define OMAP_I2C_SYSC_REG 0x20 61#define OMAP_I2C_SYSC_REG 0x08
62#define OMAP_I2C_CON_REG 0x24 62#define OMAP_I2C_CON_REG 0x09
63#define OMAP_I2C_OA_REG 0x28 63#define OMAP_I2C_OA_REG 0x0a
64#define OMAP_I2C_SA_REG 0x2c 64#define OMAP_I2C_SA_REG 0x0b
65#define OMAP_I2C_PSC_REG 0x30 65#define OMAP_I2C_PSC_REG 0x0c
66#define OMAP_I2C_SCLL_REG 0x34 66#define OMAP_I2C_SCLL_REG 0x0d
67#define OMAP_I2C_SCLH_REG 0x38 67#define OMAP_I2C_SCLH_REG 0x0e
68#define OMAP_I2C_SYSTEST_REG 0x3c 68#define OMAP_I2C_SYSTEST_REG 0x0f
69#define OMAP_I2C_BUFSTAT_REG 0x40 69#define OMAP_I2C_BUFSTAT_REG 0x10
70 70
71/* I2C Interrupt Enable Register (OMAP_I2C_IE): */ 71/* I2C Interrupt Enable Register (OMAP_I2C_IE): */
72#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */ 72#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
@@ -161,6 +161,7 @@ struct omap_i2c_dev {
161 struct device *dev; 161 struct device *dev;
162 void __iomem *base; /* virtual */ 162 void __iomem *base; /* virtual */
163 int irq; 163 int irq;
164 int reg_shift; /* bit shift for I2C register addresses */
164 struct clk *iclk; /* Interface clock */ 165 struct clk *iclk; /* Interface clock */
165 struct clk *fclk; /* Functional clock */ 166 struct clk *fclk; /* Functional clock */
166 struct completion cmd_complete; 167 struct completion cmd_complete;
@@ -189,12 +190,12 @@ struct omap_i2c_dev {
189static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev, 190static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
190 int reg, u16 val) 191 int reg, u16 val)
191{ 192{
192 __raw_writew(val, i2c_dev->base + reg); 193 __raw_writew(val, i2c_dev->base + (reg << i2c_dev->reg_shift));
193} 194}
194 195
195static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg) 196static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
196{ 197{
197 return __raw_readw(i2c_dev->base + reg); 198 return __raw_readw(i2c_dev->base + (reg << i2c_dev->reg_shift));
198} 199}
199 200
200static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev) 201static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
@@ -924,6 +925,11 @@ omap_i2c_probe(struct platform_device *pdev)
924 dev->b_hw = 1; /* Enable hardware fixes */ 925 dev->b_hw = 1; /* Enable hardware fixes */
925 } 926 }
926 927
928 if (cpu_is_omap7xx())
929 dev->reg_shift = 1;
930 else
931 dev->reg_shift = 2;
932
927 /* reset ASAP, clearing any IRQs */ 933 /* reset ASAP, clearing any IRQs */
928 omap_i2c_init(dev); 934 omap_i2c_init(dev);
929 935
diff --git a/drivers/i2c/busses/i2c-parport-light.c b/drivers/i2c/busses/i2c-parport-light.c
index 322c5691e38e..5f41ec0f72d2 100644
--- a/drivers/i2c/busses/i2c-parport-light.c
+++ b/drivers/i2c/busses/i2c-parport-light.c
@@ -1,7 +1,7 @@
1/* ------------------------------------------------------------------------ * 1/* ------------------------------------------------------------------------ *
2 * i2c-parport-light.c I2C bus over parallel port * 2 * i2c-parport-light.c I2C bus over parallel port *
3 * ------------------------------------------------------------------------ * 3 * ------------------------------------------------------------------------ *
4 Copyright (C) 2003-2007 Jean Delvare <khali@linux-fr.org> 4 Copyright (C) 2003-2010 Jean Delvare <khali@linux-fr.org>
5 5
6 Based on older i2c-velleman.c driver 6 Based on older i2c-velleman.c driver
7 Copyright (C) 1995-2000 Simon G. Vogl 7 Copyright (C) 1995-2000 Simon G. Vogl
@@ -27,10 +27,12 @@
27#include <linux/kernel.h> 27#include <linux/kernel.h>
28#include <linux/module.h> 28#include <linux/module.h>
29#include <linux/init.h> 29#include <linux/init.h>
30#include <linux/delay.h>
30#include <linux/platform_device.h> 31#include <linux/platform_device.h>
31#include <linux/ioport.h> 32#include <linux/ioport.h>
32#include <linux/i2c.h> 33#include <linux/i2c.h>
33#include <linux/i2c-algo-bit.h> 34#include <linux/i2c-algo-bit.h>
35#include <linux/i2c-smbus.h>
34#include <asm/io.h> 36#include <asm/io.h>
35#include "i2c-parport.h" 37#include "i2c-parport.h"
36 38
@@ -43,6 +45,10 @@ static u16 base;
43module_param(base, ushort, 0); 45module_param(base, ushort, 0);
44MODULE_PARM_DESC(base, "Base I/O address"); 46MODULE_PARM_DESC(base, "Base I/O address");
45 47
48static int irq;
49module_param(irq, int, 0);
50MODULE_PARM_DESC(irq, "IRQ (optional)");
51
46/* ----- Low-level parallel port access ----------------------------------- */ 52/* ----- Low-level parallel port access ----------------------------------- */
47 53
48static inline void port_write(unsigned char p, unsigned char d) 54static inline void port_write(unsigned char p, unsigned char d)
@@ -119,6 +125,16 @@ static struct i2c_adapter parport_adapter = {
119 .name = "Parallel port adapter (light)", 125 .name = "Parallel port adapter (light)",
120}; 126};
121 127
128/* SMBus alert support */
129static struct i2c_smbus_alert_setup alert_data = {
130 .alert_edge_triggered = 1,
131};
132static struct i2c_client *ara;
133static struct lineop parport_ctrl_irq = {
134 .val = (1 << 4),
135 .port = CTRL,
136};
137
122static int __devinit i2c_parport_probe(struct platform_device *pdev) 138static int __devinit i2c_parport_probe(struct platform_device *pdev)
123{ 139{
124 int err; 140 int err;
@@ -127,18 +143,39 @@ static int __devinit i2c_parport_probe(struct platform_device *pdev)
127 parport_setsda(NULL, 1); 143 parport_setsda(NULL, 1);
128 parport_setscl(NULL, 1); 144 parport_setscl(NULL, 1);
129 /* Other init if needed (power on...) */ 145 /* Other init if needed (power on...) */
130 if (adapter_parm[type].init.val) 146 if (adapter_parm[type].init.val) {
131 line_set(1, &adapter_parm[type].init); 147 line_set(1, &adapter_parm[type].init);
148 /* Give powered devices some time to settle */
149 msleep(100);
150 }
132 151
133 parport_adapter.dev.parent = &pdev->dev; 152 parport_adapter.dev.parent = &pdev->dev;
134 err = i2c_bit_add_bus(&parport_adapter); 153 err = i2c_bit_add_bus(&parport_adapter);
135 if (err) 154 if (err) {
136 dev_err(&pdev->dev, "Unable to register with I2C\n"); 155 dev_err(&pdev->dev, "Unable to register with I2C\n");
137 return err; 156 return err;
157 }
158
159 /* Setup SMBus alert if supported */
160 if (adapter_parm[type].smbus_alert && irq) {
161 alert_data.irq = irq;
162 ara = i2c_setup_smbus_alert(&parport_adapter, &alert_data);
163 if (ara)
164 line_set(1, &parport_ctrl_irq);
165 else
166 dev_warn(&pdev->dev, "Failed to register ARA client\n");
167 }
168
169 return 0;
138} 170}
139 171
140static int __devexit i2c_parport_remove(struct platform_device *pdev) 172static int __devexit i2c_parport_remove(struct platform_device *pdev)
141{ 173{
174 if (ara) {
175 line_set(0, &parport_ctrl_irq);
176 i2c_unregister_device(ara);
177 ara = NULL;
178 }
142 i2c_del_adapter(&parport_adapter); 179 i2c_del_adapter(&parport_adapter);
143 180
144 /* Un-init if needed (power off...) */ 181 /* Un-init if needed (power off...) */
@@ -205,6 +242,9 @@ static int __init i2c_parport_init(void)
205 if (!request_region(base, 3, DRVNAME)) 242 if (!request_region(base, 3, DRVNAME))
206 return -EBUSY; 243 return -EBUSY;
207 244
245 if (irq != 0)
246 pr_info(DRVNAME ": using irq %d\n", irq);
247
208 if (!adapter_parm[type].getscl.val) 248 if (!adapter_parm[type].getscl.val)
209 parport_algo_data.getscl = NULL; 249 parport_algo_data.getscl = NULL;
210 250
diff --git a/drivers/i2c/busses/i2c-parport.c b/drivers/i2c/busses/i2c-parport.c
index 0d8998610c74..220fca7f23a6 100644
--- a/drivers/i2c/busses/i2c-parport.c
+++ b/drivers/i2c/busses/i2c-parport.c
@@ -1,7 +1,7 @@
1/* ------------------------------------------------------------------------ * 1/* ------------------------------------------------------------------------ *
2 * i2c-parport.c I2C bus over parallel port * 2 * i2c-parport.c I2C bus over parallel port *
3 * ------------------------------------------------------------------------ * 3 * ------------------------------------------------------------------------ *
4 Copyright (C) 2003-2007 Jean Delvare <khali@linux-fr.org> 4 Copyright (C) 2003-2010 Jean Delvare <khali@linux-fr.org>
5 5
6 Based on older i2c-philips-par.c driver 6 Based on older i2c-philips-par.c driver
7 Copyright (C) 1995-2000 Simon G. Vogl 7 Copyright (C) 1995-2000 Simon G. Vogl
@@ -27,9 +27,11 @@
27#include <linux/kernel.h> 27#include <linux/kernel.h>
28#include <linux/module.h> 28#include <linux/module.h>
29#include <linux/init.h> 29#include <linux/init.h>
30#include <linux/delay.h>
30#include <linux/parport.h> 31#include <linux/parport.h>
31#include <linux/i2c.h> 32#include <linux/i2c.h>
32#include <linux/i2c-algo-bit.h> 33#include <linux/i2c-algo-bit.h>
34#include <linux/i2c-smbus.h>
33#include "i2c-parport.h" 35#include "i2c-parport.h"
34 36
35/* ----- Device list ------------------------------------------------------ */ 37/* ----- Device list ------------------------------------------------------ */
@@ -38,6 +40,8 @@ struct i2c_par {
38 struct pardevice *pdev; 40 struct pardevice *pdev;
39 struct i2c_adapter adapter; 41 struct i2c_adapter adapter;
40 struct i2c_algo_bit_data algo_data; 42 struct i2c_algo_bit_data algo_data;
43 struct i2c_smbus_alert_setup alert_data;
44 struct i2c_client *ara;
41 struct i2c_par *next; 45 struct i2c_par *next;
42}; 46};
43 47
@@ -143,6 +147,19 @@ static struct i2c_algo_bit_data parport_algo_data = {
143 147
144/* ----- I2c and parallel port call-back functions and structures --------- */ 148/* ----- I2c and parallel port call-back functions and structures --------- */
145 149
150void i2c_parport_irq(void *data)
151{
152 struct i2c_par *adapter = data;
153 struct i2c_client *ara = adapter->ara;
154
155 if (ara) {
156 dev_dbg(&ara->dev, "SMBus alert received\n");
157 i2c_handle_smbus_alert(ara);
158 } else
159 dev_dbg(&adapter->adapter.dev,
160 "SMBus alert received but no ARA client!\n");
161}
162
146static void i2c_parport_attach (struct parport *port) 163static void i2c_parport_attach (struct parport *port)
147{ 164{
148 struct i2c_par *adapter; 165 struct i2c_par *adapter;
@@ -154,8 +171,9 @@ static void i2c_parport_attach (struct parport *port)
154 } 171 }
155 172
156 pr_debug("i2c-parport: attaching to %s\n", port->name); 173 pr_debug("i2c-parport: attaching to %s\n", port->name);
174 parport_disable_irq(port);
157 adapter->pdev = parport_register_device(port, "i2c-parport", 175 adapter->pdev = parport_register_device(port, "i2c-parport",
158 NULL, NULL, NULL, PARPORT_FLAG_EXCL, NULL); 176 NULL, NULL, i2c_parport_irq, PARPORT_FLAG_EXCL, adapter);
159 if (!adapter->pdev) { 177 if (!adapter->pdev) {
160 printk(KERN_ERR "i2c-parport: Unable to register with parport\n"); 178 printk(KERN_ERR "i2c-parport: Unable to register with parport\n");
161 goto ERROR0; 179 goto ERROR0;
@@ -185,14 +203,29 @@ static void i2c_parport_attach (struct parport *port)
185 parport_setsda(port, 1); 203 parport_setsda(port, 1);
186 parport_setscl(port, 1); 204 parport_setscl(port, 1);
187 /* Other init if needed (power on...) */ 205 /* Other init if needed (power on...) */
188 if (adapter_parm[type].init.val) 206 if (adapter_parm[type].init.val) {
189 line_set(port, 1, &adapter_parm[type].init); 207 line_set(port, 1, &adapter_parm[type].init);
208 /* Give powered devices some time to settle */
209 msleep(100);
210 }
190 211
191 if (i2c_bit_add_bus(&adapter->adapter) < 0) { 212 if (i2c_bit_add_bus(&adapter->adapter) < 0) {
192 printk(KERN_ERR "i2c-parport: Unable to register with I2C\n"); 213 printk(KERN_ERR "i2c-parport: Unable to register with I2C\n");
193 goto ERROR1; 214 goto ERROR1;
194 } 215 }
195 216
217 /* Setup SMBus alert if supported */
218 if (adapter_parm[type].smbus_alert) {
219 adapter->alert_data.alert_edge_triggered = 1;
220 adapter->ara = i2c_setup_smbus_alert(&adapter->adapter,
221 &adapter->alert_data);
222 if (adapter->ara)
223 parport_enable_irq(port);
224 else
225 printk(KERN_WARNING "i2c-parport: Failed to register "
226 "ARA client\n");
227 }
228
196 /* Add the new adapter to the list */ 229 /* Add the new adapter to the list */
197 adapter->next = adapter_list; 230 adapter->next = adapter_list;
198 adapter_list = adapter; 231 adapter_list = adapter;
@@ -213,6 +246,10 @@ static void i2c_parport_detach (struct parport *port)
213 for (prev = NULL, adapter = adapter_list; adapter; 246 for (prev = NULL, adapter = adapter_list; adapter;
214 prev = adapter, adapter = adapter->next) { 247 prev = adapter, adapter = adapter->next) {
215 if (adapter->pdev->port == port) { 248 if (adapter->pdev->port == port) {
249 if (adapter->ara) {
250 parport_disable_irq(port);
251 i2c_unregister_device(adapter->ara);
252 }
216 i2c_del_adapter(&adapter->adapter); 253 i2c_del_adapter(&adapter->adapter);
217 254
218 /* Un-init if needed (power off...) */ 255 /* Un-init if needed (power off...) */
diff --git a/drivers/i2c/busses/i2c-parport.h b/drivers/i2c/busses/i2c-parport.h
index ed69d846cb95..a9f66816546c 100644
--- a/drivers/i2c/busses/i2c-parport.h
+++ b/drivers/i2c/busses/i2c-parport.h
@@ -1,7 +1,7 @@
1/* ------------------------------------------------------------------------ * 1/* ------------------------------------------------------------------------ *
2 * i2c-parport.h I2C bus over parallel port * 2 * i2c-parport.h I2C bus over parallel port *
3 * ------------------------------------------------------------------------ * 3 * ------------------------------------------------------------------------ *
4 Copyright (C) 2003-2004 Jean Delvare <khali@linux-fr.org> 4 Copyright (C) 2003-2010 Jean Delvare <khali@linux-fr.org>
5 5
6 This program is free software; you can redistribute it and/or modify 6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by 7 it under the terms of the GNU General Public License as published by
@@ -38,6 +38,7 @@ struct adapter_parm {
38 struct lineop getsda; 38 struct lineop getsda;
39 struct lineop getscl; 39 struct lineop getscl;
40 struct lineop init; 40 struct lineop init;
41 unsigned int smbus_alert:1;
41}; 42};
42 43
43static struct adapter_parm adapter_parm[] = { 44static struct adapter_parm adapter_parm[] = {
@@ -73,6 +74,7 @@ static struct adapter_parm adapter_parm[] = {
73 .setscl = { 0x01, DATA, 1 }, 74 .setscl = { 0x01, DATA, 1 },
74 .getsda = { 0x10, STAT, 1 }, 75 .getsda = { 0x10, STAT, 1 },
75 .init = { 0xf0, DATA, 0 }, 76 .init = { 0xf0, DATA, 0 },
77 .smbus_alert = 1,
76 }, 78 },
77 /* type 5: ADM1025, ADM1030 and ADM1031 evaluation boards */ 79 /* type 5: ADM1025, ADM1030 and ADM1031 evaluation boards */
78 { 80 {
diff --git a/drivers/i2c/busses/i2c-pasemi.c b/drivers/i2c/busses/i2c-pasemi.c
index adf0fbb902f0..0d20ff46a518 100644
--- a/drivers/i2c/busses/i2c-pasemi.c
+++ b/drivers/i2c/busses/i2c-pasemi.c
@@ -400,7 +400,7 @@ static void __devexit pasemi_smb_remove(struct pci_dev *dev)
400 kfree(smbus); 400 kfree(smbus);
401} 401}
402 402
403static struct pci_device_id pasemi_smb_ids[] = { 403static const struct pci_device_id pasemi_smb_ids[] = {
404 { PCI_DEVICE(0x1959, 0xa003) }, 404 { PCI_DEVICE(0x1959, 0xa003) },
405 { 0, } 405 { 0, }
406}; 406};
diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c
index e56e4b6823ca..ee9da6fcf69a 100644
--- a/drivers/i2c/busses/i2c-piix4.c
+++ b/drivers/i2c/busses/i2c-piix4.c
@@ -472,7 +472,7 @@ static struct i2c_adapter piix4_adapter = {
472 .algo = &smbus_algorithm, 472 .algo = &smbus_algorithm,
473}; 473};
474 474
475static struct pci_device_id piix4_ids[] = { 475static const struct pci_device_id piix4_ids[] = {
476 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) }, 476 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) },
477 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) }, 477 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) },
478 { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) }, 478 { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) },
diff --git a/drivers/i2c/busses/i2c-pnx.c b/drivers/i2c/busses/i2c-pnx.c
index 5d1c2603a130..9532dee6b580 100644
--- a/drivers/i2c/busses/i2c-pnx.c
+++ b/drivers/i2c/busses/i2c-pnx.c
@@ -20,15 +20,15 @@
20#include <linux/platform_device.h> 20#include <linux/platform_device.h>
21#include <linux/i2c-pnx.h> 21#include <linux/i2c-pnx.h>
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/err.h>
24#include <linux/clk.h>
25
23#include <mach/hardware.h> 26#include <mach/hardware.h>
24#include <mach/i2c.h> 27#include <mach/i2c.h>
25#include <asm/irq.h>
26#include <asm/uaccess.h>
27 28
28#define I2C_PNX_TIMEOUT 10 /* msec */ 29#define I2C_PNX_TIMEOUT 10 /* msec */
29#define I2C_PNX_SPEED_KHZ 100 30#define I2C_PNX_SPEED_KHZ 100
30#define I2C_PNX_REGION_SIZE 0x100 31#define I2C_PNX_REGION_SIZE 0x100
31#define PNX_DEFAULT_FREQ 13 /* MHz */
32 32
33static inline int wait_timeout(long timeout, struct i2c_pnx_algo_data *data) 33static inline int wait_timeout(long timeout, struct i2c_pnx_algo_data *data)
34{ 34{
@@ -50,22 +50,21 @@ static inline int wait_reset(long timeout, struct i2c_pnx_algo_data *data)
50 return (timeout <= 0); 50 return (timeout <= 0);
51} 51}
52 52
53static inline void i2c_pnx_arm_timer(struct i2c_adapter *adap) 53static inline void i2c_pnx_arm_timer(struct i2c_pnx_algo_data *alg_data)
54{ 54{
55 struct i2c_pnx_algo_data *data = adap->algo_data; 55 struct timer_list *timer = &alg_data->mif.timer;
56 struct timer_list *timer = &data->mif.timer; 56 unsigned long expires = msecs_to_jiffies(I2C_PNX_TIMEOUT);
57 int expires = I2C_PNX_TIMEOUT / (1000 / HZ);
58 57
59 if (expires <= 1) 58 if (expires <= 1)
60 expires = 2; 59 expires = 2;
61 60
62 del_timer_sync(timer); 61 del_timer_sync(timer);
63 62
64 dev_dbg(&adap->dev, "Timer armed at %lu plus %u jiffies.\n", 63 dev_dbg(&alg_data->adapter.dev, "Timer armed at %lu plus %lu jiffies.\n",
65 jiffies, expires); 64 jiffies, expires);
66 65
67 timer->expires = jiffies + expires; 66 timer->expires = jiffies + expires;
68 timer->data = (unsigned long)adap; 67 timer->data = (unsigned long)&alg_data;
69 68
70 add_timer(timer); 69 add_timer(timer);
71} 70}
@@ -77,34 +76,34 @@ static inline void i2c_pnx_arm_timer(struct i2c_adapter *adap)
77 * 76 *
78 * Generate a START signal in the desired mode. 77 * Generate a START signal in the desired mode.
79 */ 78 */
80static int i2c_pnx_start(unsigned char slave_addr, struct i2c_adapter *adap) 79static int i2c_pnx_start(unsigned char slave_addr,
80 struct i2c_pnx_algo_data *alg_data)
81{ 81{
82 struct i2c_pnx_algo_data *alg_data = adap->algo_data; 82 dev_dbg(&alg_data->adapter.dev, "%s(): addr 0x%x mode %d\n", __func__,
83
84 dev_dbg(&adap->dev, "%s(): addr 0x%x mode %d\n", __func__,
85 slave_addr, alg_data->mif.mode); 83 slave_addr, alg_data->mif.mode);
86 84
87 /* Check for 7 bit slave addresses only */ 85 /* Check for 7 bit slave addresses only */
88 if (slave_addr & ~0x7f) { 86 if (slave_addr & ~0x7f) {
89 dev_err(&adap->dev, "%s: Invalid slave address %x. " 87 dev_err(&alg_data->adapter.dev,
90 "Only 7-bit addresses are supported\n", 88 "%s: Invalid slave address %x. Only 7-bit addresses are supported\n",
91 adap->name, slave_addr); 89 alg_data->adapter.name, slave_addr);
92 return -EINVAL; 90 return -EINVAL;
93 } 91 }
94 92
95 /* First, make sure bus is idle */ 93 /* First, make sure bus is idle */
96 if (wait_timeout(I2C_PNX_TIMEOUT, alg_data)) { 94 if (wait_timeout(I2C_PNX_TIMEOUT, alg_data)) {
97 /* Somebody else is monopolizing the bus */ 95 /* Somebody else is monopolizing the bus */
98 dev_err(&adap->dev, "%s: Bus busy. Slave addr = %02x, " 96 dev_err(&alg_data->adapter.dev,
99 "cntrl = %x, stat = %x\n", 97 "%s: Bus busy. Slave addr = %02x, cntrl = %x, stat = %x\n",
100 adap->name, slave_addr, 98 alg_data->adapter.name, slave_addr,
101 ioread32(I2C_REG_CTL(alg_data)), 99 ioread32(I2C_REG_CTL(alg_data)),
102 ioread32(I2C_REG_STS(alg_data))); 100 ioread32(I2C_REG_STS(alg_data)));
103 return -EBUSY; 101 return -EBUSY;
104 } else if (ioread32(I2C_REG_STS(alg_data)) & mstatus_afi) { 102 } else if (ioread32(I2C_REG_STS(alg_data)) & mstatus_afi) {
105 /* Sorry, we lost the bus */ 103 /* Sorry, we lost the bus */
106 dev_err(&adap->dev, "%s: Arbitration failure. " 104 dev_err(&alg_data->adapter.dev,
107 "Slave addr = %02x\n", adap->name, slave_addr); 105 "%s: Arbitration failure. Slave addr = %02x\n",
106 alg_data->adapter.name, slave_addr);
108 return -EIO; 107 return -EIO;
109 } 108 }
110 109
@@ -115,14 +114,14 @@ static int i2c_pnx_start(unsigned char slave_addr, struct i2c_adapter *adap)
115 iowrite32(ioread32(I2C_REG_STS(alg_data)) | mstatus_tdi | mstatus_afi, 114 iowrite32(ioread32(I2C_REG_STS(alg_data)) | mstatus_tdi | mstatus_afi,
116 I2C_REG_STS(alg_data)); 115 I2C_REG_STS(alg_data));
117 116
118 dev_dbg(&adap->dev, "%s(): sending %#x\n", __func__, 117 dev_dbg(&alg_data->adapter.dev, "%s(): sending %#x\n", __func__,
119 (slave_addr << 1) | start_bit | alg_data->mif.mode); 118 (slave_addr << 1) | start_bit | alg_data->mif.mode);
120 119
121 /* Write the slave address, START bit and R/W bit */ 120 /* Write the slave address, START bit and R/W bit */
122 iowrite32((slave_addr << 1) | start_bit | alg_data->mif.mode, 121 iowrite32((slave_addr << 1) | start_bit | alg_data->mif.mode,
123 I2C_REG_TX(alg_data)); 122 I2C_REG_TX(alg_data));
124 123
125 dev_dbg(&adap->dev, "%s(): exit\n", __func__); 124 dev_dbg(&alg_data->adapter.dev, "%s(): exit\n", __func__);
126 125
127 return 0; 126 return 0;
128} 127}
@@ -133,13 +132,12 @@ static int i2c_pnx_start(unsigned char slave_addr, struct i2c_adapter *adap)
133 * 132 *
134 * Generate a STOP signal to terminate the master transaction. 133 * Generate a STOP signal to terminate the master transaction.
135 */ 134 */
136static void i2c_pnx_stop(struct i2c_adapter *adap) 135static void i2c_pnx_stop(struct i2c_pnx_algo_data *alg_data)
137{ 136{
138 struct i2c_pnx_algo_data *alg_data = adap->algo_data;
139 /* Only 1 msec max timeout due to interrupt context */ 137 /* Only 1 msec max timeout due to interrupt context */
140 long timeout = 1000; 138 long timeout = 1000;
141 139
142 dev_dbg(&adap->dev, "%s(): entering: stat = %04x.\n", 140 dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n",
143 __func__, ioread32(I2C_REG_STS(alg_data))); 141 __func__, ioread32(I2C_REG_STS(alg_data)));
144 142
145 /* Write a STOP bit to TX FIFO */ 143 /* Write a STOP bit to TX FIFO */
@@ -153,7 +151,7 @@ static void i2c_pnx_stop(struct i2c_adapter *adap)
153 timeout--; 151 timeout--;
154 } 152 }
155 153
156 dev_dbg(&adap->dev, "%s(): exiting: stat = %04x.\n", 154 dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n",
157 __func__, ioread32(I2C_REG_STS(alg_data))); 155 __func__, ioread32(I2C_REG_STS(alg_data)));
158} 156}
159 157
@@ -163,36 +161,29 @@ static void i2c_pnx_stop(struct i2c_adapter *adap)
163 * 161 *
164 * Sends one byte of data to the slave 162 * Sends one byte of data to the slave
165 */ 163 */
166static int i2c_pnx_master_xmit(struct i2c_adapter *adap) 164static int i2c_pnx_master_xmit(struct i2c_pnx_algo_data *alg_data)
167{ 165{
168 struct i2c_pnx_algo_data *alg_data = adap->algo_data;
169 u32 val; 166 u32 val;
170 167
171 dev_dbg(&adap->dev, "%s(): entering: stat = %04x.\n", 168 dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n",
172 __func__, ioread32(I2C_REG_STS(alg_data))); 169 __func__, ioread32(I2C_REG_STS(alg_data)));
173 170
174 if (alg_data->mif.len > 0) { 171 if (alg_data->mif.len > 0) {
175 /* We still have something to talk about... */ 172 /* We still have something to talk about... */
176 val = *alg_data->mif.buf++; 173 val = *alg_data->mif.buf++;
177 174
178 if (alg_data->mif.len == 1) {
179 val |= stop_bit;
180 if (!alg_data->last)
181 val |= start_bit;
182 }
183
184 alg_data->mif.len--; 175 alg_data->mif.len--;
185 iowrite32(val, I2C_REG_TX(alg_data)); 176 iowrite32(val, I2C_REG_TX(alg_data));
186 177
187 dev_dbg(&adap->dev, "%s(): xmit %#x [%d]\n", __func__, 178 dev_dbg(&alg_data->adapter.dev, "%s(): xmit %#x [%d]\n",
188 val, alg_data->mif.len + 1); 179 __func__, val, alg_data->mif.len + 1);
189 180
190 if (alg_data->mif.len == 0) { 181 if (alg_data->mif.len == 0) {
191 if (alg_data->last) { 182 if (alg_data->last) {
192 /* Wait until the STOP is seen. */ 183 /* Wait until the STOP is seen. */
193 if (wait_timeout(I2C_PNX_TIMEOUT, alg_data)) 184 if (wait_timeout(I2C_PNX_TIMEOUT, alg_data))
194 dev_err(&adap->dev, "The bus is still " 185 dev_err(&alg_data->adapter.dev,
195 "active after timeout\n"); 186 "The bus is still active after timeout\n");
196 } 187 }
197 /* Disable master interrupts */ 188 /* Disable master interrupts */
198 iowrite32(ioread32(I2C_REG_CTL(alg_data)) & 189 iowrite32(ioread32(I2C_REG_CTL(alg_data)) &
@@ -201,14 +192,15 @@ static int i2c_pnx_master_xmit(struct i2c_adapter *adap)
201 192
202 del_timer_sync(&alg_data->mif.timer); 193 del_timer_sync(&alg_data->mif.timer);
203 194
204 dev_dbg(&adap->dev, "%s(): Waking up xfer routine.\n", 195 dev_dbg(&alg_data->adapter.dev,
196 "%s(): Waking up xfer routine.\n",
205 __func__); 197 __func__);
206 198
207 complete(&alg_data->mif.complete); 199 complete(&alg_data->mif.complete);
208 } 200 }
209 } else if (alg_data->mif.len == 0) { 201 } else if (alg_data->mif.len == 0) {
210 /* zero-sized transfer */ 202 /* zero-sized transfer */
211 i2c_pnx_stop(adap); 203 i2c_pnx_stop(alg_data);
212 204
213 /* Disable master interrupts. */ 205 /* Disable master interrupts. */
214 iowrite32(ioread32(I2C_REG_CTL(alg_data)) & 206 iowrite32(ioread32(I2C_REG_CTL(alg_data)) &
@@ -217,13 +209,14 @@ static int i2c_pnx_master_xmit(struct i2c_adapter *adap)
217 209
218 /* Stop timer. */ 210 /* Stop timer. */
219 del_timer_sync(&alg_data->mif.timer); 211 del_timer_sync(&alg_data->mif.timer);
220 dev_dbg(&adap->dev, "%s(): Waking up xfer routine after " 212 dev_dbg(&alg_data->adapter.dev,
221 "zero-xfer.\n", __func__); 213 "%s(): Waking up xfer routine after zero-xfer.\n",
214 __func__);
222 215
223 complete(&alg_data->mif.complete); 216 complete(&alg_data->mif.complete);
224 } 217 }
225 218
226 dev_dbg(&adap->dev, "%s(): exiting: stat = %04x.\n", 219 dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n",
227 __func__, ioread32(I2C_REG_STS(alg_data))); 220 __func__, ioread32(I2C_REG_STS(alg_data)));
228 221
229 return 0; 222 return 0;
@@ -235,28 +228,23 @@ static int i2c_pnx_master_xmit(struct i2c_adapter *adap)
235 * 228 *
236 * Reads one byte data from the slave 229 * Reads one byte data from the slave
237 */ 230 */
238static int i2c_pnx_master_rcv(struct i2c_adapter *adap) 231static int i2c_pnx_master_rcv(struct i2c_pnx_algo_data *alg_data)
239{ 232{
240 struct i2c_pnx_algo_data *alg_data = adap->algo_data;
241 unsigned int val = 0; 233 unsigned int val = 0;
242 u32 ctl = 0; 234 u32 ctl = 0;
243 235
244 dev_dbg(&adap->dev, "%s(): entering: stat = %04x.\n", 236 dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n",
245 __func__, ioread32(I2C_REG_STS(alg_data))); 237 __func__, ioread32(I2C_REG_STS(alg_data)));
246 238
247 /* Check, whether there is already data, 239 /* Check, whether there is already data,
248 * or we didn't 'ask' for it yet. 240 * or we didn't 'ask' for it yet.
249 */ 241 */
250 if (ioread32(I2C_REG_STS(alg_data)) & mstatus_rfe) { 242 if (ioread32(I2C_REG_STS(alg_data)) & mstatus_rfe) {
251 dev_dbg(&adap->dev, "%s(): Write dummy data to fill " 243 dev_dbg(&alg_data->adapter.dev,
252 "Rx-fifo...\n", __func__); 244 "%s(): Write dummy data to fill Rx-fifo...\n",
245 __func__);
253 246
254 if (alg_data->mif.len == 1) { 247 if (alg_data->mif.len == 1) {
255 /* Last byte, do not acknowledge next rcv. */
256 val |= stop_bit;
257 if (!alg_data->last)
258 val |= start_bit;
259
260 /* 248 /*
261 * Enable interrupt RFDAIE (data in Rx fifo), 249 * Enable interrupt RFDAIE (data in Rx fifo),
262 * and disable DRMIE (need data for Tx) 250 * and disable DRMIE (need data for Tx)
@@ -281,16 +269,16 @@ static int i2c_pnx_master_rcv(struct i2c_adapter *adap)
281 if (alg_data->mif.len > 0) { 269 if (alg_data->mif.len > 0) {
282 val = ioread32(I2C_REG_RX(alg_data)); 270 val = ioread32(I2C_REG_RX(alg_data));
283 *alg_data->mif.buf++ = (u8) (val & 0xff); 271 *alg_data->mif.buf++ = (u8) (val & 0xff);
284 dev_dbg(&adap->dev, "%s(): rcv 0x%x [%d]\n", __func__, val, 272 dev_dbg(&alg_data->adapter.dev, "%s(): rcv 0x%x [%d]\n",
285 alg_data->mif.len); 273 __func__, val, alg_data->mif.len);
286 274
287 alg_data->mif.len--; 275 alg_data->mif.len--;
288 if (alg_data->mif.len == 0) { 276 if (alg_data->mif.len == 0) {
289 if (alg_data->last) 277 if (alg_data->last)
290 /* Wait until the STOP is seen. */ 278 /* Wait until the STOP is seen. */
291 if (wait_timeout(I2C_PNX_TIMEOUT, alg_data)) 279 if (wait_timeout(I2C_PNX_TIMEOUT, alg_data))
292 dev_err(&adap->dev, "The bus is still " 280 dev_err(&alg_data->adapter.dev,
293 "active after timeout\n"); 281 "The bus is still active after timeout\n");
294 282
295 /* Disable master interrupts */ 283 /* Disable master interrupts */
296 ctl = ioread32(I2C_REG_CTL(alg_data)); 284 ctl = ioread32(I2C_REG_CTL(alg_data));
@@ -304,7 +292,7 @@ static int i2c_pnx_master_rcv(struct i2c_adapter *adap)
304 } 292 }
305 } 293 }
306 294
307 dev_dbg(&adap->dev, "%s(): exiting: stat = %04x.\n", 295 dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n",
308 __func__, ioread32(I2C_REG_STS(alg_data))); 296 __func__, ioread32(I2C_REG_STS(alg_data)));
309 297
310 return 0; 298 return 0;
@@ -312,11 +300,11 @@ static int i2c_pnx_master_rcv(struct i2c_adapter *adap)
312 300
313static irqreturn_t i2c_pnx_interrupt(int irq, void *dev_id) 301static irqreturn_t i2c_pnx_interrupt(int irq, void *dev_id)
314{ 302{
303 struct i2c_pnx_algo_data *alg_data = dev_id;
315 u32 stat, ctl; 304 u32 stat, ctl;
316 struct i2c_adapter *adap = dev_id;
317 struct i2c_pnx_algo_data *alg_data = adap->algo_data;
318 305
319 dev_dbg(&adap->dev, "%s(): mstat = %x mctrl = %x, mode = %d\n", 306 dev_dbg(&alg_data->adapter.dev,
307 "%s(): mstat = %x mctrl = %x, mode = %d\n",
320 __func__, 308 __func__,
321 ioread32(I2C_REG_STS(alg_data)), 309 ioread32(I2C_REG_STS(alg_data)),
322 ioread32(I2C_REG_CTL(alg_data)), 310 ioread32(I2C_REG_CTL(alg_data)),
@@ -339,10 +327,10 @@ static irqreturn_t i2c_pnx_interrupt(int irq, void *dev_id)
339 complete(&alg_data->mif.complete); 327 complete(&alg_data->mif.complete);
340 } else if (stat & mstatus_nai) { 328 } else if (stat & mstatus_nai) {
341 /* Slave did not acknowledge, generate a STOP */ 329 /* Slave did not acknowledge, generate a STOP */
342 dev_dbg(&adap->dev, "%s(): " 330 dev_dbg(&alg_data->adapter.dev,
343 "Slave did not acknowledge, generating a STOP.\n", 331 "%s(): Slave did not acknowledge, generating a STOP.\n",
344 __func__); 332 __func__);
345 i2c_pnx_stop(adap); 333 i2c_pnx_stop(alg_data);
346 334
347 /* Disable master interrupts. */ 335 /* Disable master interrupts. */
348 ctl = ioread32(I2C_REG_CTL(alg_data)); 336 ctl = ioread32(I2C_REG_CTL(alg_data));
@@ -368,9 +356,9 @@ static irqreturn_t i2c_pnx_interrupt(int irq, void *dev_id)
368 */ 356 */
369 if ((stat & mstatus_drmi) || !(stat & mstatus_rfe)) { 357 if ((stat & mstatus_drmi) || !(stat & mstatus_rfe)) {
370 if (alg_data->mif.mode == I2C_SMBUS_WRITE) { 358 if (alg_data->mif.mode == I2C_SMBUS_WRITE) {
371 i2c_pnx_master_xmit(adap); 359 i2c_pnx_master_xmit(alg_data);
372 } else if (alg_data->mif.mode == I2C_SMBUS_READ) { 360 } else if (alg_data->mif.mode == I2C_SMBUS_READ) {
373 i2c_pnx_master_rcv(adap); 361 i2c_pnx_master_rcv(alg_data);
374 } 362 }
375 } 363 }
376 } 364 }
@@ -379,7 +367,8 @@ static irqreturn_t i2c_pnx_interrupt(int irq, void *dev_id)
379 stat = ioread32(I2C_REG_STS(alg_data)); 367 stat = ioread32(I2C_REG_STS(alg_data));
380 iowrite32(stat | mstatus_tdi | mstatus_afi, I2C_REG_STS(alg_data)); 368 iowrite32(stat | mstatus_tdi | mstatus_afi, I2C_REG_STS(alg_data));
381 369
382 dev_dbg(&adap->dev, "%s(): exiting, stat = %x ctrl = %x.\n", 370 dev_dbg(&alg_data->adapter.dev,
371 "%s(): exiting, stat = %x ctrl = %x.\n",
383 __func__, ioread32(I2C_REG_STS(alg_data)), 372 __func__, ioread32(I2C_REG_STS(alg_data)),
384 ioread32(I2C_REG_CTL(alg_data))); 373 ioread32(I2C_REG_CTL(alg_data)));
385 374
@@ -388,14 +377,13 @@ static irqreturn_t i2c_pnx_interrupt(int irq, void *dev_id)
388 377
389static void i2c_pnx_timeout(unsigned long data) 378static void i2c_pnx_timeout(unsigned long data)
390{ 379{
391 struct i2c_adapter *adap = (struct i2c_adapter *)data; 380 struct i2c_pnx_algo_data *alg_data = (struct i2c_pnx_algo_data *)data;
392 struct i2c_pnx_algo_data *alg_data = adap->algo_data;
393 u32 ctl; 381 u32 ctl;
394 382
395 dev_err(&adap->dev, "Master timed out. stat = %04x, cntrl = %04x. " 383 dev_err(&alg_data->adapter.dev,
396 "Resetting master...\n", 384 "Master timed out. stat = %04x, cntrl = %04x. Resetting master...\n",
397 ioread32(I2C_REG_STS(alg_data)), 385 ioread32(I2C_REG_STS(alg_data)),
398 ioread32(I2C_REG_CTL(alg_data))); 386 ioread32(I2C_REG_CTL(alg_data)));
399 387
400 /* Reset master and disable interrupts */ 388 /* Reset master and disable interrupts */
401 ctl = ioread32(I2C_REG_CTL(alg_data)); 389 ctl = ioread32(I2C_REG_CTL(alg_data));
@@ -409,15 +397,14 @@ static void i2c_pnx_timeout(unsigned long data)
409 complete(&alg_data->mif.complete); 397 complete(&alg_data->mif.complete);
410} 398}
411 399
412static inline void bus_reset_if_active(struct i2c_adapter *adap) 400static inline void bus_reset_if_active(struct i2c_pnx_algo_data *alg_data)
413{ 401{
414 struct i2c_pnx_algo_data *alg_data = adap->algo_data;
415 u32 stat; 402 u32 stat;
416 403
417 if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_active) { 404 if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_active) {
418 dev_err(&adap->dev, 405 dev_err(&alg_data->adapter.dev,
419 "%s: Bus is still active after xfer. Reset it...\n", 406 "%s: Bus is still active after xfer. Reset it...\n",
420 adap->name); 407 alg_data->adapter.name);
421 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset, 408 iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
422 I2C_REG_CTL(alg_data)); 409 I2C_REG_CTL(alg_data));
423 wait_reset(I2C_PNX_TIMEOUT, alg_data); 410 wait_reset(I2C_PNX_TIMEOUT, alg_data);
@@ -451,10 +438,11 @@ i2c_pnx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
451 struct i2c_pnx_algo_data *alg_data = adap->algo_data; 438 struct i2c_pnx_algo_data *alg_data = adap->algo_data;
452 u32 stat = ioread32(I2C_REG_STS(alg_data)); 439 u32 stat = ioread32(I2C_REG_STS(alg_data));
453 440
454 dev_dbg(&adap->dev, "%s(): entering: %d messages, stat = %04x.\n", 441 dev_dbg(&alg_data->adapter.dev,
442 "%s(): entering: %d messages, stat = %04x.\n",
455 __func__, num, ioread32(I2C_REG_STS(alg_data))); 443 __func__, num, ioread32(I2C_REG_STS(alg_data)));
456 444
457 bus_reset_if_active(adap); 445 bus_reset_if_active(alg_data);
458 446
459 /* Process transactions in a loop. */ 447 /* Process transactions in a loop. */
460 for (i = 0; rc >= 0 && i < num; i++) { 448 for (i = 0; rc >= 0 && i < num; i++) {
@@ -464,9 +452,9 @@ i2c_pnx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
464 addr = pmsg->addr; 452 addr = pmsg->addr;
465 453
466 if (pmsg->flags & I2C_M_TEN) { 454 if (pmsg->flags & I2C_M_TEN) {
467 dev_err(&adap->dev, 455 dev_err(&alg_data->adapter.dev,
468 "%s: 10 bits addr not supported!\n", 456 "%s: 10 bits addr not supported!\n",
469 adap->name); 457 alg_data->adapter.name);
470 rc = -EINVAL; 458 rc = -EINVAL;
471 break; 459 break;
472 } 460 }
@@ -478,11 +466,10 @@ i2c_pnx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
478 alg_data->mif.ret = 0; 466 alg_data->mif.ret = 0;
479 alg_data->last = (i == num - 1); 467 alg_data->last = (i == num - 1);
480 468
481 dev_dbg(&adap->dev, "%s(): mode %d, %d bytes\n", __func__, 469 dev_dbg(&alg_data->adapter.dev, "%s(): mode %d, %d bytes\n",
482 alg_data->mif.mode, 470 __func__, alg_data->mif.mode, alg_data->mif.len);
483 alg_data->mif.len);
484 471
485 i2c_pnx_arm_timer(adap); 472 i2c_pnx_arm_timer(alg_data);
486 473
487 /* initialize the completion var */ 474 /* initialize the completion var */
488 init_completion(&alg_data->mif.complete); 475 init_completion(&alg_data->mif.complete);
@@ -493,7 +480,7 @@ i2c_pnx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
493 I2C_REG_CTL(alg_data)); 480 I2C_REG_CTL(alg_data));
494 481
495 /* Put start-code and slave-address on the bus. */ 482 /* Put start-code and slave-address on the bus. */
496 rc = i2c_pnx_start(addr, adap); 483 rc = i2c_pnx_start(addr, alg_data);
497 if (rc < 0) 484 if (rc < 0)
498 break; 485 break;
499 486
@@ -502,31 +489,32 @@ i2c_pnx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
502 489
503 if (!(rc = alg_data->mif.ret)) 490 if (!(rc = alg_data->mif.ret))
504 completed++; 491 completed++;
505 dev_dbg(&adap->dev, "%s(): Complete, return code = %d.\n", 492 dev_dbg(&alg_data->adapter.dev,
493 "%s(): Complete, return code = %d.\n",
506 __func__, rc); 494 __func__, rc);
507 495
508 /* Clear TDI and AFI bits in case they are set. */ 496 /* Clear TDI and AFI bits in case they are set. */
509 if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_tdi) { 497 if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_tdi) {
510 dev_dbg(&adap->dev, 498 dev_dbg(&alg_data->adapter.dev,
511 "%s: TDI still set... clearing now.\n", 499 "%s: TDI still set... clearing now.\n",
512 adap->name); 500 alg_data->adapter.name);
513 iowrite32(stat, I2C_REG_STS(alg_data)); 501 iowrite32(stat, I2C_REG_STS(alg_data));
514 } 502 }
515 if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_afi) { 503 if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_afi) {
516 dev_dbg(&adap->dev, 504 dev_dbg(&alg_data->adapter.dev,
517 "%s: AFI still set... clearing now.\n", 505 "%s: AFI still set... clearing now.\n",
518 adap->name); 506 alg_data->adapter.name);
519 iowrite32(stat, I2C_REG_STS(alg_data)); 507 iowrite32(stat, I2C_REG_STS(alg_data));
520 } 508 }
521 } 509 }
522 510
523 bus_reset_if_active(adap); 511 bus_reset_if_active(alg_data);
524 512
525 /* Cleanup to be sure... */ 513 /* Cleanup to be sure... */
526 alg_data->mif.buf = NULL; 514 alg_data->mif.buf = NULL;
527 alg_data->mif.len = 0; 515 alg_data->mif.len = 0;
528 516
529 dev_dbg(&adap->dev, "%s(): exiting, stat = %x\n", 517 dev_dbg(&alg_data->adapter.dev, "%s(): exiting, stat = %x\n",
530 __func__, ioread32(I2C_REG_STS(alg_data))); 518 __func__, ioread32(I2C_REG_STS(alg_data)));
531 519
532 if (completed != num) 520 if (completed != num)
@@ -545,69 +533,92 @@ static struct i2c_algorithm pnx_algorithm = {
545 .functionality = i2c_pnx_func, 533 .functionality = i2c_pnx_func,
546}; 534};
547 535
536#ifdef CONFIG_PM
548static int i2c_pnx_controller_suspend(struct platform_device *pdev, 537static int i2c_pnx_controller_suspend(struct platform_device *pdev,
549 pm_message_t state) 538 pm_message_t state)
550{ 539{
551 struct i2c_pnx_data *i2c_pnx = platform_get_drvdata(pdev); 540 struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev);
552 return i2c_pnx->suspend(pdev, state); 541
542 /* FIXME: shouldn't this be clk_disable? */
543 clk_enable(alg_data->clk);
544
545 return 0;
553} 546}
554 547
555static int i2c_pnx_controller_resume(struct platform_device *pdev) 548static int i2c_pnx_controller_resume(struct platform_device *pdev)
556{ 549{
557 struct i2c_pnx_data *i2c_pnx = platform_get_drvdata(pdev); 550 struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev);
558 return i2c_pnx->resume(pdev); 551
552 return clk_enable(alg_data->clk);
559} 553}
554#else
555#define i2c_pnx_controller_suspend NULL
556#define i2c_pnx_controller_resume NULL
557#endif
560 558
561static int __devinit i2c_pnx_probe(struct platform_device *pdev) 559static int __devinit i2c_pnx_probe(struct platform_device *pdev)
562{ 560{
563 unsigned long tmp; 561 unsigned long tmp;
564 int ret = 0; 562 int ret = 0;
565 struct i2c_pnx_algo_data *alg_data; 563 struct i2c_pnx_algo_data *alg_data;
566 int freq_mhz; 564 unsigned long freq;
567 struct i2c_pnx_data *i2c_pnx = pdev->dev.platform_data; 565 struct i2c_pnx_data *i2c_pnx = pdev->dev.platform_data;
568 566
569 if (!i2c_pnx || !i2c_pnx->adapter) { 567 if (!i2c_pnx || !i2c_pnx->name) {
570 dev_err(&pdev->dev, "%s: no platform data supplied\n", 568 dev_err(&pdev->dev, "%s: no platform data supplied\n",
571 __func__); 569 __func__);
572 ret = -EINVAL; 570 ret = -EINVAL;
573 goto out; 571 goto out;
574 } 572 }
575 573
576 platform_set_drvdata(pdev, i2c_pnx); 574 alg_data = kzalloc(sizeof(*alg_data), GFP_KERNEL);
577 575 if (!alg_data) {
578 if (i2c_pnx->calculate_input_freq) 576 ret = -ENOMEM;
579 freq_mhz = i2c_pnx->calculate_input_freq(pdev); 577 goto err_kzalloc;
580 else {
581 freq_mhz = PNX_DEFAULT_FREQ;
582 dev_info(&pdev->dev, "Setting bus frequency to default value: "
583 "%d MHz\n", freq_mhz);
584 } 578 }
585 579
586 i2c_pnx->adapter->algo = &pnx_algorithm; 580 platform_set_drvdata(pdev, alg_data);
581
582 strlcpy(alg_data->adapter.name, i2c_pnx->name,
583 sizeof(alg_data->adapter.name));
584 alg_data->adapter.dev.parent = &pdev->dev;
585 alg_data->adapter.algo = &pnx_algorithm;
586 alg_data->adapter.algo_data = alg_data;
587 alg_data->adapter.nr = pdev->id;
588 alg_data->i2c_pnx = i2c_pnx;
589
590 alg_data->clk = clk_get(&pdev->dev, NULL);
591 if (IS_ERR(alg_data->clk)) {
592 ret = PTR_ERR(alg_data->clk);
593 goto out_drvdata;
594 }
587 595
588 alg_data = i2c_pnx->adapter->algo_data;
589 init_timer(&alg_data->mif.timer); 596 init_timer(&alg_data->mif.timer);
590 alg_data->mif.timer.function = i2c_pnx_timeout; 597 alg_data->mif.timer.function = i2c_pnx_timeout;
591 alg_data->mif.timer.data = (unsigned long)i2c_pnx->adapter; 598 alg_data->mif.timer.data = (unsigned long)alg_data;
592 599
593 /* Register I/O resource */ 600 /* Register I/O resource */
594 if (!request_mem_region(alg_data->base, I2C_PNX_REGION_SIZE, 601 if (!request_mem_region(i2c_pnx->base, I2C_PNX_REGION_SIZE,
595 pdev->name)) { 602 pdev->name)) {
596 dev_err(&pdev->dev, 603 dev_err(&pdev->dev,
597 "I/O region 0x%08x for I2C already in use.\n", 604 "I/O region 0x%08x for I2C already in use.\n",
598 alg_data->base); 605 i2c_pnx->base);
599 ret = -ENODEV; 606 ret = -ENODEV;
600 goto out_drvdata; 607 goto out_clkget;
601 } 608 }
602 609
603 if (!(alg_data->ioaddr = 610 alg_data->ioaddr = ioremap(i2c_pnx->base, I2C_PNX_REGION_SIZE);
604 (u32)ioremap(alg_data->base, I2C_PNX_REGION_SIZE))) { 611 if (!alg_data->ioaddr) {
605 dev_err(&pdev->dev, "Couldn't ioremap I2C I/O region\n"); 612 dev_err(&pdev->dev, "Couldn't ioremap I2C I/O region\n");
606 ret = -ENOMEM; 613 ret = -ENOMEM;
607 goto out_release; 614 goto out_release;
608 } 615 }
609 616
610 i2c_pnx->set_clock_run(pdev); 617 ret = clk_enable(alg_data->clk);
618 if (ret)
619 goto out_unmap;
620
621 freq = clk_get_rate(alg_data->clk);
611 622
612 /* 623 /*
613 * Clock Divisor High This value is the number of system clocks 624 * Clock Divisor High This value is the number of system clocks
@@ -620,45 +631,47 @@ static int __devinit i2c_pnx_probe(struct platform_device *pdev)
620 * the deglitching filter length. 631 * the deglitching filter length.
621 */ 632 */
622 633
623 tmp = ((freq_mhz * 1000) / I2C_PNX_SPEED_KHZ) / 2 - 2; 634 tmp = ((freq / 1000) / I2C_PNX_SPEED_KHZ) / 2 - 2;
624 iowrite32(tmp, I2C_REG_CKH(alg_data)); 635 iowrite32(tmp, I2C_REG_CKH(alg_data));
625 iowrite32(tmp, I2C_REG_CKL(alg_data)); 636 iowrite32(tmp, I2C_REG_CKL(alg_data));
626 637
627 iowrite32(mcntrl_reset, I2C_REG_CTL(alg_data)); 638 iowrite32(mcntrl_reset, I2C_REG_CTL(alg_data));
628 if (wait_reset(I2C_PNX_TIMEOUT, alg_data)) { 639 if (wait_reset(I2C_PNX_TIMEOUT, alg_data)) {
629 ret = -ENODEV; 640 ret = -ENODEV;
630 goto out_unmap; 641 goto out_clock;
631 } 642 }
632 init_completion(&alg_data->mif.complete); 643 init_completion(&alg_data->mif.complete);
633 644
634 ret = request_irq(alg_data->irq, i2c_pnx_interrupt, 645 ret = request_irq(i2c_pnx->irq, i2c_pnx_interrupt,
635 0, pdev->name, i2c_pnx->adapter); 646 0, pdev->name, alg_data);
636 if (ret) 647 if (ret)
637 goto out_clock; 648 goto out_clock;
638 649
639 /* Register this adapter with the I2C subsystem */ 650 /* Register this adapter with the I2C subsystem */
640 i2c_pnx->adapter->dev.parent = &pdev->dev; 651 ret = i2c_add_numbered_adapter(&alg_data->adapter);
641 i2c_pnx->adapter->nr = pdev->id;
642 ret = i2c_add_numbered_adapter(i2c_pnx->adapter);
643 if (ret < 0) { 652 if (ret < 0) {
644 dev_err(&pdev->dev, "I2C: Failed to add bus\n"); 653 dev_err(&pdev->dev, "I2C: Failed to add bus\n");
645 goto out_irq; 654 goto out_irq;
646 } 655 }
647 656
648 dev_dbg(&pdev->dev, "%s: Master at %#8x, irq %d.\n", 657 dev_dbg(&pdev->dev, "%s: Master at %#8x, irq %d.\n",
649 i2c_pnx->adapter->name, alg_data->base, alg_data->irq); 658 alg_data->adapter.name, i2c_pnx->base, i2c_pnx->irq);
650 659
651 return 0; 660 return 0;
652 661
653out_irq: 662out_irq:
654 free_irq(alg_data->irq, i2c_pnx->adapter); 663 free_irq(i2c_pnx->irq, alg_data);
655out_clock: 664out_clock:
656 i2c_pnx->set_clock_stop(pdev); 665 clk_disable(alg_data->clk);
657out_unmap: 666out_unmap:
658 iounmap((void *)alg_data->ioaddr); 667 iounmap(alg_data->ioaddr);
659out_release: 668out_release:
660 release_mem_region(alg_data->base, I2C_PNX_REGION_SIZE); 669 release_mem_region(i2c_pnx->base, I2C_PNX_REGION_SIZE);
670out_clkget:
671 clk_put(alg_data->clk);
661out_drvdata: 672out_drvdata:
673 kfree(alg_data);
674err_kzalloc:
662 platform_set_drvdata(pdev, NULL); 675 platform_set_drvdata(pdev, NULL);
663out: 676out:
664 return ret; 677 return ret;
@@ -666,15 +679,16 @@ out:
666 679
667static int __devexit i2c_pnx_remove(struct platform_device *pdev) 680static int __devexit i2c_pnx_remove(struct platform_device *pdev)
668{ 681{
669 struct i2c_pnx_data *i2c_pnx = platform_get_drvdata(pdev); 682 struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev);
670 struct i2c_adapter *adap = i2c_pnx->adapter; 683 struct i2c_pnx_data *i2c_pnx = alg_data->i2c_pnx;
671 struct i2c_pnx_algo_data *alg_data = adap->algo_data; 684
672 685 free_irq(i2c_pnx->irq, alg_data);
673 free_irq(alg_data->irq, i2c_pnx->adapter); 686 i2c_del_adapter(&alg_data->adapter);
674 i2c_del_adapter(adap); 687 clk_disable(alg_data->clk);
675 i2c_pnx->set_clock_stop(pdev); 688 iounmap(alg_data->ioaddr);
676 iounmap((void *)alg_data->ioaddr); 689 release_mem_region(i2c_pnx->base, I2C_PNX_REGION_SIZE);
677 release_mem_region(alg_data->base, I2C_PNX_REGION_SIZE); 690 clk_put(alg_data->clk);
691 kfree(alg_data);
678 platform_set_drvdata(pdev, NULL); 692 platform_set_drvdata(pdev, NULL);
679 693
680 return 0; 694 return 0;
diff --git a/drivers/i2c/busses/i2c-sis5595.c b/drivers/i2c/busses/i2c-sis5595.c
index 844569f7d8b7..55a71370c79b 100644
--- a/drivers/i2c/busses/i2c-sis5595.c
+++ b/drivers/i2c/busses/i2c-sis5595.c
@@ -369,7 +369,7 @@ static struct i2c_adapter sis5595_adapter = {
369 .algo = &smbus_algorithm, 369 .algo = &smbus_algorithm,
370}; 370};
371 371
372static struct pci_device_id sis5595_ids[] __devinitdata = { 372static const struct pci_device_id sis5595_ids[] __devinitconst = {
373 { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503) }, 373 { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503) },
374 { 0, } 374 { 0, }
375}; 375};
diff --git a/drivers/i2c/busses/i2c-sis630.c b/drivers/i2c/busses/i2c-sis630.c
index 68cff7af7013..2309c7f1bde2 100644
--- a/drivers/i2c/busses/i2c-sis630.c
+++ b/drivers/i2c/busses/i2c-sis630.c
@@ -468,7 +468,7 @@ static struct i2c_adapter sis630_adapter = {
468 .algo = &smbus_algorithm, 468 .algo = &smbus_algorithm,
469}; 469};
470 470
471static struct pci_device_id sis630_ids[] __devinitdata = { 471static const struct pci_device_id sis630_ids[] __devinitconst = {
472 { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503) }, 472 { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503) },
473 { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC) }, 473 { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC) },
474 { 0, } 474 { 0, }
diff --git a/drivers/i2c/busses/i2c-sis96x.c b/drivers/i2c/busses/i2c-sis96x.c
index 1649963b00dc..d43d8f8943dd 100644
--- a/drivers/i2c/busses/i2c-sis96x.c
+++ b/drivers/i2c/busses/i2c-sis96x.c
@@ -245,7 +245,7 @@ static struct i2c_adapter sis96x_adapter = {
245 .algo = &smbus_algorithm, 245 .algo = &smbus_algorithm,
246}; 246};
247 247
248static struct pci_device_id sis96x_ids[] = { 248static const struct pci_device_id sis96x_ids[] = {
249 { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_SMBUS) }, 249 { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_SMBUS) },
250 { 0, } 250 { 0, }
251}; 251};
diff --git a/drivers/i2c/busses/i2c-tiny-usb.c b/drivers/i2c/busses/i2c-tiny-usb.c
index e29b6d5ba8ef..b5b1bbf37d3c 100644
--- a/drivers/i2c/busses/i2c-tiny-usb.c
+++ b/drivers/i2c/busses/i2c-tiny-usb.c
@@ -31,11 +31,13 @@
31#define CMD_I2C_IO_BEGIN (1<<0) 31#define CMD_I2C_IO_BEGIN (1<<0)
32#define CMD_I2C_IO_END (1<<1) 32#define CMD_I2C_IO_END (1<<1)
33 33
34/* i2c bit delay, default is 10us -> 100kHz */ 34/* i2c bit delay, default is 10us -> 100kHz max
35 (in practice, due to additional delays in the i2c bitbanging
36 code this results in a i2c clock of about 50kHz) */
35static unsigned short delay = 10; 37static unsigned short delay = 10;
36module_param(delay, ushort, 0); 38module_param(delay, ushort, 0);
37MODULE_PARM_DESC(delay, "bit delay in microseconds, " 39MODULE_PARM_DESC(delay, "bit delay in microseconds "
38 "e.g. 10 for 100kHz (default is 100kHz)"); 40 "(default is 10us for 100kHz max)");
39 41
40static int usb_read(struct i2c_adapter *adapter, int cmd, 42static int usb_read(struct i2c_adapter *adapter, int cmd,
41 int value, int index, void *data, int len); 43 int value, int index, void *data, int len);
@@ -137,7 +139,7 @@ static const struct i2c_algorithm usb_algorithm = {
137 * Future Technology Devices International Ltd., later a pair was 139 * Future Technology Devices International Ltd., later a pair was
138 * bought from EZPrototypes 140 * bought from EZPrototypes
139 */ 141 */
140static struct usb_device_id i2c_tiny_usb_table [] = { 142static const struct usb_device_id i2c_tiny_usb_table[] = {
141 { USB_DEVICE(0x0403, 0xc631) }, /* FTDI */ 143 { USB_DEVICE(0x0403, 0xc631) }, /* FTDI */
142 { USB_DEVICE(0x1c40, 0x0534) }, /* EZPrototypes */ 144 { USB_DEVICE(0x1c40, 0x0534) }, /* EZPrototypes */
143 { } /* Terminating entry */ 145 { } /* Terminating entry */
diff --git a/drivers/i2c/busses/i2c-via.c b/drivers/i2c/busses/i2c-via.c
index 8b24f192103a..de78283bddbe 100644
--- a/drivers/i2c/busses/i2c-via.c
+++ b/drivers/i2c/busses/i2c-via.c
@@ -89,7 +89,7 @@ static struct i2c_adapter vt586b_adapter = {
89}; 89};
90 90
91 91
92static struct pci_device_id vt586b_ids[] __devinitdata = { 92static const struct pci_device_id vt586b_ids[] __devinitconst = {
93 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3) }, 93 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3) },
94 { 0, } 94 { 0, }
95}; 95};
diff --git a/drivers/i2c/busses/i2c-viapro.c b/drivers/i2c/busses/i2c-viapro.c
index a84a909e1234..d57292e5dae0 100644
--- a/drivers/i2c/busses/i2c-viapro.c
+++ b/drivers/i2c/busses/i2c-viapro.c
@@ -444,7 +444,7 @@ release_region:
444 return error; 444 return error;
445} 445}
446 446
447static struct pci_device_id vt596_ids[] = { 447static const struct pci_device_id vt596_ids[] = {
448 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596_3), 448 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596_3),
449 .driver_data = SMBBA1 }, 449 .driver_data = SMBBA1 },
450 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596B_3), 450 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596B_3),
diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c
new file mode 100644
index 000000000000..eece39a5a30e
--- /dev/null
+++ b/drivers/i2c/busses/i2c-xiic.c
@@ -0,0 +1,824 @@
1/*
2 * i2c-xiic.c
3 * Copyright (c) 2002-2007 Xilinx Inc.
4 * Copyright (c) 2009-2010 Intel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 *
20 * This code was implemented by Mocean Laboratories AB when porting linux
21 * to the automotive development board Russellville. The copyright holder
22 * as seen in the header is Intel corporation.
23 * Mocean Laboratories forked off the GNU/Linux platform work into a
24 * separate company called Pelagicore AB, which commited the code to the
25 * kernel.
26 */
27
28/* Supports:
29 * Xilinx IIC
30 */
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/init.h>
34#include <linux/errno.h>
35#include <linux/platform_device.h>
36#include <linux/i2c.h>
37#include <linux/interrupt.h>
38#include <linux/wait.h>
39#include <linux/i2c-xiic.h>
40#include <linux/io.h>
41
42#define DRIVER_NAME "xiic-i2c"
43
44enum xilinx_i2c_state {
45 STATE_DONE,
46 STATE_ERROR,
47 STATE_START
48};
49
50/**
51 * struct xiic_i2c - Internal representation of the XIIC I2C bus
52 * @base: Memory base of the HW registers
53 * @wait: Wait queue for callers
54 * @adap: Kernel adapter representation
55 * @tx_msg: Messages from above to be sent
56 * @lock: Mutual exclusion
57 * @tx_pos: Current pos in TX message
58 * @nmsgs: Number of messages in tx_msg
59 * @state: See STATE_
60 * @rx_msg: Current RX message
61 * @rx_pos: Position within current RX message
62 */
63struct xiic_i2c {
64 void __iomem *base;
65 wait_queue_head_t wait;
66 struct i2c_adapter adap;
67 struct i2c_msg *tx_msg;
68 spinlock_t lock;
69 unsigned int tx_pos;
70 unsigned int nmsgs;
71 enum xilinx_i2c_state state;
72 struct i2c_msg *rx_msg;
73 int rx_pos;
74};
75
76
77#define XIIC_MSB_OFFSET 0
78#define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET)
79
80/*
81 * Register offsets in bytes from RegisterBase. Three is added to the
82 * base offset to access LSB (IBM style) of the word
83 */
84#define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */
85#define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */
86#define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */
87#define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */
88#define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */
89#define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */
90#define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */
91#define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */
92#define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */
93#define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */
94
95/* Control Register masks */
96#define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */
97#define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */
98#define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */
99#define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */
100#define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */
101#define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */
102#define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */
103
104/* Status Register masks */
105#define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */
106#define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */
107#define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */
108#define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */
109#define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */
110#define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */
111#define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */
112#define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */
113
114/* Interrupt Status Register masks Interrupt occurs when... */
115#define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */
116#define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */
117#define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */
118#define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */
119#define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */
120#define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */
121#define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */
122#define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */
123
124/* The following constants specify the depth of the FIFOs */
125#define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */
126#define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */
127
128/* The following constants specify groups of interrupts that are typically
129 * enabled or disables at the same time
130 */
131#define XIIC_TX_INTERRUPTS \
132(XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)
133
134#define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)
135
136/* The following constants are used with the following macros to specify the
137 * operation, a read or write operation.
138 */
139#define XIIC_READ_OPERATION 1
140#define XIIC_WRITE_OPERATION 0
141
142/*
143 * Tx Fifo upper bit masks.
144 */
145#define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */
146#define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */
147
148/*
149 * The following constants define the register offsets for the Interrupt
150 * registers. There are some holes in the memory map for reserved addresses
151 * to allow other registers to be added and still match the memory map of the
152 * interrupt controller registers
153 */
154#define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */
155#define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */
156#define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */
157#define XIIC_RESETR_OFFSET 0x40 /* Reset Register */
158
159#define XIIC_RESET_MASK 0xAUL
160
161/*
162 * The following constant is used for the device global interrupt enable
163 * register, to enable all interrupts for the device, this is the only bit
164 * in the register
165 */
166#define XIIC_GINTR_ENABLE_MASK 0x80000000UL
167
168#define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos)
169#define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos)
170
171static void xiic_start_xfer(struct xiic_i2c *i2c);
172static void __xiic_start_xfer(struct xiic_i2c *i2c);
173
174static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value)
175{
176 iowrite8(value, i2c->base + reg);
177}
178
179static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg)
180{
181 return ioread8(i2c->base + reg);
182}
183
184static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value)
185{
186 iowrite16(value, i2c->base + reg);
187}
188
189static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value)
190{
191 iowrite32(value, i2c->base + reg);
192}
193
194static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg)
195{
196 return ioread32(i2c->base + reg);
197}
198
199static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask)
200{
201 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
202 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask);
203}
204
205static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask)
206{
207 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
208 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask);
209}
210
211static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask)
212{
213 u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
214 xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask);
215}
216
217static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask)
218{
219 xiic_irq_clr(i2c, mask);
220 xiic_irq_en(i2c, mask);
221}
222
223static void xiic_clear_rx_fifo(struct xiic_i2c *i2c)
224{
225 u8 sr;
226 for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
227 !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK);
228 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET))
229 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
230}
231
232static void xiic_reinit(struct xiic_i2c *i2c)
233{
234 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
235
236 /* Set receive Fifo depth to maximum (zero based). */
237 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1);
238
239 /* Reset Tx Fifo. */
240 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
241
242 /* Enable IIC Device, remove Tx Fifo reset & disable general call. */
243 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK);
244
245 /* make sure RX fifo is empty */
246 xiic_clear_rx_fifo(i2c);
247
248 /* Enable interrupts */
249 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
250
251 xiic_irq_clr_en(i2c, XIIC_INTR_AAS_MASK | XIIC_INTR_ARB_LOST_MASK);
252}
253
254static void xiic_deinit(struct xiic_i2c *i2c)
255{
256 u8 cr;
257
258 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK);
259
260 /* Disable IIC Device. */
261 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET);
262 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK);
263}
264
265static void xiic_read_rx(struct xiic_i2c *i2c)
266{
267 u8 bytes_in_fifo;
268 int i;
269
270 bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1;
271
272 dev_dbg(i2c->adap.dev.parent, "%s entry, bytes in fifo: %d, msg: %d"
273 ", SR: 0x%x, CR: 0x%x\n",
274 __func__, bytes_in_fifo, xiic_rx_space(i2c),
275 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
276 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
277
278 if (bytes_in_fifo > xiic_rx_space(i2c))
279 bytes_in_fifo = xiic_rx_space(i2c);
280
281 for (i = 0; i < bytes_in_fifo; i++)
282 i2c->rx_msg->buf[i2c->rx_pos++] =
283 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET);
284
285 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET,
286 (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ?
287 IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1);
288}
289
290static int xiic_tx_fifo_space(struct xiic_i2c *i2c)
291{
292 /* return the actual space left in the FIFO */
293 return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1;
294}
295
296static void xiic_fill_tx_fifo(struct xiic_i2c *i2c)
297{
298 u8 fifo_space = xiic_tx_fifo_space(i2c);
299 int len = xiic_tx_space(i2c);
300
301 len = (len > fifo_space) ? fifo_space : len;
302
303 dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n",
304 __func__, len, fifo_space);
305
306 while (len--) {
307 u16 data = i2c->tx_msg->buf[i2c->tx_pos++];
308 if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) {
309 /* last message in transfer -> STOP */
310 data |= XIIC_TX_DYN_STOP_MASK;
311 dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__);
312
313 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
314 } else
315 xiic_setreg8(i2c, XIIC_DTR_REG_OFFSET, data);
316 }
317}
318
319static void xiic_wakeup(struct xiic_i2c *i2c, int code)
320{
321 i2c->tx_msg = NULL;
322 i2c->rx_msg = NULL;
323 i2c->nmsgs = 0;
324 i2c->state = code;
325 wake_up(&i2c->wait);
326}
327
328static void xiic_process(struct xiic_i2c *i2c)
329{
330 u32 pend, isr, ier;
331 u32 clr = 0;
332
333 /* Get the interrupt Status from the IPIF. There is no clearing of
334 * interrupts in the IPIF. Interrupts must be cleared at the source.
335 * To find which interrupts are pending; AND interrupts pending with
336 * interrupts masked.
337 */
338 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET);
339 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET);
340 pend = isr & ier;
341
342 dev_dbg(i2c->adap.dev.parent, "%s entry, IER: 0x%x, ISR: 0x%x, "
343 "pend: 0x%x, SR: 0x%x, msg: %p, nmsgs: %d\n",
344 __func__, ier, isr, pend, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET),
345 i2c->tx_msg, i2c->nmsgs);
346
347 /* Do not processes a devices interrupts if the device has no
348 * interrupts pending
349 */
350 if (!pend)
351 return;
352
353 /* Service requesting interrupt */
354 if ((pend & XIIC_INTR_ARB_LOST_MASK) ||
355 ((pend & XIIC_INTR_TX_ERROR_MASK) &&
356 !(pend & XIIC_INTR_RX_FULL_MASK))) {
357 /* bus arbritration lost, or...
358 * Transmit error _OR_ RX completed
359 * if this happens when RX_FULL is not set
360 * this is probably a TX error
361 */
362
363 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__);
364
365 /* dynamic mode seem to suffer from problems if we just flushes
366 * fifos and the next message is a TX with len 0 (only addr)
367 * reset the IP instead of just flush fifos
368 */
369 xiic_reinit(i2c);
370
371 if (i2c->tx_msg)
372 xiic_wakeup(i2c, STATE_ERROR);
373
374 } else if (pend & XIIC_INTR_RX_FULL_MASK) {
375 /* Receive register/FIFO is full */
376
377 clr = XIIC_INTR_RX_FULL_MASK;
378 if (!i2c->rx_msg) {
379 dev_dbg(i2c->adap.dev.parent,
380 "%s unexpexted RX IRQ\n", __func__);
381 xiic_clear_rx_fifo(i2c);
382 goto out;
383 }
384
385 xiic_read_rx(i2c);
386 if (xiic_rx_space(i2c) == 0) {
387 /* this is the last part of the message */
388 i2c->rx_msg = NULL;
389
390 /* also clear TX error if there (RX complete) */
391 clr |= (isr & XIIC_INTR_TX_ERROR_MASK);
392
393 dev_dbg(i2c->adap.dev.parent,
394 "%s end of message, nmsgs: %d\n",
395 __func__, i2c->nmsgs);
396
397 /* send next message if this wasn't the last,
398 * otherwise the transfer will be finialise when
399 * receiving the bus not busy interrupt
400 */
401 if (i2c->nmsgs > 1) {
402 i2c->nmsgs--;
403 i2c->tx_msg++;
404 dev_dbg(i2c->adap.dev.parent,
405 "%s will start next...\n", __func__);
406
407 __xiic_start_xfer(i2c);
408 }
409 }
410 } else if (pend & XIIC_INTR_BNB_MASK) {
411 /* IIC bus has transitioned to not busy */
412 clr = XIIC_INTR_BNB_MASK;
413
414 /* The bus is not busy, disable BusNotBusy interrupt */
415 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK);
416
417 if (!i2c->tx_msg)
418 goto out;
419
420 if ((i2c->nmsgs == 1) && !i2c->rx_msg &&
421 xiic_tx_space(i2c) == 0)
422 xiic_wakeup(i2c, STATE_DONE);
423 else
424 xiic_wakeup(i2c, STATE_ERROR);
425
426 } else if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) {
427 /* Transmit register/FIFO is empty or ½ empty */
428
429 clr = pend &
430 (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK);
431
432 if (!i2c->tx_msg) {
433 dev_dbg(i2c->adap.dev.parent,
434 "%s unexpexted TX IRQ\n", __func__);
435 goto out;
436 }
437
438 xiic_fill_tx_fifo(i2c);
439
440 /* current message sent and there is space in the fifo */
441 if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) {
442 dev_dbg(i2c->adap.dev.parent,
443 "%s end of message sent, nmsgs: %d\n",
444 __func__, i2c->nmsgs);
445 if (i2c->nmsgs > 1) {
446 i2c->nmsgs--;
447 i2c->tx_msg++;
448 __xiic_start_xfer(i2c);
449 } else {
450 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
451
452 dev_dbg(i2c->adap.dev.parent,
453 "%s Got TX IRQ but no more to do...\n",
454 __func__);
455 }
456 } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1))
457 /* current frame is sent and is last,
458 * make sure to disable tx half
459 */
460 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK);
461 } else {
462 /* got IRQ which is not acked */
463 dev_err(i2c->adap.dev.parent, "%s Got unexpected IRQ\n",
464 __func__);
465 clr = pend;
466 }
467out:
468 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr);
469
470 xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr);
471}
472
473static int xiic_bus_busy(struct xiic_i2c *i2c)
474{
475 u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET);
476
477 return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0;
478}
479
480static int xiic_busy(struct xiic_i2c *i2c)
481{
482 int tries = 3;
483 int err;
484
485 if (i2c->tx_msg)
486 return -EBUSY;
487
488 /* for instance if previous transfer was terminated due to TX error
489 * it might be that the bus is on it's way to become available
490 * give it at most 3 ms to wake
491 */
492 err = xiic_bus_busy(i2c);
493 while (err && tries--) {
494 mdelay(1);
495 err = xiic_bus_busy(i2c);
496 }
497
498 return err;
499}
500
501static void xiic_start_recv(struct xiic_i2c *i2c)
502{
503 u8 rx_watermark;
504 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg;
505
506 /* Clear and enable Rx full interrupt. */
507 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK);
508
509 /* we want to get all but last byte, because the TX_ERROR IRQ is used
510 * to inidicate error ACK on the address, and negative ack on the last
511 * received byte, so to not mix them receive all but last.
512 * In the case where there is only one byte to receive
513 * we can check if ERROR and RX full is set at the same time
514 */
515 rx_watermark = msg->len;
516 if (rx_watermark > IIC_RX_FIFO_DEPTH)
517 rx_watermark = IIC_RX_FIFO_DEPTH;
518 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1);
519
520 if (!(msg->flags & I2C_M_NOSTART))
521 /* write the address */
522 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
523 (msg->addr << 1) | XIIC_READ_OPERATION |
524 XIIC_TX_DYN_START_MASK);
525
526 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
527
528 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET,
529 msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0));
530 if (i2c->nmsgs == 1)
531 /* very last, enable bus not busy as well */
532 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK);
533
534 /* the message is tx:ed */
535 i2c->tx_pos = msg->len;
536}
537
538static void xiic_start_send(struct xiic_i2c *i2c)
539{
540 struct i2c_msg *msg = i2c->tx_msg;
541
542 xiic_irq_clr(i2c, XIIC_INTR_TX_ERROR_MASK);
543
544 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d, "
545 "ISR: 0x%x, CR: 0x%x\n",
546 __func__, msg, msg->len, xiic_getreg32(i2c, XIIC_IISR_OFFSET),
547 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET));
548
549 if (!(msg->flags & I2C_M_NOSTART)) {
550 /* write the address */
551 u16 data = ((msg->addr << 1) & 0xfe) | XIIC_WRITE_OPERATION |
552 XIIC_TX_DYN_START_MASK;
553 if ((i2c->nmsgs == 1) && msg->len == 0)
554 /* no data and last message -> add STOP */
555 data |= XIIC_TX_DYN_STOP_MASK;
556
557 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
558 }
559
560 xiic_fill_tx_fifo(i2c);
561
562 /* Clear any pending Tx empty, Tx Error and then enable them. */
563 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK |
564 XIIC_INTR_BNB_MASK);
565}
566
567static irqreturn_t xiic_isr(int irq, void *dev_id)
568{
569 struct xiic_i2c *i2c = dev_id;
570
571 spin_lock(&i2c->lock);
572 /* disable interrupts globally */
573 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, 0);
574
575 dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__);
576
577 xiic_process(i2c);
578
579 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
580 spin_unlock(&i2c->lock);
581
582 return IRQ_HANDLED;
583}
584
585static void __xiic_start_xfer(struct xiic_i2c *i2c)
586{
587 int first = 1;
588 int fifo_space = xiic_tx_fifo_space(i2c);
589 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n",
590 __func__, i2c->tx_msg, fifo_space);
591
592 if (!i2c->tx_msg)
593 return;
594
595 i2c->rx_pos = 0;
596 i2c->tx_pos = 0;
597 i2c->state = STATE_START;
598 while ((fifo_space >= 2) && (first || (i2c->nmsgs > 1))) {
599 if (!first) {
600 i2c->nmsgs--;
601 i2c->tx_msg++;
602 i2c->tx_pos = 0;
603 } else
604 first = 0;
605
606 if (i2c->tx_msg->flags & I2C_M_RD) {
607 /* we dont date putting several reads in the FIFO */
608 xiic_start_recv(i2c);
609 return;
610 } else {
611 xiic_start_send(i2c);
612 if (xiic_tx_space(i2c) != 0) {
613 /* the message could not be completely sent */
614 break;
615 }
616 }
617
618 fifo_space = xiic_tx_fifo_space(i2c);
619 }
620
621 /* there are more messages or the current one could not be completely
622 * put into the FIFO, also enable the half empty interrupt
623 */
624 if (i2c->nmsgs > 1 || xiic_tx_space(i2c))
625 xiic_irq_clr_en(i2c, XIIC_INTR_TX_HALF_MASK);
626
627}
628
629static void xiic_start_xfer(struct xiic_i2c *i2c)
630{
631 unsigned long flags;
632
633 spin_lock_irqsave(&i2c->lock, flags);
634 xiic_reinit(i2c);
635 /* disable interrupts globally */
636 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, 0);
637 spin_unlock_irqrestore(&i2c->lock, flags);
638
639 __xiic_start_xfer(i2c);
640 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK);
641}
642
643static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
644{
645 struct xiic_i2c *i2c = i2c_get_adapdata(adap);
646 int err;
647
648 dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__,
649 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET));
650
651 err = xiic_busy(i2c);
652 if (err)
653 return err;
654
655 i2c->tx_msg = msgs;
656 i2c->nmsgs = num;
657
658 xiic_start_xfer(i2c);
659
660 if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
661 (i2c->state == STATE_DONE), HZ))
662 return (i2c->state == STATE_DONE) ? num : -EIO;
663 else {
664 i2c->tx_msg = NULL;
665 i2c->rx_msg = NULL;
666 i2c->nmsgs = 0;
667 return -ETIMEDOUT;
668 }
669}
670
671static u32 xiic_func(struct i2c_adapter *adap)
672{
673 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
674}
675
676static const struct i2c_algorithm xiic_algorithm = {
677 .master_xfer = xiic_xfer,
678 .functionality = xiic_func,
679};
680
681static struct i2c_adapter xiic_adapter = {
682 .owner = THIS_MODULE,
683 .name = DRIVER_NAME,
684 .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
685 .algo = &xiic_algorithm,
686};
687
688
689static int __devinit xiic_i2c_probe(struct platform_device *pdev)
690{
691 struct xiic_i2c *i2c;
692 struct xiic_i2c_platform_data *pdata;
693 struct resource *res;
694 int ret, irq;
695 u8 i;
696
697 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
698 if (!res)
699 goto resource_missing;
700
701 irq = platform_get_irq(pdev, 0);
702 if (irq < 0)
703 goto resource_missing;
704
705 pdata = (struct xiic_i2c_platform_data *) pdev->dev.platform_data;
706 if (!pdata)
707 return -EINVAL;
708
709 i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
710 if (!i2c)
711 return -ENOMEM;
712
713 if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
714 dev_err(&pdev->dev, "Memory region busy\n");
715 ret = -EBUSY;
716 goto request_mem_failed;
717 }
718
719 i2c->base = ioremap(res->start, resource_size(res));
720 if (!i2c->base) {
721 dev_err(&pdev->dev, "Unable to map registers\n");
722 ret = -EIO;
723 goto map_failed;
724 }
725
726 /* hook up driver to tree */
727 platform_set_drvdata(pdev, i2c);
728 i2c->adap = xiic_adapter;
729 i2c_set_adapdata(&i2c->adap, i2c);
730 i2c->adap.dev.parent = &pdev->dev;
731
732 xiic_reinit(i2c);
733
734 spin_lock_init(&i2c->lock);
735 init_waitqueue_head(&i2c->wait);
736 ret = request_irq(irq, xiic_isr, 0, pdev->name, i2c);
737 if (ret) {
738 dev_err(&pdev->dev, "Cannot claim IRQ\n");
739 goto request_irq_failed;
740 }
741
742 /* add i2c adapter to i2c tree */
743 ret = i2c_add_adapter(&i2c->adap);
744 if (ret) {
745 dev_err(&pdev->dev, "Failed to add adapter\n");
746 goto add_adapter_failed;
747 }
748
749 /* add in known devices to the bus */
750 for (i = 0; i < pdata->num_devices; i++)
751 i2c_new_device(&i2c->adap, pdata->devices + i);
752
753 return 0;
754
755add_adapter_failed:
756 free_irq(irq, i2c);
757request_irq_failed:
758 xiic_deinit(i2c);
759 iounmap(i2c->base);
760map_failed:
761 release_mem_region(res->start, resource_size(res));
762request_mem_failed:
763 kfree(i2c);
764
765 return ret;
766resource_missing:
767 dev_err(&pdev->dev, "IRQ or Memory resource is missing\n");
768 return -ENOENT;
769}
770
771static int __devexit xiic_i2c_remove(struct platform_device* pdev)
772{
773 struct xiic_i2c *i2c = platform_get_drvdata(pdev);
774 struct resource *res;
775
776 /* remove adapter & data */
777 i2c_del_adapter(&i2c->adap);
778
779 xiic_deinit(i2c);
780
781 platform_set_drvdata(pdev, NULL);
782
783 free_irq(platform_get_irq(pdev, 0), i2c);
784
785 iounmap(i2c->base);
786
787 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
788 if (res)
789 release_mem_region(res->start, resource_size(res));
790
791 kfree(i2c);
792
793 return 0;
794}
795
796
797/* work with hotplug and coldplug */
798MODULE_ALIAS("platform:"DRIVER_NAME);
799
800static struct platform_driver xiic_i2c_driver = {
801 .probe = xiic_i2c_probe,
802 .remove = __devexit_p(xiic_i2c_remove),
803 .driver = {
804 .owner = THIS_MODULE,
805 .name = DRIVER_NAME,
806 },
807};
808
809static int __init xiic_i2c_init(void)
810{
811 return platform_driver_register(&xiic_i2c_driver);
812}
813
814static void __exit xiic_i2c_exit(void)
815{
816 platform_driver_unregister(&xiic_i2c_driver);
817}
818
819module_init(xiic_i2c_init);
820module_exit(xiic_i2c_exit);
821
822MODULE_AUTHOR("info@mocean-labs.com");
823MODULE_DESCRIPTION("Xilinx I2C bus driver");
824MODULE_LICENSE("GPL v2");
diff --git a/drivers/i2c/i2c-core.c b/drivers/i2c/i2c-core.c
index 10be7b5fbe97..3202a86f420e 100644
--- a/drivers/i2c/i2c-core.c
+++ b/drivers/i2c/i2c-core.c
@@ -34,6 +34,7 @@
34#include <linux/hardirq.h> 34#include <linux/hardirq.h>
35#include <linux/irqflags.h> 35#include <linux/irqflags.h>
36#include <linux/rwsem.h> 36#include <linux/rwsem.h>
37#include <linux/pm_runtime.h>
37#include <asm/uaccess.h> 38#include <asm/uaccess.h>
38 39
39#include "i2c-core.h" 40#include "i2c-core.h"
@@ -184,6 +185,52 @@ static int i2c_device_pm_resume(struct device *dev)
184#define i2c_device_pm_resume NULL 185#define i2c_device_pm_resume NULL
185#endif 186#endif
186 187
188#ifdef CONFIG_PM_RUNTIME
189static int i2c_device_runtime_suspend(struct device *dev)
190{
191 const struct dev_pm_ops *pm;
192
193 if (!dev->driver)
194 return 0;
195 pm = dev->driver->pm;
196 if (!pm || !pm->runtime_suspend)
197 return 0;
198 return pm->runtime_suspend(dev);
199}
200
201static int i2c_device_runtime_resume(struct device *dev)
202{
203 const struct dev_pm_ops *pm;
204
205 if (!dev->driver)
206 return 0;
207 pm = dev->driver->pm;
208 if (!pm || !pm->runtime_resume)
209 return 0;
210 return pm->runtime_resume(dev);
211}
212
213static int i2c_device_runtime_idle(struct device *dev)
214{
215 const struct dev_pm_ops *pm = NULL;
216 int ret;
217
218 if (dev->driver)
219 pm = dev->driver->pm;
220 if (pm && pm->runtime_idle) {
221 ret = pm->runtime_idle(dev);
222 if (ret)
223 return ret;
224 }
225
226 return pm_runtime_suspend(dev);
227}
228#else
229#define i2c_device_runtime_suspend NULL
230#define i2c_device_runtime_resume NULL
231#define i2c_device_runtime_idle NULL
232#endif
233
187static int i2c_device_suspend(struct device *dev, pm_message_t mesg) 234static int i2c_device_suspend(struct device *dev, pm_message_t mesg)
188{ 235{
189 struct i2c_client *client = i2c_verify_client(dev); 236 struct i2c_client *client = i2c_verify_client(dev);
@@ -251,6 +298,9 @@ static const struct attribute_group *i2c_dev_attr_groups[] = {
251static const struct dev_pm_ops i2c_device_pm_ops = { 298static const struct dev_pm_ops i2c_device_pm_ops = {
252 .suspend = i2c_device_pm_suspend, 299 .suspend = i2c_device_pm_suspend,
253 .resume = i2c_device_pm_resume, 300 .resume = i2c_device_pm_resume,
301 .runtime_suspend = i2c_device_runtime_suspend,
302 .runtime_resume = i2c_device_runtime_resume,
303 .runtime_idle = i2c_device_runtime_idle,
254}; 304};
255 305
256struct bus_type i2c_bus_type = { 306struct bus_type i2c_bus_type = {
@@ -1133,7 +1183,7 @@ EXPORT_SYMBOL(i2c_transfer);
1133 * i2c_master_send - issue a single I2C message in master transmit mode 1183 * i2c_master_send - issue a single I2C message in master transmit mode
1134 * @client: Handle to slave device 1184 * @client: Handle to slave device
1135 * @buf: Data that will be written to the slave 1185 * @buf: Data that will be written to the slave
1136 * @count: How many bytes to write 1186 * @count: How many bytes to write, must be less than 64k since msg.len is u16
1137 * 1187 *
1138 * Returns negative errno, or else the number of bytes written. 1188 * Returns negative errno, or else the number of bytes written.
1139 */ 1189 */
@@ -1160,7 +1210,7 @@ EXPORT_SYMBOL(i2c_master_send);
1160 * i2c_master_recv - issue a single I2C message in master receive mode 1210 * i2c_master_recv - issue a single I2C message in master receive mode
1161 * @client: Handle to slave device 1211 * @client: Handle to slave device
1162 * @buf: Where to store data read from slave 1212 * @buf: Where to store data read from slave
1163 * @count: How many bytes to read 1213 * @count: How many bytes to read, must be less than 64k since msg.len is u16
1164 * 1214 *
1165 * Returns negative errno, or else the number of bytes read. 1215 * Returns negative errno, or else the number of bytes read.
1166 */ 1216 */
diff --git a/drivers/i2c/i2c-smbus.c b/drivers/i2c/i2c-smbus.c
new file mode 100644
index 000000000000..421278221243
--- /dev/null
+++ b/drivers/i2c/i2c-smbus.c
@@ -0,0 +1,263 @@
1/*
2 * i2c-smbus.c - SMBus extensions to the I2C protocol
3 *
4 * Copyright (C) 2008 David Brownell
5 * Copyright (C) 2010 Jean Delvare <khali@linux-fr.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/device.h>
25#include <linux/semaphore.h>
26#include <linux/interrupt.h>
27#include <linux/workqueue.h>
28#include <linux/i2c.h>
29#include <linux/i2c-smbus.h>
30
31struct i2c_smbus_alert {
32 unsigned int alert_edge_triggered:1;
33 int irq;
34 struct work_struct alert;
35 struct i2c_client *ara; /* Alert response address */
36};
37
38struct alert_data {
39 unsigned short addr;
40 u8 flag:1;
41};
42
43/* If this is the alerting device, notify its driver */
44static int smbus_do_alert(struct device *dev, void *addrp)
45{
46 struct i2c_client *client = i2c_verify_client(dev);
47 struct alert_data *data = addrp;
48
49 if (!client || client->addr != data->addr)
50 return 0;
51 if (client->flags & I2C_CLIENT_TEN)
52 return 0;
53
54 /*
55 * Drivers should either disable alerts, or provide at least
56 * a minimal handler. Lock so client->driver won't change.
57 */
58 down(&dev->sem);
59 if (client->driver) {
60 if (client->driver->alert)
61 client->driver->alert(client, data->flag);
62 else
63 dev_warn(&client->dev, "no driver alert()!\n");
64 } else
65 dev_dbg(&client->dev, "alert with no driver\n");
66 up(&dev->sem);
67
68 /* Stop iterating after we find the device */
69 return -EBUSY;
70}
71
72/*
73 * The alert IRQ handler needs to hand work off to a task which can issue
74 * SMBus calls, because those sleeping calls can't be made in IRQ context.
75 */
76static void smbus_alert(struct work_struct *work)
77{
78 struct i2c_smbus_alert *alert;
79 struct i2c_client *ara;
80 unsigned short prev_addr = 0; /* Not a valid address */
81
82 alert = container_of(work, struct i2c_smbus_alert, alert);
83 ara = alert->ara;
84
85 for (;;) {
86 s32 status;
87 struct alert_data data;
88
89 /*
90 * Devices with pending alerts reply in address order, low
91 * to high, because of slave transmit arbitration. After
92 * responding, an SMBus device stops asserting SMBALERT#.
93 *
94 * Note that SMBus 2.0 reserves 10-bit addresess for future
95 * use. We neither handle them, nor try to use PEC here.
96 */
97 status = i2c_smbus_read_byte(ara);
98 if (status < 0)
99 break;
100
101 data.flag = status & 1;
102 data.addr = status >> 1;
103
104 if (data.addr == prev_addr) {
105 dev_warn(&ara->dev, "Duplicate SMBALERT# from dev "
106 "0x%02x, skipping\n", data.addr);
107 break;
108 }
109 dev_dbg(&ara->dev, "SMBALERT# from dev 0x%02x, flag %d\n",
110 data.addr, data.flag);
111
112 /* Notify driver for the device which issued the alert */
113 device_for_each_child(&ara->adapter->dev, &data,
114 smbus_do_alert);
115 prev_addr = data.addr;
116 }
117
118 /* We handled all alerts; re-enable level-triggered IRQs */
119 if (!alert->alert_edge_triggered)
120 enable_irq(alert->irq);
121}
122
123static irqreturn_t smbalert_irq(int irq, void *d)
124{
125 struct i2c_smbus_alert *alert = d;
126
127 /* Disable level-triggered IRQs until we handle them */
128 if (!alert->alert_edge_triggered)
129 disable_irq_nosync(irq);
130
131 schedule_work(&alert->alert);
132 return IRQ_HANDLED;
133}
134
135/* Setup SMBALERT# infrastructure */
136static int smbalert_probe(struct i2c_client *ara,
137 const struct i2c_device_id *id)
138{
139 struct i2c_smbus_alert_setup *setup = ara->dev.platform_data;
140 struct i2c_smbus_alert *alert;
141 struct i2c_adapter *adapter = ara->adapter;
142 int res;
143
144 alert = kzalloc(sizeof(struct i2c_smbus_alert), GFP_KERNEL);
145 if (!alert)
146 return -ENOMEM;
147
148 alert->alert_edge_triggered = setup->alert_edge_triggered;
149 alert->irq = setup->irq;
150 INIT_WORK(&alert->alert, smbus_alert);
151 alert->ara = ara;
152
153 if (setup->irq > 0) {
154 res = devm_request_irq(&ara->dev, setup->irq, smbalert_irq,
155 0, "smbus_alert", alert);
156 if (res) {
157 kfree(alert);
158 return res;
159 }
160 }
161
162 i2c_set_clientdata(ara, alert);
163 dev_info(&adapter->dev, "supports SMBALERT#, %s trigger\n",
164 setup->alert_edge_triggered ? "edge" : "level");
165
166 return 0;
167}
168
169/* IRQ resource is managed so it is freed automatically */
170static int smbalert_remove(struct i2c_client *ara)
171{
172 struct i2c_smbus_alert *alert = i2c_get_clientdata(ara);
173
174 cancel_work_sync(&alert->alert);
175
176 i2c_set_clientdata(ara, NULL);
177 kfree(alert);
178 return 0;
179}
180
181static const struct i2c_device_id smbalert_ids[] = {
182 { "smbus_alert", 0 },
183 { /* LIST END */ }
184};
185MODULE_DEVICE_TABLE(i2c, smbalert_ids);
186
187static struct i2c_driver smbalert_driver = {
188 .driver = {
189 .name = "smbus_alert",
190 },
191 .probe = smbalert_probe,
192 .remove = smbalert_remove,
193 .id_table = smbalert_ids,
194};
195
196/**
197 * i2c_setup_smbus_alert - Setup SMBus alert support
198 * @adapter: the target adapter
199 * @setup: setup data for the SMBus alert handler
200 * Context: can sleep
201 *
202 * Setup handling of the SMBus alert protocol on a given I2C bus segment.
203 *
204 * Handling can be done either through our IRQ handler, or by the
205 * adapter (from its handler, periodic polling, or whatever).
206 *
207 * NOTE that if we manage the IRQ, we *MUST* know if it's level or
208 * edge triggered in order to hand it to the workqueue correctly.
209 * If triggering the alert seems to wedge the system, you probably
210 * should have said it's level triggered.
211 *
212 * This returns the ara client, which should be saved for later use with
213 * i2c_handle_smbus_alert() and ultimately i2c_unregister_device(); or NULL
214 * to indicate an error.
215 */
216struct i2c_client *i2c_setup_smbus_alert(struct i2c_adapter *adapter,
217 struct i2c_smbus_alert_setup *setup)
218{
219 struct i2c_board_info ara_board_info = {
220 I2C_BOARD_INFO("smbus_alert", 0x0c),
221 .platform_data = setup,
222 };
223
224 return i2c_new_device(adapter, &ara_board_info);
225}
226EXPORT_SYMBOL_GPL(i2c_setup_smbus_alert);
227
228/**
229 * i2c_handle_smbus_alert - Handle an SMBus alert
230 * @ara: the ARA client on the relevant adapter
231 * Context: can't sleep
232 *
233 * Helper function to be called from an I2C bus driver's interrupt
234 * handler. It will schedule the alert work, in turn calling the
235 * corresponding I2C device driver's alert function.
236 *
237 * It is assumed that ara is a valid i2c client previously returned by
238 * i2c_setup_smbus_alert().
239 */
240int i2c_handle_smbus_alert(struct i2c_client *ara)
241{
242 struct i2c_smbus_alert *alert = i2c_get_clientdata(ara);
243
244 return schedule_work(&alert->alert);
245}
246EXPORT_SYMBOL_GPL(i2c_handle_smbus_alert);
247
248static int __init i2c_smbus_init(void)
249{
250 return i2c_add_driver(&smbalert_driver);
251}
252
253static void __exit i2c_smbus_exit(void)
254{
255 i2c_del_driver(&smbalert_driver);
256}
257
258module_init(i2c_smbus_init);
259module_exit(i2c_smbus_exit);
260
261MODULE_AUTHOR("Jean Delvare <khali@linux-fr.org>");
262MODULE_DESCRIPTION("SMBus protocol extensions support");
263MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-13 05:43:12 -0400