diff options
author | Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com> | 2011-10-06 14:26:25 -0400 |
---|---|---|
committer | Ben Dooks <ben-linux@fluff.org> | 2011-10-29 06:00:50 -0400 |
commit | 7f279601c59b814314083d572e7c0df11d09cad8 (patch) | |
tree | 2904038ce32076e0938a3627ff7e402600d2b2bb /drivers/i2c | |
parent | 1fdb24e969110fafea36d3b393bea438f702c87f (diff) |
i2c-designware: Use local version of readl & writel
Use local versions of readl & writel, so per-access manipulations may be performed
Signed-off-by: Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'drivers/i2c')
-rw-r--r-- | drivers/i2c/busses/i2c-designware.c | 88 |
1 files changed, 49 insertions, 39 deletions
diff --git a/drivers/i2c/busses/i2c-designware.c b/drivers/i2c/busses/i2c-designware.c index 1b42b50b5992..28335c3717d9 100644 --- a/drivers/i2c/busses/i2c-designware.c +++ b/drivers/i2c/busses/i2c-designware.c | |||
@@ -220,6 +220,16 @@ struct dw_i2c_dev { | |||
220 | unsigned int rx_fifo_depth; | 220 | unsigned int rx_fifo_depth; |
221 | }; | 221 | }; |
222 | 222 | ||
223 | static u32 dw_readl(struct dw_i2c_dev *dev, int offset) | ||
224 | { | ||
225 | return readl(dev->base + offset); | ||
226 | } | ||
227 | |||
228 | static void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset) | ||
229 | { | ||
230 | writel(b, dev->base + offset); | ||
231 | } | ||
232 | |||
223 | static u32 | 233 | static u32 |
224 | i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset) | 234 | i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset) |
225 | { | 235 | { |
@@ -289,7 +299,7 @@ static void i2c_dw_init(struct dw_i2c_dev *dev) | |||
289 | u32 ic_con, hcnt, lcnt; | 299 | u32 ic_con, hcnt, lcnt; |
290 | 300 | ||
291 | /* Disable the adapter */ | 301 | /* Disable the adapter */ |
292 | writel(0, dev->base + DW_IC_ENABLE); | 302 | dw_writel(dev, 0, DW_IC_ENABLE); |
293 | 303 | ||
294 | /* set standard and fast speed deviders for high/low periods */ | 304 | /* set standard and fast speed deviders for high/low periods */ |
295 | 305 | ||
@@ -303,8 +313,8 @@ static void i2c_dw_init(struct dw_i2c_dev *dev) | |||
303 | 47, /* tLOW = 4.7 us */ | 313 | 47, /* tLOW = 4.7 us */ |
304 | 3, /* tf = 0.3 us */ | 314 | 3, /* tf = 0.3 us */ |
305 | 0); /* No offset */ | 315 | 0); /* No offset */ |
306 | writel(hcnt, dev->base + DW_IC_SS_SCL_HCNT); | 316 | dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT); |
307 | writel(lcnt, dev->base + DW_IC_SS_SCL_LCNT); | 317 | dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT); |
308 | dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); | 318 | dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); |
309 | 319 | ||
310 | /* Fast-mode */ | 320 | /* Fast-mode */ |
@@ -317,18 +327,18 @@ static void i2c_dw_init(struct dw_i2c_dev *dev) | |||
317 | 13, /* tLOW = 1.3 us */ | 327 | 13, /* tLOW = 1.3 us */ |
318 | 3, /* tf = 0.3 us */ | 328 | 3, /* tf = 0.3 us */ |
319 | 0); /* No offset */ | 329 | 0); /* No offset */ |
320 | writel(hcnt, dev->base + DW_IC_FS_SCL_HCNT); | 330 | dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT); |
321 | writel(lcnt, dev->base + DW_IC_FS_SCL_LCNT); | 331 | dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT); |
322 | dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); | 332 | dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); |
323 | 333 | ||
324 | /* Configure Tx/Rx FIFO threshold levels */ | 334 | /* Configure Tx/Rx FIFO threshold levels */ |
325 | writel(dev->tx_fifo_depth - 1, dev->base + DW_IC_TX_TL); | 335 | dw_writel(dev, dev->tx_fifo_depth - 1, DW_IC_TX_TL); |
326 | writel(0, dev->base + DW_IC_RX_TL); | 336 | dw_writel(dev, 0, DW_IC_RX_TL); |
327 | 337 | ||
328 | /* configure the i2c master */ | 338 | /* configure the i2c master */ |
329 | ic_con = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE | | 339 | ic_con = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE | |
330 | DW_IC_CON_RESTART_EN | DW_IC_CON_SPEED_FAST; | 340 | DW_IC_CON_RESTART_EN | DW_IC_CON_SPEED_FAST; |
331 | writel(ic_con, dev->base + DW_IC_CON); | 341 | dw_writel(dev, ic_con, DW_IC_CON); |
332 | } | 342 | } |
333 | 343 | ||
334 | /* | 344 | /* |
@@ -338,7 +348,7 @@ static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev) | |||
338 | { | 348 | { |
339 | int timeout = TIMEOUT; | 349 | int timeout = TIMEOUT; |
340 | 350 | ||
341 | while (readl(dev->base + DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) { | 351 | while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) { |
342 | if (timeout <= 0) { | 352 | if (timeout <= 0) { |
343 | dev_warn(dev->dev, "timeout waiting for bus ready\n"); | 353 | dev_warn(dev->dev, "timeout waiting for bus ready\n"); |
344 | return -ETIMEDOUT; | 354 | return -ETIMEDOUT; |
@@ -356,24 +366,24 @@ static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) | |||
356 | u32 ic_con; | 366 | u32 ic_con; |
357 | 367 | ||
358 | /* Disable the adapter */ | 368 | /* Disable the adapter */ |
359 | writel(0, dev->base + DW_IC_ENABLE); | 369 | dw_writel(dev, 0, DW_IC_ENABLE); |
360 | 370 | ||
361 | /* set the slave (target) address */ | 371 | /* set the slave (target) address */ |
362 | writel(msgs[dev->msg_write_idx].addr, dev->base + DW_IC_TAR); | 372 | dw_writel(dev, msgs[dev->msg_write_idx].addr, DW_IC_TAR); |
363 | 373 | ||
364 | /* if the slave address is ten bit address, enable 10BITADDR */ | 374 | /* if the slave address is ten bit address, enable 10BITADDR */ |
365 | ic_con = readl(dev->base + DW_IC_CON); | 375 | ic_con = dw_readl(dev, DW_IC_CON); |
366 | if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) | 376 | if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) |
367 | ic_con |= DW_IC_CON_10BITADDR_MASTER; | 377 | ic_con |= DW_IC_CON_10BITADDR_MASTER; |
368 | else | 378 | else |
369 | ic_con &= ~DW_IC_CON_10BITADDR_MASTER; | 379 | ic_con &= ~DW_IC_CON_10BITADDR_MASTER; |
370 | writel(ic_con, dev->base + DW_IC_CON); | 380 | dw_writel(dev, ic_con, DW_IC_CON); |
371 | 381 | ||
372 | /* Enable the adapter */ | 382 | /* Enable the adapter */ |
373 | writel(1, dev->base + DW_IC_ENABLE); | 383 | dw_writel(dev, 1, DW_IC_ENABLE); |
374 | 384 | ||
375 | /* Enable interrupts */ | 385 | /* Enable interrupts */ |
376 | writel(DW_IC_INTR_DEFAULT_MASK, dev->base + DW_IC_INTR_MASK); | 386 | dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK); |
377 | } | 387 | } |
378 | 388 | ||
379 | /* | 389 | /* |
@@ -420,15 +430,15 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev) | |||
420 | buf_len = msgs[dev->msg_write_idx].len; | 430 | buf_len = msgs[dev->msg_write_idx].len; |
421 | } | 431 | } |
422 | 432 | ||
423 | tx_limit = dev->tx_fifo_depth - readl(dev->base + DW_IC_TXFLR); | 433 | tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR); |
424 | rx_limit = dev->rx_fifo_depth - readl(dev->base + DW_IC_RXFLR); | 434 | rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR); |
425 | 435 | ||
426 | while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) { | 436 | while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) { |
427 | if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { | 437 | if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { |
428 | writel(0x100, dev->base + DW_IC_DATA_CMD); | 438 | dw_writel(dev, 0x100, DW_IC_DATA_CMD); |
429 | rx_limit--; | 439 | rx_limit--; |
430 | } else | 440 | } else |
431 | writel(*buf++, dev->base + DW_IC_DATA_CMD); | 441 | dw_writel(dev, *buf++, DW_IC_DATA_CMD); |
432 | tx_limit--; buf_len--; | 442 | tx_limit--; buf_len--; |
433 | } | 443 | } |
434 | 444 | ||
@@ -453,7 +463,7 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev) | |||
453 | if (dev->msg_err) | 463 | if (dev->msg_err) |
454 | intr_mask = 0; | 464 | intr_mask = 0; |
455 | 465 | ||
456 | writel(intr_mask, dev->base + DW_IC_INTR_MASK); | 466 | dw_writel(dev, intr_mask, DW_IC_INTR_MASK); |
457 | } | 467 | } |
458 | 468 | ||
459 | static void | 469 | static void |
@@ -477,10 +487,10 @@ i2c_dw_read(struct dw_i2c_dev *dev) | |||
477 | buf = dev->rx_buf; | 487 | buf = dev->rx_buf; |
478 | } | 488 | } |
479 | 489 | ||
480 | rx_valid = readl(dev->base + DW_IC_RXFLR); | 490 | rx_valid = dw_readl(dev, DW_IC_RXFLR); |
481 | 491 | ||
482 | for (; len > 0 && rx_valid > 0; len--, rx_valid--) | 492 | for (; len > 0 && rx_valid > 0; len--, rx_valid--) |
483 | *buf++ = readl(dev->base + DW_IC_DATA_CMD); | 493 | *buf++ = dw_readl(dev, DW_IC_DATA_CMD); |
484 | 494 | ||
485 | if (len > 0) { | 495 | if (len > 0) { |
486 | dev->status |= STATUS_READ_IN_PROGRESS; | 496 | dev->status |= STATUS_READ_IN_PROGRESS; |
@@ -563,7 +573,7 @@ i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) | |||
563 | /* no error */ | 573 | /* no error */ |
564 | if (likely(!dev->cmd_err)) { | 574 | if (likely(!dev->cmd_err)) { |
565 | /* Disable the adapter */ | 575 | /* Disable the adapter */ |
566 | writel(0, dev->base + DW_IC_ENABLE); | 576 | dw_writel(dev, 0, DW_IC_ENABLE); |
567 | ret = num; | 577 | ret = num; |
568 | goto done; | 578 | goto done; |
569 | } | 579 | } |
@@ -607,7 +617,7 @@ static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev) | |||
607 | * | 617 | * |
608 | * The raw version might be useful for debugging purposes. | 618 | * The raw version might be useful for debugging purposes. |
609 | */ | 619 | */ |
610 | stat = readl(dev->base + DW_IC_INTR_STAT); | 620 | stat = dw_readl(dev, DW_IC_INTR_STAT); |
611 | 621 | ||
612 | /* | 622 | /* |
613 | * Do not use the IC_CLR_INTR register to clear interrupts, or | 623 | * Do not use the IC_CLR_INTR register to clear interrupts, or |
@@ -617,31 +627,31 @@ static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev) | |||
617 | * Instead, use the separately-prepared IC_CLR_* registers. | 627 | * Instead, use the separately-prepared IC_CLR_* registers. |
618 | */ | 628 | */ |
619 | if (stat & DW_IC_INTR_RX_UNDER) | 629 | if (stat & DW_IC_INTR_RX_UNDER) |
620 | readl(dev->base + DW_IC_CLR_RX_UNDER); | 630 | dw_readl(dev, DW_IC_CLR_RX_UNDER); |
621 | if (stat & DW_IC_INTR_RX_OVER) | 631 | if (stat & DW_IC_INTR_RX_OVER) |
622 | readl(dev->base + DW_IC_CLR_RX_OVER); | 632 | dw_readl(dev, DW_IC_CLR_RX_OVER); |
623 | if (stat & DW_IC_INTR_TX_OVER) | 633 | if (stat & DW_IC_INTR_TX_OVER) |
624 | readl(dev->base + DW_IC_CLR_TX_OVER); | 634 | dw_readl(dev, DW_IC_CLR_TX_OVER); |
625 | if (stat & DW_IC_INTR_RD_REQ) | 635 | if (stat & DW_IC_INTR_RD_REQ) |
626 | readl(dev->base + DW_IC_CLR_RD_REQ); | 636 | dw_readl(dev, DW_IC_CLR_RD_REQ); |
627 | if (stat & DW_IC_INTR_TX_ABRT) { | 637 | if (stat & DW_IC_INTR_TX_ABRT) { |
628 | /* | 638 | /* |
629 | * The IC_TX_ABRT_SOURCE register is cleared whenever | 639 | * The IC_TX_ABRT_SOURCE register is cleared whenever |
630 | * the IC_CLR_TX_ABRT is read. Preserve it beforehand. | 640 | * the IC_CLR_TX_ABRT is read. Preserve it beforehand. |
631 | */ | 641 | */ |
632 | dev->abort_source = readl(dev->base + DW_IC_TX_ABRT_SOURCE); | 642 | dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE); |
633 | readl(dev->base + DW_IC_CLR_TX_ABRT); | 643 | dw_readl(dev, DW_IC_CLR_TX_ABRT); |
634 | } | 644 | } |
635 | if (stat & DW_IC_INTR_RX_DONE) | 645 | if (stat & DW_IC_INTR_RX_DONE) |
636 | readl(dev->base + DW_IC_CLR_RX_DONE); | 646 | dw_readl(dev, DW_IC_CLR_RX_DONE); |
637 | if (stat & DW_IC_INTR_ACTIVITY) | 647 | if (stat & DW_IC_INTR_ACTIVITY) |
638 | readl(dev->base + DW_IC_CLR_ACTIVITY); | 648 | dw_readl(dev, DW_IC_CLR_ACTIVITY); |
639 | if (stat & DW_IC_INTR_STOP_DET) | 649 | if (stat & DW_IC_INTR_STOP_DET) |
640 | readl(dev->base + DW_IC_CLR_STOP_DET); | 650 | dw_readl(dev, DW_IC_CLR_STOP_DET); |
641 | if (stat & DW_IC_INTR_START_DET) | 651 | if (stat & DW_IC_INTR_START_DET) |
642 | readl(dev->base + DW_IC_CLR_START_DET); | 652 | dw_readl(dev, DW_IC_CLR_START_DET); |
643 | if (stat & DW_IC_INTR_GEN_CALL) | 653 | if (stat & DW_IC_INTR_GEN_CALL) |
644 | readl(dev->base + DW_IC_CLR_GEN_CALL); | 654 | dw_readl(dev, DW_IC_CLR_GEN_CALL); |
645 | 655 | ||
646 | return stat; | 656 | return stat; |
647 | } | 657 | } |
@@ -666,7 +676,7 @@ static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) | |||
666 | * Anytime TX_ABRT is set, the contents of the tx/rx | 676 | * Anytime TX_ABRT is set, the contents of the tx/rx |
667 | * buffers are flushed. Make sure to skip them. | 677 | * buffers are flushed. Make sure to skip them. |
668 | */ | 678 | */ |
669 | writel(0, dev->base + DW_IC_INTR_MASK); | 679 | dw_writel(dev, 0, DW_IC_INTR_MASK); |
670 | goto tx_aborted; | 680 | goto tx_aborted; |
671 | } | 681 | } |
672 | 682 | ||
@@ -747,14 +757,14 @@ static int __devinit dw_i2c_probe(struct platform_device *pdev) | |||
747 | goto err_unuse_clocks; | 757 | goto err_unuse_clocks; |
748 | } | 758 | } |
749 | { | 759 | { |
750 | u32 param1 = readl(dev->base + DW_IC_COMP_PARAM_1); | 760 | u32 param1 = dw_readl(dev, DW_IC_COMP_PARAM_1); |
751 | 761 | ||
752 | dev->tx_fifo_depth = ((param1 >> 16) & 0xff) + 1; | 762 | dev->tx_fifo_depth = ((param1 >> 16) & 0xff) + 1; |
753 | dev->rx_fifo_depth = ((param1 >> 8) & 0xff) + 1; | 763 | dev->rx_fifo_depth = ((param1 >> 8) & 0xff) + 1; |
754 | } | 764 | } |
755 | i2c_dw_init(dev); | 765 | i2c_dw_init(dev); |
756 | 766 | ||
757 | writel(0, dev->base + DW_IC_INTR_MASK); /* disable IRQ */ | 767 | dw_writel(dev, 0, DW_IC_INTR_MASK); /* disable IRQ */ |
758 | r = request_irq(dev->irq, i2c_dw_isr, IRQF_DISABLED, pdev->name, dev); | 768 | r = request_irq(dev->irq, i2c_dw_isr, IRQF_DISABLED, pdev->name, dev); |
759 | if (r) { | 769 | if (r) { |
760 | dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq); | 770 | dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq); |
@@ -810,7 +820,7 @@ static int __devexit dw_i2c_remove(struct platform_device *pdev) | |||
810 | clk_put(dev->clk); | 820 | clk_put(dev->clk); |
811 | dev->clk = NULL; | 821 | dev->clk = NULL; |
812 | 822 | ||
813 | writel(0, dev->base + DW_IC_ENABLE); | 823 | dw_writel(dev, 0, DW_IC_ENABLE); |
814 | free_irq(dev->irq, dev); | 824 | free_irq(dev->irq, dev); |
815 | kfree(dev); | 825 | kfree(dev); |
816 | 826 | ||