diff options
author | Ben Dooks <ben-linux@fluff.org> | 2008-12-16 17:06:30 -0500 |
---|---|---|
committer | Ben Dooks <ben-linux@fluff.org> | 2008-12-16 17:06:30 -0500 |
commit | 5a93f42017a3d1dc7869939d46d4158732227dd7 (patch) | |
tree | 9bdf12c1e066b472866e14bc8c70f8c8d93b8998 /drivers/i2c | |
parent | 1bda71282ded6a2e09a2db7c8884542fb46bfd4f (diff) | |
parent | 5043e9e737c4909e7f187d479227df46f5a2dd53 (diff) |
Merge branch 'i2c-for-ben' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 into i2c-next
Diffstat (limited to 'drivers/i2c')
-rw-r--r-- | drivers/i2c/busses/i2c-omap.c | 420 |
1 files changed, 328 insertions, 92 deletions
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c index 608038d64f81..96f3bedb2799 100644 --- a/drivers/i2c/busses/i2c-omap.c +++ b/drivers/i2c/busses/i2c-omap.c | |||
@@ -2,13 +2,16 @@ | |||
2 | * TI OMAP I2C master mode driver | 2 | * TI OMAP I2C master mode driver |
3 | * | 3 | * |
4 | * Copyright (C) 2003 MontaVista Software, Inc. | 4 | * Copyright (C) 2003 MontaVista Software, Inc. |
5 | * Copyright (C) 2004 Texas Instruments. | ||
6 | * | ||
7 | * Updated to work with multiple I2C interfaces on 24xx by | ||
8 | * Tony Lindgren <tony@atomide.com> and Imre Deak <imre.deak@nokia.com> | ||
9 | * Copyright (C) 2005 Nokia Corporation | 5 | * Copyright (C) 2005 Nokia Corporation |
6 | * Copyright (C) 2004 - 2007 Texas Instruments. | ||
10 | * | 7 | * |
11 | * Cleaned up by Juha Yrjölä <juha.yrjola@nokia.com> | 8 | * Originally written by MontaVista Software, Inc. |
9 | * Additional contributions by: | ||
10 | * Tony Lindgren <tony@atomide.com> | ||
11 | * Imre Deak <imre.deak@nokia.com> | ||
12 | * Juha Yrjölä <juha.yrjola@solidboot.com> | ||
13 | * Syed Khasim <x0khasim@ti.com> | ||
14 | * Nishant Menon <nm@ti.com> | ||
12 | * | 15 | * |
13 | * This program is free software; you can redistribute it and/or modify | 16 | * This program is free software; you can redistribute it and/or modify |
14 | * it under the terms of the GNU General Public License as published by | 17 | * it under the terms of the GNU General Public License as published by |
@@ -33,8 +36,14 @@ | |||
33 | #include <linux/completion.h> | 36 | #include <linux/completion.h> |
34 | #include <linux/platform_device.h> | 37 | #include <linux/platform_device.h> |
35 | #include <linux/clk.h> | 38 | #include <linux/clk.h> |
39 | #include <linux/io.h> | ||
40 | |||
41 | /* I2C controller revisions */ | ||
42 | #define OMAP_I2C_REV_2 0x20 | ||
36 | 43 | ||
37 | #include <asm/io.h> | 44 | /* I2C controller revisions present on specific hardware */ |
45 | #define OMAP_I2C_REV_ON_2430 0x36 | ||
46 | #define OMAP_I2C_REV_ON_3430 0x3C | ||
38 | 47 | ||
39 | /* timeout waiting for the controller to respond */ | 48 | /* timeout waiting for the controller to respond */ |
40 | #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000)) | 49 | #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000)) |
@@ -43,6 +52,8 @@ | |||
43 | #define OMAP_I2C_IE_REG 0x04 | 52 | #define OMAP_I2C_IE_REG 0x04 |
44 | #define OMAP_I2C_STAT_REG 0x08 | 53 | #define OMAP_I2C_STAT_REG 0x08 |
45 | #define OMAP_I2C_IV_REG 0x0c | 54 | #define OMAP_I2C_IV_REG 0x0c |
55 | /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */ | ||
56 | #define OMAP_I2C_WE_REG 0x0c | ||
46 | #define OMAP_I2C_SYSS_REG 0x10 | 57 | #define OMAP_I2C_SYSS_REG 0x10 |
47 | #define OMAP_I2C_BUF_REG 0x14 | 58 | #define OMAP_I2C_BUF_REG 0x14 |
48 | #define OMAP_I2C_CNT_REG 0x18 | 59 | #define OMAP_I2C_CNT_REG 0x18 |
@@ -55,8 +66,11 @@ | |||
55 | #define OMAP_I2C_SCLL_REG 0x34 | 66 | #define OMAP_I2C_SCLL_REG 0x34 |
56 | #define OMAP_I2C_SCLH_REG 0x38 | 67 | #define OMAP_I2C_SCLH_REG 0x38 |
57 | #define OMAP_I2C_SYSTEST_REG 0x3c | 68 | #define OMAP_I2C_SYSTEST_REG 0x3c |
69 | #define OMAP_I2C_BUFSTAT_REG 0x40 | ||
58 | 70 | ||
59 | /* I2C Interrupt Enable Register (OMAP_I2C_IE): */ | 71 | /* I2C Interrupt Enable Register (OMAP_I2C_IE): */ |
72 | #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */ | ||
73 | #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */ | ||
60 | #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */ | 74 | #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */ |
61 | #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */ | 75 | #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */ |
62 | #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */ | 76 | #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */ |
@@ -64,7 +78,8 @@ | |||
64 | #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */ | 78 | #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */ |
65 | 79 | ||
66 | /* I2C Status Register (OMAP_I2C_STAT): */ | 80 | /* I2C Status Register (OMAP_I2C_STAT): */ |
67 | #define OMAP_I2C_STAT_SBD (1 << 15) /* Single byte data */ | 81 | #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */ |
82 | #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */ | ||
68 | #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */ | 83 | #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */ |
69 | #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */ | 84 | #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */ |
70 | #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ | 85 | #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ |
@@ -76,13 +91,34 @@ | |||
76 | #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */ | 91 | #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */ |
77 | #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */ | 92 | #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */ |
78 | 93 | ||
94 | /* I2C WE wakeup enable register */ | ||
95 | #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */ | ||
96 | #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */ | ||
97 | #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/ | ||
98 | #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */ | ||
99 | #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */ | ||
100 | #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */ | ||
101 | #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */ | ||
102 | #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */ | ||
103 | #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */ | ||
104 | #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */ | ||
105 | |||
106 | #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \ | ||
107 | OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \ | ||
108 | OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \ | ||
109 | OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \ | ||
110 | OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE) | ||
111 | |||
79 | /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */ | 112 | /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */ |
80 | #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */ | 113 | #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */ |
114 | #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */ | ||
81 | #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */ | 115 | #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */ |
116 | #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */ | ||
82 | 117 | ||
83 | /* I2C Configuration Register (OMAP_I2C_CON): */ | 118 | /* I2C Configuration Register (OMAP_I2C_CON): */ |
84 | #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */ | 119 | #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */ |
85 | #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */ | 120 | #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */ |
121 | #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */ | ||
86 | #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */ | 122 | #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */ |
87 | #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */ | 123 | #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */ |
88 | #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */ | 124 | #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */ |
@@ -91,6 +127,10 @@ | |||
91 | #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */ | 127 | #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */ |
92 | #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */ | 128 | #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */ |
93 | 129 | ||
130 | /* I2C SCL time value when Master */ | ||
131 | #define OMAP_I2C_SCLL_HSSCLL 8 | ||
132 | #define OMAP_I2C_SCLH_HSSCLH 8 | ||
133 | |||
94 | /* I2C System Test Register (OMAP_I2C_SYSTEST): */ | 134 | /* I2C System Test Register (OMAP_I2C_SYSTEST): */ |
95 | #ifdef DEBUG | 135 | #ifdef DEBUG |
96 | #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ | 136 | #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ |
@@ -103,17 +143,19 @@ | |||
103 | #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */ | 143 | #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */ |
104 | #endif | 144 | #endif |
105 | 145 | ||
106 | /* I2C System Status register (OMAP_I2C_SYSS): */ | 146 | /* OCP_SYSSTATUS bit definitions */ |
107 | #define OMAP_I2C_SYSS_RDONE (1 << 0) /* Reset Done */ | 147 | #define SYSS_RESETDONE_MASK (1 << 0) |
148 | |||
149 | /* OCP_SYSCONFIG bit definitions */ | ||
150 | #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8) | ||
151 | #define SYSC_SIDLEMODE_MASK (0x3 << 3) | ||
152 | #define SYSC_ENAWAKEUP_MASK (1 << 2) | ||
153 | #define SYSC_SOFTRESET_MASK (1 << 1) | ||
154 | #define SYSC_AUTOIDLE_MASK (1 << 0) | ||
108 | 155 | ||
109 | /* I2C System Configuration Register (OMAP_I2C_SYSC): */ | 156 | #define SYSC_IDLEMODE_SMART 0x2 |
110 | #define OMAP_I2C_SYSC_SRST (1 << 1) /* Soft Reset */ | 157 | #define SYSC_CLOCKACTIVITY_FCLK 0x2 |
111 | 158 | ||
112 | /* REVISIT: Use platform_data instead of module parameters */ | ||
113 | /* Fast Mode = 400 kHz, Standard = 100 kHz */ | ||
114 | static int clock = 100; /* Default: 100 kHz */ | ||
115 | module_param(clock, int, 0); | ||
116 | MODULE_PARM_DESC(clock, "Set I2C clock in kHz: 400=fast mode (default == 100)"); | ||
117 | 159 | ||
118 | struct omap_i2c_dev { | 160 | struct omap_i2c_dev { |
119 | struct device *dev; | 161 | struct device *dev; |
@@ -123,11 +165,17 @@ struct omap_i2c_dev { | |||
123 | struct clk *fclk; /* Functional clock */ | 165 | struct clk *fclk; /* Functional clock */ |
124 | struct completion cmd_complete; | 166 | struct completion cmd_complete; |
125 | struct resource *ioarea; | 167 | struct resource *ioarea; |
168 | u32 speed; /* Speed of bus in Khz */ | ||
126 | u16 cmd_err; | 169 | u16 cmd_err; |
127 | u8 *buf; | 170 | u8 *buf; |
128 | size_t buf_len; | 171 | size_t buf_len; |
129 | struct i2c_adapter adapter; | 172 | struct i2c_adapter adapter; |
130 | unsigned rev1:1; | 173 | u8 fifo_size; /* use as flag and value |
174 | * fifo_size==0 implies no fifo | ||
175 | * if set, should be trsh+1 | ||
176 | */ | ||
177 | u8 rev; | ||
178 | unsigned b_hw:1; /* bad h/w fixes */ | ||
131 | unsigned idle:1; | 179 | unsigned idle:1; |
132 | u16 iestate; /* Saved interrupt register */ | 180 | u16 iestate; /* Saved interrupt register */ |
133 | }; | 181 | }; |
@@ -143,9 +191,9 @@ static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg) | |||
143 | return __raw_readw(i2c_dev->base + reg); | 191 | return __raw_readw(i2c_dev->base + reg); |
144 | } | 192 | } |
145 | 193 | ||
146 | static int omap_i2c_get_clocks(struct omap_i2c_dev *dev) | 194 | static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev) |
147 | { | 195 | { |
148 | if (cpu_is_omap16xx() || cpu_is_omap24xx()) { | 196 | if (cpu_is_omap16xx() || cpu_class_is_omap2()) { |
149 | dev->iclk = clk_get(dev->dev, "i2c_ick"); | 197 | dev->iclk = clk_get(dev->dev, "i2c_ick"); |
150 | if (IS_ERR(dev->iclk)) { | 198 | if (IS_ERR(dev->iclk)) { |
151 | dev->iclk = NULL; | 199 | dev->iclk = NULL; |
@@ -178,25 +226,33 @@ static void omap_i2c_put_clocks(struct omap_i2c_dev *dev) | |||
178 | 226 | ||
179 | static void omap_i2c_unidle(struct omap_i2c_dev *dev) | 227 | static void omap_i2c_unidle(struct omap_i2c_dev *dev) |
180 | { | 228 | { |
229 | WARN_ON(!dev->idle); | ||
230 | |||
181 | if (dev->iclk != NULL) | 231 | if (dev->iclk != NULL) |
182 | clk_enable(dev->iclk); | 232 | clk_enable(dev->iclk); |
183 | clk_enable(dev->fclk); | 233 | clk_enable(dev->fclk); |
234 | dev->idle = 0; | ||
184 | if (dev->iestate) | 235 | if (dev->iestate) |
185 | omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate); | 236 | omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate); |
186 | dev->idle = 0; | ||
187 | } | 237 | } |
188 | 238 | ||
189 | static void omap_i2c_idle(struct omap_i2c_dev *dev) | 239 | static void omap_i2c_idle(struct omap_i2c_dev *dev) |
190 | { | 240 | { |
191 | u16 iv; | 241 | u16 iv; |
192 | 242 | ||
193 | dev->idle = 1; | 243 | WARN_ON(dev->idle); |
244 | |||
194 | dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); | 245 | dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG); |
195 | omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0); | 246 | omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0); |
196 | if (dev->rev1) | 247 | if (dev->rev < OMAP_I2C_REV_2) { |
197 | iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */ | 248 | iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */ |
198 | else | 249 | } else { |
199 | omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate); | 250 | omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate); |
251 | |||
252 | /* Flush posted write before the dev->idle store occurs */ | ||
253 | omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG); | ||
254 | } | ||
255 | dev->idle = 1; | ||
200 | clk_disable(dev->fclk); | 256 | clk_disable(dev->fclk); |
201 | if (dev->iclk != NULL) | 257 | if (dev->iclk != NULL) |
202 | clk_disable(dev->iclk); | 258 | clk_disable(dev->iclk); |
@@ -204,18 +260,20 @@ static void omap_i2c_idle(struct omap_i2c_dev *dev) | |||
204 | 260 | ||
205 | static int omap_i2c_init(struct omap_i2c_dev *dev) | 261 | static int omap_i2c_init(struct omap_i2c_dev *dev) |
206 | { | 262 | { |
207 | u16 psc = 0; | 263 | u16 psc = 0, scll = 0, sclh = 0; |
264 | u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0; | ||
208 | unsigned long fclk_rate = 12000000; | 265 | unsigned long fclk_rate = 12000000; |
209 | unsigned long timeout; | 266 | unsigned long timeout; |
267 | unsigned long internal_clk = 0; | ||
210 | 268 | ||
211 | if (!dev->rev1) { | 269 | if (dev->rev >= OMAP_I2C_REV_2) { |
212 | omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, OMAP_I2C_SYSC_SRST); | 270 | omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK); |
213 | /* For some reason we need to set the EN bit before the | 271 | /* For some reason we need to set the EN bit before the |
214 | * reset done bit gets set. */ | 272 | * reset done bit gets set. */ |
215 | timeout = jiffies + OMAP_I2C_TIMEOUT; | 273 | timeout = jiffies + OMAP_I2C_TIMEOUT; |
216 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); | 274 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); |
217 | while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) & | 275 | while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) & |
218 | OMAP_I2C_SYSS_RDONE)) { | 276 | SYSS_RESETDONE_MASK)) { |
219 | if (time_after(jiffies, timeout)) { | 277 | if (time_after(jiffies, timeout)) { |
220 | dev_warn(dev->dev, "timeout waiting " | 278 | dev_warn(dev->dev, "timeout waiting " |
221 | "for controller reset\n"); | 279 | "for controller reset\n"); |
@@ -223,6 +281,33 @@ static int omap_i2c_init(struct omap_i2c_dev *dev) | |||
223 | } | 281 | } |
224 | msleep(1); | 282 | msleep(1); |
225 | } | 283 | } |
284 | |||
285 | /* SYSC register is cleared by the reset; rewrite it */ | ||
286 | if (dev->rev == OMAP_I2C_REV_ON_2430) { | ||
287 | |||
288 | omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, | ||
289 | SYSC_AUTOIDLE_MASK); | ||
290 | |||
291 | } else if (dev->rev >= OMAP_I2C_REV_ON_3430) { | ||
292 | u32 v; | ||
293 | |||
294 | v = SYSC_AUTOIDLE_MASK; | ||
295 | v |= SYSC_ENAWAKEUP_MASK; | ||
296 | v |= (SYSC_IDLEMODE_SMART << | ||
297 | __ffs(SYSC_SIDLEMODE_MASK)); | ||
298 | v |= (SYSC_CLOCKACTIVITY_FCLK << | ||
299 | __ffs(SYSC_CLOCKACTIVITY_MASK)); | ||
300 | |||
301 | omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, v); | ||
302 | /* | ||
303 | * Enabling all wakup sources to stop I2C freezing on | ||
304 | * WFI instruction. | ||
305 | * REVISIT: Some wkup sources might not be needed. | ||
306 | */ | ||
307 | omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, | ||
308 | OMAP_I2C_WE_ALL); | ||
309 | |||
310 | } | ||
226 | } | 311 | } |
227 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); | 312 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); |
228 | 313 | ||
@@ -249,27 +334,65 @@ static int omap_i2c_init(struct omap_i2c_dev *dev) | |||
249 | psc = fclk_rate / 12000000; | 334 | psc = fclk_rate / 12000000; |
250 | } | 335 | } |
251 | 336 | ||
337 | if (cpu_is_omap2430() || cpu_is_omap34xx()) { | ||
338 | |||
339 | /* HSI2C controller internal clk rate should be 19.2 Mhz */ | ||
340 | internal_clk = 19200; | ||
341 | fclk_rate = clk_get_rate(dev->fclk) / 1000; | ||
342 | |||
343 | /* Compute prescaler divisor */ | ||
344 | psc = fclk_rate / internal_clk; | ||
345 | psc = psc - 1; | ||
346 | |||
347 | /* If configured for High Speed */ | ||
348 | if (dev->speed > 400) { | ||
349 | /* For first phase of HS mode */ | ||
350 | fsscll = internal_clk / (400 * 2) - 6; | ||
351 | fssclh = internal_clk / (400 * 2) - 6; | ||
352 | |||
353 | /* For second phase of HS mode */ | ||
354 | hsscll = fclk_rate / (dev->speed * 2) - 6; | ||
355 | hssclh = fclk_rate / (dev->speed * 2) - 6; | ||
356 | } else { | ||
357 | /* To handle F/S modes */ | ||
358 | fsscll = internal_clk / (dev->speed * 2) - 6; | ||
359 | fssclh = internal_clk / (dev->speed * 2) - 6; | ||
360 | } | ||
361 | scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll; | ||
362 | sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh; | ||
363 | } else { | ||
364 | /* Program desired operating rate */ | ||
365 | fclk_rate /= (psc + 1) * 1000; | ||
366 | if (psc > 2) | ||
367 | psc = 2; | ||
368 | scll = fclk_rate / (dev->speed * 2) - 7 + psc; | ||
369 | sclh = fclk_rate / (dev->speed * 2) - 7 + psc; | ||
370 | } | ||
371 | |||
252 | /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */ | 372 | /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */ |
253 | omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc); | 373 | omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc); |
254 | 374 | ||
255 | /* Program desired operating rate */ | 375 | /* SCL low and high time values */ |
256 | fclk_rate /= (psc + 1) * 1000; | 376 | omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll); |
257 | if (psc > 2) | 377 | omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh); |
258 | psc = 2; | ||
259 | 378 | ||
260 | omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, | 379 | if (dev->fifo_size) |
261 | fclk_rate / (clock * 2) - 7 + psc); | 380 | /* Note: setup required fifo size - 1 */ |
262 | omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, | 381 | omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, |
263 | fclk_rate / (clock * 2) - 7 + psc); | 382 | (dev->fifo_size - 1) << 8 | /* RTRSH */ |
383 | OMAP_I2C_BUF_RXFIF_CLR | | ||
384 | (dev->fifo_size - 1) | /* XTRSH */ | ||
385 | OMAP_I2C_BUF_TXFIF_CLR); | ||
264 | 386 | ||
265 | /* Take the I2C module out of reset: */ | 387 | /* Take the I2C module out of reset: */ |
266 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); | 388 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); |
267 | 389 | ||
268 | /* Enable interrupts */ | 390 | /* Enable interrupts */ |
269 | omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, | 391 | omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, |
270 | (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY | | 392 | (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY | |
271 | OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK | | 393 | OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK | |
272 | OMAP_I2C_IE_AL)); | 394 | OMAP_I2C_IE_AL) | ((dev->fifo_size) ? |
395 | (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0)); | ||
273 | return 0; | 396 | return 0; |
274 | } | 397 | } |
275 | 398 | ||
@@ -316,20 +439,59 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap, | |||
316 | 439 | ||
317 | omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len); | 440 | omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len); |
318 | 441 | ||
442 | /* Clear the FIFO Buffers */ | ||
443 | w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG); | ||
444 | w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR; | ||
445 | omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w); | ||
446 | |||
319 | init_completion(&dev->cmd_complete); | 447 | init_completion(&dev->cmd_complete); |
320 | dev->cmd_err = 0; | 448 | dev->cmd_err = 0; |
321 | 449 | ||
322 | w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT; | 450 | w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT; |
451 | |||
452 | /* High speed configuration */ | ||
453 | if (dev->speed > 400) | ||
454 | w |= OMAP_I2C_CON_OPMODE_HS; | ||
455 | |||
323 | if (msg->flags & I2C_M_TEN) | 456 | if (msg->flags & I2C_M_TEN) |
324 | w |= OMAP_I2C_CON_XA; | 457 | w |= OMAP_I2C_CON_XA; |
325 | if (!(msg->flags & I2C_M_RD)) | 458 | if (!(msg->flags & I2C_M_RD)) |
326 | w |= OMAP_I2C_CON_TRX; | 459 | w |= OMAP_I2C_CON_TRX; |
327 | if (stop) | 460 | |
461 | if (!dev->b_hw && stop) | ||
328 | w |= OMAP_I2C_CON_STP; | 462 | w |= OMAP_I2C_CON_STP; |
463 | |||
329 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); | 464 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); |
330 | 465 | ||
331 | r = wait_for_completion_interruptible_timeout(&dev->cmd_complete, | 466 | /* |
332 | OMAP_I2C_TIMEOUT); | 467 | * Don't write stt and stp together on some hardware. |
468 | */ | ||
469 | if (dev->b_hw && stop) { | ||
470 | unsigned long delay = jiffies + OMAP_I2C_TIMEOUT; | ||
471 | u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); | ||
472 | while (con & OMAP_I2C_CON_STT) { | ||
473 | con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG); | ||
474 | |||
475 | /* Let the user know if i2c is in a bad state */ | ||
476 | if (time_after(jiffies, delay)) { | ||
477 | dev_err(dev->dev, "controller timed out " | ||
478 | "waiting for start condition to finish\n"); | ||
479 | return -ETIMEDOUT; | ||
480 | } | ||
481 | cpu_relax(); | ||
482 | } | ||
483 | |||
484 | w |= OMAP_I2C_CON_STP; | ||
485 | w &= ~OMAP_I2C_CON_STT; | ||
486 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); | ||
487 | } | ||
488 | |||
489 | /* | ||
490 | * REVISIT: We should abort the transfer on signals, but the bus goes | ||
491 | * into arbitration and we're currently unable to recover from it. | ||
492 | */ | ||
493 | r = wait_for_completion_timeout(&dev->cmd_complete, | ||
494 | OMAP_I2C_TIMEOUT); | ||
333 | dev->buf_len = 0; | 495 | dev->buf_len = 0; |
334 | if (r < 0) | 496 | if (r < 0) |
335 | return r; | 497 | return r; |
@@ -376,7 +538,8 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) | |||
376 | 538 | ||
377 | omap_i2c_unidle(dev); | 539 | omap_i2c_unidle(dev); |
378 | 540 | ||
379 | if ((r = omap_i2c_wait_for_bb(dev)) < 0) | 541 | r = omap_i2c_wait_for_bb(dev); |
542 | if (r < 0) | ||
380 | goto out; | 543 | goto out; |
381 | 544 | ||
382 | for (i = 0; i < num; i++) { | 545 | for (i = 0; i < num; i++) { |
@@ -411,6 +574,9 @@ omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat) | |||
411 | omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat); | 574 | omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat); |
412 | } | 575 | } |
413 | 576 | ||
577 | /* rev1 devices are apparently only on some 15xx */ | ||
578 | #ifdef CONFIG_ARCH_OMAP15XX | ||
579 | |||
414 | static irqreturn_t | 580 | static irqreturn_t |
415 | omap_i2c_rev1_isr(int this_irq, void *dev_id) | 581 | omap_i2c_rev1_isr(int this_irq, void *dev_id) |
416 | { | 582 | { |
@@ -465,6 +631,9 @@ omap_i2c_rev1_isr(int this_irq, void *dev_id) | |||
465 | 631 | ||
466 | return IRQ_HANDLED; | 632 | return IRQ_HANDLED; |
467 | } | 633 | } |
634 | #else | ||
635 | #define omap_i2c_rev1_isr NULL | ||
636 | #endif | ||
468 | 637 | ||
469 | static irqreturn_t | 638 | static irqreturn_t |
470 | omap_i2c_isr(int this_irq, void *dev_id) | 639 | omap_i2c_isr(int this_irq, void *dev_id) |
@@ -472,7 +641,7 @@ omap_i2c_isr(int this_irq, void *dev_id) | |||
472 | struct omap_i2c_dev *dev = dev_id; | 641 | struct omap_i2c_dev *dev = dev_id; |
473 | u16 bits; | 642 | u16 bits; |
474 | u16 stat, w; | 643 | u16 stat, w; |
475 | int count = 0; | 644 | int err, count = 0; |
476 | 645 | ||
477 | if (dev->idle) | 646 | if (dev->idle) |
478 | return IRQ_NONE; | 647 | return IRQ_NONE; |
@@ -487,39 +656,96 @@ omap_i2c_isr(int this_irq, void *dev_id) | |||
487 | 656 | ||
488 | omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat); | 657 | omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat); |
489 | 658 | ||
490 | if (stat & OMAP_I2C_STAT_ARDY) { | 659 | err = 0; |
491 | omap_i2c_complete_cmd(dev, 0); | 660 | if (stat & OMAP_I2C_STAT_NACK) { |
492 | continue; | 661 | err |= OMAP_I2C_STAT_NACK; |
662 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, | ||
663 | OMAP_I2C_CON_STP); | ||
493 | } | 664 | } |
494 | if (stat & OMAP_I2C_STAT_RRDY) { | 665 | if (stat & OMAP_I2C_STAT_AL) { |
495 | w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG); | 666 | dev_err(dev->dev, "Arbitration lost\n"); |
496 | if (dev->buf_len) { | 667 | err |= OMAP_I2C_STAT_AL; |
497 | *dev->buf++ = w; | 668 | } |
498 | dev->buf_len--; | 669 | if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK | |
670 | OMAP_I2C_STAT_AL)) | ||
671 | omap_i2c_complete_cmd(dev, err); | ||
672 | if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) { | ||
673 | u8 num_bytes = 1; | ||
674 | if (dev->fifo_size) { | ||
675 | if (stat & OMAP_I2C_STAT_RRDY) | ||
676 | num_bytes = dev->fifo_size; | ||
677 | else | ||
678 | num_bytes = omap_i2c_read_reg(dev, | ||
679 | OMAP_I2C_BUFSTAT_REG); | ||
680 | } | ||
681 | while (num_bytes) { | ||
682 | num_bytes--; | ||
683 | w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG); | ||
499 | if (dev->buf_len) { | 684 | if (dev->buf_len) { |
500 | *dev->buf++ = w >> 8; | 685 | *dev->buf++ = w; |
501 | dev->buf_len--; | 686 | dev->buf_len--; |
687 | /* Data reg from 2430 is 8 bit wide */ | ||
688 | if (!cpu_is_omap2430() && | ||
689 | !cpu_is_omap34xx()) { | ||
690 | if (dev->buf_len) { | ||
691 | *dev->buf++ = w >> 8; | ||
692 | dev->buf_len--; | ||
693 | } | ||
694 | } | ||
695 | } else { | ||
696 | if (stat & OMAP_I2C_STAT_RRDY) | ||
697 | dev_err(dev->dev, | ||
698 | "RRDY IRQ while no data" | ||
699 | " requested\n"); | ||
700 | if (stat & OMAP_I2C_STAT_RDR) | ||
701 | dev_err(dev->dev, | ||
702 | "RDR IRQ while no data" | ||
703 | " requested\n"); | ||
704 | break; | ||
502 | } | 705 | } |
503 | } else | 706 | } |
504 | dev_err(dev->dev, "RRDY IRQ while no data " | 707 | omap_i2c_ack_stat(dev, |
505 | "requested\n"); | 708 | stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)); |
506 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY); | ||
507 | continue; | 709 | continue; |
508 | } | 710 | } |
509 | if (stat & OMAP_I2C_STAT_XRDY) { | 711 | if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) { |
510 | w = 0; | 712 | u8 num_bytes = 1; |
511 | if (dev->buf_len) { | 713 | if (dev->fifo_size) { |
512 | w = *dev->buf++; | 714 | if (stat & OMAP_I2C_STAT_XRDY) |
513 | dev->buf_len--; | 715 | num_bytes = dev->fifo_size; |
716 | else | ||
717 | num_bytes = omap_i2c_read_reg(dev, | ||
718 | OMAP_I2C_BUFSTAT_REG); | ||
719 | } | ||
720 | while (num_bytes) { | ||
721 | num_bytes--; | ||
722 | w = 0; | ||
514 | if (dev->buf_len) { | 723 | if (dev->buf_len) { |
515 | w |= *dev->buf++ << 8; | 724 | w = *dev->buf++; |
516 | dev->buf_len--; | 725 | dev->buf_len--; |
726 | /* Data reg from 2430 is 8 bit wide */ | ||
727 | if (!cpu_is_omap2430() && | ||
728 | !cpu_is_omap34xx()) { | ||
729 | if (dev->buf_len) { | ||
730 | w |= *dev->buf++ << 8; | ||
731 | dev->buf_len--; | ||
732 | } | ||
733 | } | ||
734 | } else { | ||
735 | if (stat & OMAP_I2C_STAT_XRDY) | ||
736 | dev_err(dev->dev, | ||
737 | "XRDY IRQ while no " | ||
738 | "data to send\n"); | ||
739 | if (stat & OMAP_I2C_STAT_XDR) | ||
740 | dev_err(dev->dev, | ||
741 | "XDR IRQ while no " | ||
742 | "data to send\n"); | ||
743 | break; | ||
517 | } | 744 | } |
518 | } else | 745 | omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w); |
519 | dev_err(dev->dev, "XRDY IRQ while no " | 746 | } |
520 | "data to send\n"); | 747 | omap_i2c_ack_stat(dev, |
521 | omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w); | 748 | stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)); |
522 | omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY); | ||
523 | continue; | 749 | continue; |
524 | } | 750 | } |
525 | if (stat & OMAP_I2C_STAT_ROVR) { | 751 | if (stat & OMAP_I2C_STAT_ROVR) { |
@@ -527,18 +753,9 @@ omap_i2c_isr(int this_irq, void *dev_id) | |||
527 | dev->cmd_err |= OMAP_I2C_STAT_ROVR; | 753 | dev->cmd_err |= OMAP_I2C_STAT_ROVR; |
528 | } | 754 | } |
529 | if (stat & OMAP_I2C_STAT_XUDF) { | 755 | if (stat & OMAP_I2C_STAT_XUDF) { |
530 | dev_err(dev->dev, "Transmit overflow\n"); | 756 | dev_err(dev->dev, "Transmit underflow\n"); |
531 | dev->cmd_err |= OMAP_I2C_STAT_XUDF; | 757 | dev->cmd_err |= OMAP_I2C_STAT_XUDF; |
532 | } | 758 | } |
533 | if (stat & OMAP_I2C_STAT_NACK) { | ||
534 | omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK); | ||
535 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, | ||
536 | OMAP_I2C_CON_STP); | ||
537 | } | ||
538 | if (stat & OMAP_I2C_STAT_AL) { | ||
539 | dev_err(dev->dev, "Arbitration lost\n"); | ||
540 | omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL); | ||
541 | } | ||
542 | } | 759 | } |
543 | 760 | ||
544 | return count ? IRQ_HANDLED : IRQ_NONE; | 761 | return count ? IRQ_HANDLED : IRQ_NONE; |
@@ -549,13 +766,15 @@ static const struct i2c_algorithm omap_i2c_algo = { | |||
549 | .functionality = omap_i2c_func, | 766 | .functionality = omap_i2c_func, |
550 | }; | 767 | }; |
551 | 768 | ||
552 | static int | 769 | static int __init |
553 | omap_i2c_probe(struct platform_device *pdev) | 770 | omap_i2c_probe(struct platform_device *pdev) |
554 | { | 771 | { |
555 | struct omap_i2c_dev *dev; | 772 | struct omap_i2c_dev *dev; |
556 | struct i2c_adapter *adap; | 773 | struct i2c_adapter *adap; |
557 | struct resource *mem, *irq, *ioarea; | 774 | struct resource *mem, *irq, *ioarea; |
775 | void *isr; | ||
558 | int r; | 776 | int r; |
777 | u32 speed = 0; | ||
559 | 778 | ||
560 | /* NOTE: driver uses the static register mapping */ | 779 | /* NOTE: driver uses the static register mapping */ |
561 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 780 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
@@ -576,17 +795,19 @@ omap_i2c_probe(struct platform_device *pdev) | |||
576 | return -EBUSY; | 795 | return -EBUSY; |
577 | } | 796 | } |
578 | 797 | ||
579 | if (clock > 200) | ||
580 | clock = 400; /* Fast mode */ | ||
581 | else | ||
582 | clock = 100; /* Standard mode */ | ||
583 | |||
584 | dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL); | 798 | dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL); |
585 | if (!dev) { | 799 | if (!dev) { |
586 | r = -ENOMEM; | 800 | r = -ENOMEM; |
587 | goto err_release_region; | 801 | goto err_release_region; |
588 | } | 802 | } |
589 | 803 | ||
804 | if (pdev->dev.platform_data != NULL) | ||
805 | speed = *(u32 *)pdev->dev.platform_data; | ||
806 | else | ||
807 | speed = 100; /* Defualt speed */ | ||
808 | |||
809 | dev->speed = speed; | ||
810 | dev->idle = 1; | ||
590 | dev->dev = &pdev->dev; | 811 | dev->dev = &pdev->dev; |
591 | dev->irq = irq->start; | 812 | dev->irq = irq->start; |
592 | dev->base = ioremap(mem->start, mem->end - mem->start + 1); | 813 | dev->base = ioremap(mem->start, mem->end - mem->start + 1); |
@@ -602,22 +823,39 @@ omap_i2c_probe(struct platform_device *pdev) | |||
602 | 823 | ||
603 | omap_i2c_unidle(dev); | 824 | omap_i2c_unidle(dev); |
604 | 825 | ||
605 | if (cpu_is_omap15xx()) | 826 | dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff; |
606 | dev->rev1 = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) < 0x20; | 827 | |
828 | if (cpu_is_omap2430() || cpu_is_omap34xx()) { | ||
829 | u16 s; | ||
830 | |||
831 | /* Set up the fifo size - Get total size */ | ||
832 | s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3; | ||
833 | dev->fifo_size = 0x8 << s; | ||
834 | |||
835 | /* | ||
836 | * Set up notification threshold as half the total available | ||
837 | * size. This is to ensure that we can handle the status on int | ||
838 | * call back latencies. | ||
839 | */ | ||
840 | dev->fifo_size = (dev->fifo_size / 2); | ||
841 | dev->b_hw = 1; /* Enable hardware fixes */ | ||
842 | } | ||
607 | 843 | ||
608 | /* reset ASAP, clearing any IRQs */ | 844 | /* reset ASAP, clearing any IRQs */ |
609 | omap_i2c_init(dev); | 845 | omap_i2c_init(dev); |
610 | 846 | ||
611 | r = request_irq(dev->irq, dev->rev1 ? omap_i2c_rev1_isr : omap_i2c_isr, | 847 | isr = (dev->rev < OMAP_I2C_REV_2) ? omap_i2c_rev1_isr : omap_i2c_isr; |
612 | 0, pdev->name, dev); | 848 | r = request_irq(dev->irq, isr, 0, pdev->name, dev); |
613 | 849 | ||
614 | if (r) { | 850 | if (r) { |
615 | dev_err(dev->dev, "failure requesting irq %i\n", dev->irq); | 851 | dev_err(dev->dev, "failure requesting irq %i\n", dev->irq); |
616 | goto err_unuse_clocks; | 852 | goto err_unuse_clocks; |
617 | } | 853 | } |
618 | r = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff; | 854 | |
619 | dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n", | 855 | dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n", |
620 | pdev->id, r >> 4, r & 0xf, clock); | 856 | pdev->id, dev->rev >> 4, dev->rev & 0xf, dev->speed); |
857 | |||
858 | omap_i2c_idle(dev); | ||
621 | 859 | ||
622 | adap = &dev->adapter; | 860 | adap = &dev->adapter; |
623 | i2c_set_adapdata(adap, dev); | 861 | i2c_set_adapdata(adap, dev); |
@@ -635,8 +873,6 @@ omap_i2c_probe(struct platform_device *pdev) | |||
635 | goto err_free_irq; | 873 | goto err_free_irq; |
636 | } | 874 | } |
637 | 875 | ||
638 | omap_i2c_idle(dev); | ||
639 | |||
640 | return 0; | 876 | return 0; |
641 | 877 | ||
642 | err_free_irq: | 878 | err_free_irq: |