Merge branch 'i2c-next' of git://aeryn.fluff.org.uk/bjdooks/linux

* 'i2c-next' of git://aeryn.fluff.org.uk/bjdooks/linux:
  i2c-omap: fix type of irq handler function
  i2c-s3c2410: Change IRQ to be plain integer.
  i2c-s3c2410: Allow more than one i2c-s3c2410 adapter
  i2c-s3c2410: Remove default platform data.
  i2c-s3c2410: Use platform data for gpio configuration
  i2c-s3c2410: Fixup style problems from checkpatch.pl
  i2c-omap: Enable I2C wakeups for 34xx
  i2c-omap: reprogram OCP_SYSCONFIG register after reset
  i2c-omap: convert 'rev1' flag to generic 'rev' u8
  i2c-omap: fix I2C timeouts due to recursive omap_i2c_{un,}idle()
  i2c-omap: Clean-up i2c-omap
  i2c-omap: Don't compile in OMAP15xx I2C ISR for non-OMAP15xx builds
  i2c-omap: Mark init-only functions as __init
  i2c-omap: Add support for omap34xx
  i2c-omap: FIFO handling support and broken hw workaround for i2c-omap
  i2c-omap: Add high-speed support to omap-i2c
  i2c-omap: Close suspected race between omap_i2c_idle() and omap_i2c_isr()
  i2c-omap: Do not use interruptible wait call in omap_i2c_xfer_msg

Fix up apparently-trivial conflict in drivers/i2c/busses/i2c-s3c2410.c

2 files changed, 406 insertions, 199 deletions

diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 608038d64f81..be8ee2cac8bb 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -2,13 +2,16 @@
  * TI OMAP I2C master mode driver
  *
  * Copyright (C) 2003 MontaVista Software, Inc.
- * Copyright (C) 2004 Texas Instruments.
- *
- * Updated to work with multiple I2C interfaces on 24xx by
- * Tony Lindgren <tony@atomide.com> and Imre Deak <imre.deak@nokia.com>
  * Copyright (C) 2005 Nokia Corporation
+ * Copyright (C) 2004 - 2007 Texas Instruments.
  *
- * Cleaned up by Juha Yrjölä <juha.yrjola@nokia.com>
+ * Originally written by MontaVista Software, Inc.
+ * Additional contributions by:
+ *      Tony Lindgren <tony@atomide.com>
+ *      Imre Deak <imre.deak@nokia.com>
+ *      Juha Yrjölä <juha.yrjola@solidboot.com>
+ *      Syed Khasim <x0khasim@ti.com>
+ *      Nishant Menon <nm@ti.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -33,8 +36,14 @@
 #include <linux/completion.h>
 #include <linux/platform_device.h>
 #include <linux/clk.h>
+#include <linux/io.h>
+
+/* I2C controller revisions */
+#define OMAP_I2C_REV_2                  0x20
 
-#include <asm/io.h>
+/* I2C controller revisions present on specific hardware */
+#define OMAP_I2C_REV_ON_2430            0x36
+#define OMAP_I2C_REV_ON_3430            0x3C
 
 /* timeout waiting for the controller to respond */
 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
@@ -43,6 +52,8 @@
 #define OMAP_I2C_IE_REG                 0x04
 #define OMAP_I2C_STAT_REG               0x08
 #define OMAP_I2C_IV_REG                 0x0c
+/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
+#define OMAP_I2C_WE_REG                 0x0c
 #define OMAP_I2C_SYSS_REG               0x10
 #define OMAP_I2C_BUF_REG                0x14
 #define OMAP_I2C_CNT_REG                0x18
@@ -55,8 +66,11 @@
 #define OMAP_I2C_SCLL_REG               0x34
 #define OMAP_I2C_SCLH_REG               0x38
 #define OMAP_I2C_SYSTEST_REG            0x3c
+#define OMAP_I2C_BUFSTAT_REG            0x40
 
 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
+#define OMAP_I2C_IE_XDR         (1 << 14)       /* TX Buffer drain int enable */
+#define OMAP_I2C_IE_RDR         (1 << 13)       /* RX Buffer drain int enable */
 #define OMAP_I2C_IE_XRDY        (1 << 4)        /* TX data ready int enable */
 #define OMAP_I2C_IE_RRDY        (1 << 3)        /* RX data ready int enable */
 #define OMAP_I2C_IE_ARDY        (1 << 2)        /* Access ready int enable */
@@ -64,7 +78,8 @@
 #define OMAP_I2C_IE_AL          (1 << 0)        /* Arbitration lost int ena */
 
 /* I2C Status Register (OMAP_I2C_STAT): */
-#define OMAP_I2C_STAT_SBD       (1 << 15)       /* Single byte data */
+#define OMAP_I2C_STAT_XDR       (1 << 14)       /* TX Buffer draining */
+#define OMAP_I2C_STAT_RDR       (1 << 13)       /* RX Buffer draining */
 #define OMAP_I2C_STAT_BB        (1 << 12)       /* Bus busy */
 #define OMAP_I2C_STAT_ROVR      (1 << 11)       /* Receive overrun */
 #define OMAP_I2C_STAT_XUDF      (1 << 10)       /* Transmit underflow */
@@ -76,13 +91,34 @@
 #define OMAP_I2C_STAT_NACK      (1 << 1)        /* No ack interrupt enable */
 #define OMAP_I2C_STAT_AL        (1 << 0)        /* Arbitration lost int ena */
 
+/* I2C WE wakeup enable register */
+#define OMAP_I2C_WE_XDR_WE      (1 << 14)       /* TX drain wakup */
+#define OMAP_I2C_WE_RDR_WE      (1 << 13)       /* RX drain wakeup */
+#define OMAP_I2C_WE_AAS_WE      (1 << 9)        /* Address as slave wakeup*/
+#define OMAP_I2C_WE_BF_WE       (1 << 8)        /* Bus free wakeup */
+#define OMAP_I2C_WE_STC_WE      (1 << 6)        /* Start condition wakeup */
+#define OMAP_I2C_WE_GC_WE       (1 << 5)        /* General call wakeup */
+#define OMAP_I2C_WE_DRDY_WE     (1 << 3)        /* TX/RX data ready wakeup */
+#define OMAP_I2C_WE_ARDY_WE     (1 << 2)        /* Reg access ready wakeup */
+#define OMAP_I2C_WE_NACK_WE     (1 << 1)        /* No acknowledgment wakeup */
+#define OMAP_I2C_WE_AL_WE       (1 << 0)        /* Arbitration lost wakeup */
+
+#define OMAP_I2C_WE_ALL         (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
+                                OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
+                                OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
+                                OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
+                                OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
+
 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
 #define OMAP_I2C_BUF_RDMA_EN    (1 << 15)       /* RX DMA channel enable */
+#define OMAP_I2C_BUF_RXFIF_CLR  (1 << 14)       /* RX FIFO Clear */
 #define OMAP_I2C_BUF_XDMA_EN    (1 << 7)        /* TX DMA channel enable */
+#define OMAP_I2C_BUF_TXFIF_CLR  (1 << 6)        /* TX FIFO Clear */
 
 /* I2C Configuration Register (OMAP_I2C_CON): */
 #define OMAP_I2C_CON_EN         (1 << 15)       /* I2C module enable */
 #define OMAP_I2C_CON_BE         (1 << 14)       /* Big endian mode */
+#define OMAP_I2C_CON_OPMODE_HS  (1 << 12)       /* High Speed support */
 #define OMAP_I2C_CON_STB        (1 << 11)       /* Start byte mode (master) */
 #define OMAP_I2C_CON_MST        (1 << 10)       /* Master/slave mode */
 #define OMAP_I2C_CON_TRX        (1 << 9)        /* TX/RX mode (master only) */
@@ -91,6 +127,10 @@
 #define OMAP_I2C_CON_STP        (1 << 1)        /* Stop cond (master only) */
 #define OMAP_I2C_CON_STT        (1 << 0)        /* Start condition (master) */
 
+/* I2C SCL time value when Master */
+#define OMAP_I2C_SCLL_HSSCLL    8
+#define OMAP_I2C_SCLH_HSSCLH    8
+
 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
 #ifdef DEBUG
 #define OMAP_I2C_SYSTEST_ST_EN          (1 << 15)       /* System test enable */
@@ -103,17 +143,19 @@
 #define OMAP_I2C_SYSTEST_SDA_O          (1 << 0)        /* SDA line drive out */
 #endif
 
-/* I2C System Status register (OMAP_I2C_SYSS): */
-#define OMAP_I2C_SYSS_RDONE             (1 << 0)        /* Reset Done */
+/* OCP_SYSSTATUS bit definitions */
+#define SYSS_RESETDONE_MASK             (1 << 0)
+
+/* OCP_SYSCONFIG bit definitions */
+#define SYSC_CLOCKACTIVITY_MASK         (0x3 << 8)
+#define SYSC_SIDLEMODE_MASK             (0x3 << 3)
+#define SYSC_ENAWAKEUP_MASK             (1 << 2)
+#define SYSC_SOFTRESET_MASK             (1 << 1)
+#define SYSC_AUTOIDLE_MASK              (1 << 0)
 
-/* I2C System Configuration Register (OMAP_I2C_SYSC): */
-#define OMAP_I2C_SYSC_SRST              (1 << 1)        /* Soft Reset */
+#define SYSC_IDLEMODE_SMART             0x2
+#define SYSC_CLOCKACTIVITY_FCLK         0x2
 
-/* REVISIT: Use platform_data instead of module parameters */
-/* Fast Mode = 400 kHz, Standard = 100 kHz */
-static int clock = 100; /* Default: 100 kHz */
-module_param(clock, int, 0);
-MODULE_PARM_DESC(clock, "Set I2C clock in kHz: 400=fast mode (default == 100)");
 
 struct omap_i2c_dev {
         struct device           *dev;
@@ -123,11 +165,17 @@ struct omap_i2c_dev {
         struct clk              *fclk;          /* Functional clock */
         struct completion       cmd_complete;
         struct resource         *ioarea;
+        u32                     speed;          /* Speed of bus in Khz */
         u16                     cmd_err;
         u8                      *buf;
         size_t                  buf_len;
         struct i2c_adapter      adapter;
-        unsigned                rev1:1;
+        u8                      fifo_size;      /* use as flag and value
+                                                 * fifo_size==0 implies no fifo
+                                                 * if set, should be trsh+1
+                                                 */
+        u8                      rev;
+        unsigned                b_hw:1;         /* bad h/w fixes */
         unsigned                idle:1;
         u16                     iestate;        /* Saved interrupt register */
 };
@@ -143,9 +191,9 @@ static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
         return __raw_readw(i2c_dev->base + reg);
 }
 
-static int omap_i2c_get_clocks(struct omap_i2c_dev *dev)
+static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
 {
-        if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
+        if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
                 dev->iclk = clk_get(dev->dev, "i2c_ick");
                 if (IS_ERR(dev->iclk)) {
                         dev->iclk = NULL;
@@ -178,25 +226,33 @@ static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
 
 static void omap_i2c_unidle(struct omap_i2c_dev *dev)
 {
+        WARN_ON(!dev->idle);
+
         if (dev->iclk != NULL)
                 clk_enable(dev->iclk);
         clk_enable(dev->fclk);
+        dev->idle = 0;
         if (dev->iestate)
                 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
-        dev->idle = 0;
 }
 
 static void omap_i2c_idle(struct omap_i2c_dev *dev)
 {
         u16 iv;
 
-        dev->idle = 1;
+        WARN_ON(dev->idle);
+
         dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
         omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
-        if (dev->rev1)
-                iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);   /* Read clears */
-        else
+        if (dev->rev < OMAP_I2C_REV_2) {
+                iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
+        } else {
                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
+
+                /* Flush posted write before the dev->idle store occurs */
+                omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
+        }
+        dev->idle = 1;
         clk_disable(dev->fclk);
         if (dev->iclk != NULL)
                 clk_disable(dev->iclk);
@@ -204,18 +260,20 @@ static void omap_i2c_idle(struct omap_i2c_dev *dev)
 
 static int omap_i2c_init(struct omap_i2c_dev *dev)
 {
-        u16 psc = 0;
+        u16 psc = 0, scll = 0, sclh = 0;
+        u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
         unsigned long fclk_rate = 12000000;
         unsigned long timeout;
+        unsigned long internal_clk = 0;
 
-        if (!dev->rev1) {
-                omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, OMAP_I2C_SYSC_SRST);
+        if (dev->rev >= OMAP_I2C_REV_2) {
+                omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
                 /* For some reason we need to set the EN bit before the
                  * reset done bit gets set. */
                 timeout = jiffies + OMAP_I2C_TIMEOUT;
                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
                 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
-                         OMAP_I2C_SYSS_RDONE)) {
+                         SYSS_RESETDONE_MASK)) {
                         if (time_after(jiffies, timeout)) {
                                 dev_warn(dev->dev, "timeout waiting "
                                                 "for controller reset\n");
@@ -223,6 +281,33 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
                         }
                         msleep(1);
                 }
+
+                /* SYSC register is cleared by the reset; rewrite it */
+                if (dev->rev == OMAP_I2C_REV_ON_2430) {
+
+                        omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
+                                           SYSC_AUTOIDLE_MASK);
+
+                } else if (dev->rev >= OMAP_I2C_REV_ON_3430) {
+                        u32 v;
+
+                        v = SYSC_AUTOIDLE_MASK;
+                        v |= SYSC_ENAWAKEUP_MASK;
+                        v |= (SYSC_IDLEMODE_SMART <<
+                              __ffs(SYSC_SIDLEMODE_MASK));
+                        v |= (SYSC_CLOCKACTIVITY_FCLK <<
+                              __ffs(SYSC_CLOCKACTIVITY_MASK));
+
+                        omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, v);
+                        /*
+                         * Enabling all wakup sources to stop I2C freezing on
+                         * WFI instruction.
+                         * REVISIT: Some wkup sources might not be needed.
+                         */
+                        omap_i2c_write_reg(dev, OMAP_I2C_WE_REG,
+                                                        OMAP_I2C_WE_ALL);
+
+                }
         }
         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 
@@ -249,27 +334,65 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
                         psc = fclk_rate / 12000000;
         }
 
+        if (cpu_is_omap2430() || cpu_is_omap34xx()) {
+
+                /* HSI2C controller internal clk rate should be 19.2 Mhz */
+                internal_clk = 19200;
+                fclk_rate = clk_get_rate(dev->fclk) / 1000;
+
+                /* Compute prescaler divisor */
+                psc = fclk_rate / internal_clk;
+                psc = psc - 1;
+
+                /* If configured for High Speed */
+                if (dev->speed > 400) {
+                        /* For first phase of HS mode */
+                        fsscll = internal_clk / (400 * 2) - 6;
+                        fssclh = internal_clk / (400 * 2) - 6;
+
+                        /* For second phase of HS mode */
+                        hsscll = fclk_rate / (dev->speed * 2) - 6;
+                        hssclh = fclk_rate / (dev->speed * 2) - 6;
+                } else {
+                        /* To handle F/S modes */
+                        fsscll = internal_clk / (dev->speed * 2) - 6;
+                        fssclh = internal_clk / (dev->speed * 2) - 6;
+                }
+                scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
+                sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
+        } else {
+                /* Program desired operating rate */
+                fclk_rate /= (psc + 1) * 1000;
+                if (psc > 2)
+                        psc = 2;
+                scll = fclk_rate / (dev->speed * 2) - 7 + psc;
+                sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
+        }
+
         /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
         omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
 
-        /* Program desired operating rate */
-        fclk_rate /= (psc + 1) * 1000;
-        if (psc > 2)
-                psc = 2;
+        /* SCL low and high time values */
+        omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
+        omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
 
-        omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG,
-                           fclk_rate / (clock * 2) - 7 + psc);
-        omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG,
-                           fclk_rate / (clock * 2) - 7 + psc);
+        if (dev->fifo_size)
+                /* Note: setup required fifo size - 1 */
+                omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG,
+                                        (dev->fifo_size - 1) << 8 | /* RTRSH */
+                                        OMAP_I2C_BUF_RXFIF_CLR |
+                                        (dev->fifo_size - 1) | /* XTRSH */
+                                        OMAP_I2C_BUF_TXFIF_CLR);
 
         /* Take the I2C module out of reset: */
         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 
         /* Enable interrupts */
         omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
-                           (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
-                            OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
-                            OMAP_I2C_IE_AL));
+                        (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
+                        OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
+                        OMAP_I2C_IE_AL)  | ((dev->fifo_size) ?
+                                (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0));
         return 0;
 }
 
@@ -316,20 +439,59 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
 
         omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
 
+        /* Clear the FIFO Buffers */
+        w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
+        w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
+        omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
+
         init_completion(&dev->cmd_complete);
         dev->cmd_err = 0;
 
         w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
+
+        /* High speed configuration */
+        if (dev->speed > 400)
+                w |= OMAP_I2C_CON_OPMODE_HS;
+
         if (msg->flags & I2C_M_TEN)
                 w |= OMAP_I2C_CON_XA;
         if (!(msg->flags & I2C_M_RD))
                 w |= OMAP_I2C_CON_TRX;
-        if (stop)
+
+        if (!dev->b_hw && stop)
                 w |= OMAP_I2C_CON_STP;
+
         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 
-        r = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
-                                                      OMAP_I2C_TIMEOUT);
+        /*
+         * Don't write stt and stp together on some hardware.
+         */
+        if (dev->b_hw && stop) {
+                unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
+                u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
+                while (con & OMAP_I2C_CON_STT) {
+                        con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
+
+                        /* Let the user know if i2c is in a bad state */
+                        if (time_after(jiffies, delay)) {
+                                dev_err(dev->dev, "controller timed out "
+                                "waiting for start condition to finish\n");
+                                return -ETIMEDOUT;
+                        }
+                        cpu_relax();
+                }
+
+                w |= OMAP_I2C_CON_STP;
+                w &= ~OMAP_I2C_CON_STT;
+                omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
+        }
+
+        /*
+         * REVISIT: We should abort the transfer on signals, but the bus goes
+         * into arbitration and we're currently unable to recover from it.
+         */
+        r = wait_for_completion_timeout(&dev->cmd_complete,
+                                        OMAP_I2C_TIMEOUT);
         dev->buf_len = 0;
         if (r < 0)
                 return r;
@@ -376,7 +538,8 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 
         omap_i2c_unidle(dev);
 
-        if ((r = omap_i2c_wait_for_bb(dev)) < 0)
+        r = omap_i2c_wait_for_bb(dev);
+        if (r < 0)
                 goto out;
 
         for (i = 0; i < num; i++) {
@@ -411,6 +574,9 @@ omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
         omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
 }
 
+/* rev1 devices are apparently only on some 15xx */
+#ifdef CONFIG_ARCH_OMAP15XX
+
 static irqreturn_t
 omap_i2c_rev1_isr(int this_irq, void *dev_id)
 {
@@ -465,6 +631,9 @@ omap_i2c_rev1_isr(int this_irq, void *dev_id)
 
         return IRQ_HANDLED;
 }
+#else
+#define omap_i2c_rev1_isr               NULL
+#endif
 
 static irqreturn_t
 omap_i2c_isr(int this_irq, void *dev_id)
@@ -472,7 +641,7 @@ omap_i2c_isr(int this_irq, void *dev_id)
         struct omap_i2c_dev *dev = dev_id;
         u16 bits;
         u16 stat, w;
-        int count = 0;
+        int err, count = 0;
 
         if (dev->idle)
                 return IRQ_NONE;
@@ -487,39 +656,96 @@ omap_i2c_isr(int this_irq, void *dev_id)
 
                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
 
-                if (stat & OMAP_I2C_STAT_ARDY) {
-                        omap_i2c_complete_cmd(dev, 0);
-                        continue;
+                err = 0;
+                if (stat & OMAP_I2C_STAT_NACK) {
+                        err |= OMAP_I2C_STAT_NACK;
+                        omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
+                                           OMAP_I2C_CON_STP);
                 }
-                if (stat & OMAP_I2C_STAT_RRDY) {
-                        w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
-                        if (dev->buf_len) {
-                                *dev->buf++ = w;
-                                dev->buf_len--;
+                if (stat & OMAP_I2C_STAT_AL) {
+                        dev_err(dev->dev, "Arbitration lost\n");
+                        err |= OMAP_I2C_STAT_AL;
+                }
+                if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
+                                        OMAP_I2C_STAT_AL))
+                        omap_i2c_complete_cmd(dev, err);
+                if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
+                        u8 num_bytes = 1;
+                        if (dev->fifo_size) {
+                                if (stat & OMAP_I2C_STAT_RRDY)
+                                        num_bytes = dev->fifo_size;
+                                else
+                                        num_bytes = omap_i2c_read_reg(dev,
+                                                        OMAP_I2C_BUFSTAT_REG);
+                        }
+                        while (num_bytes) {
+                                num_bytes--;
+                                w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
                                 if (dev->buf_len) {
-                                        *dev->buf++ = w >> 8;
+                                        *dev->buf++ = w;
                                         dev->buf_len--;
+                                        /* Data reg from 2430 is 8 bit wide */
+                                        if (!cpu_is_omap2430() &&
+                                                        !cpu_is_omap34xx()) {
+                                                if (dev->buf_len) {
+                                                        *dev->buf++ = w >> 8;
+                                                        dev->buf_len--;
+                                                }
+                                        }
+                                } else {
+                                        if (stat & OMAP_I2C_STAT_RRDY)
+                                                dev_err(dev->dev,
+                                                        "RRDY IRQ while no data"
+                                                                " requested\n");
+                                        if (stat & OMAP_I2C_STAT_RDR)
+                                                dev_err(dev->dev,
+                                                        "RDR IRQ while no data"
+                                                                " requested\n");
+                                        break;
                                 }
-                        } else
-                                dev_err(dev->dev, "RRDY IRQ while no data "
-                                                "requested\n");
-                        omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
+                        }
+                        omap_i2c_ack_stat(dev,
+                                stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
                         continue;
                 }
-                if (stat & OMAP_I2C_STAT_XRDY) {
-                        w = 0;
-                        if (dev->buf_len) {
-                                w = *dev->buf++;
-                                dev->buf_len--;
+                if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
+                        u8 num_bytes = 1;
+                        if (dev->fifo_size) {
+                                if (stat & OMAP_I2C_STAT_XRDY)
+                                        num_bytes = dev->fifo_size;
+                                else
+                                        num_bytes = omap_i2c_read_reg(dev,
+                                                        OMAP_I2C_BUFSTAT_REG);
+                        }
+                        while (num_bytes) {
+                                num_bytes--;
+                                w = 0;
                                 if (dev->buf_len) {
-                                        w |= *dev->buf++ << 8;
+                                        w = *dev->buf++;
                                         dev->buf_len--;
+                                        /* Data reg from  2430 is 8 bit wide */
+                                        if (!cpu_is_omap2430() &&
+                                                        !cpu_is_omap34xx()) {
+                                                if (dev->buf_len) {
+                                                        w |= *dev->buf++ << 8;
+                                                        dev->buf_len--;
+                                                }
+                                        }
+                                } else {
+                                        if (stat & OMAP_I2C_STAT_XRDY)
+                                                dev_err(dev->dev,
+                                                        "XRDY IRQ while no "
+                                                        "data to send\n");
+                                        if (stat & OMAP_I2C_STAT_XDR)
+                                                dev_err(dev->dev,
+                                                        "XDR IRQ while no "
+                                                        "data to send\n");
+                                        break;
                                 }
-                        } else
-                                dev_err(dev->dev, "XRDY IRQ while no "
-                                        "data to send\n");
-                        omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
-                        omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
+                                omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
+                        }
+                        omap_i2c_ack_stat(dev,
+                                stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
                         continue;
                 }
                 if (stat & OMAP_I2C_STAT_ROVR) {
@@ -527,18 +753,9 @@ omap_i2c_isr(int this_irq, void *dev_id)
                         dev->cmd_err |= OMAP_I2C_STAT_ROVR;
                 }
                 if (stat & OMAP_I2C_STAT_XUDF) {
-                        dev_err(dev->dev, "Transmit overflow\n");
+                        dev_err(dev->dev, "Transmit underflow\n");
                         dev->cmd_err |= OMAP_I2C_STAT_XUDF;
                 }
-                if (stat & OMAP_I2C_STAT_NACK) {
-                        omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
-                        omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
-                                           OMAP_I2C_CON_STP);
-                }
-                if (stat & OMAP_I2C_STAT_AL) {
-                        dev_err(dev->dev, "Arbitration lost\n");
-                        omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
-                }
         }
 
         return count ? IRQ_HANDLED : IRQ_NONE;
@@ -549,13 +766,15 @@ static const struct i2c_algorithm omap_i2c_algo = {
         .functionality  = omap_i2c_func,
 };
 
-static int
+static int __init
 omap_i2c_probe(struct platform_device *pdev)
 {
         struct omap_i2c_dev     *dev;
         struct i2c_adapter      *adap;
         struct resource         *mem, *irq, *ioarea;
+        irq_handler_t isr;
         int r;
+        u32 speed = 0;
 
         /* NOTE: driver uses the static register mapping */
         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -576,17 +795,19 @@ omap_i2c_probe(struct platform_device *pdev)
                 return -EBUSY;
         }
 
-        if (clock > 200)
-                clock = 400;    /* Fast mode */
-        else
-                clock = 100;    /* Standard mode */
-
         dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
         if (!dev) {
                 r = -ENOMEM;
                 goto err_release_region;
         }
 
+        if (pdev->dev.platform_data != NULL)
+                speed = *(u32 *)pdev->dev.platform_data;
+        else
+                speed = 100;    /* Defualt speed */
+
+        dev->speed = speed;
+        dev->idle = 1;
         dev->dev = &pdev->dev;
         dev->irq = irq->start;
         dev->base = ioremap(mem->start, mem->end - mem->start + 1);
@@ -602,22 +823,39 @@ omap_i2c_probe(struct platform_device *pdev)
 
         omap_i2c_unidle(dev);
 
-        if (cpu_is_omap15xx())
-                dev->rev1 = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) < 0x20;
+        dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
+
+        if (cpu_is_omap2430() || cpu_is_omap34xx()) {
+                u16 s;
+
+                /* Set up the fifo size - Get total size */
+                s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
+                dev->fifo_size = 0x8 << s;
+
+                /*
+                 * Set up notification threshold as half the total available
+                 * size. This is to ensure that we can handle the status on int
+                 * call back latencies.
+                 */
+                dev->fifo_size = (dev->fifo_size / 2);
+                dev->b_hw = 1; /* Enable hardware fixes */
+        }
 
         /* reset ASAP, clearing any IRQs */
         omap_i2c_init(dev);
 
-        r = request_irq(dev->irq, dev->rev1 ? omap_i2c_rev1_isr : omap_i2c_isr,
-                        0, pdev->name, dev);
+        isr = (dev->rev < OMAP_I2C_REV_2) ? omap_i2c_rev1_isr : omap_i2c_isr;
+        r = request_irq(dev->irq, isr, 0, pdev->name, dev);
 
         if (r) {
                 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
                 goto err_unuse_clocks;
         }
-        r = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
+
         dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
-                 pdev->id, r >> 4, r & 0xf, clock);
+                 pdev->id, dev->rev >> 4, dev->rev & 0xf, dev->speed);
+
+        omap_i2c_idle(dev);
 
         adap = &dev->adapter;
         i2c_set_adapdata(adap, dev);
@@ -635,8 +873,6 @@ omap_i2c_probe(struct platform_device *pdev)
                 goto err_free_irq;
         }
 
-        omap_i2c_idle(dev);
-
         return 0;
 
 err_free_irq:
diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c
index c39079f9c73f..f69f91ffb469 100644
--- a/drivers/i2c/busses/i2c-s3c2410.c
+++ b/drivers/i2c/busses/i2c-s3c2410.c
@@ -35,11 +35,9 @@
 #include <linux/clk.h>
 #include <linux/cpufreq.h>
 
-#include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/io.h>
 
-#include <mach/regs-gpio.h>
 #include <plat/regs-iic.h>
 #include <plat/iic.h>
 
@@ -64,6 +62,7 @@ struct s3c24xx_i2c {
         unsigned int            msg_ptr;
 
         unsigned int            tx_setup;
+        unsigned int            irq;
 
         enum s3c24xx_i2c_state  state;
         unsigned long           clkrate;
@@ -71,7 +70,6 @@ struct s3c24xx_i2c {
         void __iomem            *regs;
         struct clk              *clk;
         struct device           *dev;
-        struct resource         *irq;
         struct resource         *ioarea;
         struct i2c_adapter      adap;
 
@@ -80,16 +78,7 @@ struct s3c24xx_i2c {
 #endif
 };
 
-/* default platform data to use if not supplied in the platform_device
-*/
-
-static struct s3c2410_platform_i2c s3c24xx_i2c_default_platform = {
-        .flags          = 0,
-        .slave_addr     = 0x10,
-        .bus_freq       = 100*1000,
-        .max_freq       = 400*1000,
-        .sda_delay      = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
-};
+/* default platform data removed, dev should always carry data. */
 
 /* s3c24xx_i2c_is2440()
  *
@@ -103,21 +92,6 @@ static inline int s3c24xx_i2c_is2440(struct s3c24xx_i2c *i2c)
         return !strcmp(pdev->name, "s3c2440-i2c");
 }
 
-
-/* s3c24xx_i2c_get_platformdata
- *
- * get the platform data associated with the given device, or return
- * the default if there is none
-*/
-
-static inline struct s3c2410_platform_i2c *s3c24xx_i2c_get_platformdata(struct device *dev)
-{
-        if (dev->platform_data != NULL)
-                return (struct s3c2410_platform_i2c *)dev->platform_data;
-
-        return &s3c24xx_i2c_default_platform;
-}
-
 /* s3c24xx_i2c_master_complete
  *
  * complete the message and wake up the caller, using the given return code,
@@ -130,7 +104,7 @@ static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
 
         i2c->msg_ptr = 0;
         i2c->msg = NULL;
-        i2c->msg_idx ++;
+        i2c->msg_idx++;
         i2c->msg_num = 0;
         if (ret)
                 i2c->msg_idx = ret;
@@ -141,19 +115,17 @@ static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
 {
         unsigned long tmp;
-        
+
         tmp = readl(i2c->regs + S3C2410_IICCON);
         writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
-
 }
 
 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
 {
         unsigned long tmp;
-        
+
         tmp = readl(i2c->regs + S3C2410_IICCON);
         writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
-
 }
 
 /* irq enable/disable functions */
@@ -161,7 +133,7 @@ static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
 {
         unsigned long tmp;
-        
+
         tmp = readl(i2c->regs + S3C2410_IICCON);
         writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
 }
@@ -169,7 +141,7 @@ static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
 {
         unsigned long tmp;
-        
+
         tmp = readl(i2c->regs + S3C2410_IICCON);
         writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
 }
@@ -177,10 +149,10 @@ static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
 
 /* s3c24xx_i2c_message_start
  *
- * put the start of a message onto the bus 
+ * put the start of a message onto the bus
 */
 
-static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c, 
+static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
                                       struct i2c_msg *msg)
 {
         unsigned int addr = (msg->addr & 0x7f) << 1;
@@ -199,15 +171,15 @@ static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
         if (msg->flags & I2C_M_REV_DIR_ADDR)
                 addr ^= 1;
 
-        // todo - check for wether ack wanted or not
+        /* todo - check for wether ack wanted or not */
         s3c24xx_i2c_enable_ack(i2c);
 
         iiccon = readl(i2c->regs + S3C2410_IICCON);
         writel(stat, i2c->regs + S3C2410_IICSTAT);
-        
+
         dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
         writeb(addr, i2c->regs + S3C2410_IICDS);
-        
+
         /* delay here to ensure the data byte has gotten onto the bus
          * before the transaction is started */
 
@@ -215,8 +187,8 @@ static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
 
         dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
         writel(iiccon, i2c->regs + S3C2410_IICCON);
-        
-        stat |=  S3C2410_IICSTAT_START;
+
+        stat |= S3C2410_IICSTAT_START;
         writel(stat, i2c->regs + S3C2410_IICSTAT);
 }
 
@@ -227,11 +199,11 @@ static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
         dev_dbg(i2c->dev, "STOP\n");
 
         /* stop the transfer */
-        iicstat &= ~ S3C2410_IICSTAT_START;
+        iicstat &= ~S3C2410_IICSTAT_START;
         writel(iicstat, i2c->regs + S3C2410_IICSTAT);
-        
+
         i2c->state = STATE_STOP;
-        
+
         s3c24xx_i2c_master_complete(i2c, ret);
         s3c24xx_i2c_disable_irq(i2c);
 }
@@ -241,7 +213,7 @@ static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
 
 /* is_lastmsg()
  *
- * returns TRUE if the current message is the last in the set 
+ * returns TRUE if the current message is the last in the set
 */
 
 static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
@@ -289,14 +261,14 @@ static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
 
         case STATE_STOP:
                 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
-                s3c24xx_i2c_disable_irq(i2c);           
+                s3c24xx_i2c_disable_irq(i2c);
                 goto out_ack;
 
         case STATE_START:
                 /* last thing we did was send a start condition on the
                  * bus, or started a new i2c message
                  */
-                
+
                 if (iicstat & S3C2410_IICSTAT_LASTBIT &&
                     !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
                         /* ack was not received... */
@@ -322,7 +294,7 @@ static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
                 if (i2c->state == STATE_READ)
                         goto prepare_read;
 
-                /* fall through to the write state, as we will need to 
+                /* fall through to the write state, as we will need to
                  * send a byte as well */
 
         case STATE_WRITE:
@@ -339,7 +311,7 @@ static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
                         }
                 }
 
-        retry_write:
+ retry_write:
 
                 if (!is_msgend(i2c)) {
                         byte = i2c->msg->buf[i2c->msg_ptr++];
@@ -359,9 +331,9 @@ static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
                         dev_dbg(i2c->dev, "WRITE: Next Message\n");
 
                         i2c->msg_ptr = 0;
-                        i2c->msg_idx ++;
+                        i2c->msg_idx++;
                         i2c->msg++;
-                        
+
                         /* check to see if we need to do another message */
                         if (i2c->msg->flags & I2C_M_NOSTART) {
 
@@ -375,7 +347,6 @@ static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
 
                                 goto retry_write;
                         } else {
-                        
                                 /* send the new start */
                                 s3c24xx_i2c_message_start(i2c, i2c->msg);
                                 i2c->state = STATE_START;
@@ -389,7 +360,7 @@ static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
                 break;
 
         case STATE_READ:
-                /* we have a byte of data in the data register, do 
+                /* we have a byte of data in the data register, do
                  * something with it, and then work out wether we are
                  * going to do any more read/write
                  */
@@ -397,13 +368,13 @@ static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
                 byte = readb(i2c->regs + S3C2410_IICDS);
                 i2c->msg->buf[i2c->msg_ptr++] = byte;
 
-        prepare_read:
+ prepare_read:
                 if (is_msglast(i2c)) {
                         /* last byte of buffer */
 
                         if (is_lastmsg(i2c))
                                 s3c24xx_i2c_disable_ack(i2c);
-                        
+
                 } else if (is_msgend(i2c)) {
                         /* ok, we've read the entire buffer, see if there
                          * is anything else we need to do */
@@ -429,7 +400,7 @@ static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
         /* acknowlegde the IRQ and get back on with the work */
 
  out_ack:
-        tmp = readl(i2c->regs + S3C2410_IICCON);        
+        tmp = readl(i2c->regs + S3C2410_IICCON);
         tmp &= ~S3C2410_IICCON_IRQPEND;
         writel(tmp, i2c->regs + S3C2410_IICCON);
  out:
@@ -450,19 +421,19 @@ static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
         status = readl(i2c->regs + S3C2410_IICSTAT);
 
         if (status & S3C2410_IICSTAT_ARBITR) {
-                // deal with arbitration loss
+                /* deal with arbitration loss */
                 dev_err(i2c->dev, "deal with arbitration loss\n");
         }
 
         if (i2c->state == STATE_IDLE) {
                 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
 
-                tmp = readl(i2c->regs + S3C2410_IICCON);        
+                tmp = readl(i2c->regs + S3C2410_IICCON);
                 tmp &= ~S3C2410_IICCON_IRQPEND;
                 writel(tmp, i2c->regs +  S3C2410_IICCON);
                 goto out;
         }
-        
+
         /* pretty much this leaves us with the fact that we've
          * transmitted or received whatever byte we last sent */
 
@@ -485,16 +456,13 @@ static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
 
         while (timeout-- > 0) {
                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
-                
+
                 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
                         return 0;
 
                 msleep(1);
         }
 
-        dev_dbg(i2c->dev, "timeout: GPEDAT is %08x\n",
-                __raw_readl(S3C2410_GPEDAT));
-
         return -ETIMEDOUT;
 }
 
@@ -503,7 +471,8 @@ static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
  * this starts an i2c transfer
 */
 
-static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, struct i2c_msg *msgs, int num)
+static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
+                              struct i2c_msg *msgs, int num)
 {
         unsigned long timeout;
         int ret;
@@ -529,12 +498,12 @@ static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, struct i2c_msg *msgs, int
         s3c24xx_i2c_enable_irq(i2c);
         s3c24xx_i2c_message_start(i2c, msgs);
         spin_unlock_irq(&i2c->lock);
-        
+
         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
 
         ret = i2c->msg_idx;
 
-        /* having these next two as dev_err() makes life very 
+        /* having these next two as dev_err() makes life very
          * noisy when doing an i2cdetect */
 
         if (timeout == 0)
@@ -591,19 +560,6 @@ static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
         .functionality          = s3c24xx_i2c_func,
 };
 
-static struct s3c24xx_i2c s3c24xx_i2c = {
-        .lock           = __SPIN_LOCK_UNLOCKED(s3c24xx_i2c.lock),
-        .wait           = __WAIT_QUEUE_HEAD_INITIALIZER(s3c24xx_i2c.wait),
-        .tx_setup       = 50,
-        .adap           = {
-                .name                   = "s3c2410-i2c",
-                .owner                  = THIS_MODULE,
-                .algo                   = &s3c24xx_i2c_algorithm,
-                .retries                = 2,
-                .class                  = I2C_CLASS_HWMON | I2C_CLASS_SPD,
-        },
-};
-
 /* s3c24xx_i2c_calcdivisor
  *
  * return the divisor settings for a given frequency
@@ -643,7 +599,7 @@ static inline int freq_acceptable(unsigned int freq, unsigned int wanted)
 {
         int diff = freq - wanted;
 
-        return (diff >= -2 && diff <= 2);
+        return diff >= -2 && diff <= 2;
 }
 
 /* s3c24xx_i2c_clockrate
@@ -655,7 +611,7 @@ static inline int freq_acceptable(unsigned int freq, unsigned int wanted)
 
 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
 {
-        struct s3c2410_platform_i2c *pdata;
+        struct s3c2410_platform_i2c *pdata = i2c->dev->platform_data;
         unsigned long clkin = clk_get_rate(i2c->clk);
         unsigned int divs, div1;
         u32 iiccon;
@@ -663,10 +619,8 @@ static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
         int start, end;
 
         i2c->clkrate = clkin;
-
-        pdata = s3c24xx_i2c_get_platformdata(i2c->adap.dev.parent);
         clkin /= 1000;          /* clkin now in KHz */
-     
+
         dev_dbg(i2c->dev, "pdata %p, freq %lu %lu..%lu\n",
                  pdata, pdata->bus_freq, pdata->min_freq, pdata->max_freq);
 
@@ -774,7 +728,7 @@ static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
 
 /* s3c24xx_i2c_init
  *
- * initialise the controller, set the IO lines and frequency 
+ * initialise the controller, set the IO lines and frequency
 */
 
 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
@@ -785,15 +739,15 @@ static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
 
         /* get the plafrom data */
 
-        pdata = s3c24xx_i2c_get_platformdata(i2c->adap.dev.parent);
+        pdata = i2c->dev->platform_data;
 
         /* inititalise the gpio */
 
-        s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA);
-        s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL);
+        if (pdata->cfg_gpio)
+                pdata->cfg_gpio(to_platform_device(i2c->dev));
 
         /* write slave address */
-        
+
         writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
 
         dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
@@ -831,12 +785,32 @@ static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
 
 static int s3c24xx_i2c_probe(struct platform_device *pdev)
 {
-        struct s3c24xx_i2c *i2c = &s3c24xx_i2c;
+        struct s3c24xx_i2c *i2c;
         struct s3c2410_platform_i2c *pdata;
         struct resource *res;
         int ret;
 
-        pdata = s3c24xx_i2c_get_platformdata(&pdev->dev);
+        pdata = pdev->dev.platform_data;
+        if (!pdata) {
+                dev_err(&pdev->dev, "no platform data\n");
+                return -EINVAL;
+        }
+
+        i2c = kzalloc(sizeof(struct s3c24xx_i2c), GFP_KERNEL);
+        if (!i2c) {
+                dev_err(&pdev->dev, "no memory for state\n");
+                return -ENOMEM;
+        }
+
+        strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
+        i2c->adap.owner   = THIS_MODULE;
+        i2c->adap.algo    = &s3c24xx_i2c_algorithm;
+        i2c->adap.retries = 2;
+        i2c->adap.class   = I2C_CLASS_HWMON | I2C_CLASS_SPD;
+        i2c->tx_setup     = 50;
+
+        spin_lock_init(&i2c->lock);
+        init_waitqueue_head(&i2c->wait);
 
         /* find the clock and enable it */
 
@@ -878,7 +852,8 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev)
                 goto err_ioarea;
         }
 
-        dev_dbg(&pdev->dev, "registers %p (%p, %p)\n", i2c->regs, i2c->ioarea, res);
+        dev_dbg(&pdev->dev, "registers %p (%p, %p)\n",
+                i2c->regs, i2c->ioarea, res);
 
         /* setup info block for the i2c core */
 
@@ -892,29 +867,23 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev)
                 goto err_iomap;
 
         /* find the IRQ for this unit (note, this relies on the init call to
-         * ensure no current IRQs pending 
+         * ensure no current IRQs pending
          */
 
-        res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-        if (res == NULL) {
+        i2c->irq = ret = platform_get_irq(pdev, 0);
+        if (ret <= 0) {
                 dev_err(&pdev->dev, "cannot find IRQ\n");
-                ret = -ENOENT;
                 goto err_iomap;
         }
 
-        ret = request_irq(res->start, s3c24xx_i2c_irq, IRQF_DISABLED,
-                          pdev->name, i2c);
+        ret = request_irq(i2c->irq, s3c24xx_i2c_irq, IRQF_DISABLED,
+                          dev_name(&pdev->dev), i2c);
 
         if (ret != 0) {
-                dev_err(&pdev->dev, "cannot claim IRQ\n");
+                dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
                 goto err_iomap;
         }
 
-        i2c->irq = res;
-                
-        dev_dbg(&pdev->dev, "irq resource %p (%lu)\n", res,
-                (unsigned long)res->start);
-
         ret = s3c24xx_i2c_register_cpufreq(i2c);
         if (ret < 0) {
                 dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
@@ -944,7 +913,7 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev)
         s3c24xx_i2c_deregister_cpufreq(i2c);
 
  err_irq:
-        free_irq(i2c->irq->start, i2c);
+        free_irq(i2c->irq, i2c);
 
  err_iomap:
         iounmap(i2c->regs);
@@ -958,6 +927,7 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev)
         clk_put(i2c->clk);
 
  err_noclk:
+        kfree(i2c);
         return ret;
 }
 
@@ -973,7 +943,7 @@ static int s3c24xx_i2c_remove(struct platform_device *pdev)
         s3c24xx_i2c_deregister_cpufreq(i2c);
 
         i2c_del_adapter(&i2c->adap);
-        free_irq(i2c->irq->start, i2c);
+        free_irq(i2c->irq, i2c);
 
         clk_disable(i2c->clk);
         clk_put(i2c->clk);
@@ -982,6 +952,7 @@ static int s3c24xx_i2c_remove(struct platform_device *pdev)
 
         release_resource(i2c->ioarea);
         kfree(i2c->ioarea);
+        kfree(i2c);
 
         return 0;
 }