Linux-2.6.12-rc2v2.6.12-rc2

Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!

47 files changed, 15628 insertions, 0 deletions

diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
new file mode 100644
index 000000000000..edf8051da3b4
--- /dev/null
+++ b/drivers/i2c/busses/Kconfig
@@ -0,0 +1,499 @@
+#
+# Sensor device configuration
+#
+
+menu "I2C Hardware Bus support"
+        depends on I2C
+
+config I2C_ALI1535
+        tristate "ALI 1535"
+        depends on I2C && PCI && EXPERIMENTAL
+        help
+          If you say yes to this option, support will be included for the SMB
+          Host controller on Acer Labs Inc. (ALI) M1535 South Bridges.  The SMB
+          controller is part of the 7101 device, which is an ACPI-compliant
+          Power Management Unit (PMU).
+
+          This driver can also be built as a module.  If so, the module
+          will be called i2c-ali1535.
+
+config I2C_ALI1563
+        tristate "ALI 1563"
+        depends on I2C && PCI && EXPERIMENTAL
+        help
+          If you say yes to this option, support will be included for the SMB
+          Host controller on Acer Labs Inc. (ALI) M1563 South Bridges.  The SMB
+          controller is part of the 7101 device, which is an ACPI-compliant
+          Power Management Unit (PMU).
+
+          This driver can also be built as a module.  If so, the module
+          will be called i2c-ali1563.
+
+config I2C_ALI15X3
+        tristate "ALI 15x3"
+        depends on I2C && PCI && EXPERIMENTAL
+        help
+          If you say yes to this option, support will be included for the
+          Acer Labs Inc. (ALI) M1514 and M1543 motherboard I2C interfaces.
+
+          This driver can also be built as a module.  If so, the module
+          will be called i2c-ali15x3.
+
+config I2C_AMD756
+        tristate "AMD 756/766/768/8111 and nVidia nForce"
+        depends on I2C && PCI && EXPERIMENTAL
+        help
+          If you say yes to this option, support will be included for the AMD
+          756/766/768 mainboard I2C interfaces.  The driver also includes
+          support for the first (SMBus 1.0) I2C interface of the AMD 8111 and
+          the nVidia nForce I2C interface.
+
+          This driver can also be built as a module.  If so, the module
+          will be called i2c-amd756.
+
+config I2C_AMD756_S4882
+        tristate "SMBus multiplexing on the Tyan S4882"
+        depends on I2C_AMD756 && EXPERIMENTAL
+        help
+          Enabling this option will add specific SMBus support for the Tyan
+          S4882 motherboard.  On this 4-CPU board, the SMBus is multiplexed
+          over 8 different channels, where the various memory module EEPROMs
+          and temperature sensors live.  Saying yes here will give you access
+          to these in addition to the trunk.
+
+          This driver can also be built as a module.  If so, the module
+          will be called i2c-amd756-s4882.
+
+config I2C_AMD8111
+        tristate "AMD 8111"
+        depends on I2C && PCI && EXPERIMENTAL
+        help
+          If you say yes to this option, support will be included for the
+          second (SMBus 2.0) AMD 8111 mainboard I2C interface.
+
+          This driver can also be built as a module.  If so, the module
+          will be called i2c-amd8111.
+
+config I2C_AU1550
+        tristate "Au1550 SMBus interface"
+        depends on I2C && SOC_AU1550
+        help
+          If you say yes to this option, support will be included for the
+          Au1550 SMBus interface.
+
+          This driver can also be built as a module.  If so, the module
+          will be called i2c-au1550.
+
+config I2C_ELEKTOR
+        tristate "Elektor ISA card"
+        depends on I2C && ISA && BROKEN_ON_SMP
+        select I2C_ALGOPCF
+        help
+          This supports the PCF8584 ISA bus I2C adapter.  Say Y if you own
+          such an adapter.
+
+          This support is also available as a module.  If so, the module 
+          will be called i2c-elektor.
+
+config I2C_HYDRA
+        tristate "CHRP Apple Hydra Mac I/O I2C interface"
+        depends on I2C && PCI && PPC_CHRP && EXPERIMENTAL
+        select I2C_ALGOBIT
+        help
+          This supports the use of the I2C interface in the Apple Hydra Mac
+          I/O chip on some CHRP machines (e.g. the LongTrail).  Say Y if you
+          have such a machine.
+
+          This support is also available as a module.  If so, the module
+          will be called i2c-hydra.
+
+config I2C_I801
+        tristate "Intel 82801 (ICH)"
+        depends on I2C && PCI && EXPERIMENTAL
+        help
+          If you say yes to this option, support will be included for the Intel
+          801 family of mainboard I2C interfaces.  Specifically, the following
+          versions of the chipset are supported:
+            82801AA
+            82801AB
+            82801BA
+            82801CA/CAM
+            82801DB
+            82801EB/ER (ICH5/ICH5R)
+            6300ESB
+            ICH6
+            ICH7
+
+          This driver can also be built as a module.  If so, the module
+          will be called i2c-i801.
+
+config I2C_I810
+        tristate "Intel 810/815"
+        depends on I2C && PCI && EXPERIMENTAL
+        select I2C_ALGOBIT
+        help
+          If you say yes to this option, support will be included for the Intel
+          810/815 family of mainboard I2C interfaces.  Specifically, the 
+          following versions of the chipset is supported:
+            i810AA
+            i810AB
+            i810E
+            i815
+
+          This driver can also be built as a module.  If so, the module
+          will be called i2c-i810.
+
+config I2C_PIIX4
+        tristate "Intel PIIX4"
+        depends on I2C && PCI
+        help
+          If you say yes to this option, support will be included for the Intel
+          PIIX4 family of mainboard I2C interfaces.  Specifically, the following
+          versions of the chipset are supported:
+            Intel PIIX4
+            Intel 440MX
+            Serverworks OSB4
+            Serverworks CSB5
+            Serverworks CSB6
+            SMSC Victory66
+
+          This driver can also be built as a module.  If so, the module
+          will be called i2c-piix4.
+
+config I2C_IBM_IIC
+        tristate "IBM PPC 4xx on-chip I2C interface"
+        depends on IBM_OCP && I2C
+        help
+          Say Y here if you want to use IIC peripheral found on 
+          embedded IBM PPC 4xx based systems. 
+
+          This driver can also be built as a module.  If so, the module
+          will be called i2c-ibm_iic.
+
+config I2C_IOP3XX
+        tristate "Intel IOP3xx and IXP4xx on-chip I2C interface"
+        depends on (ARCH_IOP3XX || ARCH_IXP4XX) && I2C
+        help
+          Say Y here if you want to use the IIC bus controller on
+          the Intel IOP3xx I/O Processors or IXP4xx Network Processors.
+
+          This driver can also be built as a module.  If so, the module
+          will be called i2c-iop3xx.
+
+config I2C_ISA
+        tristate "ISA Bus support"
+        depends on I2C && EXPERIMENTAL
+        help
+          If you say yes to this option, support will be included for i2c
+          interfaces that are on the ISA bus.
+
+          This driver can also be built as a module.  If so, the module
+          will be called i2c-isa.
+
+config I2C_ITE
+        tristate "ITE I2C Adapter"
+        depends on I2C && MIPS_ITE8172
+        select I2C_ALGOITE
+        help
+          This supports the ITE8172 I2C peripheral found on some MIPS
+          systems. Say Y if you have one of these. You should also say Y for
+          the ITE I2C driver algorithm support above.
+
+          This support is also available as a module.  If so, the module 
+          will be called i2c-ite.
+
+config I2C_IXP4XX
+        tristate "IXP4xx GPIO-Based I2C Interface"
+        depends on I2C && ARCH_IXP4XX
+        select I2C_ALGOBIT
+        help
+          Say Y here if you have an Intel IXP4xx(420,421,422,425) based 
+          system and are using GPIO lines for an I2C bus.
+
+          This support is also available as a module. If so, the module
+          will be called i2c-ixp4xx.
+
+config I2C_IXP2000
+        tristate "IXP2000 GPIO-Based I2C Interface"
+        depends on I2C && ARCH_IXP2000
+        select I2C_ALGOBIT
+        help
+          Say Y here if you have an Intel IXP2000(2400, 2800, 2850) based 
+          system and are using GPIO lines for an I2C bus.
+
+          This support is also available as a module. If so, the module
+          will be called i2c-ixp2000.
+
+config I2C_KEYWEST
+        tristate "Powermac Keywest I2C interface"
+        depends on I2C && PPC_PMAC
+        help
+          This supports the use of the I2C interface in the combo-I/O
+          chip on recent Apple machines.  Say Y if you have such a machine.
+
+          This support is also available as a module.  If so, the module 
+          will be called i2c-keywest.
+
+config I2C_MPC
+        tristate "MPC107/824x/85xx/52xx"
+        depends on I2C && PPC
+        help
+          If you say yes to this option, support will be included for the
+          built-in I2C interface on the MPC107/Tsi107/MPC8240/MPC8245 and
+          MPC85xx family processors. The driver may also work on 52xx
+          family processors, though interrupts are known not to work.
+
+          This driver can also be built as a module.  If so, the module
+          will be called i2c-mpc.
+
+config I2C_NFORCE2
+        tristate "Nvidia Nforce2"
+        depends on I2C && PCI && EXPERIMENTAL
+        help
+          If you say yes to this option, support will be included for the Nvidia
+          Nforce2 family of mainboard I2C interfaces.
+          This driver also supports the nForce3 Pro 150 MCP.
+
+          This driver can also be built as a module.  If so, the module
+          will be called i2c-nforce2.
+
+config I2C_PARPORT
+        tristate "Parallel port adapter"
+        depends on I2C && PARPORT
+        select I2C_ALGOBIT
+        help
+          This supports parallel port I2C adapters such as the ones made by
+          Philips or Velleman, Analog Devices evaluation boards, and more.
+          Basically any adapter using the parallel port as an I2C bus with
+          no extra chipset is supported by this driver, or could be.
+
+          This driver is a replacement for (and was inspired by) an older
+          driver named i2c-philips-par.  The new driver supports more devices,
+          and makes it easier to add support for new devices.
+          
+          Another driver exists, named i2c-parport-light, which doesn't depend
+          on the parport driver.  This is meant for embedded systems. Don't say
+          Y here if you intend to say Y or M there.
+
+          This support is also available as a module.  If so, the module 
+          will be called i2c-parport.
+
+config I2C_PARPORT_LIGHT
+        tristate "Parallel port adapter (light)"
+        depends on I2C
+        select I2C_ALGOBIT
+        help
+          This supports parallel port I2C adapters such as the ones made by
+          Philips or Velleman, Analog Devices evaluation boards, and more.
+          Basically any adapter using the parallel port as an I2C bus with
+          no extra chipset is supported by this driver, or could be.
+
+          This driver is a light version of i2c-parport.  It doesn't depend
+          on the parport driver, and uses direct I/O access instead.  This
+          might be prefered on embedded systems where wasting memory for
+          the clean but heavy parport handling is not an option.  The
+          drawback is a reduced portability and the impossibility to
+          dasiy-chain other parallel port devices.
+          
+          Don't say Y here if you said Y or M to i2c-parport.  Saying M to
+          both is possible but both modules should not be loaded at the same
+          time.
+
+          This support is also available as a module.  If so, the module 
+          will be called i2c-parport-light.
+
+config I2C_PROSAVAGE
+        tristate "S3/VIA (Pro)Savage"
+        depends on I2C && PCI && EXPERIMENTAL
+        select I2C_ALGOBIT
+        help
+          If you say yes to this option, support will be included for the
+          I2C bus and DDC bus of the S3VIA embedded Savage4 and ProSavage8
+          graphics processors.
+          chipsets supported:
+            S3/VIA KM266/VT8375 aka ProSavage8
+            S3/VIA KM133/VT8365 aka Savage4
+
+          This support is also available as a module.  If so, the module 
+          will be called i2c-prosavage.
+
+config I2C_RPXLITE
+        tristate "Embedded Planet RPX Lite/Classic support"
+        depends on (RPXLITE || RPXCLASSIC) && I2C
+        select I2C_ALGO8XX
+
+config I2C_S3C2410
+        tristate "S3C2410 I2C Driver"
+        depends on I2C && ARCH_S3C2410
+        help
+          Say Y here to include support for I2C controller in the
+          Samsung S3C2410 based System-on-Chip devices.
+
+config I2C_SAVAGE4
+        tristate "S3 Savage 4"
+        depends on I2C && PCI && EXPERIMENTAL
+        select I2C_ALGOBIT
+        help
+          If you say yes to this option, support will be included for the 
+          S3 Savage 4 I2C interface.
+
+          This driver can also be built as a module.  If so, the module
+          will be called i2c-savage4.
+
+config I2C_SIBYTE
+        tristate "SiByte SMBus interface"
+        depends on SIBYTE_SB1xxx_SOC && I2C
+        help
+          Supports the SiByte SOC on-chip I2C interfaces (2 channels).
+
+config SCx200_I2C
+        tristate "NatSemi SCx200 I2C using GPIO pins"
+        depends on SCx200_GPIO && I2C
+        select I2C_ALGOBIT
+        help
+          Enable the use of two GPIO pins of a SCx200 processor as an I2C bus.
+
+          If you don't know what to do here, say N.
+
+          This support is also available as a module.  If so, the module 
+          will be called scx200_i2c.
+
+config SCx200_I2C_SCL
+        int "GPIO pin used for SCL"
+        depends on SCx200_I2C
+        default "12"
+        help
+          Enter the GPIO pin number used for the SCL signal.  This value can
+          also be specified with a module parameter.
+
+config SCx200_I2C_SDA
+        int "GPIO pin used for SDA"
+        depends on SCx200_I2C
+        default "13"
+        help
+          Enter the GPIO pin number used for the SSA signal.  This value can
+          also be specified with a module parameter.
+
+config SCx200_ACB
+        tristate "NatSemi SCx200 ACCESS.bus"
+        depends on I2C && PCI
+        help
+          Enable the use of the ACCESS.bus controllers of a SCx200 processor.
+
+          If you don't know what to do here, say N.
+
+          This support is also available as a module.  If so, the module 
+          will be called scx200_acb.
+
+config I2C_SIS5595
+        tristate "SiS 5595"
+        depends on I2C && PCI && EXPERIMENTAL
+        help
+          If you say yes to this option, support will be included for the 
+          SiS5595 SMBus (a subset of I2C) interface.
+
+          This driver can also be built as a module.  If so, the module
+          will be called i2c-sis5595.
+
+config I2C_SIS630
+        tristate "SiS 630/730"
+        depends on I2C && PCI && EXPERIMENTAL
+        help
+          If you say yes to this option, support will be included for the 
+          SiS630 and SiS730 SMBus (a subset of I2C) interface.
+
+          This driver can also be built as a module.  If so, the module
+          will be called i2c-sis630.
+
+config I2C_SIS96X
+        tristate "SiS 96x"
+        depends on I2C && PCI && EXPERIMENTAL
+        help
+          If you say yes to this option, support will be included for the SiS
+          96x SMBus (a subset of I2C) interfaces.  Specifically, the following
+          chipsets are supported:
+            645/961
+            645DX/961
+            645DX/962
+            648/961
+            650/961
+            735
+
+          This driver can also be built as a module.  If so, the module
+          will be called i2c-sis96x.
+
+config I2C_STUB
+        tristate "I2C/SMBus Test Stub"
+        depends on I2C && EXPERIMENTAL && 'm'
+        default 'n'
+        help
+          This module may be useful to developers of SMBus client drivers,
+          especially for certain kinds of sensor chips.
+
+          If you do build this module, be sure to read the notes and warnings
+          in <file:Documentation/i2c/i2c-stub>.
+
+          If you don't know what to do here, definitely say N.
+
+config I2C_VIA
+        tristate "VIA 82C586B"
+        depends on I2C && PCI && EXPERIMENTAL
+        select I2C_ALGOBIT
+        help
+          If you say yes to this option, support will be included for the VIA
+          82C586B I2C interface
+
+          This driver can also be built as a module.  If so, the module
+          will be called i2c-via.
+
+config I2C_VIAPRO
+        tristate "VIA 82C596/82C686/823x"
+        depends on I2C && PCI && EXPERIMENTAL
+        help
+          If you say yes to this option, support will be included for the VIA
+          82C596/82C686/823x I2C interfaces.  Specifically, the following 
+          chipsets are supported:
+          82C596A/B
+          82C686A/B
+          8231
+          8233
+          8233A
+          8235
+          8237
+
+          This driver can also be built as a module.  If so, the module
+          will be called i2c-viapro.
+
+config I2C_VOODOO3
+        tristate "Voodoo 3"
+        depends on I2C && PCI && EXPERIMENTAL
+        select I2C_ALGOBIT
+        help
+          If you say yes to this option, support will be included for the
+          Voodoo 3 I2C interface.
+
+          This driver can also be built as a module.  If so, the module
+          will be called i2c-voodoo3.
+
+config I2C_PCA_ISA
+        tristate "PCA9564 on an ISA bus"
+        depends on I2C
+        select I2C_ALGOPCA
+        help
+          This driver supports ISA boards using the Philips PCA 9564
+          Parallel bus to I2C bus controller
+          
+          This driver can also be built as a module.  If so, the module
+          will be called i2c-pca-isa.
+
+config I2C_MV64XXX
+        tristate "Marvell mv64xxx I2C Controller"
+        depends on I2C && MV64X60 && EXPERIMENTAL
+        help
+          If you say yes to this option, support will be included for the
+          built-in I2C interface on the Marvell 64xxx line of host bridges.
+
+          This driver can also be built as a module.  If so, the module
+          will be called i2c-mv64xxx.
+
+endmenu
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
new file mode 100644
index 000000000000..42d6d814da72
--- /dev/null
+++ b/drivers/i2c/busses/Makefile
@@ -0,0 +1,47 @@
+#
+# Makefile for the i2c bus drivers.
+#
+
+obj-$(CONFIG_I2C_ALI1535)       += i2c-ali1535.o
+obj-$(CONFIG_I2C_ALI1563)       += i2c-ali1563.o
+obj-$(CONFIG_I2C_ALI15X3)       += i2c-ali15x3.o
+obj-$(CONFIG_I2C_AMD756)        += i2c-amd756.o
+obj-$(CONFIG_I2C_AMD756_S4882)  += i2c-amd756-s4882.o
+obj-$(CONFIG_I2C_AMD8111)       += i2c-amd8111.o
+obj-$(CONFIG_I2C_AU1550)        += i2c-au1550.o
+obj-$(CONFIG_I2C_ELEKTOR)       += i2c-elektor.o
+obj-$(CONFIG_I2C_HYDRA)         += i2c-hydra.o
+obj-$(CONFIG_I2C_I801)          += i2c-i801.o
+obj-$(CONFIG_I2C_I810)          += i2c-i810.o
+obj-$(CONFIG_I2C_IBM_IIC)       += i2c-ibm_iic.o
+obj-$(CONFIG_I2C_IOP3XX)        += i2c-iop3xx.o
+obj-$(CONFIG_I2C_ISA)           += i2c-isa.o
+obj-$(CONFIG_I2C_ITE)           += i2c-ite.o
+obj-$(CONFIG_I2C_IXP2000)       += i2c-ixp2000.o
+obj-$(CONFIG_I2C_IXP4XX)        += i2c-ixp4xx.o
+obj-$(CONFIG_I2C_KEYWEST)       += i2c-keywest.o
+obj-$(CONFIG_I2C_MPC)           += i2c-mpc.o
+obj-$(CONFIG_I2C_MV64XXX)       += i2c-mv64xxx.o
+obj-$(CONFIG_I2C_NFORCE2)       += i2c-nforce2.o
+obj-$(CONFIG_I2C_PARPORT)       += i2c-parport.o
+obj-$(CONFIG_I2C_PARPORT_LIGHT) += i2c-parport-light.o
+obj-$(CONFIG_I2C_PCA_ISA)       += i2c-pca-isa.o
+obj-$(CONFIG_I2C_PIIX4)         += i2c-piix4.o
+obj-$(CONFIG_I2C_PROSAVAGE)     += i2c-prosavage.o
+obj-$(CONFIG_I2C_RPXLITE)       += i2c-rpx.o
+obj-$(CONFIG_I2C_S3C2410)       += i2c-s3c2410.o
+obj-$(CONFIG_I2C_SAVAGE4)       += i2c-savage4.o
+obj-$(CONFIG_I2C_SIBYTE)        += i2c-sibyte.o
+obj-$(CONFIG_I2C_SIS5595)       += i2c-sis5595.o
+obj-$(CONFIG_I2C_SIS630)        += i2c-sis630.o
+obj-$(CONFIG_I2C_SIS96X)        += i2c-sis96x.o
+obj-$(CONFIG_I2C_STUB)          += i2c-stub.o
+obj-$(CONFIG_I2C_VIA)           += i2c-via.o
+obj-$(CONFIG_I2C_VIAPRO)        += i2c-viapro.o
+obj-$(CONFIG_I2C_VOODOO3)       += i2c-voodoo3.o
+obj-$(CONFIG_SCx200_ACB)        += scx200_acb.o
+obj-$(CONFIG_SCx200_I2C)        += scx200_i2c.o
+
+ifeq ($(CONFIG_I2C_DEBUG_BUS),y)
+EXTRA_CFLAGS += -DDEBUG
+endif
diff --git a/drivers/i2c/busses/i2c-ali1535.c b/drivers/i2c/busses/i2c-ali1535.c
new file mode 100644
index 000000000000..b00cd4098221
--- /dev/null
+++ b/drivers/i2c/busses/i2c-ali1535.c
@@ -0,0 +1,543 @@
+/*
+    i2c-ali1535.c - Part of lm_sensors, Linux kernel modules for hardware
+                    monitoring
+    Copyright (c) 2000  Frodo Looijaard <frodol@dds.nl>, 
+                        Philip Edelbrock <phil@netroedge.com>, 
+                        Mark D. Studebaker <mdsxyz123@yahoo.com>,
+                        Dan Eaton <dan.eaton@rocketlogix.com> and 
+                        Stephen Rousset<stephen.rousset@rocketlogix.com> 
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+/*
+    This is the driver for the SMB Host controller on
+    Acer Labs Inc. (ALI) M1535 South Bridge.
+
+    The M1535 is a South bridge for portable systems.
+    It is very similar to the M15x3 South bridges also produced
+    by Acer Labs Inc.  Some of the registers within the part
+    have moved and some have been redefined slightly. Additionally,
+    the sequencing of the SMBus transactions has been modified
+    to be more consistent with the sequencing recommended by
+    the manufacturer and observed through testing.  These
+    changes are reflected in this driver and can be identified
+    by comparing this driver to the i2c-ali15x3 driver.
+    For an overview of these chips see http://www.acerlabs.com
+
+    The SMB controller is part of the 7101 device, which is an
+    ACPI-compliant Power Management Unit (PMU).
+
+    The whole 7101 device has to be enabled for the SMB to work.
+    You can't just enable the SMB alone.
+    The SMB and the ACPI have separate I/O spaces.
+    We make sure that the SMB is enabled. We leave the ACPI alone.
+
+    This driver controls the SMB Host only.
+
+    This driver does not use interrupts.
+*/
+
+
+/* Note: we assume there can only be one ALI1535, with one SMBus interface */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/stddef.h>
+#include <linux/sched.h>
+#include <linux/delay.h>
+#include <linux/ioport.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <asm/io.h>
+#include <asm/semaphore.h>
+
+
+/* ALI1535 SMBus address offsets */
+#define SMBHSTSTS       (0 + ali1535_smba)
+#define SMBHSTTYP       (1 + ali1535_smba)
+#define SMBHSTPORT      (2 + ali1535_smba)
+#define SMBHSTCMD       (7 + ali1535_smba)
+#define SMBHSTADD       (3 + ali1535_smba)
+#define SMBHSTDAT0      (4 + ali1535_smba)
+#define SMBHSTDAT1      (5 + ali1535_smba)
+#define SMBBLKDAT       (6 + ali1535_smba)
+
+/* PCI Address Constants */
+#define SMBCOM          0x004
+#define SMBREV          0x008
+#define SMBCFG          0x0D1
+#define SMBBA           0x0E2
+#define SMBHSTCFG       0x0F0
+#define SMBCLK          0x0F2
+
+/* Other settings */
+#define MAX_TIMEOUT             500     /* times 1/100 sec */
+#define ALI1535_SMB_IOSIZE      32
+
+#define ALI1535_SMB_DEFAULTBASE 0x8040
+
+/* ALI1535 address lock bits */
+#define ALI1535_LOCK            0x06    /* dwe */
+
+/* ALI1535 command constants */
+#define ALI1535_QUICK           0x00
+#define ALI1535_BYTE            0x10
+#define ALI1535_BYTE_DATA       0x20
+#define ALI1535_WORD_DATA       0x30
+#define ALI1535_BLOCK_DATA      0x40
+#define ALI1535_I2C_READ        0x60
+
+#define ALI1535_DEV10B_EN       0x80    /* Enable 10-bit addressing in  */
+                                        /*  I2C read                    */
+#define ALI1535_T_OUT           0x08    /* Time-out Command (write)     */
+#define ALI1535_A_HIGH_BIT9     0x08    /* Bit 9 of 10-bit address in   */
+                                        /* Alert-Response-Address       */
+                                        /* (read)                       */
+#define ALI1535_KILL            0x04    /* Kill Command (write)         */
+#define ALI1535_A_HIGH_BIT8     0x04    /* Bit 8 of 10-bit address in   */
+                                        /*  Alert-Response-Address      */
+                                        /*  (read)                      */
+
+#define ALI1535_D_HI_MASK       0x03    /* Mask for isolating bits 9-8  */
+                                        /*  of 10-bit address in I2C    */
+                                        /*  Read Command                */
+
+/* ALI1535 status register bits */
+#define ALI1535_STS_IDLE        0x04
+#define ALI1535_STS_BUSY        0x08    /* host busy */
+#define ALI1535_STS_DONE        0x10    /* transaction complete */
+#define ALI1535_STS_DEV         0x20    /* device error */
+#define ALI1535_STS_BUSERR      0x40    /* bus error    */
+#define ALI1535_STS_FAIL        0x80    /* failed bus transaction */
+#define ALI1535_STS_ERR         0xE0    /* all the bad error bits */
+
+#define ALI1535_BLOCK_CLR       0x04    /* reset block data index */
+
+/* ALI1535 device address register bits */
+#define ALI1535_RD_ADDR         0x01    /* Read/Write Bit in Device     */
+                                        /*  Address field               */
+                                        /*  -> Write = 0                */
+                                        /*  -> Read  = 1                */
+#define ALI1535_SMBIO_EN        0x04    /* SMB I/O Space enable         */
+
+
+static unsigned short ali1535_smba;
+static DECLARE_MUTEX(i2c_ali1535_sem);
+
+/* Detect whether a ALI1535 can be found, and initialize it, where necessary.
+   Note the differences between kernels with the old PCI BIOS interface and
+   newer kernels with the real PCI interface. In compat.h some things are
+   defined to make the transition easier. */
+static int ali1535_setup(struct pci_dev *dev)
+{
+        int retval = -ENODEV;
+        unsigned char temp;
+
+        /* Check the following things:
+                - SMB I/O address is initialized
+                - Device is enabled
+                - We can use the addresses
+        */
+
+        /* Determine the address of the SMBus area */
+        pci_read_config_word(dev, SMBBA, &ali1535_smba);
+        ali1535_smba &= (0xffff & ~(ALI1535_SMB_IOSIZE - 1));
+        if (ali1535_smba == 0) {
+                dev_warn(&dev->dev,
+                        "ALI1535_smb region uninitialized - upgrade BIOS?\n");
+                goto exit;
+        }
+
+        if (!request_region(ali1535_smba, ALI1535_SMB_IOSIZE, "ali1535-smb")) {
+                dev_err(&dev->dev, "ALI1535_smb region 0x%x already in use!\n",
+                        ali1535_smba);
+                goto exit;
+        }
+
+        /* check if whole device is enabled */
+        pci_read_config_byte(dev, SMBCFG, &temp);
+        if ((temp & ALI1535_SMBIO_EN) == 0) {
+                dev_err(&dev->dev, "SMB device not enabled - upgrade BIOS?\n");
+                goto exit_free;
+        }
+
+        /* Is SMB Host controller enabled? */
+        pci_read_config_byte(dev, SMBHSTCFG, &temp);
+        if ((temp & 1) == 0) {
+                dev_err(&dev->dev, "SMBus controller not enabled - upgrade BIOS?\n");
+                goto exit_free;
+        }
+
+        /* set SMB clock to 74KHz as recommended in data sheet */
+        pci_write_config_byte(dev, SMBCLK, 0x20);
+
+        /*
+          The interrupt routing for SMB is set up in register 0x77 in the
+          1533 ISA Bridge device, NOT in the 7101 device.
+          Don't bother with finding the 1533 device and reading the register.
+        if ((....... & 0x0F) == 1)
+                dev_dbg(&dev->dev, "ALI1535 using Interrupt 9 for SMBus.\n");
+        */
+        pci_read_config_byte(dev, SMBREV, &temp);
+        dev_dbg(&dev->dev, "SMBREV = 0x%X\n", temp);
+        dev_dbg(&dev->dev, "ALI1535_smba = 0x%X\n", ali1535_smba);
+
+        retval = 0;
+exit:
+        return retval;
+
+exit_free:
+        release_region(ali1535_smba, ALI1535_SMB_IOSIZE);
+        return retval;
+}
+
+static int ali1535_transaction(struct i2c_adapter *adap)
+{
+        int temp;
+        int result = 0;
+        int timeout = 0;
+
+        dev_dbg(&adap->dev, "Transaction (pre): STS=%02x, TYP=%02x, "
+                "CMD=%02x, ADD=%02x, DAT0=%02x, DAT1=%02x\n",
+                inb_p(SMBHSTSTS), inb_p(SMBHSTTYP), inb_p(SMBHSTCMD),
+                inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), inb_p(SMBHSTDAT1));
+
+        /* get status */
+        temp = inb_p(SMBHSTSTS);
+
+        /* Make sure the SMBus host is ready to start transmitting */
+        /* Check the busy bit first */
+        if (temp & ALI1535_STS_BUSY) {
+                /* If the host controller is still busy, it may have timed out
+                 * in the previous transaction, resulting in a "SMBus Timeout"
+                 * printk.  I've tried the following to reset a stuck busy bit.
+                 *   1. Reset the controller with an KILL command. (this
+                 *      doesn't seem to clear the controller if an external
+                 *      device is hung)
+                 *   2. Reset the controller and the other SMBus devices with a
+                 *      T_OUT command. (this clears the host busy bit if an
+                 *      external device is hung, but it comes back upon a new
+                 *      access to a device)
+                 *   3. Disable and reenable the controller in SMBHSTCFG. Worst
+                 *      case, nothing seems to work except power reset.
+                 */
+
+                /* Try resetting entire SMB bus, including other devices - This
+                 * may not work either - it clears the BUSY bit but then the
+                 * BUSY bit may come back on when you try and use the chip
+                 * again.  If that's the case you are stuck.
+                 */
+                dev_info(&adap->dev,
+                        "Resetting entire SMB Bus to clear busy condition (%02x)\n",
+                        temp);
+                outb_p(ALI1535_T_OUT, SMBHSTTYP);
+                temp = inb_p(SMBHSTSTS);
+        }
+
+        /* now check the error bits and the busy bit */
+        if (temp & (ALI1535_STS_ERR | ALI1535_STS_BUSY)) {
+                /* do a clear-on-write */
+                outb_p(0xFF, SMBHSTSTS);
+                if ((temp = inb_p(SMBHSTSTS)) &
+                    (ALI1535_STS_ERR | ALI1535_STS_BUSY)) {
+                        /* This is probably going to be correctable only by a
+                         * power reset as one of the bits now appears to be
+                         * stuck */
+                        /* This may be a bus or device with electrical problems. */
+                        dev_err(&adap->dev,
+                                "SMBus reset failed! (0x%02x) - controller or "
+                                "device on bus is probably hung\n", temp);
+                        return -1;
+                }
+        } else {
+                /* check and clear done bit */
+                if (temp & ALI1535_STS_DONE) {
+                        outb_p(temp, SMBHSTSTS);
+                }
+        }
+
+        /* start the transaction by writing anything to the start register */
+        outb_p(0xFF, SMBHSTPORT);
+
+        /* We will always wait for a fraction of a second! */
+        timeout = 0;
+        do {
+                msleep(1);
+                temp = inb_p(SMBHSTSTS);
+        } while (((temp & ALI1535_STS_BUSY) && !(temp & ALI1535_STS_IDLE))
+                 && (timeout++ < MAX_TIMEOUT));
+
+        /* If the SMBus is still busy, we give up */
+        if (timeout >= MAX_TIMEOUT) {
+                result = -1;
+                dev_err(&adap->dev, "SMBus Timeout!\n");
+        }
+
+        if (temp & ALI1535_STS_FAIL) {
+                result = -1;
+                dev_dbg(&adap->dev, "Error: Failed bus transaction\n");
+        }
+
+        /* Unfortunately the ALI SMB controller maps "no response" and "bus
+         * collision" into a single bit. No reponse is the usual case so don't
+         * do a printk.  This means that bus collisions go unreported.
+         */
+        if (temp & ALI1535_STS_BUSERR) {
+                result = -1;
+                dev_dbg(&adap->dev,
+                        "Error: no response or bus collision ADD=%02x\n",
+                        inb_p(SMBHSTADD));
+        }
+
+        /* haven't ever seen this */
+        if (temp & ALI1535_STS_DEV) {
+                result = -1;
+                dev_err(&adap->dev, "Error: device error\n");
+        }
+
+        /* check to see if the "command complete" indication is set */
+        if (!(temp & ALI1535_STS_DONE)) {
+                result = -1;
+                dev_err(&adap->dev, "Error: command never completed\n");
+        }
+
+        dev_dbg(&adap->dev, "Transaction (post): STS=%02x, TYP=%02x, "
+                "CMD=%02x, ADD=%02x, DAT0=%02x, DAT1=%02x\n",
+                inb_p(SMBHSTSTS), inb_p(SMBHSTTYP), inb_p(SMBHSTCMD),
+                inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), inb_p(SMBHSTDAT1));
+
+        /* take consequent actions for error conditions */
+        if (!(temp & ALI1535_STS_DONE)) {
+                /* issue "kill" to reset host controller */
+                outb_p(ALI1535_KILL,SMBHSTTYP);
+                outb_p(0xFF,SMBHSTSTS);
+        } else if (temp & ALI1535_STS_ERR) {
+                /* issue "timeout" to reset all devices on bus */
+                outb_p(ALI1535_T_OUT,SMBHSTTYP);
+                outb_p(0xFF,SMBHSTSTS);
+        }
+
+        return result;
+}
+
+/* Return -1 on error. */
+static s32 ali1535_access(struct i2c_adapter *adap, u16 addr,
+                          unsigned short flags, char read_write, u8 command,
+                          int size, union i2c_smbus_data *data)
+{
+        int i, len;
+        int temp;
+        int timeout;
+        s32 result = 0;
+
+        down(&i2c_ali1535_sem);
+        /* make sure SMBus is idle */
+        temp = inb_p(SMBHSTSTS);
+        for (timeout = 0;
+             (timeout < MAX_TIMEOUT) && !(temp & ALI1535_STS_IDLE);
+             timeout++) {
+                msleep(1);
+                temp = inb_p(SMBHSTSTS);
+        }
+        if (timeout >= MAX_TIMEOUT)
+                dev_warn(&adap->dev, "Idle wait Timeout! STS=0x%02x\n", temp);
+
+        /* clear status register (clear-on-write) */
+        outb_p(0xFF, SMBHSTSTS);
+
+        switch (size) {
+        case I2C_SMBUS_PROC_CALL:
+                dev_err(&adap->dev, "I2C_SMBUS_PROC_CALL not supported!\n");
+                result = -1;
+                goto EXIT;
+        case I2C_SMBUS_QUICK:
+                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
+                       SMBHSTADD);
+                size = ALI1535_QUICK;
+                outb_p(size, SMBHSTTYP);        /* output command */
+                break;
+        case I2C_SMBUS_BYTE:
+                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
+                       SMBHSTADD);
+                size = ALI1535_BYTE;
+                outb_p(size, SMBHSTTYP);        /* output command */
+                if (read_write == I2C_SMBUS_WRITE)
+                        outb_p(command, SMBHSTCMD);
+                break;
+        case I2C_SMBUS_BYTE_DATA:
+                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
+                       SMBHSTADD);
+                size = ALI1535_BYTE_DATA;
+                outb_p(size, SMBHSTTYP);        /* output command */
+                outb_p(command, SMBHSTCMD);
+                if (read_write == I2C_SMBUS_WRITE)
+                        outb_p(data->byte, SMBHSTDAT0);
+                break;
+        case I2C_SMBUS_WORD_DATA:
+                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
+                       SMBHSTADD);
+                size = ALI1535_WORD_DATA;
+                outb_p(size, SMBHSTTYP);        /* output command */
+                outb_p(command, SMBHSTCMD);
+                if (read_write == I2C_SMBUS_WRITE) {
+                        outb_p(data->word & 0xff, SMBHSTDAT0);
+                        outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
+                }
+                break;
+        case I2C_SMBUS_BLOCK_DATA:
+                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
+                       SMBHSTADD);
+                size = ALI1535_BLOCK_DATA;
+                outb_p(size, SMBHSTTYP);        /* output command */
+                outb_p(command, SMBHSTCMD);
+                if (read_write == I2C_SMBUS_WRITE) {
+                        len = data->block[0];
+                        if (len < 0) {
+                                len = 0;
+                                data->block[0] = len;
+                        }
+                        if (len > 32) {
+                                len = 32;
+                                data->block[0] = len;
+                        }
+                        outb_p(len, SMBHSTDAT0);
+                        /* Reset SMBBLKDAT */
+                        outb_p(inb_p(SMBHSTTYP) | ALI1535_BLOCK_CLR, SMBHSTTYP);
+                        for (i = 1; i <= len; i++)
+                                outb_p(data->block[i], SMBBLKDAT);
+                }
+                break;
+        }
+
+        if (ali1535_transaction(adap)) {
+                /* Error in transaction */
+                result = -1;
+                goto EXIT;
+        }
+
+        if ((read_write == I2C_SMBUS_WRITE) || (size == ALI1535_QUICK)) {
+                result = 0;
+                goto EXIT;
+        }
+
+        switch (size) {
+        case ALI1535_BYTE:      /* Result put in SMBHSTDAT0 */
+                data->byte = inb_p(SMBHSTDAT0);
+                break;
+        case ALI1535_BYTE_DATA:
+                data->byte = inb_p(SMBHSTDAT0);
+                break;
+        case ALI1535_WORD_DATA:
+                data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
+                break;
+        case ALI1535_BLOCK_DATA:
+                len = inb_p(SMBHSTDAT0);
+                if (len > 32)
+                        len = 32;
+                data->block[0] = len;
+                /* Reset SMBBLKDAT */
+                outb_p(inb_p(SMBHSTTYP) | ALI1535_BLOCK_CLR, SMBHSTTYP);
+                for (i = 1; i <= data->block[0]; i++) {
+                        data->block[i] = inb_p(SMBBLKDAT);
+                        dev_dbg(&adap->dev, "Blk: len=%d, i=%d, data=%02x\n",
+                                len, i, data->block[i]);
+                }
+                break;
+        }
+EXIT:
+        up(&i2c_ali1535_sem);
+        return result;
+}
+
+
+static u32 ali1535_func(struct i2c_adapter *adapter)
+{
+        return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
+            I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
+            I2C_FUNC_SMBUS_BLOCK_DATA;
+}
+
+static struct i2c_algorithm smbus_algorithm = {
+        .name           = "Non-i2c SMBus adapter",
+        .id             = I2C_ALGO_SMBUS,
+        .smbus_xfer     = ali1535_access,
+        .functionality  = ali1535_func,
+};
+
+static struct i2c_adapter ali1535_adapter = {
+        .owner          = THIS_MODULE,
+        .class          = I2C_CLASS_HWMON,
+        .algo           = &smbus_algorithm,
+        .name           = "unset",
+};
+
+static struct pci_device_id ali1535_ids[] = {
+        { PCI_DEVICE(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101) },
+        { },
+};
+
+MODULE_DEVICE_TABLE (pci, ali1535_ids);
+
+static int __devinit ali1535_probe(struct pci_dev *dev, const struct pci_device_id *id)
+{
+        if (ali1535_setup(dev)) {
+                dev_warn(&dev->dev,
+                        "ALI1535 not detected, module not inserted.\n");
+                return -ENODEV;
+        }
+
+        /* set up the driverfs linkage to our parent device */
+        ali1535_adapter.dev.parent = &dev->dev;
+
+        snprintf(ali1535_adapter.name, I2C_NAME_SIZE, 
+                "SMBus ALI1535 adapter at %04x", ali1535_smba);
+        return i2c_add_adapter(&ali1535_adapter);
+}
+
+static void __devexit ali1535_remove(struct pci_dev *dev)
+{
+        i2c_del_adapter(&ali1535_adapter);
+        release_region(ali1535_smba, ALI1535_SMB_IOSIZE);
+}
+
+static struct pci_driver ali1535_driver = {
+        .name           = "ali1535_smbus",
+        .id_table       = ali1535_ids,
+        .probe          = ali1535_probe,
+        .remove         = __devexit_p(ali1535_remove),
+};
+
+static int __init i2c_ali1535_init(void)
+{
+        return pci_register_driver(&ali1535_driver);
+}
+
+static void __exit i2c_ali1535_exit(void)
+{
+        pci_unregister_driver(&ali1535_driver);
+}
+
+MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl>, "
+              "Philip Edelbrock <phil@netroedge.com>, "
+              "Mark D. Studebaker <mdsxyz123@yahoo.com> "
+              "and Dan Eaton <dan.eaton@rocketlogix.com>");
+MODULE_DESCRIPTION("ALI1535 SMBus driver");
+MODULE_LICENSE("GPL");
+
+module_init(i2c_ali1535_init);
+module_exit(i2c_ali1535_exit);
diff --git a/drivers/i2c/busses/i2c-ali1563.c b/drivers/i2c/busses/i2c-ali1563.c
new file mode 100644
index 000000000000..35710818fe47
--- /dev/null
+++ b/drivers/i2c/busses/i2c-ali1563.c
@@ -0,0 +1,415 @@
+/**
+ *      i2c-ali1563.c - i2c driver for the ALi 1563 Southbridge
+ *
+ *      Copyright (C) 2004 Patrick Mochel
+ *
+ *      The 1563 southbridge is deceptively similar to the 1533, with a
+ *      few notable exceptions. One of those happens to be the fact they
+ *      upgraded the i2c core to be 2.0 compliant, and happens to be almost
+ *      identical to the i2c controller found in the Intel 801 south
+ *      bridges.
+ *
+ *      This driver is based on a mix of the 15x3, 1535, and i801 drivers,
+ *      with a little help from the ALi 1563 spec.
+ *
+ *      This file is released under the GPLv2
+ */
+
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+
+#define ALI1563_MAX_TIMEOUT     500
+#define ALI1563_SMBBA           0x80
+#define ALI1563_SMB_IOEN        1
+#define ALI1563_SMB_HOSTEN      2
+#define ALI1563_SMB_IOSIZE      16
+
+#define SMB_HST_STS     (ali1563_smba + 0)
+#define SMB_HST_CNTL1   (ali1563_smba + 1)
+#define SMB_HST_CNTL2   (ali1563_smba + 2)
+#define SMB_HST_CMD     (ali1563_smba + 3)
+#define SMB_HST_ADD     (ali1563_smba + 4)
+#define SMB_HST_DAT0    (ali1563_smba + 5)
+#define SMB_HST_DAT1    (ali1563_smba + 6)
+#define SMB_BLK_DAT     (ali1563_smba + 7)
+
+#define HST_STS_BUSY    0x01
+#define HST_STS_INTR    0x02
+#define HST_STS_DEVERR  0x04
+#define HST_STS_BUSERR  0x08
+#define HST_STS_FAIL    0x10
+#define HST_STS_DONE    0x80
+#define HST_STS_BAD     0x1c
+
+
+#define HST_CNTL1_TIMEOUT       0x80
+#define HST_CNTL1_LAST          0x40
+
+#define HST_CNTL2_KILL          0x04
+#define HST_CNTL2_START         0x40
+#define HST_CNTL2_QUICK         0x00
+#define HST_CNTL2_BYTE          0x01
+#define HST_CNTL2_BYTE_DATA     0x02
+#define HST_CNTL2_WORD_DATA     0x03
+#define HST_CNTL2_BLOCK         0x05
+
+
+
+static unsigned short ali1563_smba;
+
+static int ali1563_transaction(struct i2c_adapter * a)
+{
+        u32 data;
+        int timeout;
+
+        dev_dbg(&a->dev, "Transaction (pre): STS=%02x, CNTL1=%02x, "
+                "CNTL2=%02x, CMD=%02x, ADD=%02x, DAT0=%02x, DAT1=%02x\n",
+                inb_p(SMB_HST_STS), inb_p(SMB_HST_CNTL1), inb_p(SMB_HST_CNTL2),
+                inb_p(SMB_HST_CMD), inb_p(SMB_HST_ADD), inb_p(SMB_HST_DAT0),
+                inb_p(SMB_HST_DAT1));
+
+        data = inb_p(SMB_HST_STS);
+        if (data & HST_STS_BAD) {
+                dev_warn(&a->dev,"ali1563: Trying to reset busy device\n");
+                outb_p(data | HST_STS_BAD,SMB_HST_STS);
+                data = inb_p(SMB_HST_STS);
+                if (data & HST_STS_BAD)
+                        return -EBUSY;
+        }
+        outb_p(inb_p(SMB_HST_CNTL2) | HST_CNTL2_START, SMB_HST_CNTL2);
+
+        timeout = ALI1563_MAX_TIMEOUT;
+        do
+                msleep(1);
+        while (((data = inb_p(SMB_HST_STS)) & HST_STS_BUSY) && --timeout);
+
+        dev_dbg(&a->dev, "Transaction (post): STS=%02x, CNTL1=%02x, "
+                "CNTL2=%02x, CMD=%02x, ADD=%02x, DAT0=%02x, DAT1=%02x\n",
+                inb_p(SMB_HST_STS), inb_p(SMB_HST_CNTL1), inb_p(SMB_HST_CNTL2),
+                inb_p(SMB_HST_CMD), inb_p(SMB_HST_ADD), inb_p(SMB_HST_DAT0),
+                inb_p(SMB_HST_DAT1));
+
+        if (timeout && !(data & HST_STS_BAD))
+                return 0;
+        dev_warn(&a->dev, "SMBus Error: %s%s%s%s%s\n",
+                timeout ? "Timeout " : "",
+                data & HST_STS_FAIL ? "Transaction Failed " : "",
+                data & HST_STS_BUSERR ? "No response or Bus Collision " : "",
+                data & HST_STS_DEVERR ? "Device Error " : "",
+                !(data & HST_STS_DONE) ? "Transaction Never Finished " : "");
+
+        if (!(data & HST_STS_DONE))
+                /* Issue 'kill' to host controller */
+                outb_p(HST_CNTL2_KILL,SMB_HST_CNTL2);
+        else
+                /* Issue timeout to reset all devices on bus */
+                outb_p(HST_CNTL1_TIMEOUT,SMB_HST_CNTL1);
+        return -1;
+}
+
+static int ali1563_block_start(struct i2c_adapter * a)
+{
+        u32 data;
+        int timeout;
+
+        dev_dbg(&a->dev, "Block (pre): STS=%02x, CNTL1=%02x, "
+                "CNTL2=%02x, CMD=%02x, ADD=%02x, DAT0=%02x, DAT1=%02x\n",
+                inb_p(SMB_HST_STS), inb_p(SMB_HST_CNTL1), inb_p(SMB_HST_CNTL2),
+                inb_p(SMB_HST_CMD), inb_p(SMB_HST_ADD), inb_p(SMB_HST_DAT0),
+                inb_p(SMB_HST_DAT1));
+
+        data = inb_p(SMB_HST_STS);
+        if (data & HST_STS_BAD) {
+                dev_warn(&a->dev,"ali1563: Trying to reset busy device\n");
+                outb_p(data | HST_STS_BAD,SMB_HST_STS);
+                data = inb_p(SMB_HST_STS);
+                if (data & HST_STS_BAD)
+                        return -EBUSY;
+        }
+
+        /* Clear byte-ready bit */
+        outb_p(data | HST_STS_DONE, SMB_HST_STS);
+
+        /* Start transaction and wait for byte-ready bit to be set */
+        outb_p(inb_p(SMB_HST_CNTL2) | HST_CNTL2_START, SMB_HST_CNTL2);
+
+        timeout = ALI1563_MAX_TIMEOUT;
+        do
+                msleep(1);
+        while (!((data = inb_p(SMB_HST_STS)) & HST_STS_DONE) && --timeout);
+
+        dev_dbg(&a->dev, "Block (post): STS=%02x, CNTL1=%02x, "
+                "CNTL2=%02x, CMD=%02x, ADD=%02x, DAT0=%02x, DAT1=%02x\n",
+                inb_p(SMB_HST_STS), inb_p(SMB_HST_CNTL1), inb_p(SMB_HST_CNTL2),
+                inb_p(SMB_HST_CMD), inb_p(SMB_HST_ADD), inb_p(SMB_HST_DAT0),
+                inb_p(SMB_HST_DAT1));
+
+        if (timeout && !(data & HST_STS_BAD))
+                return 0;
+        dev_warn(&a->dev, "SMBus Error: %s%s%s%s%s\n",
+                timeout ? "Timeout " : "",
+                data & HST_STS_FAIL ? "Transaction Failed " : "",
+                data & HST_STS_BUSERR ? "No response or Bus Collision " : "",
+                data & HST_STS_DEVERR ? "Device Error " : "",
+                !(data & HST_STS_DONE) ? "Transaction Never Finished " : "");
+        return -1;
+}
+
+static int ali1563_block(struct i2c_adapter * a, union i2c_smbus_data * data, u8 rw)
+{
+        int i, len;
+        int error = 0;
+
+        /* Do we need this? */
+        outb_p(HST_CNTL1_LAST,SMB_HST_CNTL1);
+
+        if (rw == I2C_SMBUS_WRITE) {
+                len = data->block[0];
+                if (len < 1)
+                        len = 1;
+                else if (len > 32)
+                        len = 32;
+                outb_p(len,SMB_HST_DAT0);
+                outb_p(data->block[1],SMB_BLK_DAT);
+        } else
+                len = 32;
+
+        outb_p(inb_p(SMB_HST_CNTL2) | HST_CNTL2_BLOCK, SMB_HST_CNTL2);
+
+        for (i = 0; i < len; i++) {
+                if (rw == I2C_SMBUS_WRITE) {
+                        outb_p(data->block[i + 1], SMB_BLK_DAT);
+                        if ((error = ali1563_block_start(a)))
+                                break;
+                } else {
+                        if ((error = ali1563_block_start(a)))
+                                break;
+                        if (i == 0) {
+                                len = inb_p(SMB_HST_DAT0);
+                                if (len < 1)
+                                        len = 1;
+                                else if (len > 32)
+                                        len = 32;
+                        }
+                        data->block[i+1] = inb_p(SMB_BLK_DAT);
+                }
+        }
+        /* Do we need this? */
+        outb_p(HST_CNTL1_LAST,SMB_HST_CNTL1);
+        return error;
+}
+
+static s32 ali1563_access(struct i2c_adapter * a, u16 addr,
+                          unsigned short flags, char rw, u8 cmd,
+                          int size, union i2c_smbus_data * data)
+{
+        int error = 0;
+        int timeout;
+        u32 reg;
+
+        for (timeout = ALI1563_MAX_TIMEOUT; timeout; timeout--) {
+                if (!(reg = inb_p(SMB_HST_STS) & HST_STS_BUSY))
+                        break;
+        }
+        if (!timeout)
+                dev_warn(&a->dev,"SMBus not idle. HST_STS = %02x\n",reg);
+        outb_p(0xff,SMB_HST_STS);
+
+        /* Map the size to what the chip understands */
+        switch (size) {
+        case I2C_SMBUS_PROC_CALL:
+                dev_err(&a->dev, "I2C_SMBUS_PROC_CALL not supported!\n");
+                error = -EINVAL;
+                break;
+        case I2C_SMBUS_QUICK:
+                size = HST_CNTL2_QUICK;
+                break;
+        case I2C_SMBUS_BYTE:
+                size = HST_CNTL2_BYTE;
+                break;
+        case I2C_SMBUS_BYTE_DATA:
+                size = HST_CNTL2_BYTE_DATA;
+                break;
+        case I2C_SMBUS_WORD_DATA:
+                size = HST_CNTL2_WORD_DATA;
+                break;
+        case I2C_SMBUS_BLOCK_DATA:
+                size = HST_CNTL2_BLOCK;
+                break;
+        }
+
+        outb_p(((addr & 0x7f) << 1) | (rw & 0x01), SMB_HST_ADD);
+        outb_p(inb_p(SMB_HST_CNTL2) | (size << 3), SMB_HST_CNTL2);
+
+        /* Write the command register */
+        switch(size) {
+        case HST_CNTL2_BYTE:
+                if (rw== I2C_SMBUS_WRITE)
+                        outb_p(cmd, SMB_HST_CMD);
+                break;
+        case HST_CNTL2_BYTE_DATA:
+                outb_p(cmd, SMB_HST_CMD);
+                if (rw == I2C_SMBUS_WRITE)
+                        outb_p(data->byte, SMB_HST_DAT0);
+                break;
+        case HST_CNTL2_WORD_DATA:
+                outb_p(cmd, SMB_HST_CMD);
+                if (rw == I2C_SMBUS_WRITE) {
+                        outb_p(data->word & 0xff, SMB_HST_DAT0);
+                        outb_p((data->word & 0xff00) >> 8, SMB_HST_DAT1);
+                }
+                break;
+        case HST_CNTL2_BLOCK:
+                outb_p(cmd, SMB_HST_CMD);
+                error = ali1563_block(a,data,rw);
+                goto Done;
+        }
+
+        if ((error = ali1563_transaction(a)))
+                goto Done;
+
+        if ((rw == I2C_SMBUS_WRITE) || (size == HST_CNTL2_QUICK))
+                goto Done;
+
+        switch (size) {
+        case HST_CNTL2_BYTE:    /* Result put in SMBHSTDAT0 */
+                data->byte = inb_p(SMB_HST_DAT0);
+                break;
+        case HST_CNTL2_BYTE_DATA:
+                data->byte = inb_p(SMB_HST_DAT0);
+                break;
+        case HST_CNTL2_WORD_DATA:
+                data->word = inb_p(SMB_HST_DAT0) + (inb_p(SMB_HST_DAT1) << 8);
+                break;
+        }
+Done:
+        return error;
+}
+
+static u32 ali1563_func(struct i2c_adapter * a)
+{
+        return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
+            I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
+            I2C_FUNC_SMBUS_BLOCK_DATA;
+}
+
+
+static void ali1563_enable(struct pci_dev * dev)
+{
+        u16 ctrl;
+
+        pci_read_config_word(dev,ALI1563_SMBBA,&ctrl);
+        ctrl |= 0x7;
+        pci_write_config_word(dev,ALI1563_SMBBA,ctrl);
+}
+
+static int __devinit ali1563_setup(struct pci_dev * dev)
+{
+        u16 ctrl;
+
+        pci_read_config_word(dev,ALI1563_SMBBA,&ctrl);
+        printk("ali1563: SMBus control = %04x\n",ctrl);
+
+        /* Check if device is even enabled first */
+        if (!(ctrl & ALI1563_SMB_IOEN)) {
+                dev_warn(&dev->dev,"I/O space not enabled, trying manually\n");
+                ali1563_enable(dev);
+        }
+        if (!(ctrl & ALI1563_SMB_IOEN)) {
+                dev_warn(&dev->dev,"I/O space still not enabled, giving up\n");
+                goto Err;
+        }
+        if (!(ctrl & ALI1563_SMB_HOSTEN)) {
+                dev_warn(&dev->dev,"Host Controller not enabled\n");
+                goto Err;
+        }
+
+        /* SMB I/O Base in high 12 bits and must be aligned with the
+         * size of the I/O space. */
+        ali1563_smba = ctrl & ~(ALI1563_SMB_IOSIZE - 1);
+        if (!ali1563_smba) {
+                dev_warn(&dev->dev,"ali1563_smba Uninitialized\n");
+                goto Err;
+        }
+        if (!request_region(ali1563_smba,ALI1563_SMB_IOSIZE,"i2c-ali1563")) {
+                dev_warn(&dev->dev,"Could not allocate I/O space");
+                goto Err;
+        }
+
+        return 0;
+Err:
+        return -ENODEV;
+}
+
+static void ali1563_shutdown(struct pci_dev *dev)
+{
+        release_region(ali1563_smba,ALI1563_SMB_IOSIZE);
+}
+
+static struct i2c_algorithm ali1563_algorithm = {
+        .name           = "Non-i2c SMBus adapter",
+        .id             = I2C_ALGO_SMBUS,
+        .smbus_xfer     = ali1563_access,
+        .functionality  = ali1563_func,
+};
+
+static struct i2c_adapter ali1563_adapter = {
+        .owner  = THIS_MODULE,
+        .class  = I2C_CLASS_HWMON,
+        .algo   = &ali1563_algorithm,
+};
+
+static int __devinit ali1563_probe(struct pci_dev * dev,
+                                const struct pci_device_id * id_table)
+{
+        int error;
+
+        if ((error = ali1563_setup(dev)))
+                return error;
+        ali1563_adapter.dev.parent = &dev->dev;
+        sprintf(ali1563_adapter.name,"SMBus ALi 1563 Adapter @ %04x",
+                ali1563_smba);
+        if ((error = i2c_add_adapter(&ali1563_adapter)))
+                ali1563_shutdown(dev);
+        printk("%s: Returning %d\n",__FUNCTION__,error);
+        return error;
+}
+
+static void __devexit ali1563_remove(struct pci_dev * dev)
+{
+        i2c_del_adapter(&ali1563_adapter);
+        ali1563_shutdown(dev);
+}
+
+static struct pci_device_id __devinitdata ali1563_id_table[] = {
+        { PCI_DEVICE(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1563) },
+        {},
+};
+
+MODULE_DEVICE_TABLE (pci, ali1563_id_table);
+
+static struct pci_driver ali1563_pci_driver = {
+        .name           = "ali1563_i2c",
+        .id_table       = ali1563_id_table,
+        .probe          = ali1563_probe,
+        .remove         = __devexit_p(ali1563_remove),
+};
+
+static int __init ali1563_init(void)
+{
+        return pci_register_driver(&ali1563_pci_driver);
+}
+
+module_init(ali1563_init);
+
+static void __exit ali1563_exit(void)
+{
+        pci_unregister_driver(&ali1563_pci_driver);
+}
+
+module_exit(ali1563_exit);
+
+MODULE_LICENSE("GPL");
diff --git a/drivers/i2c/busses/i2c-ali15x3.c b/drivers/i2c/busses/i2c-ali15x3.c
new file mode 100644
index 000000000000..5bd6a4a77c1e
--- /dev/null
+++ b/drivers/i2c/busses/i2c-ali15x3.c
@@ -0,0 +1,532 @@
+/*
+    ali15x3.c - Part of lm_sensors, Linux kernel modules for hardware
+              monitoring
+    Copyright (c) 1999  Frodo Looijaard <frodol@dds.nl> and
+    Philip Edelbrock <phil@netroedge.com> and
+    Mark D. Studebaker <mdsxyz123@yahoo.com>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+/*
+    This is the driver for the SMB Host controller on
+    Acer Labs Inc. (ALI) M1541 and M1543C South Bridges.
+
+    The M1543C is a South bridge for desktop systems.
+    The M1533 is a South bridge for portable systems.
+    They are part of the following ALI chipsets:
+       "Aladdin Pro 2": Includes the M1621 Slot 1 North bridge
+       with AGP and 100MHz CPU Front Side bus
+       "Aladdin V": Includes the M1541 Socket 7 North bridge
+       with AGP and 100MHz CPU Front Side bus
+       "Aladdin IV": Includes the M1541 Socket 7 North bridge
+       with host bus up to 83.3 MHz.
+    For an overview of these chips see http://www.acerlabs.com
+
+    The M1533/M1543C devices appear as FOUR separate devices
+    on the PCI bus. An output of lspci will show something similar
+    to the following:
+
+        00:02.0 USB Controller: Acer Laboratories Inc. M5237
+        00:03.0 Bridge: Acer Laboratories Inc. M7101
+        00:07.0 ISA bridge: Acer Laboratories Inc. M1533
+        00:0f.0 IDE interface: Acer Laboratories Inc. M5229
+
+    The SMB controller is part of the 7101 device, which is an
+    ACPI-compliant Power Management Unit (PMU).
+
+    The whole 7101 device has to be enabled for the SMB to work.
+    You can't just enable the SMB alone.
+    The SMB and the ACPI have separate I/O spaces.
+    We make sure that the SMB is enabled. We leave the ACPI alone.
+
+    This driver controls the SMB Host only.
+    The SMB Slave controller on the M15X3 is not enabled.
+
+    This driver does not use interrupts.
+*/
+
+/* Note: we assume there can only be one ALI15X3, with one SMBus interface */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/stddef.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <asm/io.h>
+
+/* ALI15X3 SMBus address offsets */
+#define SMBHSTSTS       (0 + ali15x3_smba)
+#define SMBHSTCNT       (1 + ali15x3_smba)
+#define SMBHSTSTART     (2 + ali15x3_smba)
+#define SMBHSTCMD       (7 + ali15x3_smba)
+#define SMBHSTADD       (3 + ali15x3_smba)
+#define SMBHSTDAT0      (4 + ali15x3_smba)
+#define SMBHSTDAT1      (5 + ali15x3_smba)
+#define SMBBLKDAT       (6 + ali15x3_smba)
+
+/* PCI Address Constants */
+#define SMBCOM          0x004
+#define SMBBA           0x014
+#define SMBATPC         0x05B   /* used to unlock xxxBA registers */
+#define SMBHSTCFG       0x0E0
+#define SMBSLVC         0x0E1
+#define SMBCLK          0x0E2
+#define SMBREV          0x008
+
+/* Other settings */
+#define MAX_TIMEOUT             200     /* times 1/100 sec */
+#define ALI15X3_SMB_IOSIZE      32
+
+/* this is what the Award 1004 BIOS sets them to on a ASUS P5A MB.
+   We don't use these here. If the bases aren't set to some value we
+   tell user to upgrade BIOS and we fail.
+*/
+#define ALI15X3_SMB_DEFAULTBASE 0xE800
+
+/* ALI15X3 address lock bits */
+#define ALI15X3_LOCK            0x06
+
+/* ALI15X3 command constants */
+#define ALI15X3_ABORT           0x02
+#define ALI15X3_T_OUT           0x04
+#define ALI15X3_QUICK           0x00
+#define ALI15X3_BYTE            0x10
+#define ALI15X3_BYTE_DATA       0x20
+#define ALI15X3_WORD_DATA       0x30
+#define ALI15X3_BLOCK_DATA      0x40
+#define ALI15X3_BLOCK_CLR       0x80
+
+/* ALI15X3 status register bits */
+#define ALI15X3_STS_IDLE        0x04
+#define ALI15X3_STS_BUSY        0x08
+#define ALI15X3_STS_DONE        0x10
+#define ALI15X3_STS_DEV         0x20    /* device error */
+#define ALI15X3_STS_COLL        0x40    /* collision or no response */
+#define ALI15X3_STS_TERM        0x80    /* terminated by abort */
+#define ALI15X3_STS_ERR         0xE0    /* all the bad error bits */
+
+
+/* If force_addr is set to anything different from 0, we forcibly enable
+   the device at the given address. */
+static u16 force_addr = 0;
+module_param(force_addr, ushort, 0);
+MODULE_PARM_DESC(force_addr,
+                 "Initialize the base address of the i2c controller");
+
+static unsigned short ali15x3_smba = 0;
+
+static int ali15x3_setup(struct pci_dev *ALI15X3_dev)
+{
+        u16 a;
+        unsigned char temp;
+
+        /* Check the following things:
+                - SMB I/O address is initialized
+                - Device is enabled
+                - We can use the addresses
+        */
+
+        /* Unlock the register.
+           The data sheet says that the address registers are read-only
+           if the lock bits are 1, but in fact the address registers
+           are zero unless you clear the lock bits.
+        */
+        pci_read_config_byte(ALI15X3_dev, SMBATPC, &temp);
+        if (temp & ALI15X3_LOCK) {
+                temp &= ~ALI15X3_LOCK;
+                pci_write_config_byte(ALI15X3_dev, SMBATPC, temp);
+        }
+
+        /* Determine the address of the SMBus area */
+        pci_read_config_word(ALI15X3_dev, SMBBA, &ali15x3_smba);
+        ali15x3_smba &= (0xffff & ~(ALI15X3_SMB_IOSIZE - 1));
+        if (ali15x3_smba == 0 && force_addr == 0) {
+                dev_err(&ALI15X3_dev->dev, "ALI15X3_smb region uninitialized "
+                        "- upgrade BIOS or use force_addr=0xaddr\n");
+                return -ENODEV;
+        }
+
+        if(force_addr)
+                ali15x3_smba = force_addr & ~(ALI15X3_SMB_IOSIZE - 1);
+
+        if (!request_region(ali15x3_smba, ALI15X3_SMB_IOSIZE, "ali15x3-smb")) {
+                dev_err(&ALI15X3_dev->dev,
+                        "ALI15X3_smb region 0x%x already in use!\n",
+                        ali15x3_smba);
+                return -ENODEV;
+        }
+
+        if(force_addr) {
+                dev_info(&ALI15X3_dev->dev, "forcing ISA address 0x%04X\n",
+                        ali15x3_smba);
+                if (PCIBIOS_SUCCESSFUL != pci_write_config_word(ALI15X3_dev,
+                                                                SMBBA,
+                                                                ali15x3_smba))
+                        goto error;
+                if (PCIBIOS_SUCCESSFUL != pci_read_config_word(ALI15X3_dev,
+                                                                SMBBA, &a))
+                        goto error;
+                if ((a & ~(ALI15X3_SMB_IOSIZE - 1)) != ali15x3_smba) {
+                        /* make sure it works */
+                        dev_err(&ALI15X3_dev->dev,
+                                "force address failed - not supported?\n");
+                        goto error;
+                }
+        }
+        /* check if whole device is enabled */
+        pci_read_config_byte(ALI15X3_dev, SMBCOM, &temp);
+        if ((temp & 1) == 0) {
+                dev_info(&ALI15X3_dev->dev, "enabling SMBus device\n");
+                pci_write_config_byte(ALI15X3_dev, SMBCOM, temp | 0x01);
+        }
+
+        /* Is SMB Host controller enabled? */
+        pci_read_config_byte(ALI15X3_dev, SMBHSTCFG, &temp);
+        if ((temp & 1) == 0) {
+                dev_info(&ALI15X3_dev->dev, "enabling SMBus controller\n");
+                pci_write_config_byte(ALI15X3_dev, SMBHSTCFG, temp | 0x01);
+        }
+
+        /* set SMB clock to 74KHz as recommended in data sheet */
+        pci_write_config_byte(ALI15X3_dev, SMBCLK, 0x20);
+
+        /*
+          The interrupt routing for SMB is set up in register 0x77 in the
+          1533 ISA Bridge device, NOT in the 7101 device.
+          Don't bother with finding the 1533 device and reading the register.
+        if ((....... & 0x0F) == 1)
+                dev_dbg(&ALI15X3_dev->dev, "ALI15X3 using Interrupt 9 for SMBus.\n");
+        */
+        pci_read_config_byte(ALI15X3_dev, SMBREV, &temp);
+        dev_dbg(&ALI15X3_dev->dev, "SMBREV = 0x%X\n", temp);
+        dev_dbg(&ALI15X3_dev->dev, "iALI15X3_smba = 0x%X\n", ali15x3_smba);
+
+        return 0;
+error:
+        release_region(ali15x3_smba, ALI15X3_SMB_IOSIZE);
+        return -ENODEV;
+}
+
+/* Another internally used function */
+static int ali15x3_transaction(struct i2c_adapter *adap)
+{
+        int temp;
+        int result = 0;
+        int timeout = 0;
+
+        dev_dbg(&adap->dev, "Transaction (pre): STS=%02x, CNT=%02x, CMD=%02x, "
+                "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTSTS),
+                inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
+                inb_p(SMBHSTDAT0), inb_p(SMBHSTDAT1));
+
+        /* get status */
+        temp = inb_p(SMBHSTSTS);
+
+        /* Make sure the SMBus host is ready to start transmitting */
+        /* Check the busy bit first */
+        if (temp & ALI15X3_STS_BUSY) {
+        /*
+           If the host controller is still busy, it may have timed out in the
+           previous transaction, resulting in a "SMBus Timeout" Dev.
+           I've tried the following to reset a stuck busy bit.
+                1. Reset the controller with an ABORT command.
+                   (this doesn't seem to clear the controller if an external
+                   device is hung)
+                2. Reset the controller and the other SMBus devices with a
+                   T_OUT command.  (this clears the host busy bit if an
+                   external device is hung, but it comes back upon a new access
+                   to a device)
+                3. Disable and reenable the controller in SMBHSTCFG
+           Worst case, nothing seems to work except power reset.
+        */
+        /* Abort - reset the host controller */
+        /*
+           Try resetting entire SMB bus, including other devices -
+           This may not work either - it clears the BUSY bit but
+           then the BUSY bit may come back on when you try and use the chip again.
+           If that's the case you are stuck.
+        */
+                dev_info(&adap->dev, "Resetting entire SMB Bus to "
+                        "clear busy condition (%02x)\n", temp);
+                outb_p(ALI15X3_T_OUT, SMBHSTCNT);
+                temp = inb_p(SMBHSTSTS);
+        }
+
+        /* now check the error bits and the busy bit */
+        if (temp & (ALI15X3_STS_ERR | ALI15X3_STS_BUSY)) {
+                /* do a clear-on-write */
+                outb_p(0xFF, SMBHSTSTS);
+                if ((temp = inb_p(SMBHSTSTS)) &
+                    (ALI15X3_STS_ERR | ALI15X3_STS_BUSY)) {
+                        /* this is probably going to be correctable only by a power reset
+                           as one of the bits now appears to be stuck */
+                        /* This may be a bus or device with electrical problems. */
+                        dev_err(&adap->dev, "SMBus reset failed! (0x%02x) - "
+                                "controller or device on bus is probably hung\n",
+                                temp);
+                        return -1;
+                }
+        } else {
+                /* check and clear done bit */
+                if (temp & ALI15X3_STS_DONE) {
+                        outb_p(temp, SMBHSTSTS);
+                }
+        }
+
+        /* start the transaction by writing anything to the start register */
+        outb_p(0xFF, SMBHSTSTART);
+
+        /* We will always wait for a fraction of a second! */
+        timeout = 0;
+        do {
+                msleep(1);
+                temp = inb_p(SMBHSTSTS);
+        } while ((!(temp & (ALI15X3_STS_ERR | ALI15X3_STS_DONE)))
+                 && (timeout++ < MAX_TIMEOUT));
+
+        /* If the SMBus is still busy, we give up */
+        if (timeout >= MAX_TIMEOUT) {
+                result = -1;
+                dev_err(&adap->dev, "SMBus Timeout!\n");
+        }
+
+        if (temp & ALI15X3_STS_TERM) {
+                result = -1;
+                dev_dbg(&adap->dev, "Error: Failed bus transaction\n");
+        }
+
+        /*
+          Unfortunately the ALI SMB controller maps "no response" and "bus
+          collision" into a single bit. No reponse is the usual case so don't
+          do a printk.
+          This means that bus collisions go unreported.
+        */
+        if (temp & ALI15X3_STS_COLL) {
+                result = -1;
+                dev_dbg(&adap->dev,
+                        "Error: no response or bus collision ADD=%02x\n",
+                        inb_p(SMBHSTADD));
+        }
+
+        /* haven't ever seen this */
+        if (temp & ALI15X3_STS_DEV) {
+                result = -1;
+                dev_err(&adap->dev, "Error: device error\n");
+        }
+        dev_dbg(&adap->dev, "Transaction (post): STS=%02x, CNT=%02x, CMD=%02x, "
+                "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTSTS),
+                inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
+                inb_p(SMBHSTDAT0), inb_p(SMBHSTDAT1));
+        return result;
+}
+
+/* Return -1 on error. */
+static s32 ali15x3_access(struct i2c_adapter * adap, u16 addr,
+                   unsigned short flags, char read_write, u8 command,
+                   int size, union i2c_smbus_data * data)
+{
+        int i, len;
+        int temp;
+        int timeout;
+
+        /* clear all the bits (clear-on-write) */
+        outb_p(0xFF, SMBHSTSTS);
+        /* make sure SMBus is idle */
+        temp = inb_p(SMBHSTSTS);
+        for (timeout = 0;
+             (timeout < MAX_TIMEOUT) && !(temp & ALI15X3_STS_IDLE);
+             timeout++) {
+                msleep(1);
+                temp = inb_p(SMBHSTSTS);
+        }
+        if (timeout >= MAX_TIMEOUT) {
+                dev_err(&adap->dev, "Idle wait Timeout! STS=0x%02x\n", temp);
+        }
+
+        switch (size) {
+        case I2C_SMBUS_PROC_CALL:
+                dev_err(&adap->dev, "I2C_SMBUS_PROC_CALL not supported!\n");
+                return -1;
+        case I2C_SMBUS_QUICK:
+                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
+                       SMBHSTADD);
+                size = ALI15X3_QUICK;
+                break;
+        case I2C_SMBUS_BYTE:
+                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
+                       SMBHSTADD);
+                if (read_write == I2C_SMBUS_WRITE)
+                        outb_p(command, SMBHSTCMD);
+                size = ALI15X3_BYTE;
+                break;
+        case I2C_SMBUS_BYTE_DATA:
+                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
+                       SMBHSTADD);
+                outb_p(command, SMBHSTCMD);
+                if (read_write == I2C_SMBUS_WRITE)
+                        outb_p(data->byte, SMBHSTDAT0);
+                size = ALI15X3_BYTE_DATA;
+                break;
+        case I2C_SMBUS_WORD_DATA:
+                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
+                       SMBHSTADD);
+                outb_p(command, SMBHSTCMD);
+                if (read_write == I2C_SMBUS_WRITE) {
+                        outb_p(data->word & 0xff, SMBHSTDAT0);
+                        outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
+                }
+                size = ALI15X3_WORD_DATA;
+                break;
+        case I2C_SMBUS_BLOCK_DATA:
+                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
+                       SMBHSTADD);
+                outb_p(command, SMBHSTCMD);
+                if (read_write == I2C_SMBUS_WRITE) {
+                        len = data->block[0];
+                        if (len < 0) {
+                                len = 0;
+                                data->block[0] = len;
+                        }
+                        if (len > 32) {
+                                len = 32;
+                                data->block[0] = len;
+                        }
+                        outb_p(len, SMBHSTDAT0);
+                        /* Reset SMBBLKDAT */
+                        outb_p(inb_p(SMBHSTCNT) | ALI15X3_BLOCK_CLR, SMBHSTCNT);
+                        for (i = 1; i <= len; i++)
+                                outb_p(data->block[i], SMBBLKDAT);
+                }
+                size = ALI15X3_BLOCK_DATA;
+                break;
+        }
+
+        outb_p(size, SMBHSTCNT);        /* output command */
+
+        if (ali15x3_transaction(adap))  /* Error in transaction */
+                return -1;
+
+        if ((read_write == I2C_SMBUS_WRITE) || (size == ALI15X3_QUICK))
+                return 0;
+
+
+        switch (size) {
+        case ALI15X3_BYTE:      /* Result put in SMBHSTDAT0 */
+                data->byte = inb_p(SMBHSTDAT0);
+                break;
+        case ALI15X3_BYTE_DATA:
+                data->byte = inb_p(SMBHSTDAT0);
+                break;
+        case ALI15X3_WORD_DATA:
+                data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
+                break;
+        case ALI15X3_BLOCK_DATA:
+                len = inb_p(SMBHSTDAT0);
+                if (len > 32)
+                        len = 32;
+                data->block[0] = len;
+                /* Reset SMBBLKDAT */
+                outb_p(inb_p(SMBHSTCNT) | ALI15X3_BLOCK_CLR, SMBHSTCNT);
+                for (i = 1; i <= data->block[0]; i++) {
+                        data->block[i] = inb_p(SMBBLKDAT);
+                        dev_dbg(&adap->dev, "Blk: len=%d, i=%d, data=%02x\n",
+                                len, i, data->block[i]);
+                }
+                break;
+        }
+        return 0;
+}
+
+static u32 ali15x3_func(struct i2c_adapter *adapter)
+{
+        return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
+            I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
+            I2C_FUNC_SMBUS_BLOCK_DATA;
+}
+
+static struct i2c_algorithm smbus_algorithm = {
+        .name           = "Non-I2C SMBus adapter",
+        .id             = I2C_ALGO_SMBUS,
+        .smbus_xfer     = ali15x3_access,
+        .functionality  = ali15x3_func,
+};
+
+static struct i2c_adapter ali15x3_adapter = {
+        .owner          = THIS_MODULE,
+        .class          = I2C_CLASS_HWMON,
+        .algo           = &smbus_algorithm,
+        .name           = "unset",
+};
+
+static struct pci_device_id ali15x3_ids[] = {
+        { PCI_DEVICE(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101) },
+        { 0, }
+};
+
+MODULE_DEVICE_TABLE (pci, ali15x3_ids);
+
+static int __devinit ali15x3_probe(struct pci_dev *dev, const struct pci_device_id *id)
+{
+        if (ali15x3_setup(dev)) {
+                dev_err(&dev->dev,
+                        "ALI15X3 not detected, module not inserted.\n");
+                return -ENODEV;
+        }
+
+        /* set up the driverfs linkage to our parent device */
+        ali15x3_adapter.dev.parent = &dev->dev;
+
+        snprintf(ali15x3_adapter.name, I2C_NAME_SIZE,
+                "SMBus ALI15X3 adapter at %04x", ali15x3_smba);
+        return i2c_add_adapter(&ali15x3_adapter);
+}
+
+static void __devexit ali15x3_remove(struct pci_dev *dev)
+{
+        i2c_del_adapter(&ali15x3_adapter);
+        release_region(ali15x3_smba, ALI15X3_SMB_IOSIZE);
+}
+
+static struct pci_driver ali15x3_driver = {
+        .name           = "ali15x3_smbus",
+        .id_table       = ali15x3_ids,
+        .probe          = ali15x3_probe,
+        .remove         = __devexit_p(ali15x3_remove),
+};
+
+static int __init i2c_ali15x3_init(void)
+{
+        return pci_register_driver(&ali15x3_driver);
+}
+
+static void __exit i2c_ali15x3_exit(void)
+{
+        pci_unregister_driver(&ali15x3_driver);
+}
+
+MODULE_AUTHOR ("Frodo Looijaard <frodol@dds.nl>, "
+                "Philip Edelbrock <phil@netroedge.com>, "
+                "and Mark D. Studebaker <mdsxyz123@yahoo.com>");
+MODULE_DESCRIPTION("ALI15X3 SMBus driver");
+MODULE_LICENSE("GPL");
+
+module_init(i2c_ali15x3_init);
+module_exit(i2c_ali15x3_exit);
diff --git a/drivers/i2c/busses/i2c-amd756-s4882.c b/drivers/i2c/busses/i2c-amd756-s4882.c
new file mode 100644
index 000000000000..4e553e8c5cba
--- /dev/null
+++ b/drivers/i2c/busses/i2c-amd756-s4882.c
@@ -0,0 +1,264 @@
+/*
+ * i2c-amd756-s4882.c - i2c-amd756 extras for the Tyan S4882 motherboard
+ *
+ * Copyright (C) 2004 Jean Delvare <khali@linux-fr.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+ 
+/*
+ * We select the channels by sending commands to the Philips
+ * PCA9556 chip at I2C address 0x18. The main adapter is used for
+ * the non-multiplexed part of the bus, and 4 virtual adapters
+ * are defined for the multiplexed addresses: 0x50-0x53 (memory
+ * module EEPROM) located on channels 1-4, and 0x4c (LM63)
+ * located on multiplexed channels 0 and 5-7. We define one
+ * virtual adapter per CPU, which corresponds to two multiplexed
+ * channels:
+ *   CPU0: virtual adapter 1, channels 1 and 0
+ *   CPU1: virtual adapter 2, channels 2 and 5
+ *   CPU2: virtual adapter 3, channels 3 and 6
+ *   CPU3: virtual adapter 4, channels 4 and 7
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+
+extern struct i2c_adapter amd756_smbus;
+
+static struct i2c_adapter *s4882_adapter;
+static struct i2c_algorithm *s4882_algo;
+
+/* Wrapper access functions for multiplexed SMBus */
+static struct semaphore amd756_lock;
+
+static s32 amd756_access_virt0(struct i2c_adapter * adap, u16 addr,
+                               unsigned short flags, char read_write,
+                               u8 command, int size,
+                               union i2c_smbus_data * data)
+{
+        int error;
+
+        /* We exclude the multiplexed addresses */
+        if (addr == 0x4c || (addr & 0xfc) == 0x50 || (addr & 0xfc) == 0x30
+         || addr == 0x18)
+                return -1;
+
+        down(&amd756_lock);
+
+        error = amd756_smbus.algo->smbus_xfer(adap, addr, flags, read_write,
+                                              command, size, data);
+
+        up(&amd756_lock);
+
+        return error;
+}
+
+/* We remember the last used channels combination so as to only switch
+   channels when it is really needed. This greatly reduces the SMBus
+   overhead, but also assumes that nobody will be writing to the PCA9556
+   in our back. */
+static u8 last_channels;
+
+static inline s32 amd756_access_channel(struct i2c_adapter * adap, u16 addr,
+                                        unsigned short flags, char read_write,
+                                        u8 command, int size,
+                                        union i2c_smbus_data * data,
+                                        u8 channels)
+{
+        int error;
+
+        /* We exclude the non-multiplexed addresses */
+        if (addr != 0x4c && (addr & 0xfc) != 0x50 && (addr & 0xfc) != 0x30)
+                return -1;
+
+        down(&amd756_lock);
+
+        if (last_channels != channels) {
+                union i2c_smbus_data mplxdata;
+                mplxdata.byte = channels;
+
+                error = amd756_smbus.algo->smbus_xfer(adap, 0x18, 0,
+                                                      I2C_SMBUS_WRITE, 0x01,
+                                                      I2C_SMBUS_BYTE_DATA,
+                                                      &mplxdata);
+                if (error)
+                        goto UNLOCK;
+                last_channels = channels;
+        }
+        error = amd756_smbus.algo->smbus_xfer(adap, addr, flags, read_write,
+                                              command, size, data);
+
+UNLOCK:
+        up(&amd756_lock);
+        return error;
+}
+
+static s32 amd756_access_virt1(struct i2c_adapter * adap, u16 addr,
+                               unsigned short flags, char read_write,
+                               u8 command, int size,
+                               union i2c_smbus_data * data)
+{
+        /* CPU0: channels 1 and 0 enabled */
+        return amd756_access_channel(adap, addr, flags, read_write, command,
+                                     size, data, 0x03);
+}
+
+static s32 amd756_access_virt2(struct i2c_adapter * adap, u16 addr,
+                               unsigned short flags, char read_write,
+                               u8 command, int size,
+                               union i2c_smbus_data * data)
+{
+        /* CPU1: channels 2 and 5 enabled */
+        return amd756_access_channel(adap, addr, flags, read_write, command,
+                                     size, data, 0x24);
+}
+
+static s32 amd756_access_virt3(struct i2c_adapter * adap, u16 addr,
+                               unsigned short flags, char read_write,
+                               u8 command, int size,
+                               union i2c_smbus_data * data)
+{
+        /* CPU2: channels 3 and 6 enabled */
+        return amd756_access_channel(adap, addr, flags, read_write, command,
+                                     size, data, 0x48);
+}
+
+static s32 amd756_access_virt4(struct i2c_adapter * adap, u16 addr,
+                               unsigned short flags, char read_write,
+                               u8 command, int size,
+                               union i2c_smbus_data * data)
+{
+        /* CPU3: channels 4 and 7 enabled */
+        return amd756_access_channel(adap, addr, flags, read_write, command,
+                                     size, data, 0x90);
+}
+
+static int __init amd756_s4882_init(void)
+{
+        int i, error;
+        union i2c_smbus_data ioconfig;
+
+        /* Unregister physical bus */
+        error = i2c_del_adapter(&amd756_smbus);
+        if (error) {
+                if (error == -EINVAL)
+                        error = -ENODEV;
+                else
+                        dev_err(&amd756_smbus.dev, "Physical bus removal "
+                                "failed\n");
+                goto ERROR0;
+        }
+
+        printk(KERN_INFO "Enabling SMBus multiplexing for Tyan S4882\n");
+        init_MUTEX(&amd756_lock);
+
+        /* Define the 5 virtual adapters and algorithms structures */
+        if (!(s4882_adapter = kmalloc(5 * sizeof(struct i2c_adapter),
+                                      GFP_KERNEL))) {
+                error = -ENOMEM;
+                goto ERROR1;
+        }
+        if (!(s4882_algo = kmalloc(5 * sizeof(struct i2c_algorithm),
+                                   GFP_KERNEL))) {
+                error = -ENOMEM;
+                goto ERROR2;
+        }
+
+        /* Fill in the new structures */
+        s4882_algo[0] = *(amd756_smbus.algo);
+        s4882_algo[0].smbus_xfer = amd756_access_virt0;
+        s4882_adapter[0] = amd756_smbus;
+        s4882_adapter[0].algo = s4882_algo;
+        for (i = 1; i < 5; i++) {
+                s4882_algo[i] = *(amd756_smbus.algo);
+                s4882_adapter[i] = amd756_smbus;
+                sprintf(s4882_adapter[i].name,
+                        "SMBus 8111 adapter (CPU%d)", i-1);
+                s4882_adapter[i].algo = s4882_algo+i;
+        }
+        s4882_algo[1].smbus_xfer = amd756_access_virt1;
+        s4882_algo[2].smbus_xfer = amd756_access_virt2;
+        s4882_algo[3].smbus_xfer = amd756_access_virt3;
+        s4882_algo[4].smbus_xfer = amd756_access_virt4;
+
+        /* Configure the PCA9556 multiplexer */
+        ioconfig.byte = 0x00; /* All I/O to output mode */
+        error = amd756_smbus.algo->smbus_xfer(&amd756_smbus, 0x18, 0,
+                                              I2C_SMBUS_WRITE, 0x03,
+                                              I2C_SMBUS_BYTE_DATA, &ioconfig);
+        if (error) {
+                dev_err(&amd756_smbus.dev, "PCA9556 configuration failed\n");
+                error = -EIO;
+                goto ERROR3;
+        }
+
+        /* Register virtual adapters */
+        for (i = 0; i < 5; i++) {
+                error = i2c_add_adapter(s4882_adapter+i);
+                if (error) {
+                        dev_err(&amd756_smbus.dev,
+                               "Virtual adapter %d registration "
+                               "failed, module not inserted\n", i);
+                        for (i--; i >= 0; i--)
+                                i2c_del_adapter(s4882_adapter+i);
+                        goto ERROR3;
+                }
+        }
+
+        return 0;
+
+ERROR3:
+        kfree(s4882_algo);
+        s4882_algo = NULL;
+ERROR2:
+        kfree(s4882_adapter);
+        s4882_adapter = NULL;
+ERROR1:
+        i2c_del_adapter(&amd756_smbus);
+ERROR0:
+        return error;
+}
+
+static void __exit amd756_s4882_exit(void)
+{
+        if (s4882_adapter) {
+                int i;
+
+                for (i = 0; i < 5; i++)
+                        i2c_del_adapter(s4882_adapter+i);
+                kfree(s4882_adapter);
+                s4882_adapter = NULL;
+        }
+        if (s4882_algo) {
+                kfree(s4882_algo);
+                s4882_algo = NULL;
+        }
+
+        /* Restore physical bus */
+        if (i2c_add_adapter(&amd756_smbus))
+                dev_err(&amd756_smbus.dev, "Physical bus restoration "
+                        "failed\n");
+}
+
+MODULE_AUTHOR("Jean Delvare <khali@linux-fr.org>");
+MODULE_DESCRIPTION("S4882 SMBus multiplexing");
+MODULE_LICENSE("GPL");
+
+module_init(amd756_s4882_init);
+module_exit(amd756_s4882_exit);
diff --git a/drivers/i2c/busses/i2c-amd756.c b/drivers/i2c/busses/i2c-amd756.c
new file mode 100644
index 000000000000..eca5ed3738b8
--- /dev/null
+++ b/drivers/i2c/busses/i2c-amd756.c
@@ -0,0 +1,431 @@
+/*
+    amd756.c - Part of lm_sensors, Linux kernel modules for hardware
+              monitoring
+
+    Copyright (c) 1999-2002 Merlin Hughes <merlin@merlin.org>
+
+    Shamelessly ripped from i2c-piix4.c:
+
+    Copyright (c) 1998, 1999  Frodo Looijaard <frodol@dds.nl> and
+    Philip Edelbrock <phil@netroedge.com>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+/*
+    2002-04-08: Added nForce support. (Csaba Halasz)
+    2002-10-03: Fixed nForce PnP I/O port. (Michael Steil)
+    2002-12-28: Rewritten into something that resembles a Linux driver (hch)
+    2003-11-29: Added back AMD8111 removed by the previous rewrite.
+                (Philip Pokorny)
+*/
+
+/*
+   Supports AMD756, AMD766, AMD768, AMD8111 and nVidia nForce
+   Note: we assume there can only be one device, with one SMBus interface.
+*/
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/stddef.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <asm/io.h>
+
+/* AMD756 SMBus address offsets */
+#define SMB_ADDR_OFFSET         0xE0
+#define SMB_IOSIZE              16
+#define SMB_GLOBAL_STATUS       (0x0 + amd756_ioport)
+#define SMB_GLOBAL_ENABLE       (0x2 + amd756_ioport)
+#define SMB_HOST_ADDRESS        (0x4 + amd756_ioport)
+#define SMB_HOST_DATA           (0x6 + amd756_ioport)
+#define SMB_HOST_COMMAND        (0x8 + amd756_ioport)
+#define SMB_HOST_BLOCK_DATA     (0x9 + amd756_ioport)
+#define SMB_HAS_DATA            (0xA + amd756_ioport)
+#define SMB_HAS_DEVICE_ADDRESS  (0xC + amd756_ioport)
+#define SMB_HAS_HOST_ADDRESS    (0xE + amd756_ioport)
+#define SMB_SNOOP_ADDRESS       (0xF + amd756_ioport)
+
+/* PCI Address Constants */
+
+/* address of I/O space */
+#define SMBBA           0x058           /* mh */
+#define SMBBANFORCE     0x014
+
+/* general configuration */
+#define SMBGCFG         0x041           /* mh */
+
+/* silicon revision code */
+#define SMBREV          0x008
+
+/* Other settings */
+#define MAX_TIMEOUT     500
+
+/* AMD756 constants */
+#define AMD756_QUICK            0x00
+#define AMD756_BYTE             0x01
+#define AMD756_BYTE_DATA        0x02
+#define AMD756_WORD_DATA        0x03
+#define AMD756_PROCESS_CALL     0x04
+#define AMD756_BLOCK_DATA       0x05
+
+
+static unsigned short amd756_ioport = 0;
+
+/* 
+  SMBUS event = I/O 28-29 bit 11
+     see E0 for the status bits and enabled in E2
+     
+*/
+#define GS_ABRT_STS     (1 << 0)
+#define GS_COL_STS      (1 << 1)
+#define GS_PRERR_STS    (1 << 2)
+#define GS_HST_STS      (1 << 3)
+#define GS_HCYC_STS     (1 << 4)
+#define GS_TO_STS       (1 << 5)
+#define GS_SMB_STS      (1 << 11)
+
+#define GS_CLEAR_STS    (GS_ABRT_STS | GS_COL_STS | GS_PRERR_STS | \
+                         GS_HCYC_STS | GS_TO_STS )
+
+#define GE_CYC_TYPE_MASK        (7)
+#define GE_HOST_STC             (1 << 3)
+#define GE_ABORT                (1 << 5)
+
+
+static int amd756_transaction(struct i2c_adapter *adap)
+{
+        int temp;
+        int result = 0;
+        int timeout = 0;
+
+        dev_dbg(&adap->dev, "Transaction (pre): GS=%04x, GE=%04x, ADD=%04x, "
+                "DAT=%04x\n", inw_p(SMB_GLOBAL_STATUS),
+                inw_p(SMB_GLOBAL_ENABLE), inw_p(SMB_HOST_ADDRESS),
+                inb_p(SMB_HOST_DATA));
+
+        /* Make sure the SMBus host is ready to start transmitting */
+        if ((temp = inw_p(SMB_GLOBAL_STATUS)) & (GS_HST_STS | GS_SMB_STS)) {
+                dev_dbg(&adap->dev, "SMBus busy (%04x). Waiting...\n", temp);
+                do {
+                        msleep(1);
+                        temp = inw_p(SMB_GLOBAL_STATUS);
+                } while ((temp & (GS_HST_STS | GS_SMB_STS)) &&
+                         (timeout++ < MAX_TIMEOUT));
+                /* If the SMBus is still busy, we give up */
+                if (timeout >= MAX_TIMEOUT) {
+                        dev_dbg(&adap->dev, "Busy wait timeout (%04x)\n", temp);
+                        goto abort;
+                }
+                timeout = 0;
+        }
+
+        /* start the transaction by setting the start bit */
+        outw_p(inw(SMB_GLOBAL_ENABLE) | GE_HOST_STC, SMB_GLOBAL_ENABLE);
+
+        /* We will always wait for a fraction of a second! */
+        do {
+                msleep(1);
+                temp = inw_p(SMB_GLOBAL_STATUS);
+        } while ((temp & GS_HST_STS) && (timeout++ < MAX_TIMEOUT));
+
+        /* If the SMBus is still busy, we give up */
+        if (timeout >= MAX_TIMEOUT) {
+                dev_dbg(&adap->dev, "Completion timeout!\n");
+                goto abort;
+        }
+
+        if (temp & GS_PRERR_STS) {
+                result = -1;
+                dev_dbg(&adap->dev, "SMBus Protocol error (no response)!\n");
+        }
+
+        if (temp & GS_COL_STS) {
+                result = -1;
+                dev_warn(&adap->dev, "SMBus collision!\n");
+        }
+
+        if (temp & GS_TO_STS) {
+                result = -1;
+                dev_dbg(&adap->dev, "SMBus protocol timeout!\n");
+        }
+
+        if (temp & GS_HCYC_STS)
+                dev_dbg(&adap->dev, "SMBus protocol success!\n");
+
+        outw_p(GS_CLEAR_STS, SMB_GLOBAL_STATUS);
+
+#ifdef DEBUG
+        if (((temp = inw_p(SMB_GLOBAL_STATUS)) & GS_CLEAR_STS) != 0x00) {
+                dev_dbg(&adap->dev,
+                        "Failed reset at end of transaction (%04x)\n", temp);
+        }
+#endif
+
+        dev_dbg(&adap->dev,
+                "Transaction (post): GS=%04x, GE=%04x, ADD=%04x, DAT=%04x\n",
+                inw_p(SMB_GLOBAL_STATUS), inw_p(SMB_GLOBAL_ENABLE),
+                inw_p(SMB_HOST_ADDRESS), inb_p(SMB_HOST_DATA));
+
+        return result;
+
+ abort:
+        dev_warn(&adap->dev, "Sending abort\n");
+        outw_p(inw(SMB_GLOBAL_ENABLE) | GE_ABORT, SMB_GLOBAL_ENABLE);
+        msleep(100);
+        outw_p(GS_CLEAR_STS, SMB_GLOBAL_STATUS);
+        return -1;
+}
+
+/* Return -1 on error. */
+static s32 amd756_access(struct i2c_adapter * adap, u16 addr,
+                  unsigned short flags, char read_write,
+                  u8 command, int size, union i2c_smbus_data * data)
+{
+        int i, len;
+
+        /** TODO: Should I supporte the 10-bit transfers? */
+        switch (size) {
+        case I2C_SMBUS_PROC_CALL:
+                dev_dbg(&adap->dev, "I2C_SMBUS_PROC_CALL not supported!\n");
+                /* TODO: Well... It is supported, I'm just not sure what to do here... */
+                return -1;
+        case I2C_SMBUS_QUICK:
+                outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
+                       SMB_HOST_ADDRESS);
+                size = AMD756_QUICK;
+                break;
+        case I2C_SMBUS_BYTE:
+                outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
+                       SMB_HOST_ADDRESS);
+                if (read_write == I2C_SMBUS_WRITE)
+                        outb_p(command, SMB_HOST_DATA);
+                size = AMD756_BYTE;
+                break;
+        case I2C_SMBUS_BYTE_DATA:
+                outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
+                       SMB_HOST_ADDRESS);
+                outb_p(command, SMB_HOST_COMMAND);
+                if (read_write == I2C_SMBUS_WRITE)
+                        outw_p(data->byte, SMB_HOST_DATA);
+                size = AMD756_BYTE_DATA;
+                break;
+        case I2C_SMBUS_WORD_DATA:
+                outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
+                       SMB_HOST_ADDRESS);
+                outb_p(command, SMB_HOST_COMMAND);
+                if (read_write == I2C_SMBUS_WRITE)
+                        outw_p(data->word, SMB_HOST_DATA);      /* TODO: endian???? */
+                size = AMD756_WORD_DATA;
+                break;
+        case I2C_SMBUS_BLOCK_DATA:
+                outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
+                       SMB_HOST_ADDRESS);
+                outb_p(command, SMB_HOST_COMMAND);
+                if (read_write == I2C_SMBUS_WRITE) {
+                        len = data->block[0];
+                        if (len < 0)
+                                len = 0;
+                        if (len > 32)
+                                len = 32;
+                        outw_p(len, SMB_HOST_DATA);
+                        /* i = inw_p(SMBHSTCNT); Reset SMBBLKDAT */
+                        for (i = 1; i <= len; i++)
+                                outb_p(data->block[i],
+                                       SMB_HOST_BLOCK_DATA);
+                }
+                size = AMD756_BLOCK_DATA;
+                break;
+        }
+
+        /* How about enabling interrupts... */
+        outw_p(size & GE_CYC_TYPE_MASK, SMB_GLOBAL_ENABLE);
+
+        if (amd756_transaction(adap))   /* Error in transaction */
+                return -1;
+
+        if ((read_write == I2C_SMBUS_WRITE) || (size == AMD756_QUICK))
+                return 0;
+
+
+        switch (size) {
+        case AMD756_BYTE:
+                data->byte = inw_p(SMB_HOST_DATA);
+                break;
+        case AMD756_BYTE_DATA:
+                data->byte = inw_p(SMB_HOST_DATA);
+                break;
+        case AMD756_WORD_DATA:
+                data->word = inw_p(SMB_HOST_DATA);      /* TODO: endian???? */
+                break;
+        case AMD756_BLOCK_DATA:
+                data->block[0] = inw_p(SMB_HOST_DATA) & 0x3f;
+                if(data->block[0] > 32)
+                        data->block[0] = 32;
+                /* i = inw_p(SMBHSTCNT); Reset SMBBLKDAT */
+                for (i = 1; i <= data->block[0]; i++)
+                        data->block[i] = inb_p(SMB_HOST_BLOCK_DATA);
+                break;
+        }
+
+        return 0;
+}
+
+static u32 amd756_func(struct i2c_adapter *adapter)
+{
+        return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
+            I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
+            I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL;
+}
+
+static struct i2c_algorithm smbus_algorithm = {
+        .name           = "Non-I2C SMBus adapter",
+        .id             = I2C_ALGO_SMBUS,
+        .smbus_xfer     = amd756_access,
+        .functionality  = amd756_func,
+};
+
+struct i2c_adapter amd756_smbus = {
+        .owner          = THIS_MODULE,
+        .class          = I2C_CLASS_HWMON,
+        .algo           = &smbus_algorithm,
+        .name           = "unset",
+};
+
+enum chiptype { AMD756, AMD766, AMD768, NFORCE, AMD8111 };
+static const char* chipname[] = {
+        "AMD756", "AMD766", "AMD768",
+        "nVidia nForce", "AMD8111",
+};
+
+static struct pci_device_id amd756_ids[] = {
+        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_740B),
+          .driver_data = AMD756 },
+        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7413),
+          .driver_data = AMD766 },
+        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_OPUS_7443),
+          .driver_data = AMD768 },
+        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS),
+          .driver_data = AMD8111 },
+        { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_SMBUS),
+          .driver_data = NFORCE },
+        { 0, }
+};
+
+MODULE_DEVICE_TABLE (pci, amd756_ids);
+
+static int __devinit amd756_probe(struct pci_dev *pdev,
+                                  const struct pci_device_id *id)
+{
+        int nforce = (id->driver_data == NFORCE);
+        int error;
+        u8 temp;
+        
+        if (amd756_ioport) {
+                dev_err(&pdev->dev, "Only one device supported "
+                       "(you have a strange motherboard, btw)\n");
+                return -ENODEV;
+        }
+
+        if (nforce) {
+                if (PCI_FUNC(pdev->devfn) != 1)
+                        return -ENODEV;
+
+                pci_read_config_word(pdev, SMBBANFORCE, &amd756_ioport);
+                amd756_ioport &= 0xfffc;
+        } else { /* amd */
+                if (PCI_FUNC(pdev->devfn) != 3)
+                        return -ENODEV;
+
+                pci_read_config_byte(pdev, SMBGCFG, &temp);
+                if ((temp & 128) == 0) {
+                        dev_err(&pdev->dev,
+                                "Error: SMBus controller I/O not enabled!\n");
+                        return -ENODEV;
+                }
+
+                /* Determine the address of the SMBus areas */
+                /* Technically it is a dword but... */
+                pci_read_config_word(pdev, SMBBA, &amd756_ioport);
+                amd756_ioport &= 0xff00;
+                amd756_ioport += SMB_ADDR_OFFSET;
+        }
+
+        if (!request_region(amd756_ioport, SMB_IOSIZE, "amd756-smbus")) {
+                dev_err(&pdev->dev, "SMB region 0x%x already in use!\n",
+                        amd756_ioport);
+                return -ENODEV;
+        }
+
+        pci_read_config_byte(pdev, SMBREV, &temp);
+        dev_dbg(&pdev->dev, "SMBREV = 0x%X\n", temp);
+        dev_dbg(&pdev->dev, "AMD756_smba = 0x%X\n", amd756_ioport);
+
+        /* set up the driverfs linkage to our parent device */
+        amd756_smbus.dev.parent = &pdev->dev;
+
+        sprintf(amd756_smbus.name, "SMBus %s adapter at %04x",
+                chipname[id->driver_data], amd756_ioport);
+
+        error = i2c_add_adapter(&amd756_smbus);
+        if (error) {
+                dev_err(&pdev->dev,
+                        "Adapter registration failed, module not inserted\n");
+                goto out_err;
+        }
+
+        return 0;
+
+ out_err:
+        release_region(amd756_ioport, SMB_IOSIZE);
+        return error;
+}
+
+static void __devexit amd756_remove(struct pci_dev *dev)
+{
+        i2c_del_adapter(&amd756_smbus);
+        release_region(amd756_ioport, SMB_IOSIZE);
+}
+
+static struct pci_driver amd756_driver = {
+        .name           = "amd756_smbus",
+        .id_table       = amd756_ids,
+        .probe          = amd756_probe,
+        .remove         = __devexit_p(amd756_remove),
+};
+
+static int __init amd756_init(void)
+{
+        return pci_register_driver(&amd756_driver);
+}
+
+static void __exit amd756_exit(void)
+{
+        pci_unregister_driver(&amd756_driver);
+}
+
+MODULE_AUTHOR("Merlin Hughes <merlin@merlin.org>");
+MODULE_DESCRIPTION("AMD756/766/768/8111 and nVidia nForce SMBus driver");
+MODULE_LICENSE("GPL");
+
+EXPORT_SYMBOL(amd756_smbus);
+
+module_init(amd756_init)
+module_exit(amd756_exit)
diff --git a/drivers/i2c/busses/i2c-amd8111.c b/drivers/i2c/busses/i2c-amd8111.c
new file mode 100644
index 000000000000..af22b401a38b
--- /dev/null
+++ b/drivers/i2c/busses/i2c-amd8111.c
@@ -0,0 +1,415 @@
+/*
+ * SMBus 2.0 driver for AMD-8111 IO-Hub.
+ *
+ * Copyright (c) 2002 Vojtech Pavlik
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation version 2.
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/stddef.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR ("Vojtech Pavlik <vojtech@suse.cz>");
+MODULE_DESCRIPTION("AMD8111 SMBus 2.0 driver");
+
+struct amd_smbus {
+        struct pci_dev *dev;
+        struct i2c_adapter adapter;
+        int base;
+        int size;
+};
+
+/*
+ * AMD PCI control registers definitions.
+ */
+
+#define AMD_PCI_MISC    0x48
+
+#define AMD_PCI_MISC_SCI        0x04    /* deliver SCI */
+#define AMD_PCI_MISC_INT        0x02    /* deliver PCI IRQ */
+#define AMD_PCI_MISC_SPEEDUP    0x01    /* 16x clock speedup */
+
+/*
+ * ACPI 2.0 chapter 13 PCI interface definitions.
+ */
+
+#define AMD_EC_DATA     0x00    /* data register */
+#define AMD_EC_SC       0x04    /* status of controller */
+#define AMD_EC_CMD      0x04    /* command register */
+#define AMD_EC_ICR      0x08    /* interrupt control register */
+
+#define AMD_EC_SC_SMI   0x04    /* smi event pending */
+#define AMD_EC_SC_SCI   0x02    /* sci event pending */
+#define AMD_EC_SC_BURST 0x01    /* burst mode enabled */
+#define AMD_EC_SC_CMD   0x08    /* byte in data reg is command */
+#define AMD_EC_SC_IBF   0x02    /* data ready for embedded controller */
+#define AMD_EC_SC_OBF   0x01    /* data ready for host */
+
+#define AMD_EC_CMD_RD   0x80    /* read EC */
+#define AMD_EC_CMD_WR   0x81    /* write EC */
+#define AMD_EC_CMD_BE   0x82    /* enable burst mode */
+#define AMD_EC_CMD_BD   0x83    /* disable burst mode */
+#define AMD_EC_CMD_QR   0x84    /* query EC */
+
+/*
+ * ACPI 2.0 chapter 13 access of registers of the EC
+ */
+
+static unsigned int amd_ec_wait_write(struct amd_smbus *smbus)
+{
+        int timeout = 500;
+
+        while (timeout-- && (inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_IBF))
+                udelay(1);
+
+        if (!timeout) {
+                dev_warn(&smbus->dev->dev, "Timeout while waiting for IBF to clear\n");
+                return -1;
+        }
+
+        return 0;
+}
+
+static unsigned int amd_ec_wait_read(struct amd_smbus *smbus)
+{
+        int timeout = 500;
+
+        while (timeout-- && (~inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_OBF))
+                udelay(1);
+
+        if (!timeout) {
+                dev_warn(&smbus->dev->dev, "Timeout while waiting for OBF to set\n");
+                return -1;
+        }
+
+        return 0;
+}
+
+static unsigned int amd_ec_read(struct amd_smbus *smbus, unsigned char address, unsigned char *data)
+{
+        if (amd_ec_wait_write(smbus))
+                return -1;
+        outb(AMD_EC_CMD_RD, smbus->base + AMD_EC_CMD);
+
+        if (amd_ec_wait_write(smbus))
+                return -1;
+        outb(address, smbus->base + AMD_EC_DATA);
+
+        if (amd_ec_wait_read(smbus))
+                return -1;
+        *data = inb(smbus->base + AMD_EC_DATA);
+
+        return 0;
+}
+
+static unsigned int amd_ec_write(struct amd_smbus *smbus, unsigned char address, unsigned char data)
+{
+        if (amd_ec_wait_write(smbus))
+                return -1;
+        outb(AMD_EC_CMD_WR, smbus->base + AMD_EC_CMD);
+
+        if (amd_ec_wait_write(smbus))
+                return -1;
+        outb(address, smbus->base + AMD_EC_DATA);
+
+        if (amd_ec_wait_write(smbus))
+                return -1;
+        outb(data, smbus->base + AMD_EC_DATA);
+
+        return 0;
+}
+
+/*
+ * ACPI 2.0 chapter 13 SMBus 2.0 EC register model
+ */
+
+#define AMD_SMB_PRTCL   0x00    /* protocol, PEC */
+#define AMD_SMB_STS     0x01    /* status */
+#define AMD_SMB_ADDR    0x02    /* address */
+#define AMD_SMB_CMD     0x03    /* command */
+#define AMD_SMB_DATA    0x04    /* 32 data registers */
+#define AMD_SMB_BCNT    0x24    /* number of data bytes */
+#define AMD_SMB_ALRM_A  0x25    /* alarm address */
+#define AMD_SMB_ALRM_D  0x26    /* 2 bytes alarm data */
+
+#define AMD_SMB_STS_DONE        0x80
+#define AMD_SMB_STS_ALRM        0x40
+#define AMD_SMB_STS_RES         0x20
+#define AMD_SMB_STS_STATUS      0x1f
+
+#define AMD_SMB_STATUS_OK       0x00
+#define AMD_SMB_STATUS_FAIL     0x07
+#define AMD_SMB_STATUS_DNAK     0x10
+#define AMD_SMB_STATUS_DERR     0x11
+#define AMD_SMB_STATUS_CMD_DENY 0x12
+#define AMD_SMB_STATUS_UNKNOWN  0x13
+#define AMD_SMB_STATUS_ACC_DENY 0x17
+#define AMD_SMB_STATUS_TIMEOUT  0x18
+#define AMD_SMB_STATUS_NOTSUP   0x19
+#define AMD_SMB_STATUS_BUSY     0x1A
+#define AMD_SMB_STATUS_PEC      0x1F
+
+#define AMD_SMB_PRTCL_WRITE             0x00
+#define AMD_SMB_PRTCL_READ              0x01
+#define AMD_SMB_PRTCL_QUICK             0x02
+#define AMD_SMB_PRTCL_BYTE              0x04
+#define AMD_SMB_PRTCL_BYTE_DATA         0x06
+#define AMD_SMB_PRTCL_WORD_DATA         0x08
+#define AMD_SMB_PRTCL_BLOCK_DATA        0x0a
+#define AMD_SMB_PRTCL_PROC_CALL         0x0c
+#define AMD_SMB_PRTCL_BLOCK_PROC_CALL   0x0d
+#define AMD_SMB_PRTCL_I2C_BLOCK_DATA    0x4a
+#define AMD_SMB_PRTCL_PEC               0x80
+
+
+static s32 amd8111_access(struct i2c_adapter * adap, u16 addr, unsigned short flags,
+                char read_write, u8 command, int size, union i2c_smbus_data * data)
+{
+        struct amd_smbus *smbus = adap->algo_data;
+        unsigned char protocol, len, pec, temp[2];
+        int i;
+
+        protocol = (read_write == I2C_SMBUS_READ) ? AMD_SMB_PRTCL_READ : AMD_SMB_PRTCL_WRITE;
+        pec = (flags & I2C_CLIENT_PEC) ? AMD_SMB_PRTCL_PEC : 0;
+
+        switch (size) {
+
+                case I2C_SMBUS_QUICK:
+                        protocol |= AMD_SMB_PRTCL_QUICK;
+                        read_write = I2C_SMBUS_WRITE;
+                        break;
+
+                case I2C_SMBUS_BYTE:
+                        if (read_write == I2C_SMBUS_WRITE)
+                                amd_ec_write(smbus, AMD_SMB_CMD, command);
+                        protocol |= AMD_SMB_PRTCL_BYTE;
+                        break;
+
+                case I2C_SMBUS_BYTE_DATA:
+                        amd_ec_write(smbus, AMD_SMB_CMD, command);
+                        if (read_write == I2C_SMBUS_WRITE)
+                                amd_ec_write(smbus, AMD_SMB_DATA, data->byte);
+                        protocol |= AMD_SMB_PRTCL_BYTE_DATA;
+                        break;
+
+                case I2C_SMBUS_WORD_DATA:
+                        amd_ec_write(smbus, AMD_SMB_CMD, command);
+                        if (read_write == I2C_SMBUS_WRITE) {
+                                amd_ec_write(smbus, AMD_SMB_DATA, data->word);
+                                amd_ec_write(smbus, AMD_SMB_DATA + 1, data->word >> 8);
+                        }
+                        protocol |= AMD_SMB_PRTCL_WORD_DATA | pec;
+                        break;
+
+                case I2C_SMBUS_BLOCK_DATA:
+                        amd_ec_write(smbus, AMD_SMB_CMD, command);
+                        if (read_write == I2C_SMBUS_WRITE) {
+                                len = min_t(u8, data->block[0], 32);
+                                amd_ec_write(smbus, AMD_SMB_BCNT, len);
+                                for (i = 0; i < len; i++)
+                                        amd_ec_write(smbus, AMD_SMB_DATA + i, data->block[i + 1]);
+                        }
+                        protocol |= AMD_SMB_PRTCL_BLOCK_DATA | pec;
+                        break;
+
+                case I2C_SMBUS_I2C_BLOCK_DATA:
+                        len = min_t(u8, data->block[0], 32);
+                        amd_ec_write(smbus, AMD_SMB_CMD, command);
+                        amd_ec_write(smbus, AMD_SMB_BCNT, len);
+                        if (read_write == I2C_SMBUS_WRITE)
+                                for (i = 0; i < len; i++)
+                                        amd_ec_write(smbus, AMD_SMB_DATA + i, data->block[i + 1]);
+                        protocol |= AMD_SMB_PRTCL_I2C_BLOCK_DATA;
+                        break;
+
+                case I2C_SMBUS_PROC_CALL:
+                        amd_ec_write(smbus, AMD_SMB_CMD, command);
+                        amd_ec_write(smbus, AMD_SMB_DATA, data->word);
+                        amd_ec_write(smbus, AMD_SMB_DATA + 1, data->word >> 8);
+                        protocol = AMD_SMB_PRTCL_PROC_CALL | pec;
+                        read_write = I2C_SMBUS_READ;
+                        break;
+
+                case I2C_SMBUS_BLOCK_PROC_CALL:
+                        protocol |= pec;
+                        len = min_t(u8, data->block[0], 31);
+                        amd_ec_write(smbus, AMD_SMB_CMD, command);
+                        amd_ec_write(smbus, AMD_SMB_BCNT, len);
+                        for (i = 0; i < len; i++)
+                                amd_ec_write(smbus, AMD_SMB_DATA + i, data->block[i + 1]);
+                        protocol = AMD_SMB_PRTCL_BLOCK_PROC_CALL | pec;
+                        read_write = I2C_SMBUS_READ;
+                        break;
+
+                case I2C_SMBUS_WORD_DATA_PEC:
+                case I2C_SMBUS_BLOCK_DATA_PEC:
+                case I2C_SMBUS_PROC_CALL_PEC:
+                case I2C_SMBUS_BLOCK_PROC_CALL_PEC:
+                        dev_warn(&adap->dev, "Unexpected software PEC transaction %d\n.", size);
+                        return -1;
+
+                default:
+                        dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
+                        return -1;
+        }
+
+        amd_ec_write(smbus, AMD_SMB_ADDR, addr << 1);
+        amd_ec_write(smbus, AMD_SMB_PRTCL, protocol);
+
+        amd_ec_read(smbus, AMD_SMB_STS, temp + 0);
+
+        if (~temp[0] & AMD_SMB_STS_DONE) {
+                udelay(500);
+                amd_ec_read(smbus, AMD_SMB_STS, temp + 0);
+        }
+
+        if (~temp[0] & AMD_SMB_STS_DONE) {
+                msleep(1);
+                amd_ec_read(smbus, AMD_SMB_STS, temp + 0);
+        }
+
+        if ((~temp[0] & AMD_SMB_STS_DONE) || (temp[0] & AMD_SMB_STS_STATUS))
+                return -1;
+
+        if (read_write == I2C_SMBUS_WRITE)
+                return 0;
+
+        switch (size) {
+
+                case I2C_SMBUS_BYTE:
+                case I2C_SMBUS_BYTE_DATA:
+                        amd_ec_read(smbus, AMD_SMB_DATA, &data->byte);
+                        break;
+
+                case I2C_SMBUS_WORD_DATA:
+                case I2C_SMBUS_PROC_CALL:
+                        amd_ec_read(smbus, AMD_SMB_DATA, temp + 0);
+                        amd_ec_read(smbus, AMD_SMB_DATA + 1, temp + 1);
+                        data->word = (temp[1] << 8) | temp[0];
+                        break;
+
+                case I2C_SMBUS_BLOCK_DATA:
+                case I2C_SMBUS_BLOCK_PROC_CALL:
+                        amd_ec_read(smbus, AMD_SMB_BCNT, &len);
+                        len = min_t(u8, len, 32);
+                case I2C_SMBUS_I2C_BLOCK_DATA:
+                        for (i = 0; i < len; i++)
+                                amd_ec_read(smbus, AMD_SMB_DATA + i, data->block + i + 1);
+                        data->block[0] = len;
+                        break;
+        }
+
+        return 0;
+}
+
+
+static u32 amd8111_func(struct i2c_adapter *adapter)
+{
+        return  I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA |
+                I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_BLOCK_DATA |
+                I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
+                I2C_FUNC_SMBUS_I2C_BLOCK | I2C_FUNC_SMBUS_HWPEC_CALC;
+}
+
+static struct i2c_algorithm smbus_algorithm = {
+        .name = "Non-I2C SMBus 2.0 adapter",
+        .id = I2C_ALGO_SMBUS,
+        .smbus_xfer = amd8111_access,
+        .functionality = amd8111_func,
+};
+
+
+static struct pci_device_id amd8111_ids[] = {
+        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS2) },
+        { 0, }
+};
+
+MODULE_DEVICE_TABLE (pci, amd8111_ids);
+
+static int __devinit amd8111_probe(struct pci_dev *dev, const struct pci_device_id *id)
+{
+        struct amd_smbus *smbus;
+        int error = -ENODEV;
+
+        if (~pci_resource_flags(dev, 0) & IORESOURCE_IO)
+                return -ENODEV;
+
+        smbus = kmalloc(sizeof(struct amd_smbus), GFP_KERNEL);
+        if (!smbus)
+                return -ENOMEM;
+        memset(smbus, 0, sizeof(struct amd_smbus));
+
+        smbus->dev = dev;
+        smbus->base = pci_resource_start(dev, 0);
+        smbus->size = pci_resource_len(dev, 0);
+
+        if (!request_region(smbus->base, smbus->size, "amd8111 SMBus 2.0"))
+                goto out_kfree;
+
+        smbus->adapter.owner = THIS_MODULE;
+        snprintf(smbus->adapter.name, I2C_NAME_SIZE,
+                "SMBus2 AMD8111 adapter at %04x", smbus->base);
+        smbus->adapter.class = I2C_CLASS_HWMON;
+        smbus->adapter.algo = &smbus_algorithm;
+        smbus->adapter.algo_data = smbus;
+
+        /* set up the driverfs linkage to our parent device */
+        smbus->adapter.dev.parent = &dev->dev;
+
+        error = i2c_add_adapter(&smbus->adapter);
+        if (error)
+                goto out_release_region;
+
+        pci_write_config_dword(smbus->dev, AMD_PCI_MISC, 0);
+        pci_set_drvdata(dev, smbus);
+        return 0;
+
+ out_release_region:
+        release_region(smbus->base, smbus->size);
+ out_kfree:
+        kfree(smbus);
+        return -1;
+}
+
+
+static void __devexit amd8111_remove(struct pci_dev *dev)
+{
+        struct amd_smbus *smbus = pci_get_drvdata(dev);
+
+        i2c_del_adapter(&smbus->adapter);
+        release_region(smbus->base, smbus->size);
+        kfree(smbus);
+}
+
+static struct pci_driver amd8111_driver = {
+        .name           = "amd8111_smbus2",
+        .id_table       = amd8111_ids,
+        .probe          = amd8111_probe,
+        .remove         = __devexit_p(amd8111_remove),
+};
+
+static int __init i2c_amd8111_init(void)
+{
+        return pci_register_driver(&amd8111_driver);
+}
+
+
+static void __exit i2c_amd8111_exit(void)
+{
+        pci_unregister_driver(&amd8111_driver);
+}
+
+module_init(i2c_amd8111_init);
+module_exit(i2c_amd8111_exit);
diff --git a/drivers/i2c/busses/i2c-au1550.c b/drivers/i2c/busses/i2c-au1550.c
new file mode 100644
index 000000000000..75831a20b0bd
--- /dev/null
+++ b/drivers/i2c/busses/i2c-au1550.c
@@ -0,0 +1,435 @@
+/*
+ * i2c-au1550.c: SMBus (i2c) adapter for Alchemy PSC interface
+ * Copyright (C) 2004 Embedded Edge, LLC <dan@embeddededge.com>
+ *
+ * 2.6 port by Matt Porter <mporter@kernel.crashing.org>
+ *
+ * The documentation describes this as an SMBus controller, but it doesn't
+ * understand any of the SMBus protocol in hardware.  It's really an I2C
+ * controller that could emulate most of the SMBus in software.
+ *
+ * This is just a skeleton adapter to use with the Au1550 PSC
+ * algorithm.  It was developed for the Pb1550, but will work with
+ * any Au1550 board that has a similar PSC configuration.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+
+#include <linux/config.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/i2c.h>
+
+#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-pb1x00/pb1550.h>
+#include <asm/mach-au1x00/au1xxx_psc.h>
+
+#include "i2c-au1550.h"
+
+static int
+wait_xfer_done(struct i2c_au1550_data *adap)
+{
+        u32     stat;
+        int     i;
+        volatile psc_smb_t      *sp;
+
+        sp = (volatile psc_smb_t *)(adap->psc_base);
+
+        /* Wait for Tx FIFO Underflow.
+        */
+        for (i = 0; i < adap->xfer_timeout; i++) {
+                stat = sp->psc_smbevnt;
+                au_sync();
+                if ((stat & PSC_SMBEVNT_TU) != 0) {
+                        /* Clear it.  */
+                        sp->psc_smbevnt = PSC_SMBEVNT_TU;
+                        au_sync();
+                        return 0;
+                }
+                udelay(1);
+        }
+
+        return -ETIMEDOUT;
+}
+
+static int
+wait_ack(struct i2c_au1550_data *adap)
+{
+        u32     stat;
+        volatile psc_smb_t      *sp;
+
+        if (wait_xfer_done(adap))
+                return -ETIMEDOUT;
+
+        sp = (volatile psc_smb_t *)(adap->psc_base);
+
+        stat = sp->psc_smbevnt;
+        au_sync();
+
+        if ((stat & (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | PSC_SMBEVNT_AL)) != 0)
+                return -ETIMEDOUT;
+
+        return 0;
+}
+
+static int
+wait_master_done(struct i2c_au1550_data *adap)
+{
+        u32     stat;
+        int     i;
+        volatile psc_smb_t      *sp;
+
+        sp = (volatile psc_smb_t *)(adap->psc_base);
+
+        /* Wait for Master Done.
+        */
+        for (i = 0; i < adap->xfer_timeout; i++) {
+                stat = sp->psc_smbevnt;
+                au_sync();
+                if ((stat & PSC_SMBEVNT_MD) != 0)
+                        return 0;
+                udelay(1);
+        }
+
+        return -ETIMEDOUT;
+}
+
+static int
+do_address(struct i2c_au1550_data *adap, unsigned int addr, int rd)
+{
+        volatile psc_smb_t      *sp;
+        u32                     stat;
+
+        sp = (volatile psc_smb_t *)(adap->psc_base);
+
+        /* Reset the FIFOs, clear events.
+        */
+        sp->psc_smbpcr = PSC_SMBPCR_DC;
+        sp->psc_smbevnt = PSC_SMBEVNT_ALLCLR;
+        au_sync();
+        do {
+                stat = sp->psc_smbpcr;
+                au_sync();
+        } while ((stat & PSC_SMBPCR_DC) != 0);
+
+        /* Write out the i2c chip address and specify operation
+        */
+        addr <<= 1;
+        if (rd)
+                addr |= 1;
+
+        /* Put byte into fifo, start up master.
+        */
+        sp->psc_smbtxrx = addr;
+        au_sync();
+        sp->psc_smbpcr = PSC_SMBPCR_MS;
+        au_sync();
+        if (wait_ack(adap))
+                return -EIO;
+        return 0;
+}
+
+static u32
+wait_for_rx_byte(struct i2c_au1550_data *adap, u32 *ret_data)
+{
+        int     j;
+        u32     data, stat;
+        volatile psc_smb_t      *sp;
+
+        if (wait_xfer_done(adap))
+                return -EIO;
+
+        sp = (volatile psc_smb_t *)(adap->psc_base);
+
+        j =  adap->xfer_timeout * 100;
+        do {
+                j--;
+                if (j <= 0)
+                        return -EIO;
+
+                stat = sp->psc_smbstat;
+                au_sync();
+                if ((stat & PSC_SMBSTAT_RE) == 0)
+                        j = 0;
+                else
+                        udelay(1);
+        } while (j > 0);
+        data = sp->psc_smbtxrx;
+        au_sync();
+        *ret_data = data;
+
+        return 0;
+}
+
+static int
+i2c_read(struct i2c_au1550_data *adap, unsigned char *buf,
+                    unsigned int len)
+{
+        int     i;
+        u32     data;
+        volatile psc_smb_t      *sp;
+
+        if (len == 0)
+                return 0;
+
+        /* A read is performed by stuffing the transmit fifo with
+         * zero bytes for timing, waiting for bytes to appear in the
+         * receive fifo, then reading the bytes.
+         */
+
+        sp = (volatile psc_smb_t *)(adap->psc_base);
+
+        i = 0;
+        while (i < (len-1)) {
+                sp->psc_smbtxrx = 0;
+                au_sync();
+                if (wait_for_rx_byte(adap, &data))
+                        return -EIO;
+
+                buf[i] = data;
+                i++;
+        }
+
+        /* The last byte has to indicate transfer done.
+        */
+        sp->psc_smbtxrx = PSC_SMBTXRX_STP;
+        au_sync();
+        if (wait_master_done(adap))
+                return -EIO;
+
+        data = sp->psc_smbtxrx;
+        au_sync();
+        buf[i] = data;
+        return 0;
+}
+
+static int
+i2c_write(struct i2c_au1550_data *adap, unsigned char *buf,
+                     unsigned int len)
+{
+        int     i;
+        u32     data;
+        volatile psc_smb_t      *sp;
+
+        if (len == 0)
+                return 0;
+
+        sp = (volatile psc_smb_t *)(adap->psc_base);
+
+        i = 0;
+        while (i < (len-1)) {
+                data = buf[i];
+                sp->psc_smbtxrx = data;
+                au_sync();
+                if (wait_ack(adap))
+                        return -EIO;
+                i++;
+        }
+
+        /* The last byte has to indicate transfer done.
+        */
+        data = buf[i];
+        data |= PSC_SMBTXRX_STP;
+        sp->psc_smbtxrx = data;
+        au_sync();
+        if (wait_master_done(adap))
+                return -EIO;
+        return 0;
+}
+
+static int
+au1550_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, int num)
+{
+        struct i2c_au1550_data *adap = i2c_adap->algo_data;
+        struct i2c_msg *p;
+        int i, err = 0;
+
+        for (i = 0; !err && i < num; i++) {
+                p = &msgs[i];
+                err = do_address(adap, p->addr, p->flags & I2C_M_RD);
+                if (err || !p->len)
+                        continue;
+                if (p->flags & I2C_M_RD)
+                        err = i2c_read(adap, p->buf, p->len);
+                else
+                        err = i2c_write(adap, p->buf, p->len);
+        }
+
+        /* Return the number of messages processed, or the error code.
+        */
+        if (err == 0)
+                err = num;
+        return err;
+}
+
+static u32
+au1550_func(struct i2c_adapter *adap)
+{
+        return I2C_FUNC_I2C;
+}
+
+static struct i2c_algorithm au1550_algo = {
+        .name           = "Au1550 algorithm",
+        .id             = I2C_ALGO_AU1550,
+        .master_xfer    = au1550_xfer,
+        .functionality  = au1550_func,
+};
+
+/*
+ * registering functions to load algorithms at runtime
+ * Prior to calling us, the 50MHz clock frequency and routing
+ * must have been set up for the PSC indicated by the adapter.
+ */
+int
+i2c_au1550_add_bus(struct i2c_adapter *i2c_adap)
+{
+        struct i2c_au1550_data *adap = i2c_adap->algo_data;
+        volatile psc_smb_t      *sp;
+        u32     stat;
+
+        i2c_adap->algo = &au1550_algo;
+
+        /* Now, set up the PSC for SMBus PIO mode.
+        */
+        sp = (volatile psc_smb_t *)(adap->psc_base);
+        sp->psc_ctrl = PSC_CTRL_DISABLE;
+        au_sync();
+        sp->psc_sel = PSC_SEL_PS_SMBUSMODE;
+        sp->psc_smbcfg = 0;
+        au_sync();
+        sp->psc_ctrl = PSC_CTRL_ENABLE;
+        au_sync();
+        do {
+                stat = sp->psc_smbstat;
+                au_sync();
+        } while ((stat & PSC_SMBSTAT_SR) == 0);
+
+        sp->psc_smbcfg = (PSC_SMBCFG_RT_FIFO8 | PSC_SMBCFG_TT_FIFO8 |
+                                PSC_SMBCFG_DD_DISABLE);
+
+        /* Divide by 8 to get a 6.25 MHz clock.  The later protocol
+         * timings are based on this clock.
+         */
+        sp->psc_smbcfg |= PSC_SMBCFG_SET_DIV(PSC_SMBCFG_DIV8);
+        sp->psc_smbmsk = PSC_SMBMSK_ALLMASK;
+        au_sync();
+
+        /* Set the protocol timer values.  See Table 71 in the
+         * Au1550 Data Book for standard timing values.
+         */
+        sp->psc_smbtmr = PSC_SMBTMR_SET_TH(0) | PSC_SMBTMR_SET_PS(15) | \
+                PSC_SMBTMR_SET_PU(15) | PSC_SMBTMR_SET_SH(15) | \
+                PSC_SMBTMR_SET_SU(15) | PSC_SMBTMR_SET_CL(15) | \
+                PSC_SMBTMR_SET_CH(15);
+        au_sync();
+
+        sp->psc_smbcfg |= PSC_SMBCFG_DE_ENABLE;
+        do {
+                stat = sp->psc_smbstat;
+                au_sync();
+        } while ((stat & PSC_SMBSTAT_DR) == 0);
+
+        return i2c_add_adapter(i2c_adap);
+}
+
+
+int
+i2c_au1550_del_bus(struct i2c_adapter *adap)
+{
+        return i2c_del_adapter(adap);
+}
+
+static int
+pb1550_reg(struct i2c_client *client)
+{
+        return 0;
+}
+
+static int
+pb1550_unreg(struct i2c_client *client)
+{
+        return 0;
+}
+
+static struct i2c_au1550_data pb1550_i2c_info = {
+        SMBUS_PSC_BASE, 200, 200
+};
+
+static struct i2c_adapter pb1550_board_adapter = {
+        name:              "pb1550 adapter",
+        id:                I2C_HW_AU1550_PSC,
+        algo:              NULL,
+        algo_data:         &pb1550_i2c_info,
+        client_register:   pb1550_reg,
+        client_unregister: pb1550_unreg,
+};
+
+/* BIG hack to support the control interface on the Wolfson WM8731
+ * audio codec on the Pb1550 board.  We get an address and two data
+ * bytes to write, create an i2c message, and send it across the
+ * i2c transfer function.  We do this here because we have access to
+ * the i2c adapter structure.
+ */
+static struct i2c_msg wm_i2c_msg;  /* We don't want this stuff on the stack */
+static  u8 i2cbuf[2];
+
+int
+pb1550_wm_codec_write(u8 addr, u8 reg, u8 val)
+{
+        wm_i2c_msg.addr = addr;
+        wm_i2c_msg.flags = 0;
+        wm_i2c_msg.buf = i2cbuf;
+        wm_i2c_msg.len = 2;
+        i2cbuf[0] = reg;
+        i2cbuf[1] = val;
+
+        return pb1550_board_adapter.algo->master_xfer(&pb1550_board_adapter, &wm_i2c_msg, 1);
+}
+
+static int __init
+i2c_au1550_init(void)
+{
+        printk(KERN_INFO "Au1550 I2C: ");
+
+        /* This is where we would set up a 50MHz clock source
+         * and routing.  On the Pb1550, the SMBus is PSC2, which
+         * uses a shared clock with USB.  This has been already
+         * configured by Yamon as a 48MHz clock, close enough
+         * for our work.
+         */
+        if (i2c_au1550_add_bus(&pb1550_board_adapter) < 0) {
+                printk("failed to initialize.\n");
+                return -ENODEV;
+        }
+
+        printk("initialized.\n");
+        return 0;
+}
+
+static void __exit
+i2c_au1550_exit(void)
+{
+        i2c_au1550_del_bus(&pb1550_board_adapter);
+}
+
+MODULE_AUTHOR("Dan Malek, Embedded Edge, LLC.");
+MODULE_DESCRIPTION("SMBus adapter Alchemy pb1550");
+MODULE_LICENSE("GPL");
+
+module_init (i2c_au1550_init);
+module_exit (i2c_au1550_exit);
diff --git a/drivers/i2c/busses/i2c-au1550.h b/drivers/i2c/busses/i2c-au1550.h
new file mode 100644
index 000000000000..fce15d161ae7
--- /dev/null
+++ b/drivers/i2c/busses/i2c-au1550.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2004 Embedded Edge, LLC <dan@embeddededge.com>
+ * 2.6 port by Matt Porter <mporter@kernel.crashing.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef I2C_AU1550_H
+#define I2C_AU1550_H
+
+struct i2c_au1550_data {
+        u32     psc_base;
+        int     xfer_timeout;
+        int     ack_timeout;
+};
+
+int i2c_au1550_add_bus(struct i2c_adapter *);
+int i2c_au1550_del_bus(struct i2c_adapter *);
+
+#endif /* I2C_AU1550_H */
diff --git a/drivers/i2c/busses/i2c-elektor.c b/drivers/i2c/busses/i2c-elektor.c
new file mode 100644
index 000000000000..0a7720000a0c
--- /dev/null
+++ b/drivers/i2c/busses/i2c-elektor.c
@@ -0,0 +1,295 @@
+/* ------------------------------------------------------------------------- */
+/* i2c-elektor.c i2c-hw access for PCF8584 style isa bus adaptes             */
+/* ------------------------------------------------------------------------- */
+/*   Copyright (C) 1995-97 Simon G. Vogl
+                   1998-99 Hans Berglund
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.                */
+/* ------------------------------------------------------------------------- */
+
+/* With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> and even
+   Frodo Looijaard <frodol@dds.nl> */
+
+/* Partialy rewriten by Oleg I. Vdovikin for mmapped support of 
+   for Alpha Processor Inc. UP-2000(+) boards */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/ioport.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/wait.h>
+
+#include <linux/i2c.h>
+#include <linux/i2c-algo-pcf.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+
+#include "../algos/i2c-algo-pcf.h"
+
+#define DEFAULT_BASE 0x330
+
+static int base;
+static int irq;
+static int clock  = 0x1c;
+static int own    = 0x55;
+static int mmapped;
+
+/* vdovikin: removed static struct i2c_pcf_isa gpi; code - 
+  this module in real supports only one device, due to missing arguments
+  in some functions, called from the algo-pcf module. Sometimes it's
+  need to be rewriten - but for now just remove this for simpler reading */
+
+static wait_queue_head_t pcf_wait;
+static int pcf_pending;
+static spinlock_t lock;
+
+/* ----- local functions ---------------------------------------------- */
+
+static void pcf_isa_setbyte(void *data, int ctl, int val)
+{
+        int address = ctl ? (base + 1) : base;
+
+        /* enable irq if any specified for serial operation */
+        if (ctl && irq && (val & I2C_PCF_ESO)) {
+                val |= I2C_PCF_ENI;
+        }
+
+        pr_debug("i2c-elektor: Write 0x%X 0x%02X\n", address, val & 255);
+
+        switch (mmapped) {
+        case 0: /* regular I/O */
+                outb(val, address);
+                break;
+        case 2: /* double mapped I/O needed for UP2000 board,
+                   I don't know why this... */
+                writeb(val, (void *)address);
+                /* fall */
+        case 1: /* memory mapped I/O */
+                writeb(val, (void *)address);
+                break;
+        }
+}
+
+static int pcf_isa_getbyte(void *data, int ctl)
+{
+        int address = ctl ? (base + 1) : base;
+        int val = mmapped ? readb((void *)address) : inb(address);
+
+        pr_debug("i2c-elektor: Read 0x%X 0x%02X\n", address, val);
+
+        return (val);
+}
+
+static int pcf_isa_getown(void *data)
+{
+        return (own);
+}
+
+
+static int pcf_isa_getclock(void *data)
+{
+        return (clock);
+}
+
+static void pcf_isa_waitforpin(void) {
+        DEFINE_WAIT(wait);
+        int timeout = 2;
+        unsigned long flags;
+
+        if (irq > 0) {
+                spin_lock_irqsave(&lock, flags);
+                if (pcf_pending == 0) {
+                        spin_unlock_irqrestore(&lock, flags);
+                        prepare_to_wait(&pcf_wait, &wait, TASK_INTERRUPTIBLE);
+                        if (schedule_timeout(timeout*HZ)) {
+                                spin_lock_irqsave(&lock, flags);
+                                if (pcf_pending == 1) {
+                                        pcf_pending = 0;
+                                }
+                                spin_unlock_irqrestore(&lock, flags);
+                        }
+                        finish_wait(&pcf_wait, &wait);
+                } else {
+                        pcf_pending = 0;
+                        spin_unlock_irqrestore(&lock, flags);
+                }
+        } else {
+                udelay(100);
+        }
+}
+
+
+static irqreturn_t pcf_isa_handler(int this_irq, void *dev_id, struct pt_regs *regs) {
+        spin_lock(&lock);
+        pcf_pending = 1;
+        spin_unlock(&lock);
+        wake_up_interruptible(&pcf_wait);
+        return IRQ_HANDLED;
+}
+
+
+static int pcf_isa_init(void)
+{
+        spin_lock_init(&lock);
+        if (!mmapped) {
+                if (!request_region(base, 2, "i2c (isa bus adapter)")) {
+                        printk(KERN_ERR
+                               "i2c-elektor: requested I/O region (0x%X:2) "
+                               "is in use.\n", base);
+                        return -ENODEV;
+                }
+        }
+        if (irq > 0) {
+                if (request_irq(irq, pcf_isa_handler, 0, "PCF8584", NULL) < 0) {
+                        printk(KERN_ERR "i2c-elektor: Request irq%d failed\n", irq);
+                        irq = 0;
+                } else
+                        enable_irq(irq);
+        }
+        return 0;
+}
+
+/* ------------------------------------------------------------------------
+ * Encapsulate the above functions in the correct operations structure.
+ * This is only done when more than one hardware adapter is supported.
+ */
+static struct i2c_algo_pcf_data pcf_isa_data = {
+        .setpcf     = pcf_isa_setbyte,
+        .getpcf     = pcf_isa_getbyte,
+        .getown     = pcf_isa_getown,
+        .getclock   = pcf_isa_getclock,
+        .waitforpin = pcf_isa_waitforpin,
+        .udelay     = 10,
+        .mdelay     = 10,
+        .timeout    = 100,
+};
+
+static struct i2c_adapter pcf_isa_ops = {
+        .owner          = THIS_MODULE,
+        .class          = I2C_CLASS_HWMON,
+        .id             = I2C_HW_P_ELEK,
+        .algo_data      = &pcf_isa_data,
+        .name           = "PCF8584 ISA adapter",
+};
+
+static int __init i2c_pcfisa_init(void) 
+{
+#ifdef __alpha__
+        /* check to see we have memory mapped PCF8584 connected to the 
+        Cypress cy82c693 PCI-ISA bridge as on UP2000 board */
+        if (base == 0) {
+                struct pci_dev *cy693_dev;
+                
+                cy693_dev = pci_get_device(PCI_VENDOR_ID_CONTAQ, 
+                                           PCI_DEVICE_ID_CONTAQ_82C693, NULL);
+                if (cy693_dev) {
+                        char config;
+                        /* yeap, we've found cypress, let's check config */
+                        if (!pci_read_config_byte(cy693_dev, 0x47, &config)) {
+                                
+                                pr_debug("i2c-elektor: found cy82c693, config register 0x47 = 0x%02x.\n", config);
+
+                                /* UP2000 board has this register set to 0xe1,
+                                   but the most significant bit as seems can be 
+                                   reset during the proper initialisation
+                                   sequence if guys from API decides to do that
+                                   (so, we can even enable Tsunami Pchip
+                                   window for the upper 1 Gb) */
+
+                                /* so just check for ROMCS at 0xe0000,
+                                   ROMCS enabled for writes
+                                   and external XD Bus buffer in use. */
+                                if ((config & 0x7f) == 0x61) {
+                                        /* seems to be UP2000 like board */
+                                        base = 0xe0000;
+                                        /* I don't know why we need to
+                                           write twice */
+                                        mmapped = 2;
+                                        /* UP2000 drives ISA with
+                                           8.25 MHz (PCI/4) clock
+                                           (this can be read from cypress) */
+                                        clock = I2C_PCF_CLK | I2C_PCF_TRNS90;
+                                        printk(KERN_INFO "i2c-elektor: found API UP2000 like board, will probe PCF8584 later.\n");
+                                }
+                        }
+                        pci_dev_put(cy693_dev);
+                }
+        }
+#endif
+
+        /* sanity checks for mmapped I/O */
+        if (mmapped && base < 0xc8000) {
+                printk(KERN_ERR "i2c-elektor: incorrect base address (0x%0X) specified for mmapped I/O.\n", base);
+                return -ENODEV;
+        }
+
+        printk(KERN_INFO "i2c-elektor: i2c pcf8584-isa adapter driver\n");
+
+        if (base == 0) {
+                base = DEFAULT_BASE;
+        }
+
+        init_waitqueue_head(&pcf_wait);
+        if (pcf_isa_init())
+                return -ENODEV;
+        if (i2c_pcf_add_bus(&pcf_isa_ops) < 0)
+                goto fail;
+        
+        printk(KERN_ERR "i2c-elektor: found device at %#x.\n", base);
+
+        return 0;
+
+ fail:
+        if (irq > 0) {
+                disable_irq(irq);
+                free_irq(irq, NULL);
+        }
+
+        if (!mmapped)
+                release_region(base , 2);
+        return -ENODEV;
+}
+
+static void i2c_pcfisa_exit(void)
+{
+        i2c_pcf_del_bus(&pcf_isa_ops);
+
+        if (irq > 0) {
+                disable_irq(irq);
+                free_irq(irq, NULL);
+        }
+
+        if (!mmapped)
+                release_region(base , 2);
+}
+
+MODULE_AUTHOR("Hans Berglund <hb@spacetec.no>");
+MODULE_DESCRIPTION("I2C-Bus adapter routines for PCF8584 ISA bus adapter");
+MODULE_LICENSE("GPL");
+
+module_param(base, int, 0);
+module_param(irq, int, 0);
+module_param(clock, int, 0);
+module_param(own, int, 0);
+module_param(mmapped, int, 0);
+
+module_init(i2c_pcfisa_init);
+module_exit(i2c_pcfisa_exit);
diff --git a/drivers/i2c/busses/i2c-frodo.c b/drivers/i2c/busses/i2c-frodo.c
new file mode 100644
index 000000000000..e093829a0bf7
--- /dev/null
+++ b/drivers/i2c/busses/i2c-frodo.c
@@ -0,0 +1,86 @@
+
+/*
+ * linux/drivers/i2c/i2c-frodo.c
+ *
+ * Author: Abraham van der Merwe <abraham@2d3d.co.za>
+ *
+ * An I2C adapter driver for the 2d3D, Inc. StrongARM SA-1110
+ * Development board (Frodo).
+ *
+ * This source code is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/i2c-algo-bit.h>
+#include <asm/hardware.h>
+
+
+static void frodo_setsda (void *data,int state)
+{
+        if (state)
+                FRODO_CPLD_I2C |= FRODO_I2C_SDA_OUT;
+        else
+                FRODO_CPLD_I2C &= ~FRODO_I2C_SDA_OUT;
+}
+
+static void frodo_setscl (void *data,int state)
+{
+        if (state)
+                FRODO_CPLD_I2C |= FRODO_I2C_SCL_OUT;
+        else
+                FRODO_CPLD_I2C &= ~FRODO_I2C_SCL_OUT;
+}
+
+static int frodo_getsda (void *data)
+{
+        return ((FRODO_CPLD_I2C & FRODO_I2C_SDA_IN) != 0);
+}
+
+static int frodo_getscl (void *data)
+{
+        return ((FRODO_CPLD_I2C & FRODO_I2C_SCL_IN) != 0);
+}
+
+static struct i2c_algo_bit_data bit_frodo_data = {
+        .setsda         = frodo_setsda,
+        .setscl         = frodo_setscl,
+        .getsda         = frodo_getsda,
+        .getscl         = frodo_getscl,
+        .udelay         = 80,
+        .mdelay         = 80,
+        .timeout        = HZ
+};
+
+static struct i2c_adapter frodo_ops = {
+        .owner                  = THIS_MODULE,
+        .id                     = I2C_HW_B_FRODO,
+        .algo_data              = &bit_frodo_data,
+        .dev                    = {
+                .name           = "Frodo adapter driver",
+        },
+};
+
+static int __init i2c_frodo_init (void)
+{
+        return i2c_bit_add_bus(&frodo_ops);
+}
+
+static void __exit i2c_frodo_exit (void)
+{
+        i2c_bit_del_bus(&frodo_ops);
+}
+
+MODULE_AUTHOR ("Abraham van der Merwe <abraham@2d3d.co.za>");
+MODULE_DESCRIPTION ("I2C-Bus adapter routines for Frodo");
+MODULE_LICENSE ("GPL");
+
+module_init (i2c_frodo_init);
+module_exit (i2c_frodo_exit);
+
diff --git a/drivers/i2c/busses/i2c-hydra.c b/drivers/i2c/busses/i2c-hydra.c
new file mode 100644
index 000000000000..e0cb3b0f92fa
--- /dev/null
+++ b/drivers/i2c/busses/i2c-hydra.c
@@ -0,0 +1,183 @@
+/*
+    i2c-hydra.c - Part of lm_sensors,  Linux kernel modules
+                  for hardware monitoring
+
+    i2c Support for the Apple `Hydra' Mac I/O
+
+    Copyright (c) 1999-2004 Geert Uytterhoeven <geert@linux-m68k.org>
+
+    Based on i2c Support for Via Technologies 82C586B South Bridge
+    Copyright (c) 1998, 1999 Kyösti Mälkki <kmalkki@cc.hut.fi>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/types.h>
+#include <linux/i2c.h>
+#include <linux/i2c-algo-bit.h>
+#include <linux/init.h>
+#include <asm/io.h>
+#include <asm/hydra.h>
+
+
+#define HYDRA_CPD_PD0   0x00000001      /* CachePD lines */
+#define HYDRA_CPD_PD1   0x00000002
+#define HYDRA_CPD_PD2   0x00000004
+#define HYDRA_CPD_PD3   0x00000008
+
+#define HYDRA_SCLK      HYDRA_CPD_PD0
+#define HYDRA_SDAT      HYDRA_CPD_PD1
+#define HYDRA_SCLK_OE   0x00000010
+#define HYDRA_SDAT_OE   0x00000020
+
+static inline void pdregw(void *data, u32 val)
+{
+        struct Hydra *hydra = (struct Hydra *)data;
+        writel(val, &hydra->CachePD);
+}
+
+static inline u32 pdregr(void *data)
+{
+        struct Hydra *hydra = (struct Hydra *)data;
+        return readl(&hydra->CachePD);
+}
+
+static void hydra_bit_setscl(void *data, int state)
+{
+        u32 val = pdregr(data);
+        if (state)
+                val &= ~HYDRA_SCLK_OE;
+        else {
+                val &= ~HYDRA_SCLK;
+                val |= HYDRA_SCLK_OE;
+        }
+        pdregw(data, val);
+}
+
+static void hydra_bit_setsda(void *data, int state)
+{
+        u32 val = pdregr(data);
+        if (state)
+                val &= ~HYDRA_SDAT_OE;
+        else {
+                val &= ~HYDRA_SDAT;
+                val |= HYDRA_SDAT_OE;
+        }
+        pdregw(data, val);
+}
+
+static int hydra_bit_getscl(void *data)
+{
+        return (pdregr(data) & HYDRA_SCLK) != 0;
+}
+
+static int hydra_bit_getsda(void *data)
+{
+        return (pdregr(data) & HYDRA_SDAT) != 0;
+}
+
+/* ------------------------------------------------------------------------ */
+
+static struct i2c_algo_bit_data hydra_bit_data = {
+        .setsda         = hydra_bit_setsda,
+        .setscl         = hydra_bit_setscl,
+        .getsda         = hydra_bit_getsda,
+        .getscl         = hydra_bit_getscl,
+        .udelay         = 5,
+        .mdelay         = 5,
+        .timeout        = HZ
+};
+
+static struct i2c_adapter hydra_adap = {
+        .owner          = THIS_MODULE,
+        .name           = "Hydra i2c",
+        .id             = I2C_HW_B_HYDRA,
+        .algo_data      = &hydra_bit_data,
+};
+
+static struct pci_device_id hydra_ids[] = {
+        { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_HYDRA) },
+        { 0, }
+};
+
+MODULE_DEVICE_TABLE (pci, hydra_ids);
+
+static int __devinit hydra_probe(struct pci_dev *dev,
+                                 const struct pci_device_id *id)
+{
+        unsigned long base = pci_resource_start(dev, 0);
+        int res;
+
+        if (!request_mem_region(base+offsetof(struct Hydra, CachePD), 4,
+                                hydra_adap.name))
+                return -EBUSY;
+
+        hydra_bit_data.data = ioremap(base, pci_resource_len(dev, 0));
+        if (hydra_bit_data.data == NULL) {
+                release_mem_region(base+offsetof(struct Hydra, CachePD), 4);
+                return -ENODEV;
+        }
+
+        pdregw(hydra_bit_data.data, 0);         /* clear SCLK_OE and SDAT_OE */
+        hydra_adap.dev.parent = &dev->dev;
+        res = i2c_bit_add_bus(&hydra_adap);
+        if (res < 0) {
+                iounmap(hydra_bit_data.data);
+                release_mem_region(base+offsetof(struct Hydra, CachePD), 4);
+                return res;
+        }
+        return 0;
+}
+
+static void __devexit hydra_remove(struct pci_dev *dev)
+{
+        pdregw(hydra_bit_data.data, 0);         /* clear SCLK_OE and SDAT_OE */
+        i2c_bit_del_bus(&hydra_adap);
+        iounmap(hydra_bit_data.data);
+        release_mem_region(pci_resource_start(dev, 0)+
+                           offsetof(struct Hydra, CachePD), 4);
+}
+
+
+static struct pci_driver hydra_driver = {
+        .name           = "hydra_smbus",
+        .id_table       = hydra_ids,
+        .probe          = hydra_probe,
+        .remove         = __devexit_p(hydra_remove),
+};
+
+static int __init i2c_hydra_init(void)
+{
+        return pci_register_driver(&hydra_driver);
+}
+
+
+static void __exit i2c_hydra_exit(void)
+{
+        pci_unregister_driver(&hydra_driver);
+}
+
+
+
+MODULE_AUTHOR("Geert Uytterhoeven <geert@linux-m68k.org>");
+MODULE_DESCRIPTION("i2c for Apple Hydra Mac I/O");
+MODULE_LICENSE("GPL");
+
+module_init(i2c_hydra_init);
+module_exit(i2c_hydra_exit);
+
diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
new file mode 100644
index 000000000000..6ec8b21965e2
--- /dev/null
+++ b/drivers/i2c/busses/i2c-i801.c
@@ -0,0 +1,613 @@
+/*
+    i801.c - Part of lm_sensors, Linux kernel modules for hardware
+              monitoring
+    Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
+    Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
+    <mdsxyz123@yahoo.com>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+/*
+    SUPPORTED DEVICES   PCI ID
+    82801AA             2413           
+    82801AB             2423           
+    82801BA             2443           
+    82801CA/CAM         2483           
+    82801DB             24C3   (HW PEC supported, 32 byte buffer not supported)
+    82801EB             24D3   (HW PEC supported, 32 byte buffer not supported)
+    6300ESB             25A4
+    ICH6                266A
+    ICH7                27DA
+    This driver supports several versions of Intel's I/O Controller Hubs (ICH).
+    For SMBus support, they are similar to the PIIX4 and are part
+    of Intel's '810' and other chipsets.
+    See the doc/busses/i2c-i801 file for details.
+    I2C Block Read and Process Call are not supported.
+*/
+
+/* Note: we assume there can only be one I801, with one SMBus interface */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/stddef.h>
+#include <linux/delay.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+#include <asm/io.h>
+
+#ifdef I2C_FUNC_SMBUS_BLOCK_DATA_PEC
+#define HAVE_PEC
+#endif
+
+/* I801 SMBus address offsets */
+#define SMBHSTSTS       (0 + i801_smba)
+#define SMBHSTCNT       (2 + i801_smba)
+#define SMBHSTCMD       (3 + i801_smba)
+#define SMBHSTADD       (4 + i801_smba)
+#define SMBHSTDAT0      (5 + i801_smba)
+#define SMBHSTDAT1      (6 + i801_smba)
+#define SMBBLKDAT       (7 + i801_smba)
+#define SMBPEC          (8 + i801_smba) /* ICH4 only */
+#define SMBAUXSTS       (12 + i801_smba)        /* ICH4 only */
+#define SMBAUXCTL       (13 + i801_smba)        /* ICH4 only */
+
+/* PCI Address Constants */
+#define SMBBA           0x020
+#define SMBHSTCFG       0x040
+#define SMBREV          0x008
+
+/* Host configuration bits for SMBHSTCFG */
+#define SMBHSTCFG_HST_EN        1
+#define SMBHSTCFG_SMB_SMI_EN    2
+#define SMBHSTCFG_I2C_EN        4
+
+/* Other settings */
+#define MAX_TIMEOUT             100
+#define ENABLE_INT9             0       /* set to 0x01 to enable - untested */
+
+/* I801 command constants */
+#define I801_QUICK              0x00
+#define I801_BYTE               0x04
+#define I801_BYTE_DATA          0x08
+#define I801_WORD_DATA          0x0C
+#define I801_PROC_CALL          0x10    /* later chips only, unimplemented */
+#define I801_BLOCK_DATA         0x14
+#define I801_I2C_BLOCK_DATA     0x18    /* unimplemented */
+#define I801_BLOCK_LAST         0x34
+#define I801_I2C_BLOCK_LAST     0x38    /* unimplemented */
+#define I801_START              0x40
+#define I801_PEC_EN             0x80    /* ICH4 only */
+
+/* insmod parameters */
+
+/* If force_addr is set to anything different from 0, we forcibly enable
+   the I801 at the given address. VERY DANGEROUS! */
+static u16 force_addr;
+module_param(force_addr, ushort, 0);
+MODULE_PARM_DESC(force_addr,
+                 "Forcibly enable the I801 at the given address. "
+                 "EXTREMELY DANGEROUS!");
+
+static int i801_transaction(void);
+static int i801_block_transaction(union i2c_smbus_data *data,
+                                  char read_write, int command);
+
+static unsigned short i801_smba;
+static struct pci_dev *I801_dev;
+static int isich4;
+
+static int i801_setup(struct pci_dev *dev)
+{
+        int error_return = 0;
+        unsigned char temp;
+
+        /* Note: we keep on searching until we have found 'function 3' */
+        if(PCI_FUNC(dev->devfn) != 3)
+                return -ENODEV;
+
+        I801_dev = dev;
+        if ((dev->device == PCI_DEVICE_ID_INTEL_82801DB_3) ||
+            (dev->device == PCI_DEVICE_ID_INTEL_82801EB_3) ||
+            (dev->device == PCI_DEVICE_ID_INTEL_ESB_4))
+                isich4 = 1;
+        else
+                isich4 = 0;
+
+        /* Determine the address of the SMBus areas */
+        if (force_addr) {
+                i801_smba = force_addr & 0xfff0;
+        } else {
+                pci_read_config_word(I801_dev, SMBBA, &i801_smba);
+                i801_smba &= 0xfff0;
+                if(i801_smba == 0) {
+                        dev_err(&dev->dev, "SMB base address uninitialized"
+                                "- upgrade BIOS or use force_addr=0xaddr\n");
+                        return -ENODEV;
+                }
+        }
+
+        if (!request_region(i801_smba, (isich4 ? 16 : 8), "i801-smbus")) {
+                dev_err(&dev->dev, "I801_smb region 0x%x already in use!\n",
+                        i801_smba);
+                error_return = -EBUSY;
+                goto END;
+        }
+
+        pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
+        temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
+        pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
+
+        /* If force_addr is set, we program the new address here. Just to make
+           sure, we disable the device first. */
+        if (force_addr) {
+                pci_write_config_byte(I801_dev, SMBHSTCFG, temp & 0xfe);
+                pci_write_config_word(I801_dev, SMBBA, i801_smba);
+                pci_write_config_byte(I801_dev, SMBHSTCFG, temp | 0x01);
+                dev_warn(&dev->dev, "WARNING: I801 SMBus interface set to "
+                        "new address %04x!\n", i801_smba);
+        } else if ((temp & 1) == 0) {
+                pci_write_config_byte(I801_dev, SMBHSTCFG, temp | 1);
+                dev_warn(&dev->dev, "enabling SMBus device\n");
+        }
+
+        if (temp & 0x02)
+                dev_dbg(&dev->dev, "I801 using Interrupt SMI# for SMBus.\n");
+        else
+                dev_dbg(&dev->dev, "I801 using PCI Interrupt for SMBus.\n");
+
+        pci_read_config_byte(I801_dev, SMBREV, &temp);
+        dev_dbg(&dev->dev, "SMBREV = 0x%X\n", temp);
+        dev_dbg(&dev->dev, "I801_smba = 0x%X\n", i801_smba);
+
+END:
+        return error_return;
+}
+
+static int i801_transaction(void)
+{
+        int temp;
+        int result = 0;
+        int timeout = 0;
+
+        dev_dbg(&I801_dev->dev, "Transaction (pre): CNT=%02x, CMD=%02x,"
+                "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
+                inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
+                inb_p(SMBHSTDAT1));
+
+        /* Make sure the SMBus host is ready to start transmitting */
+        /* 0x1f = Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
+        if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
+                dev_dbg(&I801_dev->dev, "SMBus busy (%02x). Resetting... \n",
+                        temp);
+                outb_p(temp, SMBHSTSTS);
+                if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
+                        dev_dbg(&I801_dev->dev, "Failed! (%02x)\n", temp);
+                        return -1;
+                } else {
+                        dev_dbg(&I801_dev->dev, "Successfull!\n");
+                }
+        }
+
+        outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);
+
+        /* We will always wait for a fraction of a second! */
+        do {
+                msleep(1);
+                temp = inb_p(SMBHSTSTS);
+        } while ((temp & 0x01) && (timeout++ < MAX_TIMEOUT));
+
+        /* If the SMBus is still busy, we give up */
+        if (timeout >= MAX_TIMEOUT) {
+                dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
+                result = -1;
+        }
+
+        if (temp & 0x10) {
+                result = -1;
+                dev_dbg(&I801_dev->dev, "Error: Failed bus transaction\n");
+        }
+
+        if (temp & 0x08) {
+                result = -1;
+                dev_err(&I801_dev->dev, "Bus collision! SMBus may be locked "
+                        "until next hard reset. (sorry!)\n");
+                /* Clock stops and slave is stuck in mid-transmission */
+        }
+
+        if (temp & 0x04) {
+                result = -1;
+                dev_dbg(&I801_dev->dev, "Error: no response!\n");
+        }
+
+        if ((inb_p(SMBHSTSTS) & 0x1f) != 0x00)
+                outb_p(inb(SMBHSTSTS), SMBHSTSTS);
+
+        if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
+                dev_dbg(&I801_dev->dev, "Failed reset at end of transaction"
+                        "(%02x)\n", temp);
+        }
+        dev_dbg(&I801_dev->dev, "Transaction (post): CNT=%02x, CMD=%02x, "
+                "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
+                inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
+                inb_p(SMBHSTDAT1));
+        return result;
+}
+
+/* All-inclusive block transaction function */
+static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
+                                  int command)
+{
+        int i, len;
+        int smbcmd;
+        int temp;
+        int result = 0;
+        int timeout;
+        unsigned char hostc, errmask;
+
+        if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
+                if (read_write == I2C_SMBUS_WRITE) {
+                        /* set I2C_EN bit in configuration register */
+                        pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
+                        pci_write_config_byte(I801_dev, SMBHSTCFG,
+                                              hostc | SMBHSTCFG_I2C_EN);
+                } else {
+                        dev_err(&I801_dev->dev,
+                                "I2C_SMBUS_I2C_BLOCK_READ not DB!\n");
+                        return -1;
+                }
+        }
+
+        if (read_write == I2C_SMBUS_WRITE) {
+                len = data->block[0];
+                if (len < 1)
+                        len = 1;
+                if (len > 32)
+                        len = 32;
+                outb_p(len, SMBHSTDAT0);
+                outb_p(data->block[1], SMBBLKDAT);
+        } else {
+                len = 32;       /* max for reads */
+        }
+
+        if(isich4 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
+                /* set 32 byte buffer */
+        }
+
+        for (i = 1; i <= len; i++) {
+                if (i == len && read_write == I2C_SMBUS_READ)
+                        smbcmd = I801_BLOCK_LAST;
+                else
+                        smbcmd = I801_BLOCK_DATA;
+                outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT);
+
+                dev_dbg(&I801_dev->dev, "Block (pre %d): CNT=%02x, CMD=%02x, "
+                        "ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
+                        inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
+                        inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
+
+                /* Make sure the SMBus host is ready to start transmitting */
+                temp = inb_p(SMBHSTSTS);
+                if (i == 1) {
+                        /* Erronenous conditions before transaction: 
+                         * Byte_Done, Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
+                        errmask=0x9f; 
+                } else {
+                        /* Erronenous conditions during transaction: 
+                         * Failed, Bus_Err, Dev_Err, Intr */
+                        errmask=0x1e; 
+                }
+                if (temp & errmask) {
+                        dev_dbg(&I801_dev->dev, "SMBus busy (%02x). "
+                                "Resetting... \n", temp);
+                        outb_p(temp, SMBHSTSTS);
+                        if (((temp = inb_p(SMBHSTSTS)) & errmask) != 0x00) {
+                                dev_err(&I801_dev->dev,
+                                        "Reset failed! (%02x)\n", temp);
+                                result = -1;
+                                goto END;
+                        }
+                        if (i != 1) {
+                                /* if die in middle of block transaction, fail */
+                                result = -1;
+                                goto END;
+                        }
+                }
+
+                if (i == 1)
+                        outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);
+
+                /* We will always wait for a fraction of a second! */
+                timeout = 0;
+                do {
+                        temp = inb_p(SMBHSTSTS);
+                        msleep(1);
+                }
+                    while ((!(temp & 0x80))
+                           && (timeout++ < MAX_TIMEOUT));
+
+                /* If the SMBus is still busy, we give up */
+                if (timeout >= MAX_TIMEOUT) {
+                        result = -1;
+                        dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
+                }
+
+                if (temp & 0x10) {
+                        result = -1;
+                        dev_dbg(&I801_dev->dev,
+                                "Error: Failed bus transaction\n");
+                } else if (temp & 0x08) {
+                        result = -1;
+                        dev_err(&I801_dev->dev, "Bus collision!\n");
+                } else if (temp & 0x04) {
+                        result = -1;
+                        dev_dbg(&I801_dev->dev, "Error: no response!\n");
+                }
+
+                if (i == 1 && read_write == I2C_SMBUS_READ) {
+                        len = inb_p(SMBHSTDAT0);
+                        if (len < 1)
+                                len = 1;
+                        if (len > 32)
+                                len = 32;
+                        data->block[0] = len;
+                }
+
+                /* Retrieve/store value in SMBBLKDAT */
+                if (read_write == I2C_SMBUS_READ)
+                        data->block[i] = inb_p(SMBBLKDAT);
+                if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
+                        outb_p(data->block[i+1], SMBBLKDAT);
+                if ((temp & 0x9e) != 0x00)
+                        outb_p(temp, SMBHSTSTS);  /* signals SMBBLKDAT ready */
+
+                if ((temp = (0x1e & inb_p(SMBHSTSTS))) != 0x00) {
+                        dev_dbg(&I801_dev->dev,
+                                "Bad status (%02x) at end of transaction\n",
+                                temp);
+                }
+                dev_dbg(&I801_dev->dev, "Block (post %d): CNT=%02x, CMD=%02x, "
+                        "ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
+                        inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
+                        inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
+
+                if (result < 0)
+                        goto END;
+        }
+
+#ifdef HAVE_PEC
+        if(isich4 && command == I2C_SMBUS_BLOCK_DATA_PEC) {
+                /* wait for INTR bit as advised by Intel */
+                timeout = 0;
+                do {
+                        temp = inb_p(SMBHSTSTS);
+                        msleep(1);
+                } while ((!(temp & 0x02))
+                           && (timeout++ < MAX_TIMEOUT));
+
+                if (timeout >= MAX_TIMEOUT) {
+                        dev_dbg(&I801_dev->dev, "PEC Timeout!\n");
+                }
+                outb_p(temp, SMBHSTSTS); 
+        }
+#endif
+        result = 0;
+END:
+        if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
+                /* restore saved configuration register value */
+                pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
+        }
+        return result;
+}
+
+/* Return -1 on error. */
+static s32 i801_access(struct i2c_adapter * adap, u16 addr,
+                       unsigned short flags, char read_write, u8 command,
+                       int size, union i2c_smbus_data * data)
+{
+        int hwpec = 0;
+        int block = 0;
+        int ret, xact = 0;
+
+#ifdef HAVE_PEC
+        if(isich4)
+                hwpec = (flags & I2C_CLIENT_PEC) != 0;
+#endif
+
+        switch (size) {
+        case I2C_SMBUS_QUICK:
+                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
+                       SMBHSTADD);
+                xact = I801_QUICK;
+                break;
+        case I2C_SMBUS_BYTE:
+                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
+                       SMBHSTADD);
+                if (read_write == I2C_SMBUS_WRITE)
+                        outb_p(command, SMBHSTCMD);
+                xact = I801_BYTE;
+                break;
+        case I2C_SMBUS_BYTE_DATA:
+                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
+                       SMBHSTADD);
+                outb_p(command, SMBHSTCMD);
+                if (read_write == I2C_SMBUS_WRITE)
+                        outb_p(data->byte, SMBHSTDAT0);
+                xact = I801_BYTE_DATA;
+                break;
+        case I2C_SMBUS_WORD_DATA:
+                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
+                       SMBHSTADD);
+                outb_p(command, SMBHSTCMD);
+                if (read_write == I2C_SMBUS_WRITE) {
+                        outb_p(data->word & 0xff, SMBHSTDAT0);
+                        outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
+                }
+                xact = I801_WORD_DATA;
+                break;
+        case I2C_SMBUS_BLOCK_DATA:
+        case I2C_SMBUS_I2C_BLOCK_DATA:
+#ifdef HAVE_PEC
+        case I2C_SMBUS_BLOCK_DATA_PEC:
+                if(hwpec && size == I2C_SMBUS_BLOCK_DATA)
+                        size = I2C_SMBUS_BLOCK_DATA_PEC;
+#endif
+                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
+                       SMBHSTADD);
+                outb_p(command, SMBHSTCMD);
+                block = 1;
+                break;
+        case I2C_SMBUS_PROC_CALL:
+        default:
+                dev_err(&I801_dev->dev, "Unsupported transaction %d\n", size);
+                return -1;
+        }
+
+#ifdef HAVE_PEC
+        if(isich4 && hwpec) {
+                if(size != I2C_SMBUS_QUICK &&
+                   size != I2C_SMBUS_I2C_BLOCK_DATA)
+                        outb_p(1, SMBAUXCTL);   /* enable HW PEC */
+        }
+#endif
+        if(block)
+                ret = i801_block_transaction(data, read_write, size);
+        else {
+                outb_p(xact | ENABLE_INT9, SMBHSTCNT);
+                ret = i801_transaction();
+        }
+
+#ifdef HAVE_PEC
+        if(isich4 && hwpec) {
+                if(size != I2C_SMBUS_QUICK &&
+                   size != I2C_SMBUS_I2C_BLOCK_DATA)
+                        outb_p(0, SMBAUXCTL);
+        }
+#endif
+
+        if(block)
+                return ret;
+        if(ret)
+                return -1;
+        if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
+                return 0;
+
+        switch (xact & 0x7f) {
+        case I801_BYTE: /* Result put in SMBHSTDAT0 */
+        case I801_BYTE_DATA:
+                data->byte = inb_p(SMBHSTDAT0);
+                break;
+        case I801_WORD_DATA:
+                data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
+                break;
+        }
+        return 0;
+}
+
+
+static u32 i801_func(struct i2c_adapter *adapter)
+{
+        return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
+            I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
+            I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK
+#ifdef HAVE_PEC
+             | (isich4 ? I2C_FUNC_SMBUS_BLOCK_DATA_PEC |
+                         I2C_FUNC_SMBUS_HWPEC_CALC
+                       : 0)
+#endif
+            ;
+}
+
+static struct i2c_algorithm smbus_algorithm = {
+        .name           = "Non-I2C SMBus adapter",
+        .id             = I2C_ALGO_SMBUS,
+        .smbus_xfer     = i801_access,
+        .functionality  = i801_func,
+};
+
+static struct i2c_adapter i801_adapter = {
+        .owner          = THIS_MODULE,
+        .class          = I2C_CLASS_HWMON,
+        .algo           = &smbus_algorithm,
+        .name           = "unset",
+};
+
+static struct pci_device_id i801_ids[] = {
+        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
+        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
+        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
+        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
+        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
+        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
+        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
+        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
+        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
+        { 0, }
+};
+
+MODULE_DEVICE_TABLE (pci, i801_ids);
+
+static int __devinit i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
+{
+
+        if (i801_setup(dev)) {
+                dev_warn(&dev->dev,
+                        "I801 not detected, module not inserted.\n");
+                return -ENODEV;
+        }
+
+        /* set up the driverfs linkage to our parent device */
+        i801_adapter.dev.parent = &dev->dev;
+
+        snprintf(i801_adapter.name, I2C_NAME_SIZE,
+                "SMBus I801 adapter at %04x", i801_smba);
+        return i2c_add_adapter(&i801_adapter);
+}
+
+static void __devexit i801_remove(struct pci_dev *dev)
+{
+        i2c_del_adapter(&i801_adapter);
+        release_region(i801_smba, (isich4 ? 16 : 8));
+}
+
+static struct pci_driver i801_driver = {
+        .name           = "i801_smbus",
+        .id_table       = i801_ids,
+        .probe          = i801_probe,
+        .remove         = __devexit_p(i801_remove),
+};
+
+static int __init i2c_i801_init(void)
+{
+        return pci_register_driver(&i801_driver);
+}
+
+static void __exit i2c_i801_exit(void)
+{
+        pci_unregister_driver(&i801_driver);
+}
+
+MODULE_AUTHOR ("Frodo Looijaard <frodol@dds.nl>, "
+                "Philip Edelbrock <phil@netroedge.com>, "
+                "and Mark D. Studebaker <mdsxyz123@yahoo.com>");
+MODULE_DESCRIPTION("I801 SMBus driver");
+MODULE_LICENSE("GPL");
+
+module_init(i2c_i801_init);
+module_exit(i2c_i801_exit);
diff --git a/drivers/i2c/busses/i2c-i810.c b/drivers/i2c/busses/i2c-i810.c
new file mode 100644
index 000000000000..ef358bd9c3da
--- /dev/null
+++ b/drivers/i2c/busses/i2c-i810.c
@@ -0,0 +1,260 @@
+/*
+    i2c-i810.c - Part of lm_sensors, Linux kernel modules for hardware
+              monitoring
+    Copyright (c) 1998, 1999, 2000  Frodo Looijaard <frodol@dds.nl>,
+    Philip Edelbrock <phil@netroedge.com>,
+    Ralph Metzler <rjkm@thp.uni-koeln.de>, and
+    Mark D. Studebaker <mdsxyz123@yahoo.com>
+    
+    Based on code written by Ralph Metzler <rjkm@thp.uni-koeln.de> and
+    Simon Vogl
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+/*
+   This interfaces to the I810/I815 to provide access to
+   the DDC Bus and the I2C Bus.
+
+   SUPPORTED DEVICES    PCI ID
+   i810AA               7121           
+   i810AB               7123           
+   i810E                7125           
+   i815                 1132           
+*/
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/i2c.h>
+#include <linux/i2c-algo-bit.h>
+#include <asm/io.h>
+
+/* GPIO register locations */
+#define I810_IOCONTROL_OFFSET   0x5000
+#define I810_HVSYNC             0x00    /* not used */
+#define I810_GPIOA              0x10
+#define I810_GPIOB              0x14
+
+/* bit locations in the registers */
+#define SCL_DIR_MASK            0x0001
+#define SCL_DIR                 0x0002
+#define SCL_VAL_MASK            0x0004
+#define SCL_VAL_OUT             0x0008
+#define SCL_VAL_IN              0x0010
+#define SDA_DIR_MASK            0x0100
+#define SDA_DIR                 0x0200
+#define SDA_VAL_MASK            0x0400
+#define SDA_VAL_OUT             0x0800
+#define SDA_VAL_IN              0x1000
+
+/* initialization states */
+#define INIT1                   0x1
+#define INIT2                   0x2
+#define INIT3                   0x4
+
+/* delays */
+#define CYCLE_DELAY             10
+#define TIMEOUT                 (HZ / 2)
+
+static void __iomem *ioaddr;
+
+/* The i810 GPIO registers have individual masks for each bit
+   so we never have to read before writing. Nice. */
+
+static void bit_i810i2c_setscl(void *data, int val)
+{
+        writel((val ? SCL_VAL_OUT : 0) | SCL_DIR | SCL_DIR_MASK | SCL_VAL_MASK,
+             ioaddr + I810_GPIOB);
+        readl(ioaddr + I810_GPIOB);     /* flush posted write */
+}
+
+static void bit_i810i2c_setsda(void *data, int val)
+{
+        writel((val ? SDA_VAL_OUT : 0) | SDA_DIR | SDA_DIR_MASK | SDA_VAL_MASK,
+             ioaddr + I810_GPIOB);
+        readl(ioaddr + I810_GPIOB);     /* flush posted write */
+}
+
+/* The GPIO pins are open drain, so the pins could always remain outputs.
+   However, some chip versions don't latch the inputs unless they
+   are set as inputs.
+   We rely on the i2c-algo-bit routines to set the pins high before
+   reading the input from other chips. Following guidance in the 815
+   prog. ref. guide, we do a "dummy write" of 0 to the register before
+   reading which forces the input value to be latched. We presume this
+   applies to the 810 as well; shouldn't hurt anyway. This is necessary to get
+   i2c_algo_bit bit_test=1 to pass. */
+
+static int bit_i810i2c_getscl(void *data)
+{
+        writel(SCL_DIR_MASK, ioaddr + I810_GPIOB);
+        writel(0, ioaddr + I810_GPIOB);
+        return (0 != (readl(ioaddr + I810_GPIOB) & SCL_VAL_IN));
+}
+
+static int bit_i810i2c_getsda(void *data)
+{
+        writel(SDA_DIR_MASK, ioaddr + I810_GPIOB);
+        writel(0, ioaddr + I810_GPIOB);
+        return (0 != (readl(ioaddr + I810_GPIOB) & SDA_VAL_IN));
+}
+
+static void bit_i810ddc_setscl(void *data, int val)
+{
+        writel((val ? SCL_VAL_OUT : 0) | SCL_DIR | SCL_DIR_MASK | SCL_VAL_MASK,
+             ioaddr + I810_GPIOA);
+        readl(ioaddr + I810_GPIOA);     /* flush posted write */
+}
+
+static void bit_i810ddc_setsda(void *data, int val)
+{
+        writel((val ? SDA_VAL_OUT : 0) | SDA_DIR | SDA_DIR_MASK | SDA_VAL_MASK,
+             ioaddr + I810_GPIOA);
+        readl(ioaddr + I810_GPIOA);     /* flush posted write */
+}
+
+static int bit_i810ddc_getscl(void *data)
+{
+        writel(SCL_DIR_MASK, ioaddr + I810_GPIOA);
+        writel(0, ioaddr + I810_GPIOA);
+        return (0 != (readl(ioaddr + I810_GPIOA) & SCL_VAL_IN));
+}
+
+static int bit_i810ddc_getsda(void *data)
+{
+        writel(SDA_DIR_MASK, ioaddr + I810_GPIOA);
+        writel(0, ioaddr + I810_GPIOA);
+        return (0 != (readl(ioaddr + I810_GPIOA) & SDA_VAL_IN));
+}
+
+static int config_i810(struct pci_dev *dev)
+{
+        unsigned long cadr;
+
+        /* map I810 memory */
+        cadr = dev->resource[1].start;
+        cadr += I810_IOCONTROL_OFFSET;
+        cadr &= PCI_BASE_ADDRESS_MEM_MASK;
+        ioaddr = ioremap_nocache(cadr, 0x1000);
+        if (ioaddr) {
+                bit_i810i2c_setscl(NULL, 1);
+                bit_i810i2c_setsda(NULL, 1);
+                bit_i810ddc_setscl(NULL, 1);
+                bit_i810ddc_setsda(NULL, 1);
+                return 0;
+        }
+        return -ENODEV;
+}
+
+static struct i2c_algo_bit_data i810_i2c_bit_data = {
+        .setsda         = bit_i810i2c_setsda,
+        .setscl         = bit_i810i2c_setscl,
+        .getsda         = bit_i810i2c_getsda,
+        .getscl         = bit_i810i2c_getscl,
+        .udelay         = CYCLE_DELAY,
+        .mdelay         = CYCLE_DELAY,
+        .timeout        = TIMEOUT,
+};
+
+static struct i2c_adapter i810_i2c_adapter = {
+        .owner          = THIS_MODULE,
+        .name           = "I810/I815 I2C Adapter",
+        .algo_data      = &i810_i2c_bit_data,
+};
+
+static struct i2c_algo_bit_data i810_ddc_bit_data = {
+        .setsda         = bit_i810ddc_setsda,
+        .setscl         = bit_i810ddc_setscl,
+        .getsda         = bit_i810ddc_getsda,
+        .getscl         = bit_i810ddc_getscl,
+        .udelay         = CYCLE_DELAY,
+        .mdelay         = CYCLE_DELAY,
+        .timeout        = TIMEOUT,
+};
+
+static struct i2c_adapter i810_ddc_adapter = {
+        .owner          = THIS_MODULE,
+        .name           = "I810/I815 DDC Adapter",
+        .algo_data      = &i810_ddc_bit_data,
+};
+
+static struct pci_device_id i810_ids[] __devinitdata = {
+        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG1) },
+        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3) },
+        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_IG) },
+        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC) },
+        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_IG) },
+        { 0, },
+};
+
+MODULE_DEVICE_TABLE (pci, i810_ids);
+
+static int __devinit i810_probe(struct pci_dev *dev, const struct pci_device_id *id)
+{
+        int retval;
+
+        retval = config_i810(dev);
+        if (retval)
+                return retval;
+        dev_info(&dev->dev, "i810/i815 i2c device found.\n");
+
+        /* set up the sysfs linkage to our parent device */
+        i810_i2c_adapter.dev.parent = &dev->dev;
+        i810_ddc_adapter.dev.parent = &dev->dev;
+
+        retval = i2c_bit_add_bus(&i810_i2c_adapter);
+        if (retval)
+                return retval;
+        retval = i2c_bit_add_bus(&i810_ddc_adapter);
+        if (retval)
+                i2c_bit_del_bus(&i810_i2c_adapter);
+        return retval;
+}
+
+static void __devexit i810_remove(struct pci_dev *dev)
+{
+        i2c_bit_del_bus(&i810_ddc_adapter);
+        i2c_bit_del_bus(&i810_i2c_adapter);
+        iounmap(ioaddr);
+}
+
+static struct pci_driver i810_driver = {
+        .name           = "i810_smbus",
+        .id_table       = i810_ids,
+        .probe          = i810_probe,
+        .remove         = __devexit_p(i810_remove),
+};
+
+static int __init i2c_i810_init(void)
+{
+        return pci_register_driver(&i810_driver);
+}
+
+static void __exit i2c_i810_exit(void)
+{
+        pci_unregister_driver(&i810_driver);
+}
+
+MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl>, "
+                "Philip Edelbrock <phil@netroedge.com>, "
+                "Ralph Metzler <rjkm@thp.uni-koeln.de>, "
+                "and Mark D. Studebaker <mdsxyz123@yahoo.com>");
+MODULE_DESCRIPTION("I810/I815 I2C/DDC driver");
+MODULE_LICENSE("GPL");
+
+module_init(i2c_i810_init);
+module_exit(i2c_i810_exit);
diff --git a/drivers/i2c/busses/i2c-ibm_iic.c b/drivers/i2c/busses/i2c-ibm_iic.c
new file mode 100644
index 000000000000..bb885215c08d
--- /dev/null
+++ b/drivers/i2c/busses/i2c-ibm_iic.c
@@ -0,0 +1,819 @@
+/*
+ * drivers/i2c/i2c-ibm_iic.c
+ *
+ * Support for the IIC peripheral on IBM PPC 4xx
+ *
+ * Copyright (c) 2003, 2004 Zultys Technologies.
+ * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
+ *
+ * Based on original work by 
+ *      Ian DaSilva  <idasilva@mvista.com>
+ *      Armin Kuster <akuster@mvista.com>
+ *      Matt Porter  <mporter@mvista.com>
+ *
+ *      Copyright 2000-2003 MontaVista Software Inc.
+ *
+ * Original driver version was highly leveraged from i2c-elektor.c
+ *
+ *      Copyright 1995-97 Simon G. Vogl
+ *                1998-99 Hans Berglund
+ *
+ *      With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> 
+ *      and even Frodo Looijaard <frodol@dds.nl>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/ioport.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <asm/irq.h>
+#include <asm/io.h>
+#include <linux/i2c.h>
+#include <linux/i2c-id.h>
+#include <asm/ocp.h>
+#include <asm/ibm4xx.h>
+
+#include "i2c-ibm_iic.h"
+
+#define DRIVER_VERSION "2.1"
+
+MODULE_DESCRIPTION("IBM IIC driver v" DRIVER_VERSION);
+MODULE_LICENSE("GPL");
+
+static int iic_force_poll;
+module_param(iic_force_poll, bool, 0);
+MODULE_PARM_DESC(iic_force_poll, "Force polling mode");
+
+static int iic_force_fast;
+module_param(iic_force_fast, bool, 0);
+MODULE_PARM_DESC(iic_fast_poll, "Force fast mode (400 kHz)");
+
+#define DBG_LEVEL 0
+
+#ifdef DBG
+#undef DBG
+#endif
+
+#ifdef DBG2
+#undef DBG2
+#endif
+
+#if DBG_LEVEL > 0
+#  define DBG(f,x...)   printk(KERN_DEBUG "ibm-iic" f, ##x)
+#else
+#  define DBG(f,x...)   ((void)0)
+#endif
+#if DBG_LEVEL > 1
+#  define DBG2(f,x...)  DBG(f, ##x)
+#else
+#  define DBG2(f,x...)  ((void)0)
+#endif
+#if DBG_LEVEL > 2
+static void dump_iic_regs(const char* header, struct ibm_iic_private* dev)
+{
+        volatile struct iic_regs __iomem *iic = dev->vaddr;
+        printk(KERN_DEBUG "ibm-iic%d: %s\n", dev->idx, header);
+        printk(KERN_DEBUG "  cntl     = 0x%02x, mdcntl = 0x%02x\n"
+               KERN_DEBUG "  sts      = 0x%02x, extsts = 0x%02x\n"
+               KERN_DEBUG "  clkdiv   = 0x%02x, xfrcnt = 0x%02x\n"
+               KERN_DEBUG "  xtcntlss = 0x%02x, directcntl = 0x%02x\n",
+                in_8(&iic->cntl), in_8(&iic->mdcntl), in_8(&iic->sts), 
+                in_8(&iic->extsts), in_8(&iic->clkdiv), in_8(&iic->xfrcnt), 
+                in_8(&iic->xtcntlss), in_8(&iic->directcntl));
+}
+#  define DUMP_REGS(h,dev)      dump_iic_regs((h),(dev))
+#else
+#  define DUMP_REGS(h,dev)      ((void)0)
+#endif
+
+/* Bus timings (in ns) for bit-banging */
+static struct i2c_timings {
+        unsigned int hd_sta;
+        unsigned int su_sto;
+        unsigned int low;
+        unsigned int high;
+        unsigned int buf;
+} timings [] = {
+/* Standard mode (100 KHz) */
+{
+        .hd_sta = 4000,
+        .su_sto = 4000,
+        .low    = 4700,
+        .high   = 4000,
+        .buf    = 4700,
+},
+/* Fast mode (400 KHz) */
+{
+        .hd_sta = 600,
+        .su_sto = 600,
+        .low    = 1300,
+        .high   = 600,
+        .buf    = 1300,
+}};
+
+/* Enable/disable interrupt generation */
+static inline void iic_interrupt_mode(struct ibm_iic_private* dev, int enable)
+{
+        out_8(&dev->vaddr->intmsk, enable ? INTRMSK_EIMTC : 0);
+}
+ 
+/*
+ * Initialize IIC interface.
+ */
+static void iic_dev_init(struct ibm_iic_private* dev)
+{
+        volatile struct iic_regs __iomem *iic = dev->vaddr;
+
+        DBG("%d: init\n", dev->idx);
+        
+        /* Clear master address */
+        out_8(&iic->lmadr, 0);
+        out_8(&iic->hmadr, 0);
+
+        /* Clear slave address */
+        out_8(&iic->lsadr, 0);
+        out_8(&iic->hsadr, 0);
+
+        /* Clear status & extended status */
+        out_8(&iic->sts, STS_SCMP | STS_IRQA);
+        out_8(&iic->extsts, EXTSTS_IRQP | EXTSTS_IRQD | EXTSTS_LA
+                            | EXTSTS_ICT | EXTSTS_XFRA);
+
+        /* Set clock divider */
+        out_8(&iic->clkdiv, dev->clckdiv);
+
+        /* Clear transfer count */
+        out_8(&iic->xfrcnt, 0);
+
+        /* Clear extended control and status */
+        out_8(&iic->xtcntlss, XTCNTLSS_SRC | XTCNTLSS_SRS | XTCNTLSS_SWC
+                            | XTCNTLSS_SWS);
+
+        /* Clear control register */
+        out_8(&iic->cntl, 0);
+        
+        /* Enable interrupts if possible */
+        iic_interrupt_mode(dev, dev->irq >= 0);
+
+        /* Set mode control */
+        out_8(&iic->mdcntl, MDCNTL_FMDB | MDCNTL_EINT | MDCNTL_EUBS
+                            | (dev->fast_mode ? MDCNTL_FSM : 0));
+
+        DUMP_REGS("iic_init", dev);
+}
+
+/* 
+ * Reset IIC interface
+ */
+static void iic_dev_reset(struct ibm_iic_private* dev)
+{
+        volatile struct iic_regs __iomem *iic = dev->vaddr;
+        int i;
+        u8 dc;
+        
+        DBG("%d: soft reset\n", dev->idx);
+        DUMP_REGS("reset", dev);
+        
+        /* Place chip in the reset state */
+        out_8(&iic->xtcntlss, XTCNTLSS_SRST);
+        
+        /* Check if bus is free */
+        dc = in_8(&iic->directcntl);    
+        if (!DIRCTNL_FREE(dc)){
+                DBG("%d: trying to regain bus control\n", dev->idx);
+        
+                /* Try to set bus free state */
+                out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);    
+        
+                /* Wait until we regain bus control */
+                for (i = 0; i < 100; ++i){
+                        dc = in_8(&iic->directcntl);
+                        if (DIRCTNL_FREE(dc))
+                                break;
+                        
+                        /* Toggle SCL line */
+                        dc ^= DIRCNTL_SCC;
+                        out_8(&iic->directcntl, dc);
+                        udelay(10);
+                        dc ^= DIRCNTL_SCC;
+                        out_8(&iic->directcntl, dc);
+                        
+                        /* be nice */
+                        cond_resched();
+                }
+        }
+        
+        /* Remove reset */
+        out_8(&iic->xtcntlss, 0);
+        
+        /* Reinitialize interface */
+        iic_dev_init(dev);
+}
+
+/*
+ * Do 0-length transaction using bit-banging through IIC_DIRECTCNTL register.
+ */
+
+/* Wait for SCL and/or SDA to be high */
+static int iic_dc_wait(volatile struct iic_regs __iomem *iic, u8 mask)
+{
+        unsigned long x = jiffies + HZ / 28 + 2;
+        while ((in_8(&iic->directcntl) & mask) != mask){
+                if (unlikely(time_after(jiffies, x)))
+                        return -1;
+                cond_resched();
+        }
+        return 0;
+}
+
+static int iic_smbus_quick(struct ibm_iic_private* dev, const struct i2c_msg* p)
+{
+        volatile struct iic_regs __iomem *iic = dev->vaddr;
+        const struct i2c_timings* t = &timings[dev->fast_mode ? 1 : 0];
+        u8 mask, v, sda;
+        int i, res;
+
+        /* Only 7-bit addresses are supported */
+        if (unlikely(p->flags & I2C_M_TEN)){
+                DBG("%d: smbus_quick - 10 bit addresses are not supported\n",
+                        dev->idx);
+                return -EINVAL;
+        }
+
+        DBG("%d: smbus_quick(0x%02x)\n", dev->idx, p->addr);
+
+        /* Reset IIC interface */
+        out_8(&iic->xtcntlss, XTCNTLSS_SRST);
+
+        /* Wait for bus to become free */
+        out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
+        if (unlikely(iic_dc_wait(iic, DIRCNTL_MSDA | DIRCNTL_MSC)))
+                goto err;
+        ndelay(t->buf);
+
+        /* START */
+        out_8(&iic->directcntl, DIRCNTL_SCC);
+        sda = 0;
+        ndelay(t->hd_sta);
+
+        /* Send address */
+        v = (u8)((p->addr << 1) | ((p->flags & I2C_M_RD) ? 1 : 0));
+        for (i = 0, mask = 0x80; i < 8; ++i, mask >>= 1){
+                out_8(&iic->directcntl, sda);
+                ndelay(t->low / 2);
+                sda = (v & mask) ? DIRCNTL_SDAC : 0;
+                out_8(&iic->directcntl, sda);
+                ndelay(t->low / 2);
+
+                out_8(&iic->directcntl, DIRCNTL_SCC | sda);
+                if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC)))
+                        goto err;
+                ndelay(t->high);
+        }
+
+        /* ACK */
+        out_8(&iic->directcntl, sda);
+        ndelay(t->low / 2);
+        out_8(&iic->directcntl, DIRCNTL_SDAC);
+        ndelay(t->low / 2);
+        out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
+        if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC)))
+                goto err;
+        res = (in_8(&iic->directcntl) & DIRCNTL_MSDA) ? -EREMOTEIO : 1;
+        ndelay(t->high);
+
+        /* STOP */
+        out_8(&iic->directcntl, 0);
+        ndelay(t->low);
+        out_8(&iic->directcntl, DIRCNTL_SCC);
+        if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC)))
+                goto err;
+        ndelay(t->su_sto);
+        out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
+
+        ndelay(t->buf);
+
+        DBG("%d: smbus_quick -> %s\n", dev->idx, res ? "NACK" : "ACK");
+out:
+        /* Remove reset */
+        out_8(&iic->xtcntlss, 0);
+
+        /* Reinitialize interface */
+        iic_dev_init(dev);
+
+        return res;
+err:
+        DBG("%d: smbus_quick - bus is stuck\n", dev->idx);
+        res = -EREMOTEIO;
+        goto out;
+}
+
+/*
+ * IIC interrupt handler
+ */
+static irqreturn_t iic_handler(int irq, void *dev_id, struct pt_regs *regs)
+{
+        struct ibm_iic_private* dev = (struct ibm_iic_private*)dev_id;
+        volatile struct iic_regs __iomem *iic = dev->vaddr;
+        
+        DBG2("%d: irq handler, STS = 0x%02x, EXTSTS = 0x%02x\n", 
+             dev->idx, in_8(&iic->sts), in_8(&iic->extsts));
+        
+        /* Acknowledge IRQ and wakeup iic_wait_for_tc */
+        out_8(&iic->sts, STS_IRQA | STS_SCMP);
+        wake_up_interruptible(&dev->wq);
+        
+        return IRQ_HANDLED;
+}
+
+/*
+ * Get master transfer result and clear errors if any.
+ * Returns the number of actually transferred bytes or error (<0)
+ */
+static int iic_xfer_result(struct ibm_iic_private* dev)
+{
+        volatile struct iic_regs __iomem *iic = dev->vaddr;     
+        
+        if (unlikely(in_8(&iic->sts) & STS_ERR)){
+                DBG("%d: xfer error, EXTSTS = 0x%02x\n", dev->idx, 
+                        in_8(&iic->extsts));
+                                
+                /* Clear errors and possible pending IRQs */
+                out_8(&iic->extsts, EXTSTS_IRQP | EXTSTS_IRQD | 
+                        EXTSTS_LA | EXTSTS_ICT | EXTSTS_XFRA);
+                        
+                /* Flush master data buffer */
+                out_8(&iic->mdcntl, in_8(&iic->mdcntl) | MDCNTL_FMDB);
+                
+                /* Is bus free?
+                 * If error happened during combined xfer
+                 * IIC interface is usually stuck in some strange
+                 * state, the only way out - soft reset.
+                 */
+                if ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){
+                        DBG("%d: bus is stuck, resetting\n", dev->idx);
+                        iic_dev_reset(dev);
+                }
+                return -EREMOTEIO;
+        }
+        else
+                return in_8(&iic->xfrcnt) & XFRCNT_MTC_MASK;
+}
+
+/*
+ * Try to abort active transfer.
+ */
+static void iic_abort_xfer(struct ibm_iic_private* dev)
+{
+        volatile struct iic_regs __iomem *iic = dev->vaddr;
+        unsigned long x;
+        
+        DBG("%d: iic_abort_xfer\n", dev->idx);
+        
+        out_8(&iic->cntl, CNTL_HMT);
+        
+        /*
+         * Wait for the abort command to complete.
+         * It's not worth to be optimized, just poll (timeout >= 1 tick)
+         */
+        x = jiffies + 2;
+        while ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){
+                if (time_after(jiffies, x)){
+                        DBG("%d: abort timeout, resetting...\n", dev->idx);
+                        iic_dev_reset(dev);
+                        return;
+                }
+                schedule();
+        }
+
+        /* Just to clear errors */
+        iic_xfer_result(dev);
+}
+
+/*
+ * Wait for master transfer to complete.
+ * It puts current process to sleep until we get interrupt or timeout expires.
+ * Returns the number of transferred bytes or error (<0)
+ */
+static int iic_wait_for_tc(struct ibm_iic_private* dev){
+        
+        volatile struct iic_regs __iomem *iic = dev->vaddr;
+        int ret = 0;
+        
+        if (dev->irq >= 0){
+                /* Interrupt mode */
+                ret = wait_event_interruptible_timeout(dev->wq, 
+                        !(in_8(&iic->sts) & STS_PT), dev->adap.timeout * HZ);
+
+                if (unlikely(ret < 0))
+                        DBG("%d: wait interrupted\n", dev->idx);
+                else if (unlikely(in_8(&iic->sts) & STS_PT)){
+                        DBG("%d: wait timeout\n", dev->idx);
+                        ret = -ETIMEDOUT;
+                }
+        }
+        else {
+                /* Polling mode */
+                unsigned long x = jiffies + dev->adap.timeout * HZ;
+                
+                while (in_8(&iic->sts) & STS_PT){
+                        if (unlikely(time_after(jiffies, x))){
+                                DBG("%d: poll timeout\n", dev->idx);
+                                ret = -ETIMEDOUT;
+                                break;
+                        }
+                
+                        if (unlikely(signal_pending(current))){
+                                DBG("%d: poll interrupted\n", dev->idx);
+                                ret = -ERESTARTSYS;
+                                break;
+                        }
+                        schedule();
+                }       
+        }
+        
+        if (unlikely(ret < 0))
+                iic_abort_xfer(dev);
+        else
+                ret = iic_xfer_result(dev);
+        
+        DBG2("%d: iic_wait_for_tc -> %d\n", dev->idx, ret);
+        
+        return ret;
+}
+
+/*
+ * Low level master transfer routine
+ */
+static int iic_xfer_bytes(struct ibm_iic_private* dev, struct i2c_msg* pm, 
+                          int combined_xfer)
+{
+        volatile struct iic_regs __iomem *iic = dev->vaddr;
+        char* buf = pm->buf;
+        int i, j, loops, ret = 0;
+        int len = pm->len;
+
+        u8 cntl = (in_8(&iic->cntl) & CNTL_AMD) | CNTL_PT;
+        if (pm->flags & I2C_M_RD)
+                cntl |= CNTL_RW;
+        
+        loops = (len + 3) / 4;
+        for (i = 0; i < loops; ++i, len -= 4){
+                int count = len > 4 ? 4 : len;
+                u8 cmd = cntl | ((count - 1) << CNTL_TCT_SHIFT);
+                
+                if (!(cntl & CNTL_RW))
+                        for (j = 0; j < count; ++j)
+                                out_8((void __iomem *)&iic->mdbuf, *buf++);
+                
+                if (i < loops - 1)
+                        cmd |= CNTL_CHT;
+                else if (combined_xfer)
+                        cmd |= CNTL_RPST;
+                
+                DBG2("%d: xfer_bytes, %d, CNTL = 0x%02x\n", dev->idx, count, cmd);
+                
+                /* Start transfer */
+                out_8(&iic->cntl, cmd);
+                
+                /* Wait for completion */
+                ret = iic_wait_for_tc(dev);
+
+                if (unlikely(ret < 0))
+                        break;
+                else if (unlikely(ret != count)){
+                        DBG("%d: xfer_bytes, requested %d, transfered %d\n", 
+                                dev->idx, count, ret);
+                        
+                        /* If it's not a last part of xfer, abort it */
+                        if (combined_xfer || (i < loops - 1))
+                                iic_abort_xfer(dev);
+                                
+                        ret = -EREMOTEIO;
+                        break;                          
+                }
+                
+                if (cntl & CNTL_RW)
+                        for (j = 0; j < count; ++j)
+                                *buf++ = in_8((void __iomem *)&iic->mdbuf);
+        }
+        
+        return ret > 0 ? 0 : ret;
+}
+
+/*
+ * Set target slave address for master transfer
+ */
+static inline void iic_address(struct ibm_iic_private* dev, struct i2c_msg* msg)
+{
+        volatile struct iic_regs __iomem *iic = dev->vaddr;
+        u16 addr = msg->addr;
+        
+        DBG2("%d: iic_address, 0x%03x (%d-bit)\n", dev->idx, 
+                addr, msg->flags & I2C_M_TEN ? 10 : 7);
+        
+        if (msg->flags & I2C_M_TEN){
+            out_8(&iic->cntl, CNTL_AMD);
+            out_8(&iic->lmadr, addr);
+            out_8(&iic->hmadr, 0xf0 | ((addr >> 7) & 0x06));
+        }
+        else {
+            out_8(&iic->cntl, 0);
+            out_8(&iic->lmadr, addr << 1);
+        }
+}
+
+static inline int iic_invalid_address(const struct i2c_msg* p)
+{
+        return (p->addr > 0x3ff) || (!(p->flags & I2C_M_TEN) && (p->addr > 0x7f));
+}
+
+static inline int iic_address_neq(const struct i2c_msg* p1, 
+                                  const struct i2c_msg* p2)
+{
+        return (p1->addr != p2->addr) 
+                || ((p1->flags & I2C_M_TEN) != (p2->flags & I2C_M_TEN));
+} 
+
+/*
+ * Generic master transfer entrypoint. 
+ * Returns the number of processed messages or error (<0)
+ */
+static int iic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
+{
+        struct ibm_iic_private* dev = (struct ibm_iic_private*)(i2c_get_adapdata(adap));
+        volatile struct iic_regs __iomem *iic = dev->vaddr;
+        int i, ret = 0;
+        
+        DBG2("%d: iic_xfer, %d msg(s)\n", dev->idx, num);
+        
+        if (!num)
+                return 0;
+        
+        /* Check the sanity of the passed messages.
+         * Uhh, generic i2c layer is more suitable place for such code...
+         */
+        if (unlikely(iic_invalid_address(&msgs[0]))){
+                DBG("%d: invalid address 0x%03x (%d-bit)\n", dev->idx, 
+                        msgs[0].addr, msgs[0].flags & I2C_M_TEN ? 10 : 7);
+                return -EINVAL;
+        }               
+        for (i = 0; i < num; ++i){
+                if (unlikely(msgs[i].len <= 0)){
+                        if (num == 1 && !msgs[0].len){
+                                /* Special case for I2C_SMBUS_QUICK emulation.
+                                 * IBM IIC doesn't support 0-length transactions
+                                 * so we have to emulate them using bit-banging.
+                                 */
+                                return iic_smbus_quick(dev, &msgs[0]);
+                        }
+                        DBG("%d: invalid len %d in msg[%d]\n", dev->idx, 
+                                msgs[i].len, i);
+                        return -EINVAL;
+                }
+                if (unlikely(iic_address_neq(&msgs[0], &msgs[i]))){
+                        DBG("%d: invalid addr in msg[%d]\n", dev->idx, i);
+                        return -EINVAL;
+                }
+        }
+        
+        /* Check bus state */
+        if (unlikely((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE)){
+                DBG("%d: iic_xfer, bus is not free\n", dev->idx);
+                
+                /* Usually it means something serious has happend.
+                 * We *cannot* have unfinished previous transfer
+                 * so it doesn't make any sense to try to stop it.
+                 * Probably we were not able to recover from the 
+                 * previous error.
+                 * The only *reasonable* thing I can think of here
+                 * is soft reset.  --ebs
+                 */
+                iic_dev_reset(dev);
+                
+                if ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){
+                        DBG("%d: iic_xfer, bus is still not free\n", dev->idx);
+                        return -EREMOTEIO;
+                }
+        } 
+        else {
+                /* Flush master data buffer (just in case) */
+                out_8(&iic->mdcntl, in_8(&iic->mdcntl) | MDCNTL_FMDB);
+        }
+        
+        /* Load slave address */
+        iic_address(dev, &msgs[0]);
+        
+        /* Do real transfer */
+        for (i = 0; i < num && !ret; ++i)
+                ret = iic_xfer_bytes(dev, &msgs[i], i < num - 1);
+
+        return ret < 0 ? ret : num;
+}
+
+static u32 iic_func(struct i2c_adapter *adap)
+{
+        return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
+}
+
+static struct i2c_algorithm iic_algo = {
+        .name           = "IBM IIC algorithm",
+        .id             = I2C_ALGO_OCP,
+        .master_xfer    = iic_xfer,
+        .functionality  = iic_func
+};
+
+/*
+ * Calculates IICx_CLCKDIV value for a specific OPB clock frequency
+ */
+static inline u8 iic_clckdiv(unsigned int opb)
+{
+        /* Compatibility kludge, should go away after all cards
+         * are fixed to fill correct value for opbfreq.
+         * Previous driver version used hardcoded divider value 4,
+         * it corresponds to OPB frequency from the range (40, 50] MHz
+         */
+        if (!opb){
+                printk(KERN_WARNING "ibm-iic: using compatibility value for OPB freq,"
+                        " fix your board specific setup\n");
+                opb = 50000000;
+        }
+
+        /* Convert to MHz */
+        opb /= 1000000;
+        
+        if (opb < 20 || opb > 150){
+                printk(KERN_CRIT "ibm-iic: invalid OPB clock frequency %u MHz\n",
+                        opb);
+                opb = opb < 20 ? 20 : 150;
+        }
+        return (u8)((opb + 9) / 10 - 1);
+}
+
+/*
+ * Register single IIC interface
+ */
+static int __devinit iic_probe(struct ocp_device *ocp){
+
+        struct ibm_iic_private* dev;
+        struct i2c_adapter* adap;
+        struct ocp_func_iic_data* iic_data = ocp->def->additions;
+        int ret;
+        
+        if (!iic_data)
+                printk(KERN_WARNING"ibm-iic%d: missing additional data!\n",
+                        ocp->def->index);
+
+        if (!(dev = kmalloc(sizeof(*dev), GFP_KERNEL))){
+                printk(KERN_CRIT "ibm-iic%d: failed to allocate device data\n",
+                        ocp->def->index);
+                return -ENOMEM;
+        }
+
+        memset(dev, 0, sizeof(*dev));
+        dev->idx = ocp->def->index;
+        ocp_set_drvdata(ocp, dev);
+        
+        if (!(dev->vaddr = ioremap(ocp->def->paddr, sizeof(struct iic_regs)))){
+                printk(KERN_CRIT "ibm-iic%d: failed to ioremap device registers\n",
+                        dev->idx);
+                ret = -ENXIO;
+                goto fail2;
+        }
+        
+        init_waitqueue_head(&dev->wq);
+
+        dev->irq = iic_force_poll ? -1 : ocp->def->irq;
+        if (dev->irq >= 0){
+                /* Disable interrupts until we finish intialization,
+                   assumes level-sensitive IRQ setup...
+                 */
+                iic_interrupt_mode(dev, 0);
+                if (request_irq(dev->irq, iic_handler, 0, "IBM IIC", dev)){
+                        printk(KERN_ERR "ibm-iic%d: request_irq %d failed\n", 
+                                dev->idx, dev->irq);
+                        /* Fallback to the polling mode */      
+                        dev->irq = -1;
+                }
+        }
+        
+        if (dev->irq < 0)
+                printk(KERN_WARNING "ibm-iic%d: using polling mode\n", 
+                        dev->idx);
+                
+        /* Board specific settings */
+        dev->fast_mode = iic_force_fast ? 1 : (iic_data ? iic_data->fast_mode : 0);
+        
+        /* clckdiv is the same for *all* IIC interfaces, 
+         * but I'd rather make a copy than introduce another global. --ebs
+         */
+        dev->clckdiv = iic_clckdiv(ocp_sys_info.opb_bus_freq);
+        DBG("%d: clckdiv = %d\n", dev->idx, dev->clckdiv);
+        
+        /* Initialize IIC interface */
+        iic_dev_init(dev);
+        
+        /* Register it with i2c layer */
+        adap = &dev->adap;
+        strcpy(adap->name, "IBM IIC");
+        i2c_set_adapdata(adap, dev);
+        adap->id = I2C_HW_OCP | iic_algo.id;
+        adap->algo = &iic_algo;
+        adap->client_register = NULL;
+        adap->client_unregister = NULL;
+        adap->timeout = 1;
+        adap->retries = 1;
+
+        if ((ret = i2c_add_adapter(adap)) != 0){
+                printk(KERN_CRIT "ibm-iic%d: failed to register i2c adapter\n",
+                        dev->idx);
+                goto fail;
+        }
+        
+        printk(KERN_INFO "ibm-iic%d: using %s mode\n", dev->idx,
+                dev->fast_mode ? "fast (400 kHz)" : "standard (100 kHz)");
+
+        return 0;
+
+fail:   
+        if (dev->irq >= 0){
+                iic_interrupt_mode(dev, 0);
+                free_irq(dev->irq, dev);
+        }       
+
+        iounmap(dev->vaddr);
+fail2:  
+        ocp_set_drvdata(ocp, NULL);
+        kfree(dev);     
+        return ret;
+}
+
+/*
+ * Cleanup initialized IIC interface
+ */
+static void __devexit iic_remove(struct ocp_device *ocp)
+{
+        struct ibm_iic_private* dev = (struct ibm_iic_private*)ocp_get_drvdata(ocp);
+        BUG_ON(dev == NULL);
+        if (i2c_del_adapter(&dev->adap)){
+                printk(KERN_CRIT "ibm-iic%d: failed to delete i2c adapter :(\n",
+                        dev->idx);
+                /* That's *very* bad, just shutdown IRQ ... */
+                if (dev->irq >= 0){
+                    iic_interrupt_mode(dev, 0); 
+                    free_irq(dev->irq, dev);
+                    dev->irq = -1;
+                }
+        } else {
+                if (dev->irq >= 0){
+                    iic_interrupt_mode(dev, 0); 
+                    free_irq(dev->irq, dev);
+                }
+                iounmap(dev->vaddr);
+                kfree(dev);
+        }
+}
+
+static struct ocp_device_id ibm_iic_ids[] __devinitdata = 
+{
+        { .vendor = OCP_VENDOR_IBM, .function = OCP_FUNC_IIC },
+        { .vendor = OCP_VENDOR_INVALID }
+};
+
+MODULE_DEVICE_TABLE(ocp, ibm_iic_ids);
+
+static struct ocp_driver ibm_iic_driver =
+{
+        .name           = "iic",
+        .id_table       = ibm_iic_ids,
+        .probe          = iic_probe,
+        .remove         = __devexit_p(iic_remove),
+#if defined(CONFIG_PM)
+        .suspend        = NULL,
+        .resume         = NULL,
+#endif
+};
+
+static int __init iic_init(void)
+{
+        printk(KERN_INFO "IBM IIC driver v" DRIVER_VERSION "\n");
+        return ocp_register_driver(&ibm_iic_driver);
+}
+
+static void __exit iic_exit(void)
+{
+        ocp_unregister_driver(&ibm_iic_driver);
+}
+
+module_init(iic_init);
+module_exit(iic_exit);
diff --git a/drivers/i2c/busses/i2c-ibm_iic.h b/drivers/i2c/busses/i2c-ibm_iic.h
new file mode 100644
index 000000000000..d819a955d890
--- /dev/null
+++ b/drivers/i2c/busses/i2c-ibm_iic.h
@@ -0,0 +1,124 @@
+/*
+ * drivers/i2c/i2c-ibm_iic.h
+ *
+ * Support for the IIC peripheral on IBM PPC 4xx
+ * 
+ * Copyright (c) 2003 Zultys Technologies.
+ * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
+ *
+ * Based on original work by 
+ *      Ian DaSilva  <idasilva@mvista.com>
+ *      Armin Kuster <akuster@mvista.com>
+ *      Matt Porter  <mporter@mvista.com>
+ *
+ *      Copyright 2000-2003 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+#ifndef __I2C_IBM_IIC_H_
+#define __I2C_IBM_IIC_H_
+
+#include <linux/config.h>
+#include <linux/i2c.h> 
+
+struct iic_regs {
+        u16 mdbuf;
+        u16 sbbuf;
+        u8 lmadr;
+        u8 hmadr;
+        u8 cntl;
+        u8 mdcntl;
+        u8 sts;
+        u8 extsts;
+        u8 lsadr;
+        u8 hsadr;
+        u8 clkdiv;
+        u8 intmsk;
+        u8 xfrcnt;
+        u8 xtcntlss;
+        u8 directcntl;
+};
+
+struct ibm_iic_private {
+        struct i2c_adapter adap;
+        volatile struct iic_regs __iomem *vaddr;
+        wait_queue_head_t wq;
+        int idx;
+        int irq;
+        int fast_mode;
+        u8  clckdiv;
+};
+
+/* IICx_CNTL register */
+#define CNTL_HMT        0x80
+#define CNTL_AMD        0x40
+#define CNTL_TCT_MASK   0x30
+#define CNTL_TCT_SHIFT  4
+#define CNTL_RPST       0x08
+#define CNTL_CHT        0x04 
+#define CNTL_RW         0x02
+#define CNTL_PT         0x01
+
+/* IICx_MDCNTL register */
+#define MDCNTL_FSDB     0x80
+#define MDCNTL_FMDB     0x40
+#define MDCNTL_EGC      0x20
+#define MDCNTL_FSM      0x10
+#define MDCNTL_ESM      0x08
+#define MDCNTL_EINT     0x04
+#define MDCNTL_EUBS     0x02
+#define MDCNTL_HSCL     0x01
+
+/* IICx_STS register */
+#define STS_SSS         0x80
+#define STS_SLPR        0x40
+#define STS_MDBS        0x20
+#define STS_MDBF        0x10
+#define STS_SCMP        0x08
+#define STS_ERR         0x04
+#define STS_IRQA        0x02
+#define STS_PT          0x01
+
+/* IICx_EXTSTS register */
+#define EXTSTS_IRQP     0x80
+#define EXTSTS_BCS_MASK 0x70
+#define   EXTSTS_BCS_FREE  0x40
+#define EXTSTS_IRQD     0x08
+#define EXTSTS_LA       0x04
+#define EXTSTS_ICT      0x02
+#define EXTSTS_XFRA     0x01
+
+/* IICx_INTRMSK register */
+#define INTRMSK_EIRC    0x80
+#define INTRMSK_EIRS    0x40
+#define INTRMSK_EIWC    0x20
+#define INTRMSK_EIWS    0x10
+#define INTRMSK_EIHE    0x08
+#define INTRMSK_EIIC    0x04
+#define INTRMSK_EITA    0x02
+#define INTRMSK_EIMTC   0x01
+
+/* IICx_XFRCNT register */
+#define XFRCNT_MTC_MASK 0x07
+
+/* IICx_XTCNTLSS register */
+#define XTCNTLSS_SRC    0x80
+#define XTCNTLSS_SRS    0x40
+#define XTCNTLSS_SWC    0x20
+#define XTCNTLSS_SWS    0x10
+#define XTCNTLSS_SRST   0x01
+
+/* IICx_DIRECTCNTL register */
+#define DIRCNTL_SDAC    0x08
+#define DIRCNTL_SCC     0x04
+#define DIRCNTL_MSDA    0x02
+#define DIRCNTL_MSC     0x01
+
+/* Check if we really control the I2C bus and bus is free */
+#define DIRCTNL_FREE(v) (((v) & 0x0f) == 0x0f)
+
+#endif /* __I2C_IBM_IIC_H_ */
diff --git a/drivers/i2c/busses/i2c-iop3xx.c b/drivers/i2c/busses/i2c-iop3xx.c
new file mode 100644
index 000000000000..c961ba4cfb32
--- /dev/null
+++ b/drivers/i2c/busses/i2c-iop3xx.c
@@ -0,0 +1,554 @@
+/* ------------------------------------------------------------------------- */
+/* i2c-iop3xx.c i2c driver algorithms for Intel XScale IOP3xx & IXP46x       */
+/* ------------------------------------------------------------------------- */
+/* Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd
+ *                    <Peter dot Milne at D hyphen TACQ dot com>
+ *
+ * With acknowledgements to i2c-algo-ibm_ocp.c by 
+ * Ian DaSilva, MontaVista Software, Inc. idasilva@mvista.com
+ *
+ * And i2c-algo-pcf.c, which was created by Simon G. Vogl and Hans Berglund:
+ *
+ * Copyright (C) 1995-1997 Simon G. Vogl, 1998-2000 Hans Berglund
+ *  
+ * And which acknowledged Kyösti Mälkki <kmalkki@cc.hut.fi>,
+ * Frodo Looijaard <frodol@dds.nl>, Martin Bailey<mbailey@littlefeet-inc.com>
+ *
+ * Major cleanup by Deepak Saxena <dsaxena@plexity.net>, 01/2005:
+ *
+ * - Use driver model to pass per-chip info instead of hardcoding and #ifdefs
+ * - Use ioremap/__raw_readl/__raw_writel instead of direct dereference
+ * - Make it work with IXP46x chips
+ * - Cleanup function names, coding style, etc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2.
+ */
+
+#include <linux/config.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/device.h>
+#include <linux/i2c.h>
+
+#include <asm/io.h>
+
+#include "i2c-iop3xx.h"
+
+/* global unit counter */
+static int i2c_id = 0;
+
+static inline unsigned char 
+iic_cook_addr(struct i2c_msg *msg) 
+{
+        unsigned char addr;
+
+        addr = (msg->addr << 1);
+
+        if (msg->flags & I2C_M_RD)
+                addr |= 1;
+
+        /*
+         * Read or Write?
+         */
+        if (msg->flags & I2C_M_REV_DIR_ADDR)
+                addr ^= 1;
+
+        return addr;   
+}
+
+static void 
+iop3xx_i2c_reset(struct i2c_algo_iop3xx_data *iop3xx_adap)
+{
+        /* Follows devman 9.3 */
+        __raw_writel(IOP3XX_ICR_UNIT_RESET, iop3xx_adap->ioaddr + CR_OFFSET);
+        __raw_writel(IOP3XX_ISR_CLEARBITS, iop3xx_adap->ioaddr + SR_OFFSET);
+        __raw_writel(0, iop3xx_adap->ioaddr + CR_OFFSET);
+} 
+
+static void 
+iop3xx_i2c_set_slave_addr(struct i2c_algo_iop3xx_data *iop3xx_adap)
+{
+        __raw_writel(MYSAR, iop3xx_adap->ioaddr + SAR_OFFSET);
+}
+
+static void 
+iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap)
+{
+        u32 cr = IOP3XX_ICR_GCD | IOP3XX_ICR_SCLEN | IOP3XX_ICR_UE;
+
+        /* 
+         * Everytime unit enable is asserted, GPOD needs to be cleared
+         * on IOP321 to avoid data corruption on the bus.
+         */
+#ifdef CONFIG_ARCH_IOP321
+#define IOP321_GPOD_I2C0    0x00c0  /* clear these bits to enable ch0 */
+#define IOP321_GPOD_I2C1    0x0030  /* clear these bits to enable ch1 */
+
+        *IOP321_GPOD &= (iop3xx_adap->id == 0) ? ~IOP321_GPOD_I2C0 : 
+                ~IOP321_GPOD_I2C1;
+#endif
+        /* NB SR bits not same position as CR IE bits :-( */
+        iop3xx_adap->SR_enabled = 
+                IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD |
+                IOP3XX_ISR_RXFULL | IOP3XX_ISR_TXEMPTY;
+
+        cr |= IOP3XX_ICR_ALD_IE | IOP3XX_ICR_BERR_IE |
+                IOP3XX_ICR_RXFULL_IE | IOP3XX_ICR_TXEMPTY_IE;
+
+        __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
+}
+
+static void 
+iop3xx_i2c_transaction_cleanup(struct i2c_algo_iop3xx_data *iop3xx_adap)
+{
+        unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
+        
+        cr &= ~(IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE | 
+                IOP3XX_ICR_MSTOP | IOP3XX_ICR_SCLEN);
+
+        __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
+}
+
+/* 
+ * NB: the handler has to clear the source of the interrupt! 
+ * Then it passes the SR flags of interest to BH via adap data
+ */
+static irqreturn_t 
+iop3xx_i2c_irq_handler(int this_irq, void *dev_id, struct pt_regs *regs) 
+{
+        struct i2c_algo_iop3xx_data *iop3xx_adap = dev_id;
+        u32 sr = __raw_readl(iop3xx_adap->ioaddr + SR_OFFSET);
+
+        if ((sr &= iop3xx_adap->SR_enabled)) {
+                __raw_writel(sr, iop3xx_adap->ioaddr + SR_OFFSET);
+                iop3xx_adap->SR_received |= sr;
+                wake_up_interruptible(&iop3xx_adap->waitq);
+        }
+        return IRQ_HANDLED;
+}
+
+/* check all error conditions, clear them , report most important */
+static int 
+iop3xx_i2c_error(u32 sr)
+{
+        int rc = 0;
+
+        if ((sr & IOP3XX_ISR_BERRD)) {
+                if ( !rc ) rc = -I2C_ERR_BERR;
+        }
+        if ((sr & IOP3XX_ISR_ALD)) {
+                if ( !rc ) rc = -I2C_ERR_ALD;           
+        }
+        return rc;      
+}
+
+static inline u32 
+iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data *iop3xx_adap)
+{
+        unsigned long flags;
+        u32 sr;
+
+        spin_lock_irqsave(&iop3xx_adap->lock, flags);
+        sr = iop3xx_adap->SR_received;
+        iop3xx_adap->SR_received = 0;
+        spin_unlock_irqrestore(&iop3xx_adap->lock, flags);
+
+        return sr;
+}
+
+/*
+ * sleep until interrupted, then recover and analyse the SR
+ * saved by handler
+ */
+typedef int (* compare_func)(unsigned test, unsigned mask);
+/* returns 1 on correct comparison */
+
+static int 
+iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap, 
+                          unsigned flags, unsigned* status,
+                          compare_func compare)
+{
+        unsigned sr = 0;
+        int interrupted;
+        int done;
+        int rc = 0;
+
+        do {
+                interrupted = wait_event_interruptible_timeout (
+                        iop3xx_adap->waitq,
+                        (done = compare( sr = iop3xx_i2c_get_srstat(iop3xx_adap)                                        ,flags )),
+                        1 * HZ;
+                        );
+                if ((rc = iop3xx_i2c_error(sr)) < 0) {
+                        *status = sr;
+                        return rc;
+                } else if (!interrupted) {
+                        *status = sr;
+                        return -ETIMEDOUT;
+                }
+        } while(!done);
+
+        *status = sr;
+
+        return 0;
+}
+
+/*
+ * Concrete compare_funcs 
+ */
+static int 
+all_bits_clear(unsigned test, unsigned mask)
+{
+        return (test & mask) == 0;
+}
+
+static int 
+any_bits_set(unsigned test, unsigned mask)
+{
+        return (test & mask) != 0;
+}
+
+static int 
+iop3xx_i2c_wait_tx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
+{
+        return iop3xx_i2c_wait_event( 
+                iop3xx_adap, 
+                IOP3XX_ISR_TXEMPTY | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD,
+                status, any_bits_set);
+}
+
+static int 
+iop3xx_i2c_wait_rx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
+{
+        return iop3xx_i2c_wait_event( 
+                iop3xx_adap, 
+                IOP3XX_ISR_RXFULL | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD,
+                status, any_bits_set);
+}
+
+static int 
+iop3xx_i2c_wait_idle(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
+{
+        return iop3xx_i2c_wait_event( 
+                iop3xx_adap, IOP3XX_ISR_UNITBUSY, status, all_bits_clear);
+}
+
+static int 
+iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap, 
+                                struct i2c_msg* msg)
+{
+        unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
+        int status;
+        int rc;
+
+        __raw_writel(iic_cook_addr(msg), iop3xx_adap->ioaddr + DBR_OFFSET);
+        
+        cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK);
+        cr |= IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE;
+
+        __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
+        rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);
+
+        return rc;
+}
+
+static int 
+iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte, 
+                                int stop)
+{
+        unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
+        int status;
+        int rc = 0;
+
+        __raw_writel(byte, iop3xx_adap->ioaddr + DBR_OFFSET);
+        cr &= ~IOP3XX_ICR_MSTART;
+        if (stop) {
+                cr |= IOP3XX_ICR_MSTOP;
+        } else {
+                cr &= ~IOP3XX_ICR_MSTOP;
+        }
+        cr |= IOP3XX_ICR_TBYTE;
+        __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
+        rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);
+
+        return rc;
+} 
+
+static int 
+iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char* byte, 
+                                int stop)
+{
+        unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
+        int status;
+        int rc = 0;
+
+        cr &= ~IOP3XX_ICR_MSTART;
+
+        if (stop) {
+                cr |= IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK;
+        } else {
+                cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK);
+        }
+        cr |= IOP3XX_ICR_TBYTE;
+        __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
+
+        rc = iop3xx_i2c_wait_rx_done(iop3xx_adap, &status);
+
+        *byte = __raw_readl(iop3xx_adap->ioaddr + DBR_OFFSET);
+
+        return rc;
+}
+
+static int 
+iop3xx_i2c_writebytes(struct i2c_adapter *i2c_adap, const char *buf, int count)
+{
+        struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
+        int ii;
+        int rc = 0;
+
+        for (ii = 0; rc == 0 && ii != count; ++ii) 
+                rc = iop3xx_i2c_write_byte(iop3xx_adap, buf[ii], ii==count-1);
+        return rc;
+}
+
+static int 
+iop3xx_i2c_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count)
+{
+        struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
+        int ii;
+        int rc = 0;
+
+        for (ii = 0; rc == 0 && ii != count; ++ii)
+                rc = iop3xx_i2c_read_byte(iop3xx_adap, &buf[ii], ii==count-1);
+        
+        return rc;
+}
+
+/*
+ * Description:  This function implements combined transactions.  Combined
+ * transactions consist of combinations of reading and writing blocks of data.
+ * FROM THE SAME ADDRESS
+ * Each transfer (i.e. a read or a write) is separated by a repeated start
+ * condition.
+ */
+static int 
+iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg* pmsg) 
+{
+        struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
+        int rc;
+
+        rc = iop3xx_i2c_send_target_addr(iop3xx_adap, pmsg);
+        if (rc < 0) {
+                return rc;
+        }
+
+        if ((pmsg->flags&I2C_M_RD)) {
+                return iop3xx_i2c_readbytes(i2c_adap, pmsg->buf, pmsg->len);
+        } else {
+                return iop3xx_i2c_writebytes(i2c_adap, pmsg->buf, pmsg->len);
+        }
+}
+
+/*
+ * master_xfer() - main read/write entry
+ */
+static int 
+iop3xx_i2c_master_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, 
+                                int num)
+{
+        struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
+        int im = 0;
+        int ret = 0;
+        int status;
+
+        iop3xx_i2c_wait_idle(iop3xx_adap, &status);
+        iop3xx_i2c_reset(iop3xx_adap);
+        iop3xx_i2c_enable(iop3xx_adap);
+
+        for (im = 0; ret == 0 && im != num; im++) {
+                ret = iop3xx_i2c_handle_msg(i2c_adap, &msgs[im]);
+        }
+
+        iop3xx_i2c_transaction_cleanup(iop3xx_adap);
+        
+        if(ret)
+                return ret;
+
+        return im;   
+}
+
+static int 
+iop3xx_i2c_algo_control(struct i2c_adapter *adapter, unsigned int cmd,
+                        unsigned long arg)
+{
+        return 0;
+}
+
+static u32 
+iop3xx_i2c_func(struct i2c_adapter *adap)
+{
+        return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
+}
+
+static struct i2c_algorithm iop3xx_i2c_algo = {
+        .name           = "IOP3xx I2C algorithm",
+        .id             = I2C_ALGO_IOP3XX,
+        .master_xfer    = iop3xx_i2c_master_xfer,
+        .algo_control   = iop3xx_i2c_algo_control,
+        .functionality  = iop3xx_i2c_func,
+};
+
+static int 
+iop3xx_i2c_remove(struct device *device)
+{
+        struct platform_device *pdev = to_platform_device(device);
+        struct i2c_adapter *padapter = dev_get_drvdata(&pdev->dev);
+        struct i2c_algo_iop3xx_data *adapter_data = 
+                (struct i2c_algo_iop3xx_data *)padapter->algo_data;
+        struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        unsigned long cr = __raw_readl(adapter_data->ioaddr + CR_OFFSET);
+
+        /*
+         * Disable the actual HW unit
+         */
+        cr &= ~(IOP3XX_ICR_ALD_IE | IOP3XX_ICR_BERR_IE |
+                IOP3XX_ICR_RXFULL_IE | IOP3XX_ICR_TXEMPTY_IE);
+        __raw_writel(cr, adapter_data->ioaddr + CR_OFFSET);
+
+        iounmap((void __iomem*)adapter_data->ioaddr);
+        release_mem_region(res->start, IOP3XX_I2C_IO_SIZE);
+        kfree(adapter_data);
+        kfree(padapter);
+
+        dev_set_drvdata(&pdev->dev, NULL);
+
+        return 0;
+}
+
+static int 
+iop3xx_i2c_probe(struct device *dev)
+{
+        struct platform_device *pdev = to_platform_device(dev);
+        struct resource *res;
+        int ret;
+        struct i2c_adapter *new_adapter;
+        struct i2c_algo_iop3xx_data *adapter_data;
+
+        new_adapter = kmalloc(sizeof(struct i2c_adapter), GFP_KERNEL);
+        if (!new_adapter) {
+                ret = -ENOMEM;
+                goto out;
+        }
+        memset((void*)new_adapter, 0, sizeof(*new_adapter));
+
+        adapter_data = kmalloc(sizeof(struct i2c_algo_iop3xx_data), GFP_KERNEL);
+        if (!adapter_data) {
+                ret = -ENOMEM;
+                goto free_adapter;
+        }
+        memset((void*)adapter_data, 0, sizeof(*adapter_data));
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                ret = -ENODEV;
+                goto free_both;
+        }
+
+        if (!request_mem_region(res->start, IOP3XX_I2C_IO_SIZE, pdev->name)) {
+                ret = -EBUSY;
+                goto free_both;
+        }
+
+        /* set the adapter enumeration # */
+        adapter_data->id = i2c_id++;
+
+        adapter_data->ioaddr = (u32)ioremap(res->start, IOP3XX_I2C_IO_SIZE);
+        if (!adapter_data->ioaddr) {
+                ret = -ENOMEM;
+                goto release_region;
+        }
+
+        res = request_irq(platform_get_irq(pdev, 0), iop3xx_i2c_irq_handler, 0, 
+                                pdev->name, adapter_data);
+        if (res) {
+                ret = -EIO;
+                goto unmap;
+        }
+
+        memcpy(new_adapter->name, pdev->name, strlen(pdev->name));
+        new_adapter->id = I2C_HW_IOP3XX;
+        new_adapter->owner = THIS_MODULE;
+        new_adapter->dev.parent = &pdev->dev;
+
+        /*
+         * Default values...should these come in from board code?
+         */
+        new_adapter->timeout = 100;     
+        new_adapter->retries = 3;
+        new_adapter->algo = &iop3xx_i2c_algo;
+
+        init_waitqueue_head(&adapter_data->waitq);
+        spin_lock_init(&adapter_data->lock);
+
+        iop3xx_i2c_reset(adapter_data);
+        iop3xx_i2c_set_slave_addr(adapter_data);
+        iop3xx_i2c_enable(adapter_data);
+
+        dev_set_drvdata(&pdev->dev, new_adapter);
+        new_adapter->algo_data = adapter_data;
+
+        i2c_add_adapter(new_adapter);
+
+        return 0;
+
+unmap:
+        iounmap((void __iomem*)adapter_data->ioaddr);
+
+release_region:
+        release_mem_region(res->start, IOP3XX_I2C_IO_SIZE);
+
+free_both:
+        kfree(adapter_data);
+
+free_adapter:
+        kfree(new_adapter);
+
+out:
+        return ret;
+}
+
+
+static struct device_driver iop3xx_i2c_driver = {
+        .name           = "IOP3xx-I2C",
+        .bus            = &platform_bus_type,
+        .probe          = iop3xx_i2c_probe,
+        .remove         = iop3xx_i2c_remove
+};
+
+static int __init 
+i2c_iop3xx_init (void)
+{
+        return driver_register(&iop3xx_i2c_driver);
+}
+
+static void __exit 
+i2c_iop3xx_exit (void)
+{
+        driver_unregister(&iop3xx_i2c_driver);
+        return;
+}
+
+module_init (i2c_iop3xx_init);
+module_exit (i2c_iop3xx_exit);
+
+MODULE_AUTHOR("D-TACQ Solutions Ltd <www.d-tacq.com>");
+MODULE_DESCRIPTION("IOP3xx iic algorithm and driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/i2c/busses/i2c-iop3xx.h b/drivers/i2c/busses/i2c-iop3xx.h
new file mode 100644
index 000000000000..e46ebaea7b1e
--- /dev/null
+++ b/drivers/i2c/busses/i2c-iop3xx.h
@@ -0,0 +1,107 @@
+/* ------------------------------------------------------------------------- */
+/* i2c-iop3xx.h algorithm driver definitions private to i2c-iop3xx.c         */
+/* ------------------------------------------------------------------------- */
+/*   Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd
+ *                      <Peter dot Milne at D hyphen TACQ dot com>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, version 2.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.                */
+/* ------------------------------------------------------------------------- */
+
+
+#ifndef I2C_IOP3XX_H
+#define I2C_IOP3XX_H 1
+
+/*
+ * iop321 hardware bit definitions
+ */
+#define IOP3XX_ICR_FAST_MODE    0x8000  /* 1=400kBps, 0=100kBps */
+#define IOP3XX_ICR_UNIT_RESET   0x4000  /* 1=RESET */
+#define IOP3XX_ICR_SAD_IE       0x2000  /* 1=Slave Detect Interrupt Enable */
+#define IOP3XX_ICR_ALD_IE       0x1000  /* 1=Arb Loss Detect Interrupt Enable */
+#define IOP3XX_ICR_SSD_IE       0x0800  /* 1=Slave STOP Detect Interrupt Enable */
+#define IOP3XX_ICR_BERR_IE      0x0400  /* 1=Bus Error Interrupt Enable */
+#define IOP3XX_ICR_RXFULL_IE    0x0200  /* 1=Receive Full Interrupt Enable */
+#define IOP3XX_ICR_TXEMPTY_IE   0x0100  /* 1=Transmit Empty Interrupt Enable */
+#define IOP3XX_ICR_GCD          0x0080  /* 1=General Call Disable */
+/*
+ * IOP3XX_ICR_GCD: 1 disables response as slave. "This bit must be set
+ * when sending a master mode general call message from the I2C unit"
+ */
+#define IOP3XX_ICR_UE           0x0040  /* 1=Unit Enable */
+/*
+ * "NOTE: To avoid I2C bus integrity problems, 
+ * the user needs to ensure that the GPIO Output Data Register - 
+ * GPOD bits associated with an I2C port are cleared prior to setting 
+ * the enable bit for that I2C serial port. 
+ * The user prepares to enable I2C port 0 and 
+ * I2C port 1 by clearing GPOD bits 7:6 and GPOD bits 5:4, respectively.
+ */
+#define IOP3XX_ICR_SCLEN        0x0020  /* 1=SCL enable for master mode */
+#define IOP3XX_ICR_MABORT       0x0010  /* 1=Send a STOP with no data 
+                                         * NB TBYTE must be clear */
+#define IOP3XX_ICR_TBYTE        0x0008  /* 1=Send/Receive a byte. i2c clears */
+#define IOP3XX_ICR_NACK         0x0004  /* 1=reply with NACK */
+#define IOP3XX_ICR_MSTOP        0x0002  /* 1=send a STOP after next data byte */
+#define IOP3XX_ICR_MSTART       0x0001  /* 1=initiate a START */
+
+
+#define IOP3XX_ISR_BERRD        0x0400  /* 1=BUS ERROR Detected */
+#define IOP3XX_ISR_SAD          0x0200  /* 1=Slave ADdress Detected */
+#define IOP3XX_ISR_GCAD         0x0100  /* 1=General Call Address Detected */
+#define IOP3XX_ISR_RXFULL       0x0080  /* 1=Receive Full */
+#define IOP3XX_ISR_TXEMPTY      0x0040  /* 1=Transmit Empty */
+#define IOP3XX_ISR_ALD          0x0020  /* 1=Arbitration Loss Detected */
+#define IOP3XX_ISR_SSD          0x0010  /* 1=Slave STOP Detected */
+#define IOP3XX_ISR_BBUSY        0x0008  /* 1=Bus BUSY */
+#define IOP3XX_ISR_UNITBUSY     0x0004  /* 1=Unit Busy */
+#define IOP3XX_ISR_NACK         0x0002  /* 1=Unit Rx or Tx a NACK */
+#define IOP3XX_ISR_RXREAD       0x0001  /* 1=READ 0=WRITE (R/W bit of slave addr */
+
+#define IOP3XX_ISR_CLEARBITS    0x07f0
+
+#define IOP3XX_ISAR_SAMASK      0x007f
+
+#define IOP3XX_IDBR_MASK        0x00ff
+
+#define IOP3XX_IBMR_SCL         0x0002
+#define IOP3XX_IBMR_SDA         0x0001
+
+#define IOP3XX_GPOD_I2C0        0x00c0  /* clear these bits to enable ch0 */
+#define IOP3XX_GPOD_I2C1        0x0030  /* clear these bits to enable ch1 */
+
+#define MYSAR                   0x02    /* SWAG a suitable slave address */
+
+#define I2C_ERR                 321
+#define I2C_ERR_BERR            (I2C_ERR+0)
+#define I2C_ERR_ALD             (I2C_ERR+1)
+
+
+#define CR_OFFSET               0
+#define SR_OFFSET               0x4
+#define SAR_OFFSET              0x8
+#define DBR_OFFSET              0xc
+#define CCR_OFFSET              0x10
+#define BMR_OFFSET              0x14
+
+#define IOP3XX_I2C_IO_SIZE      0x18
+
+struct i2c_algo_iop3xx_data {
+        u32 ioaddr;
+        wait_queue_head_t waitq;
+        spinlock_t lock;
+        u32 SR_enabled, SR_received;
+        int id;
+};
+
+#endif /* I2C_IOP3XX_H */
diff --git a/drivers/i2c/busses/i2c-isa.c b/drivers/i2c/busses/i2c-isa.c
new file mode 100644
index 000000000000..0f54a2a0afa5
--- /dev/null
+++ b/drivers/i2c/busses/i2c-isa.c
@@ -0,0 +1,72 @@
+/*
+    i2c-isa.c - Part of lm_sensors, Linux kernel modules for hardware
+            monitoring
+    Copyright (c) 1998, 1999  Frodo Looijaard <frodol@dds.nl> 
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+/* This implements an i2c algorithm/adapter for ISA bus. Not that this is
+   on first sight very useful; almost no functionality is preserved.
+   Except that it makes writing drivers for chips which can be on both
+   the SMBus and the ISA bus very much easier. See lm78.c for an example
+   of this. */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/i2c.h>
+
+static u32 isa_func(struct i2c_adapter *adapter);
+
+/* This is the actual algorithm we define */
+static struct i2c_algorithm isa_algorithm = {
+        .name           = "ISA bus algorithm",
+        .id             = I2C_ALGO_ISA,
+        .functionality  = isa_func,
+};
+
+/* There can only be one... */
+static struct i2c_adapter isa_adapter = {
+        .owner          = THIS_MODULE,
+        .class          = I2C_CLASS_HWMON,
+        .algo           = &isa_algorithm,
+        .name           = "ISA main adapter",
+};
+
+/* We can't do a thing... */
+static u32 isa_func(struct i2c_adapter *adapter)
+{
+        return 0;
+}
+
+static int __init i2c_isa_init(void)
+{
+        return i2c_add_adapter(&isa_adapter);
+}
+
+static void __exit i2c_isa_exit(void)
+{
+        i2c_del_adapter(&isa_adapter);
+}
+
+MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl>");
+MODULE_DESCRIPTION("ISA bus access through i2c");
+MODULE_LICENSE("GPL");
+
+module_init(i2c_isa_init);
+module_exit(i2c_isa_exit);
diff --git a/drivers/i2c/busses/i2c-ite.c b/drivers/i2c/busses/i2c-ite.c
new file mode 100644
index 000000000000..702e3def1b81
--- /dev/null
+++ b/drivers/i2c/busses/i2c-ite.c
@@ -0,0 +1,282 @@
+/*
+   -------------------------------------------------------------------------
+   i2c-adap-ite.c i2c-hw access for the IIC peripheral on the ITE MIPS system
+   -------------------------------------------------------------------------
+   Hai-Pao Fan, MontaVista Software, Inc.
+   hpfan@mvista.com or source@mvista.com
+
+   Copyright 2001 MontaVista Software Inc.
+
+   ----------------------------------------------------------------------------
+   This file was highly leveraged from i2c-elektor.c, which was created
+   by Simon G. Vogl and Hans Berglund:
+
+ 
+     Copyright (C) 1995-97 Simon G. Vogl
+                   1998-99 Hans Berglund
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.                */
+/* ------------------------------------------------------------------------- */
+
+/* With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> and even
+   Frodo Looijaard <frodol@dds.nl> */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/ioport.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/wait.h>
+#include <asm/irq.h>
+#include <asm/io.h>
+
+#include <linux/i2c.h>
+#include <linux/i2c-algo-ite.h>
+#include <linux/i2c-adap-ite.h>
+#include "../i2c-ite.h"
+
+#define DEFAULT_BASE  0x14014030
+#define ITE_IIC_IO_SIZE 0x40
+#define DEFAULT_IRQ   0
+#define DEFAULT_CLOCK 0x1b0e    /* default 16MHz/(27+14) = 400KHz */
+#define DEFAULT_OWN   0x55
+
+static int base;
+static int irq;
+static int clock;
+static int own;
+
+static struct iic_ite gpi;
+static wait_queue_head_t iic_wait;
+static int iic_pending;
+static spinlock_t lock;
+
+/* ----- local functions ---------------------------------------------- */
+
+static void iic_ite_setiic(void *data, int ctl, short val)
+{
+        unsigned long j = jiffies + 10;
+
+        pr_debug(" Write 0x%02x to 0x%x\n",(unsigned short)val, ctl&0xff);
+#ifdef DEBUG
+        while (time_before(jiffies, j))
+                schedule();
+#endif
+        outw(val,ctl);
+}
+
+static short iic_ite_getiic(void *data, int ctl)
+{
+        short val;
+
+        val = inw(ctl);
+        pr_debug("Read 0x%02x from 0x%x\n",(unsigned short)val, ctl&0xff);
+        return (val);
+}
+
+/* Return our slave address.  This is the address
+ * put on the I2C bus when another master on the bus wants to address us
+ * as a slave
+ */
+static int iic_ite_getown(void *data)
+{
+        return (gpi.iic_own);
+}
+
+
+static int iic_ite_getclock(void *data)
+{
+        return (gpi.iic_clock);
+}
+
+
+/* Put this process to sleep.  We will wake up when the
+ * IIC controller interrupts.
+ */
+static void iic_ite_waitforpin(void) {
+   DEFINE_WAIT(wait);
+   int timeout = 2;
+   long flags;
+
+   /* If interrupts are enabled (which they are), then put the process to
+    * sleep.  This process will be awakened by two events -- either the
+    * the IIC peripheral interrupts or the timeout expires. 
+    * If interrupts are not enabled then delay for a reasonable amount 
+    * of time and return.
+    */
+   if (gpi.iic_irq > 0) {
+        spin_lock_irqsave(&lock, flags);
+        if (iic_pending == 0) {
+                spin_unlock_irqrestore(&lock, flags);
+                prepare_to_wait(&iic_wait, &wait, TASK_INTERRUPTIBLE);
+                if (schedule_timeout(timeout*HZ)) {
+                        spin_lock_irqsave(&lock, flags);
+                        if (iic_pending == 1) {
+                                iic_pending = 0;
+                        }
+                        spin_unlock_irqrestore(&lock, flags);
+                }
+                finish_wait(&iic_wait, &wait);
+        } else {
+                iic_pending = 0;
+                spin_unlock_irqrestore(&lock, flags);
+        }
+   } else {
+      udelay(100);
+   }
+}
+
+
+static irqreturn_t iic_ite_handler(int this_irq, void *dev_id,
+                                                        struct pt_regs *regs)
+{
+        spin_lock(&lock);
+        iic_pending = 1;
+        spin_unlock(&lock);
+
+        wake_up_interruptible(&iic_wait);
+
+        return IRQ_HANDLED;
+}
+
+
+/* Lock the region of memory where I/O registers exist.  Request our
+ * interrupt line and register its associated handler.
+ */
+static int iic_hw_resrc_init(void)
+{
+        if (!request_region(gpi.iic_base, ITE_IIC_IO_SIZE, "i2c"))
+                return -ENODEV;
+  
+        if (gpi.iic_irq <= 0)
+                return 0;
+
+        if (request_irq(gpi.iic_irq, iic_ite_handler, 0, "ITE IIC", 0) < 0)
+                gpi.iic_irq = 0;
+        else
+                enable_irq(gpi.iic_irq);
+
+        return 0;
+}
+
+
+static void iic_ite_release(void)
+{
+        if (gpi.iic_irq > 0) {
+                disable_irq(gpi.iic_irq);
+                free_irq(gpi.iic_irq, 0);
+        }
+        release_region(gpi.iic_base , 2);
+}
+
+/* ------------------------------------------------------------------------
+ * Encapsulate the above functions in the correct operations structure.
+ * This is only done when more than one hardware adapter is supported.
+ */
+static struct i2c_algo_iic_data iic_ite_data = {
+        NULL,
+        iic_ite_setiic,
+        iic_ite_getiic,
+        iic_ite_getown,
+        iic_ite_getclock,
+        iic_ite_waitforpin,
+        80, 80, 100,            /*      waits, timeout */
+};
+
+static struct i2c_adapter iic_ite_ops = {
+        .owner          = THIS_MODULE,
+        .id             = I2C_HW_I_IIC,
+        .algo_data      = &iic_ite_data,
+        .dev            = {
+                .name   = "ITE IIC adapter",
+        },
+};
+
+/* Called when the module is loaded.  This function starts the
+ * cascade of calls up through the hierarchy of i2c modules (i.e. up to the
+ *  algorithm layer and into to the core layer)
+ */
+static int __init iic_ite_init(void) 
+{
+
+        struct iic_ite *piic = &gpi;
+
+        printk(KERN_INFO "Initialize ITE IIC adapter module\n");
+        if (base == 0)
+                piic->iic_base = DEFAULT_BASE;
+        else
+                piic->iic_base = base;
+
+        if (irq == 0)
+                piic->iic_irq = DEFAULT_IRQ;
+        else
+                piic->iic_irq = irq;
+
+        if (clock == 0)
+                piic->iic_clock = DEFAULT_CLOCK;
+        else
+                piic->iic_clock = clock;
+
+        if (own == 0)
+                piic->iic_own = DEFAULT_OWN;
+        else
+                piic->iic_own = own;
+
+        iic_ite_data.data = (void *)piic;
+        init_waitqueue_head(&iic_wait);
+        spin_lock_init(&lock);
+        if (iic_hw_resrc_init() == 0) {
+                if (i2c_iic_add_bus(&iic_ite_ops) < 0)
+                        return -ENODEV;
+        } else {
+                return -ENODEV;
+        }
+        printk(KERN_INFO " found device at %#x irq %d.\n", 
+                piic->iic_base, piic->iic_irq);
+        return 0;
+}
+
+
+static void iic_ite_exit(void)
+{
+        i2c_iic_del_bus(&iic_ite_ops);
+        iic_ite_release();
+}
+
+/* If modules is NOT defined when this file is compiled, then the MODULE_*
+ * macros will resolve to nothing
+ */
+MODULE_AUTHOR("MontaVista Software <www.mvista.com>");
+MODULE_DESCRIPTION("I2C-Bus adapter routines for ITE IIC bus adapter");
+MODULE_LICENSE("GPL");
+
+module_param(base, int, 0);
+module_param(irq, int, 0);
+module_param(clock, int, 0);
+module_param(own, int, 0);
+
+
+/* Called when module is loaded or when kernel is initialized.
+ * If MODULES is defined when this file is compiled, then this function will
+ * resolve to init_module (the function called when insmod is invoked for a
+ * module).  Otherwise, this function is called early in the boot, when the
+ * kernel is intialized.  Check out /include/init.h to see how this works.
+ */
+module_init(iic_ite_init);
+
+/* Resolves to module_cleanup when MODULES is defined. */
+module_exit(iic_ite_exit); 
diff --git a/drivers/i2c/busses/i2c-ixp2000.c b/drivers/i2c/busses/i2c-ixp2000.c
new file mode 100644
index 000000000000..21cd54d02302
--- /dev/null
+++ b/drivers/i2c/busses/i2c-ixp2000.c
@@ -0,0 +1,171 @@
+/*
+ * drivers/i2c/busses/i2c-ixp2000.c
+ *
+ * I2C adapter for IXP2000 systems using GPIOs for I2C bus
+ *
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ * Based on IXDP2400 code by: Naeem M. Afzal <naeem.m.afzal@intel.com>
+ * Made generic by: Jeff Daly <jeffrey.daly@intel.com>
+ *
+ * Copyright (c) 2003-2004 MontaVista Software Inc.
+ *
+ * This file is licensed under  the terms of the GNU General Public 
+ * License version 2. This program is licensed "as is" without any 
+ * warranty of any kind, whether express or implied.
+ *
+ * From Jeff Daly:
+ *
+ * I2C adapter driver for Intel IXDP2xxx platforms. This should work for any
+ * IXP2000 platform if it uses the HW GPIO in the same manner.  Basically, 
+ * SDA and SCL GPIOs have external pullups.  Setting the respective GPIO to 
+ * an input will make the signal a '1' via the pullup.  Setting them to 
+ * outputs will pull them down. 
+ *
+ * The GPIOs are open drain signals and are used as configuration strap inputs
+ * during power-up so there's generally a buffer on the board that needs to be 
+ * 'enabled' to drive the GPIOs.
+ */
+
+#include <linux/config.h>
+#ifdef CONFIG_I2C_DEBUG_BUS
+#define DEBUG   1
+#endif
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/i2c.h>
+#include <linux/i2c-algo-bit.h>
+
+#include <asm/hardware.h>       /* Pick up IXP42000-specific bits */
+
+static inline int ixp2000_scl_pin(void *data)
+{
+        return ((struct ixp2000_i2c_pins*)data)->scl_pin;
+}
+
+static inline int ixp2000_sda_pin(void *data)
+{
+        return ((struct ixp2000_i2c_pins*)data)->sda_pin;
+}
+
+
+static void ixp2000_bit_setscl(void *data, int val)
+{
+        int i = 5000;
+
+        if (val) {
+                gpio_line_config(ixp2000_scl_pin(data), GPIO_IN);
+                while(!gpio_line_get(ixp2000_scl_pin(data)) && i--);
+        } else {
+                gpio_line_config(ixp2000_scl_pin(data), GPIO_OUT);
+        }
+}
+
+static void ixp2000_bit_setsda(void *data, int val)
+{
+        if (val) {
+                gpio_line_config(ixp2000_sda_pin(data), GPIO_IN);
+        } else {
+                gpio_line_config(ixp2000_sda_pin(data), GPIO_OUT);
+        }
+}
+
+static int ixp2000_bit_getscl(void *data)
+{
+        return gpio_line_get(ixp2000_scl_pin(data));
+}
+
+static int ixp2000_bit_getsda(void *data)
+{
+        return gpio_line_get(ixp2000_sda_pin(data));
+}
+
+struct ixp2000_i2c_data {
+        struct ixp2000_i2c_pins *gpio_pins;
+        struct i2c_adapter adapter;
+        struct i2c_algo_bit_data algo_data;
+};
+
+static int ixp2000_i2c_remove(struct device *dev)
+{
+        struct platform_device *plat_dev = to_platform_device(dev);
+        struct ixp2000_i2c_data *drv_data = dev_get_drvdata(&plat_dev->dev);
+
+        dev_set_drvdata(&plat_dev->dev, NULL);
+
+        i2c_bit_del_bus(&drv_data->adapter);
+
+        kfree(drv_data);
+
+        return 0;
+}
+
+static int ixp2000_i2c_probe(struct device *dev)
+{
+        int err;
+        struct platform_device *plat_dev = to_platform_device(dev);
+        struct ixp2000_i2c_pins *gpio = plat_dev->dev.platform_data;
+        struct ixp2000_i2c_data *drv_data = 
+                kmalloc(sizeof(struct ixp2000_i2c_data), GFP_KERNEL);
+
+        if (!drv_data)
+                return -ENOMEM;
+        memzero(drv_data, sizeof(*drv_data));
+        drv_data->gpio_pins = gpio;
+
+        drv_data->algo_data.data = gpio;
+        drv_data->algo_data.setsda = ixp2000_bit_setsda;
+        drv_data->algo_data.setscl = ixp2000_bit_setscl;
+        drv_data->algo_data.getsda = ixp2000_bit_getsda;
+        drv_data->algo_data.getscl = ixp2000_bit_getscl;
+        drv_data->algo_data.udelay = 6;
+        drv_data->algo_data.mdelay = 6;
+        drv_data->algo_data.timeout = 100;
+
+        drv_data->adapter.id = I2C_HW_B_IXP2000,
+        drv_data->adapter.algo_data = &drv_data->algo_data,
+
+        drv_data->adapter.dev.parent = &plat_dev->dev;
+
+        gpio_line_config(gpio->sda_pin, GPIO_IN);
+        gpio_line_config(gpio->scl_pin, GPIO_IN);
+        gpio_line_set(gpio->scl_pin, 0);
+        gpio_line_set(gpio->sda_pin, 0);
+
+        if ((err = i2c_bit_add_bus(&drv_data->adapter)) != 0) {
+                dev_err(dev, "Could not install, error %d\n", err);
+                kfree(drv_data);
+                return err;
+        } 
+
+        dev_set_drvdata(&plat_dev->dev, drv_data);
+
+        return 0;
+}
+
+static struct device_driver ixp2000_i2c_driver = {
+        .name           = "IXP2000-I2C",
+        .bus            = &platform_bus_type,
+        .probe          = ixp2000_i2c_probe,
+        .remove         = ixp2000_i2c_remove,
+};
+
+static int __init ixp2000_i2c_init(void)
+{
+        return driver_register(&ixp2000_i2c_driver);
+}
+
+static void __exit ixp2000_i2c_exit(void)
+{
+        driver_unregister(&ixp2000_i2c_driver);
+}
+
+module_init(ixp2000_i2c_init);
+module_exit(ixp2000_i2c_exit);
+
+MODULE_AUTHOR ("Deepak Saxena <dsaxena@plexity.net>");
+MODULE_DESCRIPTION("IXP2000 GPIO-based I2C bus driver");
+MODULE_LICENSE("GPL");
+
diff --git a/drivers/i2c/busses/i2c-ixp4xx.c b/drivers/i2c/busses/i2c-ixp4xx.c
new file mode 100644
index 000000000000..8c55eafc3a09
--- /dev/null
+++ b/drivers/i2c/busses/i2c-ixp4xx.c
@@ -0,0 +1,181 @@
+/*
+ * drivers/i2c/i2c-adap-ixp4xx.c
+ *
+ * Intel's IXP4xx XScale NPU chipsets (IXP420, 421, 422, 425) do not have
+ * an on board I2C controller but provide 16 GPIO pins that are often
+ * used to create an I2C bus. This driver provides an i2c_adapter 
+ * interface that plugs in under algo_bit and drives the GPIO pins
+ * as instructed by the alogorithm driver.
+ *
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright (c) 2003-2004 MontaVista Software Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public 
+ * License version 2. This program is licensed "as is" without any 
+ * warranty of any kind, whether express or implied.
+ *
+ * NOTE: Since different platforms will use different GPIO pins for
+ *       I2C, this driver uses an IXP4xx-specific platform_data
+ *       pointer to pass the GPIO numbers to the driver. This 
+ *       allows us to support all the different IXP4xx platforms
+ *       w/o having to put #ifdefs in this driver.
+ *
+ *       See arch/arm/mach-ixp4xx/ixdp425.c for an example of building a 
+ *       device list and filling in the ixp4xx_i2c_pins data structure 
+ *       that is passed as the platform_data to this driver.
+ */
+
+#include <linux/config.h>
+#ifdef CONFIG_I2C_DEBUG_BUS
+#define DEBUG   1
+#endif
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/i2c.h>
+#include <linux/i2c-algo-bit.h>
+
+#include <asm/hardware.h>       /* Pick up IXP4xx-specific bits */
+
+static inline int ixp4xx_scl_pin(void *data)
+{
+        return ((struct ixp4xx_i2c_pins*)data)->scl_pin;
+}
+
+static inline int ixp4xx_sda_pin(void *data)
+{
+        return ((struct ixp4xx_i2c_pins*)data)->sda_pin;
+}
+
+static void ixp4xx_bit_setscl(void *data, int val)
+{
+        gpio_line_set(ixp4xx_scl_pin(data), 0);
+        gpio_line_config(ixp4xx_scl_pin(data),
+                val ? IXP4XX_GPIO_IN : IXP4XX_GPIO_OUT );
+}
+
+static void ixp4xx_bit_setsda(void *data, int val)
+{
+        gpio_line_set(ixp4xx_sda_pin(data), 0);
+        gpio_line_config(ixp4xx_sda_pin(data),
+                val ? IXP4XX_GPIO_IN : IXP4XX_GPIO_OUT );
+}
+
+static int ixp4xx_bit_getscl(void *data)
+{
+        int scl;
+
+        gpio_line_config(ixp4xx_scl_pin(data), IXP4XX_GPIO_IN );
+        gpio_line_get(ixp4xx_scl_pin(data), &scl);
+
+        return scl;
+}       
+
+static int ixp4xx_bit_getsda(void *data)
+{
+        int sda;
+
+        gpio_line_config(ixp4xx_sda_pin(data), IXP4XX_GPIO_IN );
+        gpio_line_get(ixp4xx_sda_pin(data), &sda);
+
+        return sda;
+}       
+
+struct ixp4xx_i2c_data {
+        struct ixp4xx_i2c_pins *gpio_pins;
+        struct i2c_adapter adapter;
+        struct i2c_algo_bit_data algo_data;
+};
+
+static int ixp4xx_i2c_remove(struct device *dev)
+{
+        struct platform_device *plat_dev = to_platform_device(dev);
+        struct ixp4xx_i2c_data *drv_data = dev_get_drvdata(&plat_dev->dev);
+
+        dev_set_drvdata(&plat_dev->dev, NULL);
+
+        i2c_bit_del_bus(&drv_data->adapter);
+
+        kfree(drv_data);
+
+        return 0;
+}
+
+static int ixp4xx_i2c_probe(struct device *dev)
+{
+        int err;
+        struct platform_device *plat_dev = to_platform_device(dev);
+        struct ixp4xx_i2c_pins *gpio = plat_dev->dev.platform_data;
+        struct ixp4xx_i2c_data *drv_data = 
+                kmalloc(sizeof(struct ixp4xx_i2c_data), GFP_KERNEL);
+
+        if(!drv_data)
+                return -ENOMEM;
+
+        memzero(drv_data, sizeof(struct ixp4xx_i2c_data));
+        drv_data->gpio_pins = gpio;
+
+        /*
+         * We could make a lot of these structures static, but
+         * certain platforms may have multiple GPIO-based I2C
+         * buses for various device domains, so we need per-device
+         * algo_data->data. 
+         */
+        drv_data->algo_data.data = gpio;
+        drv_data->algo_data.setsda = ixp4xx_bit_setsda;
+        drv_data->algo_data.setscl = ixp4xx_bit_setscl;
+        drv_data->algo_data.getsda = ixp4xx_bit_getsda;
+        drv_data->algo_data.getscl = ixp4xx_bit_getscl;
+        drv_data->algo_data.udelay = 10;
+        drv_data->algo_data.mdelay = 10;
+        drv_data->algo_data.timeout = 100;
+
+        drv_data->adapter.id = I2C_HW_B_IXP4XX;
+        drv_data->adapter.algo_data = &drv_data->algo_data;
+
+        drv_data->adapter.dev.parent = &plat_dev->dev;
+
+        gpio_line_config(gpio->scl_pin, IXP4XX_GPIO_IN);
+        gpio_line_config(gpio->sda_pin, IXP4XX_GPIO_IN);
+        gpio_line_set(gpio->scl_pin, 0);
+        gpio_line_set(gpio->sda_pin, 0);
+
+        if ((err = i2c_bit_add_bus(&drv_data->adapter) != 0)) {
+                printk(KERN_ERR "ERROR: Could not install %s\n", dev->bus_id);
+
+                kfree(drv_data);
+                return err;
+        }
+
+        dev_set_drvdata(&plat_dev->dev, drv_data);
+
+        return 0;
+}
+
+static struct device_driver ixp4xx_i2c_driver = {
+        .name           = "IXP4XX-I2C",
+        .bus            = &platform_bus_type,
+        .probe          = ixp4xx_i2c_probe,
+        .remove         = ixp4xx_i2c_remove,
+};
+
+static int __init ixp4xx_i2c_init(void)
+{
+        return driver_register(&ixp4xx_i2c_driver);
+}
+
+static void __exit ixp4xx_i2c_exit(void)
+{
+        driver_unregister(&ixp4xx_i2c_driver);
+}
+
+module_init(ixp4xx_i2c_init);
+module_exit(ixp4xx_i2c_exit);
+
+MODULE_DESCRIPTION("GPIO-based I2C adapter for IXP4xx systems");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Deepak Saxena <dsaxena@plexity.net>");
+
diff --git a/drivers/i2c/busses/i2c-keywest.c b/drivers/i2c/busses/i2c-keywest.c
new file mode 100644
index 000000000000..dd0d4c463146
--- /dev/null
+++ b/drivers/i2c/busses/i2c-keywest.c
@@ -0,0 +1,763 @@
+/*
+    i2c Support for Apple Keywest I2C Bus Controller
+
+    Copyright (c) 2001 Benjamin Herrenschmidt <benh@kernel.crashing.org>
+
+    Original work by
+    
+    Copyright (c) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+    Changes:
+
+    2001/12/13 BenH     New implementation
+    2001/12/15 BenH     Add support for "byte" and "quick"
+                        transfers. Add i2c_xfer routine.
+    2003/09/21 BenH     Rework state machine with Paulus help
+    2004/01/21 BenH     Merge in Greg KH changes, polled mode is back
+    2004/02/05 BenH     Merge 64 bits fixes from the g5 ppc64 tree
+
+    My understanding of the various modes supported by keywest are:
+
+     - Dumb mode : not implemented, probably direct tweaking of lines
+     - Standard mode : simple i2c transaction of type
+         S Addr R/W A Data A Data ... T
+     - Standard sub mode : combined 8 bit subaddr write with data read
+         S Addr R/W A SubAddr A Data A Data ... T
+     - Combined mode : Subaddress and Data sequences appended with no stop
+         S Addr R/W A SubAddr S Addr R/W A Data A Data ... T
+
+    Currently, this driver uses only Standard mode for i2c xfer, and
+    smbus byte & quick transfers ; and uses StandardSub mode for
+    other smbus transfers instead of combined as we need that for the
+    sound driver to be happy
+*/
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/ioport.h>
+#include <linux/pci.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/timer.h>
+#include <linux/spinlock.h>
+#include <linux/completion.h>
+#include <linux/interrupt.h>
+
+#include <asm/io.h>
+#include <asm/prom.h>
+#include <asm/machdep.h>
+#include <asm/pmac_feature.h>
+#include <asm/pmac_low_i2c.h>
+
+#include "i2c-keywest.h"
+
+#undef POLLED_MODE
+
+/* Some debug macros */
+#define WRONG_STATE(name) do {\
+                pr_debug("KW: wrong state. Got %s, state: %s (isr: %02x)\n", \
+                         name, __kw_state_names[iface->state], isr);    \
+        } while(0)
+
+#ifdef DEBUG
+static const char *__kw_state_names[] = {
+        "state_idle",
+        "state_addr",
+        "state_read",
+        "state_write",
+        "state_stop",
+        "state_dead"
+};
+#endif /* DEBUG */
+
+static int probe;
+
+MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
+MODULE_DESCRIPTION("I2C driver for Apple's Keywest");
+MODULE_LICENSE("GPL");
+module_param(probe, bool, 0);
+
+#ifdef POLLED_MODE
+/* Don't schedule, the g5 fan controller is too
+ * timing sensitive
+ */
+static u8
+wait_interrupt(struct keywest_iface* iface)
+{
+        int i;
+        u8 isr;
+        
+        for (i = 0; i < 200000; i++) {
+                isr = read_reg(reg_isr) & KW_I2C_IRQ_MASK;
+                if (isr != 0)
+                        return isr;
+                udelay(10);
+        }
+        return isr;
+}
+#endif /* POLLED_MODE */
+
+static void
+do_stop(struct keywest_iface* iface, int result)
+{
+        write_reg(reg_control, KW_I2C_CTL_STOP);
+        iface->state = state_stop;
+        iface->result = result;
+}
+
+/* Main state machine for standard & standard sub mode */
+static void
+handle_interrupt(struct keywest_iface *iface, u8 isr)
+{
+        int ack;
+        
+        if (isr == 0) {
+                if (iface->state != state_stop) {
+                        pr_debug("KW: Timeout !\n");
+                        do_stop(iface, -EIO);
+                }
+                if (iface->state == state_stop) {
+                        ack = read_reg(reg_status);
+                        if (!(ack & KW_I2C_STAT_BUSY)) {
+                                iface->state = state_idle;
+                                write_reg(reg_ier, 0x00);
+#ifndef POLLED_MODE
+                                complete(&iface->complete);
+#endif /* POLLED_MODE */
+                        }
+                }
+                return;
+        }
+
+        if (isr & KW_I2C_IRQ_ADDR) {
+                ack = read_reg(reg_status);
+                if (iface->state != state_addr) {
+                        write_reg(reg_isr, KW_I2C_IRQ_ADDR);
+                        WRONG_STATE("KW_I2C_IRQ_ADDR"); 
+                        do_stop(iface, -EIO);
+                        return;
+                }
+                if ((ack & KW_I2C_STAT_LAST_AAK) == 0) {
+                        iface->state = state_stop;                   
+                        iface->result = -ENODEV;
+                        pr_debug("KW: NAK on address\n");
+                } else {
+                        /* Handle rw "quick" mode */
+                        if (iface->datalen == 0) {
+                                do_stop(iface, 0);
+                        } else if (iface->read_write == I2C_SMBUS_READ) {
+                                iface->state = state_read;
+                                if (iface->datalen > 1)
+                                        write_reg(reg_control, KW_I2C_CTL_AAK);
+                        } else {
+                                iface->state = state_write;
+                                write_reg(reg_data, *(iface->data++));
+                                iface->datalen--;
+                        }
+                }
+                write_reg(reg_isr, KW_I2C_IRQ_ADDR);
+        }
+
+        if (isr & KW_I2C_IRQ_DATA) {
+                if (iface->state == state_read) {
+                        *(iface->data++) = read_reg(reg_data);
+                        write_reg(reg_isr, KW_I2C_IRQ_DATA);
+                        iface->datalen--;
+                        if (iface->datalen == 0)
+                                iface->state = state_stop;
+                        else if (iface->datalen == 1)
+                                write_reg(reg_control, 0);
+                } else if (iface->state == state_write) {
+                        /* Check ack status */
+                        ack = read_reg(reg_status);
+                        if ((ack & KW_I2C_STAT_LAST_AAK) == 0) {
+                                pr_debug("KW: nack on data write (%x): %x\n",
+                                    iface->data[-1], ack);
+                                do_stop(iface, -EIO);
+                        } else if (iface->datalen) {
+                                write_reg(reg_data, *(iface->data++));
+                                iface->datalen--;
+                        } else {
+                                write_reg(reg_control, KW_I2C_CTL_STOP);
+                                iface->state = state_stop;
+                                iface->result = 0;
+                        }
+                        write_reg(reg_isr, KW_I2C_IRQ_DATA);
+                } else {
+                        write_reg(reg_isr, KW_I2C_IRQ_DATA);
+                        WRONG_STATE("KW_I2C_IRQ_DATA"); 
+                        if (iface->state != state_stop)
+                                do_stop(iface, -EIO);
+                }
+        }
+
+        if (isr & KW_I2C_IRQ_STOP) {
+                write_reg(reg_isr, KW_I2C_IRQ_STOP);
+                if (iface->state != state_stop) {
+                        WRONG_STATE("KW_I2C_IRQ_STOP");
+                        iface->result = -EIO;
+                }
+                iface->state = state_idle;
+                write_reg(reg_ier, 0x00);
+#ifndef POLLED_MODE
+                complete(&iface->complete);
+#endif /* POLLED_MODE */                        
+        }
+
+        if (isr & KW_I2C_IRQ_START)
+                write_reg(reg_isr, KW_I2C_IRQ_START);
+}
+
+#ifndef POLLED_MODE
+
+/* Interrupt handler */
+static irqreturn_t
+keywest_irq(int irq, void *dev_id, struct pt_regs *regs)
+{
+        struct keywest_iface *iface = (struct keywest_iface *)dev_id;
+        unsigned long flags;
+
+        spin_lock_irqsave(&iface->lock, flags);
+        del_timer(&iface->timeout_timer);
+        handle_interrupt(iface, read_reg(reg_isr));
+        if (iface->state != state_idle) {
+                iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
+                add_timer(&iface->timeout_timer);
+        }
+        spin_unlock_irqrestore(&iface->lock, flags);
+        return IRQ_HANDLED;
+}
+
+static void
+keywest_timeout(unsigned long data)
+{
+        struct keywest_iface *iface = (struct keywest_iface *)data;
+        unsigned long flags;
+
+        pr_debug("timeout !\n");
+        spin_lock_irqsave(&iface->lock, flags);
+        handle_interrupt(iface, read_reg(reg_isr));
+        if (iface->state != state_idle) {
+                iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
+                add_timer(&iface->timeout_timer);
+        }
+        spin_unlock_irqrestore(&iface->lock, flags);
+}
+
+#endif /* POLLED_MODE */
+
+/*
+ * SMBUS-type transfer entrypoint
+ */
+static s32
+keywest_smbus_xfer(     struct i2c_adapter*     adap,
+                        u16                     addr,
+                        unsigned short          flags,
+                        char                    read_write,
+                        u8                      command,
+                        int                     size,
+                        union i2c_smbus_data*   data)
+{
+        struct keywest_chan* chan = i2c_get_adapdata(adap);
+        struct keywest_iface* iface = chan->iface;
+        int len;
+        u8* buffer;
+        u16 cur_word;
+        int rc = 0;
+
+        if (iface->state == state_dead)
+                return -ENXIO;
+                
+        /* Prepare datas & select mode */
+        iface->cur_mode &= ~KW_I2C_MODE_MODE_MASK;
+        switch (size) {
+        case I2C_SMBUS_QUICK:
+                len = 0;
+                buffer = NULL;
+                iface->cur_mode |= KW_I2C_MODE_STANDARD;
+                break;
+        case I2C_SMBUS_BYTE:
+                len = 1;
+                buffer = &data->byte;
+                iface->cur_mode |= KW_I2C_MODE_STANDARD;
+                break;
+        case I2C_SMBUS_BYTE_DATA:
+                len = 1;
+                buffer = &data->byte;
+                iface->cur_mode |= KW_I2C_MODE_STANDARDSUB;
+                break;
+        case I2C_SMBUS_WORD_DATA:
+                len = 2;
+                cur_word = cpu_to_le16(data->word);
+                buffer = (u8 *)&cur_word;
+                iface->cur_mode |= KW_I2C_MODE_STANDARDSUB;
+                break;
+        case I2C_SMBUS_BLOCK_DATA:
+                len = data->block[0];
+                buffer = &data->block[1];
+                iface->cur_mode |= KW_I2C_MODE_STANDARDSUB;
+                break;
+        default:
+                return -1;
+        }
+
+        /* Turn a standardsub read into a combined mode access */
+        if (read_write == I2C_SMBUS_READ
+            && (iface->cur_mode & KW_I2C_MODE_MODE_MASK) == KW_I2C_MODE_STANDARDSUB) {
+                iface->cur_mode &= ~KW_I2C_MODE_MODE_MASK;
+                iface->cur_mode |= KW_I2C_MODE_COMBINED;
+        }
+
+        /* Original driver had this limitation */
+        if (len > 32)
+                len = 32;
+
+        if (pmac_low_i2c_lock(iface->node))
+                return -ENXIO;
+
+        pr_debug("chan: %d, addr: 0x%x, transfer len: %d, read: %d\n",
+                chan->chan_no, addr, len, read_write == I2C_SMBUS_READ);
+
+        iface->data = buffer;
+        iface->datalen = len;
+        iface->state = state_addr;
+        iface->result = 0;
+        iface->read_write = read_write;
+        
+        /* Setup channel & clear pending irqs */
+        write_reg(reg_isr, read_reg(reg_isr));
+        write_reg(reg_mode, iface->cur_mode | (chan->chan_no << 4));
+        write_reg(reg_status, 0);
+
+        /* Set up address and r/w bit */
+        write_reg(reg_addr,
+                (addr << 1) | ((read_write == I2C_SMBUS_READ) ? 0x01 : 0x00));
+
+        /* Set up the sub address */
+        if ((iface->cur_mode & KW_I2C_MODE_MODE_MASK) == KW_I2C_MODE_STANDARDSUB
+            || (iface->cur_mode & KW_I2C_MODE_MODE_MASK) == KW_I2C_MODE_COMBINED)
+                write_reg(reg_subaddr, command);
+
+#ifndef POLLED_MODE
+        /* Arm timeout */
+        iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
+        add_timer(&iface->timeout_timer);
+#endif
+
+        /* Start sending address & enable interrupt*/
+        write_reg(reg_control, KW_I2C_CTL_XADDR);
+        write_reg(reg_ier, KW_I2C_IRQ_MASK);
+
+#ifdef POLLED_MODE
+        pr_debug("using polled mode...\n");
+        /* State machine, to turn into an interrupt handler */
+        while(iface->state != state_idle) {
+                unsigned long flags;
+
+                u8 isr = wait_interrupt(iface);
+                spin_lock_irqsave(&iface->lock, flags);
+                handle_interrupt(iface, isr);
+                spin_unlock_irqrestore(&iface->lock, flags);
+        }
+#else /* POLLED_MODE */
+        pr_debug("using interrupt mode...\n");
+        wait_for_completion(&iface->complete);  
+#endif /* POLLED_MODE */        
+
+        rc = iface->result;     
+        pr_debug("transfer done, result: %d\n", rc);
+
+        if (rc == 0 && size == I2C_SMBUS_WORD_DATA && read_write == I2C_SMBUS_READ)
+                data->word = le16_to_cpu(cur_word);
+        
+        /* Release sem */
+        pmac_low_i2c_unlock(iface->node);
+        
+        return rc;
+}
+
+/*
+ * Generic i2c master transfer entrypoint
+ */
+static int
+keywest_xfer(   struct i2c_adapter *adap,
+                struct i2c_msg *msgs, 
+                int num)
+{
+        struct keywest_chan* chan = i2c_get_adapdata(adap);
+        struct keywest_iface* iface = chan->iface;
+        struct i2c_msg *pmsg;
+        int i, completed;
+        int rc = 0;
+
+        if (iface->state == state_dead)
+                return -ENXIO;
+
+        if (pmac_low_i2c_lock(iface->node))
+                return -ENXIO;
+
+        /* Set adapter to standard mode */
+        iface->cur_mode &= ~KW_I2C_MODE_MODE_MASK;
+        iface->cur_mode |= KW_I2C_MODE_STANDARD;
+
+        completed = 0;
+        for (i = 0; rc >= 0 && i < num;) {
+                u8 addr;
+                
+                pmsg = &msgs[i++];
+                addr = pmsg->addr;
+                if (pmsg->flags & I2C_M_TEN) {
+                        printk(KERN_ERR "i2c-keywest: 10 bits addr not supported !\n");
+                        rc = -EINVAL;
+                        break;
+                }
+                pr_debug("xfer: chan: %d, doing %s %d bytes to 0x%02x - %d of %d messages\n",
+                     chan->chan_no,
+                     pmsg->flags & I2C_M_RD ? "read" : "write",
+                     pmsg->len, addr, i, num);
+    
+                /* Setup channel & clear pending irqs */
+                write_reg(reg_mode, iface->cur_mode | (chan->chan_no << 4));
+                write_reg(reg_isr, read_reg(reg_isr));
+                write_reg(reg_status, 0);
+                
+                iface->data = pmsg->buf;
+                iface->datalen = pmsg->len;
+                iface->state = state_addr;
+                iface->result = 0;
+                if (pmsg->flags & I2C_M_RD)
+                        iface->read_write = I2C_SMBUS_READ;
+                else
+                        iface->read_write = I2C_SMBUS_WRITE;
+
+                /* Set up address and r/w bit */
+                if (pmsg->flags & I2C_M_REV_DIR_ADDR)
+                        addr ^= 1;              
+                write_reg(reg_addr,
+                        (addr << 1) |
+                        ((iface->read_write == I2C_SMBUS_READ) ? 0x01 : 0x00));
+
+#ifndef POLLED_MODE
+                /* Arm timeout */
+                iface->timeout_timer.expires = jiffies + POLL_TIMEOUT;
+                add_timer(&iface->timeout_timer);
+#endif
+
+                /* Start sending address & enable interrupt*/
+                write_reg(reg_ier, KW_I2C_IRQ_MASK);
+                write_reg(reg_control, KW_I2C_CTL_XADDR);
+
+#ifdef POLLED_MODE
+                pr_debug("using polled mode...\n");
+                /* State machine, to turn into an interrupt handler */
+                while(iface->state != state_idle) {
+                        u8 isr = wait_interrupt(iface);
+                        handle_interrupt(iface, isr);
+                }
+#else /* POLLED_MODE */
+                pr_debug("using interrupt mode...\n");
+                wait_for_completion(&iface->complete);  
+#endif /* POLLED_MODE */        
+
+                rc = iface->result;
+                if (rc == 0)
+                        completed++;
+                pr_debug("transfer done, result: %d\n", rc);
+        }
+
+        /* Release sem */
+        pmac_low_i2c_unlock(iface->node);
+
+        return completed;
+}
+
+static u32
+keywest_func(struct i2c_adapter * adapter)
+{
+        return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
+               I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
+               I2C_FUNC_SMBUS_BLOCK_DATA;
+}
+
+/* For now, we only handle combined mode (smbus) */
+static struct i2c_algorithm keywest_algorithm = {
+        .name           = "Keywest i2c",
+        .id             = I2C_ALGO_SMBUS,
+        .smbus_xfer     = keywest_smbus_xfer,
+        .master_xfer    = keywest_xfer,
+        .functionality  = keywest_func,
+};
+
+
+static int
+create_iface(struct device_node *np, struct device *dev)
+{
+        unsigned long steps;
+        unsigned bsteps, tsize, i, nchan, addroffset;
+        struct keywest_iface* iface;
+        u32 *psteps, *prate;
+        int rc;
+
+        if (pmac_low_i2c_lock(np))
+                return -ENODEV;
+
+        psteps = (u32 *)get_property(np, "AAPL,address-step", NULL);
+        steps = psteps ? (*psteps) : 0x10;
+
+        /* Hrm... maybe we can be smarter here */
+        for (bsteps = 0; (steps & 0x01) == 0; bsteps++)
+                steps >>= 1;
+
+        if (np->parent->name[0] == 'u') {
+                nchan = 2;
+                addroffset = 3;
+        } else {
+                addroffset = 0;
+                nchan = 1;
+        }
+
+        tsize = sizeof(struct keywest_iface) +
+                (sizeof(struct keywest_chan) + 4) * nchan;
+        iface = (struct keywest_iface *) kmalloc(tsize, GFP_KERNEL);
+        if (iface == NULL) {
+                printk(KERN_ERR "i2c-keywest: can't allocate inteface !\n");
+                pmac_low_i2c_unlock(np);
+                return -ENOMEM;
+        }
+        memset(iface, 0, tsize);
+        spin_lock_init(&iface->lock);
+        init_completion(&iface->complete);
+        iface->node = of_node_get(np);
+        iface->bsteps = bsteps;
+        iface->chan_count = nchan;
+        iface->state = state_idle;
+        iface->irq = np->intrs[0].line;
+        iface->channels = (struct keywest_chan *)
+                (((unsigned long)(iface + 1) + 3UL) & ~3UL);
+        iface->base = ioremap(np->addrs[0].address + addroffset,
+                                                np->addrs[0].size);
+        if (!iface->base) {
+                printk(KERN_ERR "i2c-keywest: can't map inteface !\n");
+                kfree(iface);
+                pmac_low_i2c_unlock(np);
+                return -ENOMEM;
+        }
+
+#ifndef POLLED_MODE
+        init_timer(&iface->timeout_timer);
+        iface->timeout_timer.function = keywest_timeout;
+        iface->timeout_timer.data = (unsigned long)iface;
+#endif
+
+        /* Select interface rate */
+        iface->cur_mode = KW_I2C_MODE_100KHZ;
+        prate = (u32 *)get_property(np, "AAPL,i2c-rate", NULL);
+        if (prate) switch(*prate) {
+        case 100:
+                iface->cur_mode = KW_I2C_MODE_100KHZ;
+                break;
+        case 50:
+                iface->cur_mode = KW_I2C_MODE_50KHZ;
+                break;
+        case 25:
+                iface->cur_mode = KW_I2C_MODE_25KHZ;
+                break;
+        default:
+                printk(KERN_WARNING "i2c-keywest: unknown rate %ldKhz, using 100KHz\n",
+                       (long)*prate);
+        }
+        
+        /* Select standard mode by default */
+        iface->cur_mode |= KW_I2C_MODE_STANDARD;
+        
+        /* Write mode */
+        write_reg(reg_mode, iface->cur_mode);
+        
+        /* Switch interrupts off & clear them*/
+        write_reg(reg_ier, 0x00);
+        write_reg(reg_isr, KW_I2C_IRQ_MASK);
+
+#ifndef POLLED_MODE
+        /* Request chip interrupt */    
+        rc = request_irq(iface->irq, keywest_irq, SA_INTERRUPT, "keywest i2c", iface);
+        if (rc) {
+                printk(KERN_ERR "i2c-keywest: can't get IRQ %d !\n", iface->irq);
+                iounmap(iface->base);
+                kfree(iface);
+                pmac_low_i2c_unlock(np);
+                return -ENODEV;
+        }
+#endif /* POLLED_MODE */
+
+        pmac_low_i2c_unlock(np);
+        dev_set_drvdata(dev, iface);
+        
+        for (i=0; i<nchan; i++) {
+                struct keywest_chan* chan = &iface->channels[i];
+                u8 addr;
+                
+                sprintf(chan->adapter.name, "%s %d", np->parent->name, i);
+                chan->iface = iface;
+                chan->chan_no = i;
+                chan->adapter.id = I2C_ALGO_SMBUS;
+                chan->adapter.algo = &keywest_algorithm;
+                chan->adapter.algo_data = NULL;
+                chan->adapter.client_register = NULL;
+                chan->adapter.client_unregister = NULL;
+                i2c_set_adapdata(&chan->adapter, chan);
+                chan->adapter.dev.parent = dev;
+
+                rc = i2c_add_adapter(&chan->adapter);
+                if (rc) {
+                        printk("i2c-keywest.c: Adapter %s registration failed\n",
+                                chan->adapter.name);
+                        i2c_set_adapdata(&chan->adapter, NULL);
+                }
+                if (probe) {
+                        printk("Probe: ");
+                        for (addr = 0x00; addr <= 0x7f; addr++) {
+                                if (i2c_smbus_xfer(&chan->adapter,addr,
+                                    0,0,0,I2C_SMBUS_QUICK,NULL) >= 0)
+                                        printk("%02x ", addr);
+                        }
+                        printk("\n");
+                }
+        }
+
+        printk(KERN_INFO "Found KeyWest i2c on \"%s\", %d channel%s, stepping: %d bits\n",
+                np->parent->name, nchan, nchan > 1 ? "s" : "", bsteps);
+                
+        return 0;
+}
+
+static int
+dispose_iface(struct device *dev)
+{
+        struct keywest_iface *iface = dev_get_drvdata(dev);
+        int i, rc;
+        
+        /* Make sure we stop all activity */
+        if (pmac_low_i2c_lock(iface->node))
+                return -ENODEV;
+
+#ifndef POLLED_MODE
+        spin_lock_irq(&iface->lock);
+        while (iface->state != state_idle) {
+                spin_unlock_irq(&iface->lock);
+                msleep(100);
+                spin_lock_irq(&iface->lock);
+        }
+#endif /* POLLED_MODE */
+        iface->state = state_dead;
+#ifndef POLLED_MODE
+        spin_unlock_irq(&iface->lock);
+        free_irq(iface->irq, iface);
+#endif /* POLLED_MODE */
+
+        pmac_low_i2c_unlock(iface->node);
+
+        /* Release all channels */
+        for (i=0; i<iface->chan_count; i++) {
+                struct keywest_chan* chan = &iface->channels[i];
+                if (i2c_get_adapdata(&chan->adapter) == NULL)
+                        continue;
+                rc = i2c_del_adapter(&chan->adapter);
+                i2c_set_adapdata(&chan->adapter, NULL);
+                /* We aren't that prepared to deal with this... */
+                if (rc)
+                        printk("i2c-keywest.c: i2c_del_adapter failed, that's bad !\n");
+        }
+        iounmap(iface->base);
+        dev_set_drvdata(dev, NULL);
+        of_node_put(iface->node);
+        kfree(iface);
+
+        return 0;
+}
+
+static int
+create_iface_macio(struct macio_dev* dev, const struct of_match *match)
+{
+        return create_iface(dev->ofdev.node, &dev->ofdev.dev);
+}
+
+static int
+dispose_iface_macio(struct macio_dev* dev)
+{
+        return dispose_iface(&dev->ofdev.dev);
+}
+
+static int
+create_iface_of_platform(struct of_device* dev, const struct of_match *match)
+{
+        return create_iface(dev->node, &dev->dev);
+}
+
+static int
+dispose_iface_of_platform(struct of_device* dev)
+{
+        return dispose_iface(&dev->dev);
+}
+
+static struct of_match i2c_keywest_match[] = 
+{
+        {
+        .name           = OF_ANY_MATCH,
+        .type           = "i2c",
+        .compatible     = "keywest"
+        },
+        {},
+};
+
+static struct macio_driver i2c_keywest_macio_driver = 
+{
+        .name           = "i2c-keywest",
+        .match_table    = i2c_keywest_match,
+        .probe          = create_iface_macio,
+        .remove         = dispose_iface_macio
+};
+
+static struct of_platform_driver i2c_keywest_of_platform_driver = 
+{
+        .name           = "i2c-keywest",
+        .match_table    = i2c_keywest_match,
+        .probe          = create_iface_of_platform,
+        .remove         = dispose_iface_of_platform
+};
+
+static int __init
+i2c_keywest_init(void)
+{
+        of_register_driver(&i2c_keywest_of_platform_driver);
+        macio_register_driver(&i2c_keywest_macio_driver);
+
+        return 0;
+}
+
+static void __exit
+i2c_keywest_cleanup(void)
+{
+        of_unregister_driver(&i2c_keywest_of_platform_driver);
+        macio_unregister_driver(&i2c_keywest_macio_driver);
+}
+
+module_init(i2c_keywest_init);
+module_exit(i2c_keywest_cleanup);
diff --git a/drivers/i2c/busses/i2c-keywest.h b/drivers/i2c/busses/i2c-keywest.h
new file mode 100644
index 000000000000..c5022e1ca6ff
--- /dev/null
+++ b/drivers/i2c/busses/i2c-keywest.h
@@ -0,0 +1,108 @@
+#ifndef __I2C_KEYWEST_H__
+#define __I2C_KEYWEST_H__
+
+/* The Tumbler audio equalizer can be really slow sometimes */
+#define POLL_TIMEOUT            (2*HZ)
+
+/* Register indices */
+typedef enum {
+        reg_mode = 0,
+        reg_control,
+        reg_status,
+        reg_isr,
+        reg_ier,
+        reg_addr,
+        reg_subaddr,
+        reg_data
+} reg_t;
+
+
+/* Mode register */
+#define KW_I2C_MODE_100KHZ      0x00
+#define KW_I2C_MODE_50KHZ       0x01
+#define KW_I2C_MODE_25KHZ       0x02
+#define KW_I2C_MODE_DUMB        0x00
+#define KW_I2C_MODE_STANDARD    0x04
+#define KW_I2C_MODE_STANDARDSUB 0x08
+#define KW_I2C_MODE_COMBINED    0x0C
+#define KW_I2C_MODE_MODE_MASK   0x0C
+#define KW_I2C_MODE_CHAN_MASK   0xF0
+
+/* Control register */
+#define KW_I2C_CTL_AAK          0x01
+#define KW_I2C_CTL_XADDR        0x02
+#define KW_I2C_CTL_STOP         0x04
+#define KW_I2C_CTL_START        0x08
+
+/* Status register */
+#define KW_I2C_STAT_BUSY        0x01
+#define KW_I2C_STAT_LAST_AAK    0x02
+#define KW_I2C_STAT_LAST_RW     0x04
+#define KW_I2C_STAT_SDA         0x08
+#define KW_I2C_STAT_SCL         0x10
+
+/* IER & ISR registers */
+#define KW_I2C_IRQ_DATA         0x01
+#define KW_I2C_IRQ_ADDR         0x02
+#define KW_I2C_IRQ_STOP         0x04
+#define KW_I2C_IRQ_START        0x08
+#define KW_I2C_IRQ_MASK         0x0F
+
+/* Physical interface */
+struct keywest_iface
+{
+        struct device_node      *node;
+        void __iomem *          base;
+        unsigned                bsteps;
+        int                     irq;
+        spinlock_t              lock;
+        struct keywest_chan     *channels;
+        unsigned                chan_count;
+        u8                      cur_mode;
+        char                    read_write;
+        u8                      *data;
+        unsigned                datalen;
+        int                     state;
+        int                     result;
+        struct timer_list       timeout_timer;
+        struct completion       complete;
+};
+
+enum {
+        state_idle,
+        state_addr,
+        state_read,
+        state_write,
+        state_stop,
+        state_dead
+};
+
+/* Channel on an interface */
+struct keywest_chan
+{
+        struct i2c_adapter      adapter;
+        struct keywest_iface*   iface;
+        unsigned                chan_no;
+};
+
+/* Register access */
+
+static inline u8 __read_reg(struct keywest_iface *iface, reg_t reg)
+{
+        return in_8(iface->base
+                + (((unsigned)reg) << iface->bsteps));
+}
+
+static inline void __write_reg(struct keywest_iface *iface, reg_t reg, u8 val)
+{
+        out_8(iface->base
+                + (((unsigned)reg) << iface->bsteps), val);
+        (void)__read_reg(iface, reg_subaddr);
+}
+
+#define write_reg(reg, val)     __write_reg(iface, reg, val) 
+#define read_reg(reg)           __read_reg(iface, reg) 
+
+
+
+#endif /* __I2C_KEYWEST_H__ */
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
new file mode 100644
index 000000000000..75b8d867dae1
--- /dev/null
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -0,0 +1,496 @@
+/*
+ * (C) Copyright 2003-2004
+ * Humboldt Solutions Ltd, adrian@humboldt.co.uk.
+
+ * This is a combined i2c adapter and algorithm driver for the
+ * MPC107/Tsi107 PowerPC northbridge and processors that include
+ * the same I2C unit (8240, 8245, 85xx).
+ *
+ * Release 0.8
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <asm/io.h>
+#ifdef CONFIG_FSL_OCP
+#include <asm/ocp.h>
+#define FSL_I2C_DEV_SEPARATE_DFSRR FS_I2C_SEPARATE_DFSRR
+#define FSL_I2C_DEV_CLOCK_5200 FS_I2C_CLOCK_5200
+#else
+#include <linux/fsl_devices.h>
+#endif
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+
+#define MPC_I2C_ADDR  0x00
+#define MPC_I2C_FDR     0x04
+#define MPC_I2C_CR      0x08
+#define MPC_I2C_SR      0x0c
+#define MPC_I2C_DR      0x10
+#define MPC_I2C_DFSRR 0x14
+#define MPC_I2C_REGION 0x20
+
+#define CCR_MEN  0x80
+#define CCR_MIEN 0x40
+#define CCR_MSTA 0x20
+#define CCR_MTX  0x10
+#define CCR_TXAK 0x08
+#define CCR_RSTA 0x04
+
+#define CSR_MCF  0x80
+#define CSR_MAAS 0x40
+#define CSR_MBB  0x20
+#define CSR_MAL  0x10
+#define CSR_SRW  0x04
+#define CSR_MIF  0x02
+#define CSR_RXAK 0x01
+
+struct mpc_i2c {
+        char *base;
+        u32 interrupt;
+        wait_queue_head_t queue;
+        struct i2c_adapter adap;
+        int irq;
+        u32 flags;
+};
+
+static __inline__ void writeccr(struct mpc_i2c *i2c, u32 x)
+{
+        writeb(x, i2c->base + MPC_I2C_CR);
+}
+
+static irqreturn_t mpc_i2c_isr(int irq, void *dev_id, struct pt_regs *regs)
+{
+        struct mpc_i2c *i2c = dev_id;
+        if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
+                /* Read again to allow register to stabilise */
+                i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
+                writeb(0, i2c->base + MPC_I2C_SR);
+                wake_up_interruptible(&i2c->queue);
+        }
+        return IRQ_HANDLED;
+}
+
+static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
+{
+        unsigned long orig_jiffies = jiffies;
+        u32 x;
+        int result = 0;
+
+        if (i2c->irq == 0)
+        {
+                while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
+                        schedule();
+                        if (time_after(jiffies, orig_jiffies + timeout)) {
+                                pr_debug("I2C: timeout\n");
+                                result = -EIO;
+                                break;
+                        }
+                }
+                x = readb(i2c->base + MPC_I2C_SR);
+                writeb(0, i2c->base + MPC_I2C_SR);
+        } else {
+                /* Interrupt mode */
+                result = wait_event_interruptible_timeout(i2c->queue,
+                        (i2c->interrupt & CSR_MIF), timeout * HZ);
+
+                if (unlikely(result < 0))
+                        pr_debug("I2C: wait interrupted\n");
+                else if (unlikely(!(i2c->interrupt & CSR_MIF))) {
+                        pr_debug("I2C: wait timeout\n");
+                        result = -ETIMEDOUT;
+                }
+
+                x = i2c->interrupt;
+                i2c->interrupt = 0;
+        }
+
+        if (result < 0)
+                return result;
+
+        if (!(x & CSR_MCF)) {
+                pr_debug("I2C: unfinished\n");
+                return -EIO;
+        }
+
+        if (x & CSR_MAL) {
+                pr_debug("I2C: MAL\n");
+                return -EIO;
+        }
+
+        if (writing && (x & CSR_RXAK)) {
+                pr_debug("I2C: No RXAK\n");
+                /* generate stop */
+                writeccr(i2c, CCR_MEN);
+                return -EIO;
+        }
+        return 0;
+}
+
+static void mpc_i2c_setclock(struct mpc_i2c *i2c)
+{
+        /* Set clock and filters */
+        if (i2c->flags & FSL_I2C_DEV_SEPARATE_DFSRR) {
+                writeb(0x31, i2c->base + MPC_I2C_FDR);
+                writeb(0x10, i2c->base + MPC_I2C_DFSRR);
+        } else if (i2c->flags & FSL_I2C_DEV_CLOCK_5200)
+                writeb(0x3f, i2c->base + MPC_I2C_FDR);
+        else
+                writel(0x1031, i2c->base + MPC_I2C_FDR);
+}
+
+static void mpc_i2c_start(struct mpc_i2c *i2c)
+{
+        /* Clear arbitration */
+        writeb(0, i2c->base + MPC_I2C_SR);
+        /* Start with MEN */
+        writeccr(i2c, CCR_MEN);
+}
+
+static void mpc_i2c_stop(struct mpc_i2c *i2c)
+{
+        writeccr(i2c, CCR_MEN);
+}
+
+static int mpc_write(struct mpc_i2c *i2c, int target,
+                     const u8 * data, int length, int restart)
+{
+        int i;
+        unsigned timeout = i2c->adap.timeout;
+        u32 flags = restart ? CCR_RSTA : 0;
+
+        /* Start with MEN */
+        if (!restart)
+                writeccr(i2c, CCR_MEN);
+        /* Start as master */
+        writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
+        /* Write target byte */
+        writeb((target << 1), i2c->base + MPC_I2C_DR);
+
+        if (i2c_wait(i2c, timeout, 1) < 0)
+                return -1;
+
+        for (i = 0; i < length; i++) {
+                /* Write data byte */
+                writeb(data[i], i2c->base + MPC_I2C_DR);
+
+                if (i2c_wait(i2c, timeout, 1) < 0)
+                        return -1;
+        }
+
+        return 0;
+}
+
+static int mpc_read(struct mpc_i2c *i2c, int target,
+                    u8 * data, int length, int restart)
+{
+        unsigned timeout = i2c->adap.timeout;
+        int i;
+        u32 flags = restart ? CCR_RSTA : 0;
+
+        /* Start with MEN */
+        if (!restart)
+                writeccr(i2c, CCR_MEN);
+        /* Switch to read - restart */
+        writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
+        /* Write target address byte - this time with the read flag set */
+        writeb((target << 1) | 1, i2c->base + MPC_I2C_DR);
+
+        if (i2c_wait(i2c, timeout, 1) < 0)
+                return -1;
+
+        if (length) {
+                if (length == 1)
+                        writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
+                else
+                        writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA);
+                /* Dummy read */
+                readb(i2c->base + MPC_I2C_DR);
+        }
+
+        for (i = 0; i < length; i++) {
+                if (i2c_wait(i2c, timeout, 0) < 0)
+                        return -1;
+
+                /* Generate txack on next to last byte */
+                if (i == length - 2)
+                        writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
+                /* Generate stop on last byte */
+                if (i == length - 1)
+                        writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_TXAK);
+                data[i] = readb(i2c->base + MPC_I2C_DR);
+        }
+
+        return length;
+}
+
+static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
+{
+        struct i2c_msg *pmsg;
+        int i;
+        int ret = 0;
+        unsigned long orig_jiffies = jiffies;
+        struct mpc_i2c *i2c = i2c_get_adapdata(adap);
+
+        mpc_i2c_start(i2c);
+
+        /* Allow bus up to 1s to become not busy */
+        while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
+                if (signal_pending(current)) {
+                        pr_debug("I2C: Interrupted\n");
+                        return -EINTR;
+                }
+                if (time_after(jiffies, orig_jiffies + HZ)) {
+                        pr_debug("I2C: timeout\n");
+                        return -EIO;
+                }
+                schedule();
+        }
+
+        for (i = 0; ret >= 0 && i < num; i++) {
+                pmsg = &msgs[i];
+                pr_debug("Doing %s %d bytes to 0x%02x - %d of %d messages\n",
+                         pmsg->flags & I2C_M_RD ? "read" : "write",
+                         pmsg->len, pmsg->addr, i + 1, num);
+                if (pmsg->flags & I2C_M_RD)
+                        ret =
+                            mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
+                else
+                        ret =
+                            mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
+        }
+        mpc_i2c_stop(i2c);
+        return (ret < 0) ? ret : num;
+}
+
+static u32 mpc_functionality(struct i2c_adapter *adap)
+{
+        return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
+}
+
+static struct i2c_algorithm mpc_algo = {
+        .name = "MPC algorithm",
+        .id = I2C_ALGO_MPC107,
+        .master_xfer = mpc_xfer,
+        .functionality = mpc_functionality,
+};
+
+static struct i2c_adapter mpc_ops = {
+        .owner = THIS_MODULE,
+        .name = "MPC adapter",
+        .id = I2C_ALGO_MPC107 | I2C_HW_MPC107,
+        .algo = &mpc_algo,
+        .class = I2C_CLASS_HWMON,
+        .timeout = 1,
+        .retries = 1
+};
+
+#ifdef CONFIG_FSL_OCP
+static int __devinit mpc_i2c_probe(struct ocp_device *ocp)
+{
+        int result = 0;
+        struct mpc_i2c *i2c;
+
+        if (!(i2c = kmalloc(sizeof(*i2c), GFP_KERNEL))) {
+                return -ENOMEM;
+        }
+        memset(i2c, 0, sizeof(*i2c));
+
+        i2c->irq = ocp->def->irq;
+        i2c->flags = ((struct ocp_fs_i2c_data *)ocp->def->additions)->flags;
+        init_waitqueue_head(&i2c->queue);
+
+        if (!request_mem_region(ocp->def->paddr, MPC_I2C_REGION, "i2c-mpc")) {
+                printk(KERN_ERR "i2c-mpc - resource unavailable\n");
+                return -ENODEV;
+        }
+
+        i2c->base = ioremap(ocp->def->paddr, MPC_I2C_REGION);
+
+        if (!i2c->base) {
+                printk(KERN_ERR "i2c-mpc - failed to map controller\n");
+                result = -ENOMEM;
+                goto fail_map;
+        }
+
+        if (i2c->irq != OCP_IRQ_NA)
+        {
+                if ((result = request_irq(ocp->def->irq, mpc_i2c_isr,
+                                          0, "i2c-mpc", i2c)) < 0) {
+                        printk(KERN_ERR
+                               "i2c-mpc - failed to attach interrupt\n");
+                        goto fail_irq;
+                }
+        } else
+                i2c->irq = 0;
+
+        i2c->adap = mpc_ops;
+        i2c_set_adapdata(&i2c->adap, i2c);
+
+        if ((result = i2c_add_adapter(&i2c->adap)) < 0) {
+                printk(KERN_ERR "i2c-mpc - failed to add adapter\n");
+                goto fail_add;
+        }
+
+        mpc_i2c_setclock(i2c);
+        ocp_set_drvdata(ocp, i2c);
+        return result;
+
+      fail_add:
+        if (ocp->def->irq != OCP_IRQ_NA)
+                free_irq(ocp->def->irq, 0);
+      fail_irq:
+        iounmap(i2c->base);
+      fail_map:
+        release_mem_region(ocp->def->paddr, MPC_I2C_REGION);
+        kfree(i2c);
+        return result;
+}
+static void __devexit mpc_i2c_remove(struct ocp_device *ocp)
+{
+        struct mpc_i2c *i2c = ocp_get_drvdata(ocp);
+        ocp_set_drvdata(ocp, NULL);
+        i2c_del_adapter(&i2c->adap);
+
+        if (ocp->def->irq != OCP_IRQ_NA)
+                free_irq(i2c->irq, i2c);
+        iounmap(i2c->base);
+        release_mem_region(ocp->def->paddr, MPC_I2C_REGION);
+        kfree(i2c);
+}
+
+static struct ocp_device_id mpc_iic_ids[] __devinitdata = {
+        {.vendor = OCP_VENDOR_FREESCALE,.function = OCP_FUNC_IIC},
+        {.vendor = OCP_VENDOR_INVALID}
+};
+
+MODULE_DEVICE_TABLE(ocp, mpc_iic_ids);
+
+static struct ocp_driver mpc_iic_driver = {
+        .name = "iic",
+        .id_table = mpc_iic_ids,
+        .probe = mpc_i2c_probe,
+        .remove = __devexit_p(mpc_i2c_remove)
+};
+
+static int __init iic_init(void)
+{
+        return ocp_register_driver(&mpc_iic_driver);
+}
+
+static void __exit iic_exit(void)
+{
+        ocp_unregister_driver(&mpc_iic_driver);
+}
+
+module_init(iic_init);
+module_exit(iic_exit);
+#else
+static int fsl_i2c_probe(struct device *device)
+{
+        int result = 0;
+        struct mpc_i2c *i2c;
+        struct platform_device *pdev = to_platform_device(device);
+        struct fsl_i2c_platform_data *pdata;
+        struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+        pdata = (struct fsl_i2c_platform_data *) pdev->dev.platform_data;
+
+        if (!(i2c = kmalloc(sizeof(*i2c), GFP_KERNEL))) {
+                return -ENOMEM;
+        }
+        memset(i2c, 0, sizeof(*i2c));
+
+        i2c->irq = platform_get_irq(pdev, 0);
+        i2c->flags = pdata->device_flags;
+        init_waitqueue_head(&i2c->queue);
+
+        i2c->base = ioremap((phys_addr_t)r->start, MPC_I2C_REGION);
+
+        if (!i2c->base) {
+                printk(KERN_ERR "i2c-mpc - failed to map controller\n");
+                result = -ENOMEM;
+                goto fail_map;
+        }
+
+        if (i2c->irq != 0)
+                if ((result = request_irq(i2c->irq, mpc_i2c_isr,
+                                          0, "fsl-i2c", i2c)) < 0) {
+                        printk(KERN_ERR
+                               "i2c-mpc - failed to attach interrupt\n");
+                        goto fail_irq;
+                }
+
+        i2c->adap = mpc_ops;
+        i2c_set_adapdata(&i2c->adap, i2c);
+        i2c->adap.dev.parent = &pdev->dev;
+        if ((result = i2c_add_adapter(&i2c->adap)) < 0) {
+                printk(KERN_ERR "i2c-mpc - failed to add adapter\n");
+                goto fail_add;
+        }
+
+        mpc_i2c_setclock(i2c);
+        dev_set_drvdata(device, i2c);
+        return result;
+
+      fail_add:
+        if (i2c->irq != 0)
+                free_irq(i2c->irq, 0);
+      fail_irq:
+        iounmap(i2c->base);
+      fail_map:
+        kfree(i2c);
+        return result;
+};
+
+static int fsl_i2c_remove(struct device *device)
+{
+        struct mpc_i2c *i2c = dev_get_drvdata(device);
+
+        dev_set_drvdata(device, NULL);
+        i2c_del_adapter(&i2c->adap);
+
+        if (i2c->irq != 0)
+                free_irq(i2c->irq, i2c);
+
+        iounmap(i2c->base);
+        kfree(i2c);
+        return 0;
+};
+
+/* Structure for a device driver */
+static struct device_driver fsl_i2c_driver = {
+        .name = "fsl-i2c",
+        .bus = &platform_bus_type,
+        .probe = fsl_i2c_probe,
+        .remove = fsl_i2c_remove,
+};
+
+static int __init fsl_i2c_init(void)
+{
+        return driver_register(&fsl_i2c_driver);
+}
+
+static void __exit fsl_i2c_exit(void)
+{
+        driver_unregister(&fsl_i2c_driver);
+}
+
+module_init(fsl_i2c_init);
+module_exit(fsl_i2c_exit);
+
+#endif /* CONFIG_FSL_OCP */
+
+MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
+MODULE_DESCRIPTION
+    ("I2C-Bus adapter for MPC107 bridge and MPC824x/85xx/52xx processors");
+MODULE_LICENSE("GPL");
diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c
new file mode 100644
index 000000000000..5b852782d2f5
--- /dev/null
+++ b/drivers/i2c/busses/i2c-mv64xxx.c
@@ -0,0 +1,598 @@
+/*
+ * drivers/i2c/busses/i2c-mv64xxx.c
+ * 
+ * Driver for the i2c controller on the Marvell line of host bridges for MIPS
+ * and PPC (e.g, gt642[46]0, mv643[46]0, mv644[46]0).
+ *
+ * Author: Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2005 (c) MontaVista, Software, Inc.  This file is licensed under
+ * the terms of the GNU General Public License version 2.  This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/mv643xx.h>
+#include <asm/io.h>
+
+/* Register defines */
+#define MV64XXX_I2C_REG_SLAVE_ADDR                      0x00
+#define MV64XXX_I2C_REG_DATA                            0x04
+#define MV64XXX_I2C_REG_CONTROL                         0x08
+#define MV64XXX_I2C_REG_STATUS                          0x0c
+#define MV64XXX_I2C_REG_BAUD                            0x0c
+#define MV64XXX_I2C_REG_EXT_SLAVE_ADDR                  0x10
+#define MV64XXX_I2C_REG_SOFT_RESET                      0x1c
+
+#define MV64XXX_I2C_REG_CONTROL_ACK                     0x00000004
+#define MV64XXX_I2C_REG_CONTROL_IFLG                    0x00000008
+#define MV64XXX_I2C_REG_CONTROL_STOP                    0x00000010
+#define MV64XXX_I2C_REG_CONTROL_START                   0x00000020
+#define MV64XXX_I2C_REG_CONTROL_TWSIEN                  0x00000040
+#define MV64XXX_I2C_REG_CONTROL_INTEN                   0x00000080
+
+/* Ctlr status values */
+#define MV64XXX_I2C_STATUS_BUS_ERR                      0x00
+#define MV64XXX_I2C_STATUS_MAST_START                   0x08
+#define MV64XXX_I2C_STATUS_MAST_REPEAT_START            0x10
+#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK             0x18
+#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK          0x20
+#define MV64XXX_I2C_STATUS_MAST_WR_ACK                  0x28
+#define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK               0x30
+#define MV64XXX_I2C_STATUS_MAST_LOST_ARB                0x38
+#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK             0x40
+#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK          0x48
+#define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK             0x50
+#define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK          0x58
+#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK           0xd0
+#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK        0xd8
+#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK           0xe0
+#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK        0xe8
+#define MV64XXX_I2C_STATUS_NO_STATUS                    0xf8
+
+/* Driver states */
+enum {
+        MV64XXX_I2C_STATE_INVALID,
+        MV64XXX_I2C_STATE_IDLE,
+        MV64XXX_I2C_STATE_WAITING_FOR_START_COND,
+        MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK,
+        MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK,
+        MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK,
+        MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA,
+        MV64XXX_I2C_STATE_ABORTING,
+};
+
+/* Driver actions */
+enum {
+        MV64XXX_I2C_ACTION_INVALID,
+        MV64XXX_I2C_ACTION_CONTINUE,
+        MV64XXX_I2C_ACTION_SEND_START,
+        MV64XXX_I2C_ACTION_SEND_ADDR_1,
+        MV64XXX_I2C_ACTION_SEND_ADDR_2,
+        MV64XXX_I2C_ACTION_SEND_DATA,
+        MV64XXX_I2C_ACTION_RCV_DATA,
+        MV64XXX_I2C_ACTION_RCV_DATA_STOP,
+        MV64XXX_I2C_ACTION_SEND_STOP,
+};
+
+struct mv64xxx_i2c_data {
+        int                     irq;
+        u32                     state;
+        u32                     action;
+        u32                     cntl_bits;
+        void __iomem            *reg_base;
+        u32                     reg_base_p;
+        u32                     addr1;
+        u32                     addr2;
+        u32                     bytes_left;
+        u32                     byte_posn;
+        u32                     block;
+        int                     rc;
+        u32                     freq_m;
+        u32                     freq_n;
+        wait_queue_head_t       waitq;
+        spinlock_t              lock;
+        struct i2c_msg          *msg;
+        struct i2c_adapter      adapter;
+};
+
+/*
+ *****************************************************************************
+ *
+ *      Finite State Machine & Interrupt Routines
+ *
+ *****************************************************************************
+ */
+static void
+mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
+{
+        /*
+         * If state is idle, then this is likely the remnants of an old
+         * operation that driver has given up on or the user has killed.
+         * If so, issue the stop condition and go to idle.
+         */
+        if (drv_data->state == MV64XXX_I2C_STATE_IDLE) {
+                drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
+                return;
+        }
+
+        if (drv_data->state == MV64XXX_I2C_STATE_ABORTING) {
+                drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
+                drv_data->state = MV64XXX_I2C_STATE_IDLE;
+                return;
+        }
+
+        /* The status from the ctlr [mostly] tells us what to do next */
+        switch (status) {
+        /* Start condition interrupt */
+        case MV64XXX_I2C_STATUS_MAST_START: /* 0x08 */
+        case MV64XXX_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */
+                drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
+                drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
+                break;
+
+        /* Performing a write */
+        case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */
+                if (drv_data->msg->flags & I2C_M_TEN) {
+                        drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
+                        drv_data->state =
+                                MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
+                        break;
+                }
+                /* FALLTHRU */
+        case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */
+        case MV64XXX_I2C_STATUS_MAST_WR_ACK: /* 0x28 */
+                if (drv_data->bytes_left > 0) {
+                        drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
+                        drv_data->state =
+                                MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
+                        drv_data->bytes_left--;
+                } else {
+                        drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
+                        drv_data->state = MV64XXX_I2C_STATE_IDLE;
+                }
+                break;
+
+        /* Performing a read */
+        case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */
+                if (drv_data->msg->flags & I2C_M_TEN) {
+                        drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
+                        drv_data->state =
+                                MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
+                        break;
+                }
+                /* FALLTHRU */
+        case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */
+                if (drv_data->bytes_left == 0) {
+                        drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
+                        drv_data->state = MV64XXX_I2C_STATE_IDLE;
+                        break;
+                }
+                /* FALLTHRU */
+        case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */
+                if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK)
+                        drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
+                else {
+                        drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA;
+                        drv_data->bytes_left--;
+                }
+                drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
+
+                if (drv_data->bytes_left == 1)
+                        drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK;
+                break;
+
+        case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */
+                drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP;
+                drv_data->state = MV64XXX_I2C_STATE_IDLE;
+                break;
+
+        case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */
+        case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */
+        case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */
+                /* Doesn't seem to be a device at other end */
+                drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
+                drv_data->state = MV64XXX_I2C_STATE_IDLE;
+                drv_data->rc = -ENODEV;
+                break;
+
+        default:
+                dev_err(&drv_data->adapter.dev,
+                        "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, "
+                        "status: 0x%x, addr: 0x%x, flags: 0x%x\n",
+                         drv_data->state, status, drv_data->msg->addr,
+                         drv_data->msg->flags);
+                drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
+                drv_data->state = MV64XXX_I2C_STATE_IDLE;
+                drv_data->rc = -EIO;
+        }
+}
+
+static void
+mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
+{
+        switch(drv_data->action) {
+        case MV64XXX_I2C_ACTION_CONTINUE:
+                writel(drv_data->cntl_bits,
+                        drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
+                break;
+
+        case MV64XXX_I2C_ACTION_SEND_START:
+                writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
+                        drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
+                break;
+
+        case MV64XXX_I2C_ACTION_SEND_ADDR_1:
+                writel(drv_data->addr1,
+                        drv_data->reg_base + MV64XXX_I2C_REG_DATA);
+                writel(drv_data->cntl_bits,
+                        drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
+                break;
+
+        case MV64XXX_I2C_ACTION_SEND_ADDR_2:
+                writel(drv_data->addr2,
+                        drv_data->reg_base + MV64XXX_I2C_REG_DATA);
+                writel(drv_data->cntl_bits,
+                        drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
+                break;
+
+        case MV64XXX_I2C_ACTION_SEND_DATA:
+                writel(drv_data->msg->buf[drv_data->byte_posn++],
+                        drv_data->reg_base + MV64XXX_I2C_REG_DATA);
+                writel(drv_data->cntl_bits,
+                        drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
+                break;
+
+        case MV64XXX_I2C_ACTION_RCV_DATA:
+                drv_data->msg->buf[drv_data->byte_posn++] =
+                        readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA);
+                writel(drv_data->cntl_bits,
+                        drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
+                break;
+
+        case MV64XXX_I2C_ACTION_RCV_DATA_STOP:
+                drv_data->msg->buf[drv_data->byte_posn++] =
+                        readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA);
+                drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
+                writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
+                        drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
+                drv_data->block = 0;
+                wake_up_interruptible(&drv_data->waitq);
+                break;
+
+        case MV64XXX_I2C_ACTION_INVALID:
+        default:
+                dev_err(&drv_data->adapter.dev,
+                        "mv64xxx_i2c_do_action: Invalid action: %d\n",
+                        drv_data->action);
+                drv_data->rc = -EIO;
+                /* FALLTHRU */
+        case MV64XXX_I2C_ACTION_SEND_STOP:
+                drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
+                writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
+                        drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
+                drv_data->block = 0;
+                wake_up_interruptible(&drv_data->waitq);
+                break;
+        }
+}
+
+static int
+mv64xxx_i2c_intr(int irq, void *dev_id, struct pt_regs *regs)
+{
+        struct mv64xxx_i2c_data *drv_data = dev_id;
+        unsigned long   flags;
+        u32             status;
+        int             rc = IRQ_NONE;
+
+        spin_lock_irqsave(&drv_data->lock, flags);
+        while (readl(drv_data->reg_base + MV64XXX_I2C_REG_CONTROL) &
+                                                MV64XXX_I2C_REG_CONTROL_IFLG) {
+                status = readl(drv_data->reg_base + MV64XXX_I2C_REG_STATUS);
+                mv64xxx_i2c_fsm(drv_data, status);
+                mv64xxx_i2c_do_action(drv_data);
+                rc = IRQ_HANDLED;
+        }
+        spin_unlock_irqrestore(&drv_data->lock, flags);
+
+        return rc;
+}
+
+/*
+ *****************************************************************************
+ *
+ *      I2C Msg Execution Routines
+ *
+ *****************************************************************************
+ */
+static void
+mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
+        struct i2c_msg *msg)
+{
+        u32     dir = 0;
+
+        drv_data->msg = msg;
+        drv_data->byte_posn = 0;
+        drv_data->bytes_left = msg->len;
+        drv_data->rc = 0;
+        drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK |
+                MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN;
+
+        if (msg->flags & I2C_M_RD)
+                dir = 1;
+
+        if (msg->flags & I2C_M_REV_DIR_ADDR)
+                dir ^= 1;
+
+        if (msg->flags & I2C_M_TEN) {
+                drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
+                drv_data->addr2 = (u32)msg->addr & 0xff;
+        } else {
+                drv_data->addr1 = ((u32)msg->addr & 0x7f) << 1 | dir;
+                drv_data->addr2 = 0;
+        }
+}
+
+static void
+mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
+{
+        long            time_left;
+        unsigned long   flags;
+        char            abort = 0;
+
+        time_left = wait_event_interruptible_timeout(drv_data->waitq,
+                !drv_data->block, msecs_to_jiffies(drv_data->adapter.timeout));
+
+        spin_lock_irqsave(&drv_data->lock, flags);
+        if (!time_left) { /* Timed out */
+                drv_data->rc = -ETIMEDOUT;
+                abort = 1;
+        } else if (time_left < 0) { /* Interrupted/Error */
+                drv_data->rc = time_left; /* errno value */
+                abort = 1;
+        }
+
+        if (abort && drv_data->block) {
+                drv_data->state = MV64XXX_I2C_STATE_ABORTING;
+                spin_unlock_irqrestore(&drv_data->lock, flags);
+
+                time_left = wait_event_timeout(drv_data->waitq,
+                        !drv_data->block,
+                        msecs_to_jiffies(drv_data->adapter.timeout));
+
+                if (time_left <= 0) {
+                        drv_data->state = MV64XXX_I2C_STATE_IDLE;
+                        dev_err(&drv_data->adapter.dev,
+                                "mv64xxx: I2C bus locked\n");
+                }
+        } else
+                spin_unlock_irqrestore(&drv_data->lock, flags);
+}
+
+static int
+mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg)
+{
+        unsigned long   flags;
+
+        spin_lock_irqsave(&drv_data->lock, flags);
+        mv64xxx_i2c_prepare_for_io(drv_data, msg);
+
+        if (unlikely(msg->flags & I2C_M_NOSTART)) { /* Skip start/addr phases */
+                if (drv_data->msg->flags & I2C_M_RD) {
+                        /* No action to do, wait for slave to send a byte */
+                        drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
+                        drv_data->state =
+                                MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
+                } else {
+                        drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
+                        drv_data->state =
+                                MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
+                        drv_data->bytes_left--;
+                }
+        } else {
+                drv_data->action = MV64XXX_I2C_ACTION_SEND_START;
+                drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
+        }
+
+        drv_data->block = 1;
+        mv64xxx_i2c_do_action(drv_data);
+        spin_unlock_irqrestore(&drv_data->lock, flags);
+
+        mv64xxx_i2c_wait_for_completion(drv_data);
+        return drv_data->rc;
+}
+
+/*
+ *****************************************************************************
+ *
+ *      I2C Core Support Routines (Interface to higher level I2C code)
+ *
+ *****************************************************************************
+ */
+static u32
+mv64xxx_i2c_functionality(struct i2c_adapter *adap)
+{
+        return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
+}
+
+static int
+mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
+{
+        struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
+        int     i, rc = 0;
+
+        for (i=0; i<num; i++)
+                if ((rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[i])) != 0)
+                        break;
+
+        return rc;
+}
+
+static struct i2c_algorithm mv64xxx_i2c_algo = {
+        .name = MV64XXX_I2C_CTLR_NAME " algorithm",
+        .id = I2C_ALGO_MV64XXX,
+        .master_xfer = mv64xxx_i2c_xfer,
+        .functionality = mv64xxx_i2c_functionality,
+};
+
+/*
+ *****************************************************************************
+ *
+ *      Driver Interface & Early Init Routines
+ *
+ *****************************************************************************
+ */
+static void __devinit
+mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
+{
+        writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SOFT_RESET);
+        writel((((drv_data->freq_m & 0xf) << 3) | (drv_data->freq_n & 0x7)),
+                drv_data->reg_base + MV64XXX_I2C_REG_BAUD);
+        writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SLAVE_ADDR);
+        writel(0, drv_data->reg_base + MV64XXX_I2C_REG_EXT_SLAVE_ADDR);
+        writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP,
+                drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
+        drv_data->state = MV64XXX_I2C_STATE_IDLE;
+}
+
+static int __devinit
+mv64xxx_i2c_map_regs(struct platform_device *pd,
+        struct mv64xxx_i2c_data *drv_data)
+{
+        struct resource *r;
+
+        if ((r = platform_get_resource(pd, IORESOURCE_MEM, 0)) &&
+                request_mem_region(r->start, MV64XXX_I2C_REG_BLOCK_SIZE,
+                        drv_data->adapter.name)) {
+
+                drv_data->reg_base = ioremap(r->start,
+                        MV64XXX_I2C_REG_BLOCK_SIZE);
+                drv_data->reg_base_p = r->start;
+        } else
+                return -ENOMEM;
+
+        return 0;
+}
+
+static void __devexit
+mv64xxx_i2c_unmap_regs(struct mv64xxx_i2c_data *drv_data)
+{
+        if (drv_data->reg_base) {
+                iounmap(drv_data->reg_base);
+                release_mem_region(drv_data->reg_base_p,
+                        MV64XXX_I2C_REG_BLOCK_SIZE);
+        }
+
+        drv_data->reg_base = NULL;
+        drv_data->reg_base_p = 0;
+}
+
+static int __devinit
+mv64xxx_i2c_probe(struct device *dev)
+{
+        struct platform_device          *pd = to_platform_device(dev);
+        struct mv64xxx_i2c_data         *drv_data;
+        struct mv64xxx_i2c_pdata        *pdata = dev->platform_data;
+        int     rc;
+
+        if ((pd->id != 0) || !pdata)
+                return -ENODEV;
+
+        drv_data = kmalloc(sizeof(struct mv64xxx_i2c_data), GFP_KERNEL);
+
+        if (!drv_data)
+                return -ENOMEM;
+
+        memset(drv_data, 0, sizeof(struct mv64xxx_i2c_data));
+
+        if (mv64xxx_i2c_map_regs(pd, drv_data)) {
+                rc = -ENODEV;
+                goto exit_kfree;
+        }
+
+        strncpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
+                I2C_NAME_SIZE);
+
+        init_waitqueue_head(&drv_data->waitq);
+        spin_lock_init(&drv_data->lock);
+
+        drv_data->freq_m = pdata->freq_m;
+        drv_data->freq_n = pdata->freq_n;
+        drv_data->irq = platform_get_irq(pd, 0);
+        drv_data->adapter.id = I2C_ALGO_MV64XXX | I2C_HW_MV64XXX;
+        drv_data->adapter.algo = &mv64xxx_i2c_algo;
+        drv_data->adapter.owner = THIS_MODULE;
+        drv_data->adapter.class = I2C_CLASS_HWMON;
+        drv_data->adapter.timeout = pdata->timeout;
+        drv_data->adapter.retries = pdata->retries;
+        dev_set_drvdata(dev, drv_data);
+        i2c_set_adapdata(&drv_data->adapter, drv_data);
+
+        if (request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
+                MV64XXX_I2C_CTLR_NAME, drv_data)) {
+
+                dev_err(dev, "mv64xxx: Can't register intr handler "
+                        "irq: %d\n", drv_data->irq);
+                rc = -EINVAL;
+                goto exit_unmap_regs;
+        } else if ((rc = i2c_add_adapter(&drv_data->adapter)) != 0) {
+                dev_err(dev, "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc);
+                goto exit_free_irq;
+        }
+
+        mv64xxx_i2c_hw_init(drv_data);
+
+        return 0;
+
+        exit_free_irq:
+                free_irq(drv_data->irq, drv_data);
+        exit_unmap_regs:
+                mv64xxx_i2c_unmap_regs(drv_data);
+        exit_kfree:
+                kfree(drv_data);
+        return rc;
+}
+
+static int __devexit
+mv64xxx_i2c_remove(struct device *dev)
+{
+        struct mv64xxx_i2c_data         *drv_data = dev_get_drvdata(dev);
+        int     rc;
+
+        rc = i2c_del_adapter(&drv_data->adapter);
+        free_irq(drv_data->irq, drv_data);
+        mv64xxx_i2c_unmap_regs(drv_data);
+        kfree(drv_data);
+
+        return rc;
+}
+
+static struct device_driver mv64xxx_i2c_driver = {
+        .name   = MV64XXX_I2C_CTLR_NAME,
+        .bus    = &platform_bus_type,
+        .probe  = mv64xxx_i2c_probe,
+        .remove = mv64xxx_i2c_remove,
+};
+
+static int __init
+mv64xxx_i2c_init(void)
+{
+        return driver_register(&mv64xxx_i2c_driver);
+}
+
+static void __exit
+mv64xxx_i2c_exit(void)
+{
+        driver_unregister(&mv64xxx_i2c_driver);
+}
+
+module_init(mv64xxx_i2c_init);
+module_exit(mv64xxx_i2c_exit);
+
+MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
+MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/i2c/busses/i2c-nforce2.c b/drivers/i2c/busses/i2c-nforce2.c
new file mode 100644
index 000000000000..6d13127c8c4e
--- /dev/null
+++ b/drivers/i2c/busses/i2c-nforce2.c
@@ -0,0 +1,410 @@
+/*
+    SMBus driver for nVidia nForce2 MCP
+
+    Added nForce3 Pro 150  Thomas Leibold <thomas@plx.com>,
+        Ported to 2.5 Patrick Dreker <patrick@dreker.de>,
+    Copyright (c) 2003  Hans-Frieder Vogt <hfvogt@arcor.de>,
+    Based on
+    SMBus 2.0 driver for AMD-8111 IO-Hub
+    Copyright (c) 2002 Vojtech Pavlik
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+/*
+    SUPPORTED DEVICES           PCI ID
+    nForce2 MCP                 0064
+    nForce2 Ultra 400 MCP       0084
+    nForce3 Pro150 MCP          00D4
+    nForce3 250Gb MCP           00E4
+    nForce4 MCP                 0052
+
+    This driver supports the 2 SMBuses that are included in the MCP of the
+    nForce2/3/4 chipsets.
+*/
+
+/* Note: we assume there can only be one nForce2, with two SMBus interfaces */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/stddef.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR ("Hans-Frieder Vogt <hfvogt@arcor.de>");
+MODULE_DESCRIPTION("nForce2 SMBus driver");
+
+
+struct nforce2_smbus {
+        struct pci_dev *dev;
+        struct i2c_adapter adapter;
+        int base;
+        int size;
+};
+
+
+/*
+ * nVidia nForce2 SMBus control register definitions
+ */
+#define NFORCE_PCI_SMB1 0x50
+#define NFORCE_PCI_SMB2 0x54
+
+
+/*
+ * ACPI 2.0 chapter 13 SMBus 2.0 EC register model
+ */
+#define NVIDIA_SMB_PRTCL        (smbus->base + 0x00)    /* protocol, PEC */
+#define NVIDIA_SMB_STS          (smbus->base + 0x01)    /* status */
+#define NVIDIA_SMB_ADDR         (smbus->base + 0x02)    /* address */
+#define NVIDIA_SMB_CMD          (smbus->base + 0x03)    /* command */
+#define NVIDIA_SMB_DATA         (smbus->base + 0x04)    /* 32 data registers */
+#define NVIDIA_SMB_BCNT         (smbus->base + 0x24)    /* number of data bytes */
+#define NVIDIA_SMB_ALRM_A       (smbus->base + 0x25)    /* alarm address */
+#define NVIDIA_SMB_ALRM_D       (smbus->base + 0x26)    /* 2 bytes alarm data */
+
+#define NVIDIA_SMB_STS_DONE     0x80
+#define NVIDIA_SMB_STS_ALRM     0x40
+#define NVIDIA_SMB_STS_RES      0x20
+#define NVIDIA_SMB_STS_STATUS   0x1f
+
+#define NVIDIA_SMB_PRTCL_WRITE                  0x00
+#define NVIDIA_SMB_PRTCL_READ                   0x01
+#define NVIDIA_SMB_PRTCL_QUICK                  0x02
+#define NVIDIA_SMB_PRTCL_BYTE                   0x04
+#define NVIDIA_SMB_PRTCL_BYTE_DATA              0x06
+#define NVIDIA_SMB_PRTCL_WORD_DATA              0x08
+#define NVIDIA_SMB_PRTCL_BLOCK_DATA             0x0a
+#define NVIDIA_SMB_PRTCL_PROC_CALL              0x0c
+#define NVIDIA_SMB_PRTCL_BLOCK_PROC_CALL        0x0d
+#define NVIDIA_SMB_PRTCL_I2C_BLOCK_DATA         0x4a
+#define NVIDIA_SMB_PRTCL_PEC                    0x80
+
+
+/* Other settings */
+#define MAX_TIMEOUT 256
+
+
+
+static s32 nforce2_access(struct i2c_adapter *adap, u16 addr,
+                       unsigned short flags, char read_write,
+                       u8 command, int size, union i2c_smbus_data *data);
+static u32 nforce2_func(struct i2c_adapter *adapter);
+
+
+static struct i2c_algorithm smbus_algorithm = {
+        .name = "Non-I2C SMBus adapter",
+        .id = I2C_ALGO_SMBUS,
+        .smbus_xfer = nforce2_access,
+        .functionality = nforce2_func,
+};
+
+static struct i2c_adapter nforce2_adapter = {
+        .owner          = THIS_MODULE,
+        .class          = I2C_CLASS_HWMON,
+        .algo           = &smbus_algorithm,
+        .name           = "unset",
+};
+
+/* Return -1 on error. See smbus.h for more information */
+static s32 nforce2_access(struct i2c_adapter * adap, u16 addr,
+                unsigned short flags, char read_write,
+                u8 command, int size, union i2c_smbus_data * data)
+{
+        struct nforce2_smbus *smbus = adap->algo_data;
+        unsigned char protocol, pec, temp;
+        unsigned char len = 0; /* to keep the compiler quiet */
+        int timeout = 0;
+        int i;
+
+        protocol = (read_write == I2C_SMBUS_READ) ? NVIDIA_SMB_PRTCL_READ :
+                NVIDIA_SMB_PRTCL_WRITE;
+        pec = (flags & I2C_CLIENT_PEC) ? NVIDIA_SMB_PRTCL_PEC : 0;
+
+        switch (size) {
+
+                case I2C_SMBUS_QUICK:
+                        protocol |= NVIDIA_SMB_PRTCL_QUICK;
+                        read_write = I2C_SMBUS_WRITE;
+                        break;
+
+                case I2C_SMBUS_BYTE:
+                        if (read_write == I2C_SMBUS_WRITE)
+                                outb_p(command, NVIDIA_SMB_CMD);
+                        protocol |= NVIDIA_SMB_PRTCL_BYTE;
+                        break;
+
+                case I2C_SMBUS_BYTE_DATA:
+                        outb_p(command, NVIDIA_SMB_CMD);
+                        if (read_write == I2C_SMBUS_WRITE)
+                                outb_p(data->byte, NVIDIA_SMB_DATA);
+                        protocol |= NVIDIA_SMB_PRTCL_BYTE_DATA;
+                        break;
+
+                case I2C_SMBUS_WORD_DATA:
+                        outb_p(command, NVIDIA_SMB_CMD);
+                        if (read_write == I2C_SMBUS_WRITE) {
+                                 outb_p(data->word, NVIDIA_SMB_DATA);
+                                 outb_p(data->word >> 8, NVIDIA_SMB_DATA+1);
+                        }
+                        protocol |= NVIDIA_SMB_PRTCL_WORD_DATA | pec;
+                        break;
+
+                case I2C_SMBUS_BLOCK_DATA:
+                        outb_p(command, NVIDIA_SMB_CMD);
+                        if (read_write == I2C_SMBUS_WRITE) {
+                                len = min_t(u8, data->block[0], 32);
+                                outb_p(len, NVIDIA_SMB_BCNT);
+                                for (i = 0; i < len; i++)
+                                        outb_p(data->block[i + 1], NVIDIA_SMB_DATA+i);
+                        }
+                        protocol |= NVIDIA_SMB_PRTCL_BLOCK_DATA | pec;
+                        break;
+
+                case I2C_SMBUS_I2C_BLOCK_DATA:
+                        len = min_t(u8, data->block[0], 32);
+                        outb_p(command, NVIDIA_SMB_CMD);
+                        outb_p(len, NVIDIA_SMB_BCNT);
+                        if (read_write == I2C_SMBUS_WRITE)
+                                for (i = 0; i < len; i++)
+                                        outb_p(data->block[i + 1], NVIDIA_SMB_DATA+i);
+                        protocol |= NVIDIA_SMB_PRTCL_I2C_BLOCK_DATA;
+                        break;
+
+                case I2C_SMBUS_PROC_CALL:
+                        dev_err(&adap->dev, "I2C_SMBUS_PROC_CALL not supported!\n");
+                        return -1;
+                        /*
+                        outb_p(command, NVIDIA_SMB_CMD);
+                        outb_p(data->word, NVIDIA_SMB_DATA);
+                        outb_p(data->word >> 8, NVIDIA_SMB_DATA + 1);
+                        protocol = NVIDIA_SMB_PRTCL_PROC_CALL | pec;
+                        read_write = I2C_SMBUS_READ;
+                        break;
+                         */
+
+                case I2C_SMBUS_BLOCK_PROC_CALL:
+                        dev_err(&adap->dev, "I2C_SMBUS_BLOCK_PROC_CALL not supported!\n");
+                        return -1;
+                        /*
+                        protocol |= pec;
+                        len = min_t(u8, data->block[0], 31);
+                        outb_p(command, NVIDIA_SMB_CMD);
+                        outb_p(len, NVIDIA_SMB_BCNT);
+                        for (i = 0; i < len; i++)
+                                outb_p(data->block[i + 1], NVIDIA_SMB_DATA + i);
+                        protocol = NVIDIA_SMB_PRTCL_BLOCK_PROC_CALL | pec;
+                        read_write = I2C_SMBUS_READ;
+                        break;
+                        */
+
+                case I2C_SMBUS_WORD_DATA_PEC:
+                case I2C_SMBUS_BLOCK_DATA_PEC:
+                case I2C_SMBUS_PROC_CALL_PEC:
+                case I2C_SMBUS_BLOCK_PROC_CALL_PEC:
+                        dev_err(&adap->dev, "Unexpected software PEC transaction %d\n.", size);
+                        return -1;
+
+                default:
+                        dev_err(&adap->dev, "Unsupported transaction %d\n", size);
+                        return -1;
+        }
+
+        outb_p((addr & 0x7f) << 1, NVIDIA_SMB_ADDR);
+        outb_p(protocol, NVIDIA_SMB_PRTCL);
+
+        temp = inb_p(NVIDIA_SMB_STS);
+
+#if 0
+        do {
+                i2c_do_pause(1);
+                temp = inb_p(NVIDIA_SMB_STS);
+        } while (((temp & NVIDIA_SMB_STS_DONE) == 0) && (timeout++ < MAX_TIMEOUT));
+#endif
+        if (~temp & NVIDIA_SMB_STS_DONE) {
+                udelay(500);
+                temp = inb_p(NVIDIA_SMB_STS);
+        }
+        if (~temp & NVIDIA_SMB_STS_DONE) {
+                msleep(10);
+                temp = inb_p(NVIDIA_SMB_STS);
+        }
+
+        if ((timeout >= MAX_TIMEOUT) || (~temp & NVIDIA_SMB_STS_DONE)
+                || (temp & NVIDIA_SMB_STS_STATUS))
+                return -1;
+
+        if (read_write == I2C_SMBUS_WRITE)
+                return 0;
+
+        switch (size) {
+
+                case I2C_SMBUS_BYTE:
+                case I2C_SMBUS_BYTE_DATA:
+                        data->byte = inb_p(NVIDIA_SMB_DATA);
+                        break;
+
+                case I2C_SMBUS_WORD_DATA:
+                /* case I2C_SMBUS_PROC_CALL: not supported */
+                        data->word = inb_p(NVIDIA_SMB_DATA) | (inb_p(NVIDIA_SMB_DATA+1) << 8);
+                        break;
+
+                case I2C_SMBUS_BLOCK_DATA:
+                /* case I2C_SMBUS_BLOCK_PROC_CALL: not supported */
+                        len = inb_p(NVIDIA_SMB_BCNT);
+                        len = min_t(u8, len, 32);
+                case I2C_SMBUS_I2C_BLOCK_DATA:
+                        for (i = 0; i < len; i++)
+                                data->block[i+1] = inb_p(NVIDIA_SMB_DATA + i);
+                        data->block[0] = len;
+                        break;
+        }
+
+        return 0;
+}
+
+
+static u32 nforce2_func(struct i2c_adapter *adapter)
+{
+        /* other functionality might be possible, but is not tested */
+        return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
+            I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA /* |
+            I2C_FUNC_SMBUS_BLOCK_DATA */;
+}
+
+
+static struct pci_device_id nforce2_ids[] = {
+        { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_SMBUS) },
+        { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SMBUS) },
+        { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_SMBUS) },
+        { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SMBUS) },
+        { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE4_SMBUS) },
+        { 0 }
+};
+
+
+MODULE_DEVICE_TABLE (pci, nforce2_ids);
+
+
+static int __devinit nforce2_probe_smb (struct pci_dev *dev, int reg,
+        struct nforce2_smbus *smbus, char *name)
+{
+        u16 iobase;
+        int error;
+
+        if (pci_read_config_word(dev, reg, &iobase) != PCIBIOS_SUCCESSFUL) {
+                dev_err(&smbus->adapter.dev, "Error reading PCI config for %s\n", name);
+                return -1;
+        }
+        smbus->dev  = dev;
+        smbus->base = iobase & 0xfffc;
+        smbus->size = 8;
+
+        if (!request_region(smbus->base, smbus->size, "nForce2 SMBus")) {
+                dev_err(&smbus->adapter.dev, "Error requesting region %02x .. %02X for %s\n",
+                        smbus->base, smbus->base+smbus->size-1, name);
+                return -1;
+        }
+        smbus->adapter = nforce2_adapter;
+        smbus->adapter.algo_data = smbus;
+        smbus->adapter.dev.parent = &dev->dev;
+        snprintf(smbus->adapter.name, I2C_NAME_SIZE,
+                "SMBus nForce2 adapter at %04x", smbus->base);
+
+        error = i2c_add_adapter(&smbus->adapter);
+        if (error) {
+                dev_err(&smbus->adapter.dev, "Failed to register adapter.\n");
+                release_region(smbus->base, smbus->size);
+                return -1;
+        }
+        dev_info(&smbus->adapter.dev, "nForce2 SMBus adapter at %#x\n", smbus->base);
+        return 0;
+}
+
+
+static int __devinit nforce2_probe(struct pci_dev *dev, const struct pci_device_id *id)
+{
+        struct nforce2_smbus *smbuses;
+        int res1, res2;
+
+        /* we support 2 SMBus adapters */
+        if (!(smbuses = (void *)kmalloc(2*sizeof(struct nforce2_smbus),
+                                        GFP_KERNEL)))
+                return -ENOMEM;
+        memset (smbuses, 0, 2*sizeof(struct nforce2_smbus));
+        pci_set_drvdata(dev, smbuses);
+
+        /* SMBus adapter 1 */
+        res1 = nforce2_probe_smb (dev, NFORCE_PCI_SMB1, &smbuses[0], "SMB1");
+        if (res1 < 0) {
+                dev_err(&dev->dev, "Error probing SMB1.\n");
+                smbuses[0].base = 0;    /* to have a check value */
+        }
+        res2 = nforce2_probe_smb (dev, NFORCE_PCI_SMB2, &smbuses[1], "SMB2");
+        if (res2 < 0) {
+                dev_err(&dev->dev, "Error probing SMB2.\n");
+                smbuses[1].base = 0;    /* to have a check value */
+        }
+        if ((res1 < 0) && (res2 < 0)) {
+                /* we did not find even one of the SMBuses, so we give up */
+                kfree(smbuses);
+                return -ENODEV;
+        }
+
+        return 0;
+}
+
+
+static void __devexit nforce2_remove(struct pci_dev *dev)
+{
+        struct nforce2_smbus *smbuses = (void*) pci_get_drvdata(dev);
+
+        if (smbuses[0].base) {
+                i2c_del_adapter(&smbuses[0].adapter);
+                release_region(smbuses[0].base, smbuses[0].size);
+        }
+        if (smbuses[1].base) {
+                i2c_del_adapter(&smbuses[1].adapter);
+                release_region(smbuses[1].base, smbuses[1].size);
+        }
+        kfree(smbuses);
+}
+
+static struct pci_driver nforce2_driver = {
+        .name           = "nForce2_smbus",
+        .id_table       = nforce2_ids,
+        .probe          = nforce2_probe,
+        .remove         = __devexit_p(nforce2_remove),
+};
+
+static int __init nforce2_init(void)
+{
+        return pci_register_driver(&nforce2_driver);
+}
+
+static void __exit nforce2_exit(void)
+{
+        pci_unregister_driver(&nforce2_driver);
+}
+
+module_init(nforce2_init);
+module_exit(nforce2_exit);
+
diff --git a/drivers/i2c/busses/i2c-parport-light.c b/drivers/i2c/busses/i2c-parport-light.c
new file mode 100644
index 000000000000..cb5e722301d8
--- /dev/null
+++ b/drivers/i2c/busses/i2c-parport-light.c
@@ -0,0 +1,175 @@
+/* ------------------------------------------------------------------------ *
+ * i2c-parport.c I2C bus over parallel port                                 *
+ * ------------------------------------------------------------------------ *
+   Copyright (C) 2003-2004 Jean Delvare <khali@linux-fr.org>
+   
+   Based on older i2c-velleman.c driver
+   Copyright (C) 1995-2000 Simon G. Vogl
+   With some changes from:
+   Frodo Looijaard <frodol@dds.nl>
+   Kyösti Mälkki <kmalkki@cc.hut.fi>
+   
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * ------------------------------------------------------------------------ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/i2c.h>
+#include <linux/i2c-algo-bit.h>
+#include <asm/io.h>
+#include "i2c-parport.h"
+
+#define DEFAULT_BASE 0x378
+
+static u16 base;
+module_param(base, ushort, 0);
+MODULE_PARM_DESC(base, "Base I/O address");
+
+/* ----- Low-level parallel port access ----------------------------------- */
+
+static inline void port_write(unsigned char p, unsigned char d)
+{
+        outb(d, base+p);
+}
+
+static inline unsigned char port_read(unsigned char p)
+{
+        return inb(base+p);
+}
+
+/* ----- Unified line operation functions --------------------------------- */
+
+static inline void line_set(int state, const struct lineop *op)
+{
+        u8 oldval = port_read(op->port);
+
+        /* Touch only the bit(s) needed */
+        if ((op->inverted && !state) || (!op->inverted && state))
+                port_write(op->port, oldval | op->val);
+        else
+                port_write(op->port, oldval & ~op->val);
+}
+
+static inline int line_get(const struct lineop *op)
+{
+        u8 oldval = port_read(op->port);
+
+        return ((op->inverted && (oldval & op->val) != op->val)
+            || (!op->inverted && (oldval & op->val) == op->val));
+}
+
+/* ----- I2C algorithm call-back functions and structures ----------------- */
+
+static void parport_setscl(void *data, int state)
+{
+        line_set(state, &adapter_parm[type].setscl);
+}
+
+static void parport_setsda(void *data, int state)
+{
+        line_set(state, &adapter_parm[type].setsda);
+}
+
+static int parport_getscl(void *data)
+{
+        return line_get(&adapter_parm[type].getscl);
+}
+
+static int parport_getsda(void *data)
+{
+        return line_get(&adapter_parm[type].getsda);
+}
+
+/* Encapsulate the functions above in the correct structure
+   Note that getscl will be set to NULL by the attaching code for adapters
+   that cannot read SCL back */
+static struct i2c_algo_bit_data parport_algo_data = {
+        .setsda         = parport_setsda,
+        .setscl         = parport_setscl,
+        .getsda         = parport_getsda,
+        .getscl         = parport_getscl,
+        .udelay         = 50,
+        .mdelay         = 50,
+        .timeout        = HZ,
+}; 
+
+/* ----- I2c structure ---------------------------------------------------- */
+
+static struct i2c_adapter parport_adapter = {
+        .owner          = THIS_MODULE,
+        .class          = I2C_CLASS_HWMON,
+        .id             = I2C_HW_B_LP,
+        .algo_data      = &parport_algo_data,
+        .name           = "Parallel port adapter (light)",
+};
+
+/* ----- Module loading, unloading and information ------------------------ */
+
+static int __init i2c_parport_init(void)
+{
+        int type_count;
+
+        type_count = sizeof(adapter_parm)/sizeof(struct adapter_parm);
+        if (type < 0 || type >= type_count) {
+                printk(KERN_WARNING "i2c-parport: invalid type (%d)\n", type);
+                type = 0;
+        }
+        
+        if (base == 0) {
+                printk(KERN_INFO "i2c-parport: using default base 0x%x\n", DEFAULT_BASE);
+                base = DEFAULT_BASE;
+        }
+
+        if (!request_region(base, 3, "i2c-parport"))
+                return -ENODEV;
+
+        if (!adapter_parm[type].getscl.val)
+                parport_algo_data.getscl = NULL;
+
+        /* Reset hardware to a sane state (SCL and SDA high) */
+        parport_setsda(NULL, 1);
+        parport_setscl(NULL, 1);
+        /* Other init if needed (power on...) */
+        if (adapter_parm[type].init.val)
+                line_set(1, &adapter_parm[type].init);
+
+        if (i2c_bit_add_bus(&parport_adapter) < 0) {
+                printk(KERN_ERR "i2c-parport: Unable to register with I2C\n");
+                release_region(base, 3);
+                return -ENODEV;
+        }
+        
+        return 0;
+}
+
+static void __exit i2c_parport_exit(void)
+{
+        /* Un-init if needed (power off...) */
+        if (adapter_parm[type].init.val)
+                line_set(0, &adapter_parm[type].init);
+
+        i2c_bit_del_bus(&parport_adapter);
+        release_region(base, 3);
+}
+
+MODULE_AUTHOR("Jean Delvare <khali@linux-fr.org>");
+MODULE_DESCRIPTION("I2C bus over parallel port (light)");
+MODULE_LICENSE("GPL");
+
+module_init(i2c_parport_init);
+module_exit(i2c_parport_exit);
diff --git a/drivers/i2c/busses/i2c-parport.c b/drivers/i2c/busses/i2c-parport.c
new file mode 100644
index 000000000000..e9560bab51c4
--- /dev/null
+++ b/drivers/i2c/busses/i2c-parport.c
@@ -0,0 +1,267 @@
+/* ------------------------------------------------------------------------ *
+ * i2c-parport.c I2C bus over parallel port                                 *
+ * ------------------------------------------------------------------------ *
+   Copyright (C) 2003-2004 Jean Delvare <khali@linux-fr.org>
+   
+   Based on older i2c-philips-par.c driver
+   Copyright (C) 1995-2000 Simon G. Vogl
+   With some changes from:
+   Frodo Looijaard <frodol@dds.nl>
+   Kyösti Mälkki <kmalkki@cc.hut.fi>
+   
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * ------------------------------------------------------------------------ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/parport.h>
+#include <linux/i2c.h>
+#include <linux/i2c-algo-bit.h>
+#include "i2c-parport.h"
+
+/* ----- Device list ------------------------------------------------------ */
+
+struct i2c_par {
+        struct pardevice *pdev;
+        struct i2c_adapter adapter;
+        struct i2c_algo_bit_data algo_data;
+        struct i2c_par *next;
+};
+
+static struct i2c_par *adapter_list;
+
+/* ----- Low-level parallel port access ----------------------------------- */
+
+static void port_write_data(struct parport *p, unsigned char d)
+{
+        parport_write_data(p, d);
+}
+
+static void port_write_control(struct parport *p, unsigned char d)
+{
+        parport_write_control(p, d);
+}
+
+static unsigned char port_read_data(struct parport *p)
+{
+        return parport_read_data(p);
+}
+
+static unsigned char port_read_status(struct parport *p)
+{
+        return parport_read_status(p);
+}
+
+static unsigned char port_read_control(struct parport *p)
+{
+        return parport_read_control(p);
+}
+
+static void (*port_write[])(struct parport *, unsigned char) = {
+        port_write_data,
+        NULL,
+        port_write_control,
+};
+
+static unsigned char (*port_read[])(struct parport *) = {
+        port_read_data,
+        port_read_status,
+        port_read_control,
+};
+
+/* ----- Unified line operation functions --------------------------------- */
+
+static inline void line_set(struct parport *data, int state,
+        const struct lineop *op)
+{
+        u8 oldval = port_read[op->port](data);
+
+        /* Touch only the bit(s) needed */
+        if ((op->inverted && !state) || (!op->inverted && state))
+                port_write[op->port](data, oldval | op->val);
+        else
+                port_write[op->port](data, oldval & ~op->val);
+}
+
+static inline int line_get(struct parport *data,
+        const struct lineop *op)
+{
+        u8 oldval = port_read[op->port](data);
+
+        return ((op->inverted && (oldval & op->val) != op->val)
+            || (!op->inverted && (oldval & op->val) == op->val));
+}
+
+/* ----- I2C algorithm call-back functions and structures ----------------- */
+
+static void parport_setscl(void *data, int state)
+{
+        line_set((struct parport *) data, state, &adapter_parm[type].setscl);
+}
+
+static void parport_setsda(void *data, int state)
+{
+        line_set((struct parport *) data, state, &adapter_parm[type].setsda);
+}
+
+static int parport_getscl(void *data)
+{
+        return line_get((struct parport *) data, &adapter_parm[type].getscl);
+}
+
+static int parport_getsda(void *data)
+{
+        return line_get((struct parport *) data, &adapter_parm[type].getsda);
+}
+
+/* Encapsulate the functions above in the correct structure.
+   Note that this is only a template, from which the real structures are
+   copied. The attaching code will set getscl to NULL for adapters that
+   cannot read SCL back, and will also make the the data field point to
+   the parallel port structure. */
+static struct i2c_algo_bit_data parport_algo_data = {
+        .setsda         = parport_setsda,
+        .setscl         = parport_setscl,
+        .getsda         = parport_getsda,
+        .getscl         = parport_getscl,
+        .udelay         = 60,
+        .mdelay         = 60,
+        .timeout        = HZ,
+}; 
+
+/* ----- I2c and parallel port call-back functions and structures --------- */
+
+static struct i2c_adapter parport_adapter = {
+        .owner          = THIS_MODULE,
+        .class          = I2C_CLASS_HWMON,
+        .id             = I2C_HW_B_LP,
+        .name           = "Parallel port adapter",
+};
+
+static void i2c_parport_attach (struct parport *port)
+{
+        struct i2c_par *adapter;
+        
+        adapter = kmalloc(sizeof(struct i2c_par), GFP_KERNEL);
+        if (adapter == NULL) {
+                printk(KERN_ERR "i2c-parport: Failed to kmalloc\n");
+                return;
+        }
+        memset(adapter, 0x00, sizeof(struct i2c_par));
+
+        pr_debug("i2c-parport: attaching to %s\n", port->name);
+        adapter->pdev = parport_register_device(port, "i2c-parport",
+                NULL, NULL, NULL, PARPORT_FLAG_EXCL, NULL);
+        if (!adapter->pdev) {
+                printk(KERN_ERR "i2c-parport: Unable to register with parport\n");
+                goto ERROR0;
+        }
+
+        /* Fill the rest of the structure */
+        adapter->adapter = parport_adapter;
+        adapter->algo_data = parport_algo_data;
+        if (!adapter_parm[type].getscl.val)
+                adapter->algo_data.getscl = NULL;
+        adapter->algo_data.data = port;
+        adapter->adapter.algo_data = &adapter->algo_data;
+
+        if (parport_claim_or_block(adapter->pdev) < 0) {
+                printk(KERN_ERR "i2c-parport: Could not claim parallel port\n");
+                goto ERROR1;
+        }
+
+        /* Reset hardware to a sane state (SCL and SDA high) */
+        parport_setsda(port, 1);
+        parport_setscl(port, 1);
+        /* Other init if needed (power on...) */
+        if (adapter_parm[type].init.val)
+                line_set(port, 1, &adapter_parm[type].init);
+
+        parport_release(adapter->pdev);
+
+        if (i2c_bit_add_bus(&adapter->adapter) < 0) {
+                printk(KERN_ERR "i2c-parport: Unable to register with I2C\n");
+                goto ERROR1;
+        }
+
+        /* Add the new adapter to the list */
+        adapter->next = adapter_list;
+        adapter_list = adapter;
+        return;
+
+ERROR1:
+        parport_unregister_device(adapter->pdev);
+ERROR0:
+        kfree(adapter);
+}
+
+static void i2c_parport_detach (struct parport *port)
+{
+        struct i2c_par *adapter, *prev;
+
+        /* Walk the list */
+        for (prev = NULL, adapter = adapter_list; adapter;
+             prev = adapter, adapter = adapter->next) {
+                if (adapter->pdev->port == port) {
+                        /* Un-init if needed (power off...) */
+                        if (adapter_parm[type].init.val)
+                                line_set(port, 0, &adapter_parm[type].init);
+                                
+                        i2c_bit_del_bus(&adapter->adapter);
+                        parport_unregister_device(adapter->pdev);
+                        if (prev)
+                                prev->next = adapter->next;
+                        else
+                                adapter_list = adapter->next;
+                        kfree(adapter);
+                        return;
+                }
+        }
+}
+
+static struct parport_driver i2c_driver = {
+        .name   = "i2c-parport",
+        .attach = i2c_parport_attach,
+        .detach = i2c_parport_detach,
+};
+
+/* ----- Module loading, unloading and information ------------------------ */
+
+static int __init i2c_parport_init(void)
+{
+        int type_count;
+
+        type_count = sizeof(adapter_parm)/sizeof(struct adapter_parm);
+        if (type < 0 || type >= type_count) {
+                printk(KERN_WARNING "i2c-parport: invalid type (%d)\n", type);
+                type = 0;
+        }
+        
+        return parport_register_driver(&i2c_driver);
+}
+
+static void __exit i2c_parport_exit(void)
+{
+        parport_unregister_driver(&i2c_driver);
+}
+
+MODULE_AUTHOR("Jean Delvare <khali@linux-fr.org>");
+MODULE_DESCRIPTION("I2C bus over parallel port");
+MODULE_LICENSE("GPL");
+
+module_init(i2c_parport_init);
+module_exit(i2c_parport_exit);
diff --git a/drivers/i2c/busses/i2c-parport.h b/drivers/i2c/busses/i2c-parport.h
new file mode 100644
index 000000000000..f63a53779281
--- /dev/null
+++ b/drivers/i2c/busses/i2c-parport.h
@@ -0,0 +1,94 @@
+/* ------------------------------------------------------------------------ *
+ * i2c-parport.h I2C bus over parallel port                                 *
+ * ------------------------------------------------------------------------ *
+   Copyright (C) 2003-2004 Jean Delvare <khali@linux-fr.org>
+   
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * ------------------------------------------------------------------------ */
+
+#ifdef DATA
+#undef DATA
+#endif
+
+#define DATA    0
+#define STAT    1
+#define CTRL    2
+
+struct lineop {
+        u8 val;
+        u8 port;
+        u8 inverted;
+};
+
+struct adapter_parm {
+        struct lineop setsda;
+        struct lineop setscl;
+        struct lineop getsda;
+        struct lineop getscl;
+        struct lineop init;
+};
+
+static struct adapter_parm adapter_parm[] = {
+        /* type 0: Philips adapter */
+        {
+                .setsda = { 0x80, DATA, 1 },
+                .setscl = { 0x08, CTRL, 0 },
+                .getsda = { 0x80, STAT, 0 },
+                .getscl = { 0x08, STAT, 0 },
+        },
+        /* type 1: home brew teletext adapter */
+        {
+                .setsda = { 0x02, DATA, 0 },
+                .setscl = { 0x01, DATA, 0 },
+                .getsda = { 0x80, STAT, 1 },
+        },
+        /* type 2: Velleman K8000 adapter */
+        {
+                .setsda = { 0x02, CTRL, 1 },
+                .setscl = { 0x08, CTRL, 1 },
+                .getsda = { 0x10, STAT, 0 },
+        },
+        /* type 3: ELV adapter */
+        {
+                .setsda = { 0x02, DATA, 1 },
+                .setscl = { 0x01, DATA, 1 },
+                .getsda = { 0x40, STAT, 1 },
+                .getscl = { 0x08, STAT, 1 },
+        },
+        /* type 4: ADM1032 evaluation board */
+        {
+                .setsda = { 0x02, DATA, 1 },
+                .setscl = { 0x01, DATA, 1 },
+                .getsda = { 0x10, STAT, 1 },
+                .init   = { 0xf0, DATA, 0 },
+        },
+        /* type 5: ADM1025, ADM1030 and ADM1031 evaluation boards */
+        {
+                .setsda = { 0x02, DATA, 1 },
+                .setscl = { 0x01, DATA, 1 },
+                .getsda = { 0x10, STAT, 1 },
+        },
+};
+
+static int type;
+module_param(type, int, 0);
+MODULE_PARM_DESC(type,
+        "Type of adapter:\n"
+        " 0 = Philips adapter\n"
+        " 1 = home brew teletext adapter\n"
+        " 2 = Velleman K8000 adapter\n"
+        " 3 = ELV adapter\n"
+        " 4 = ADM1032 evaluation board\n"
+        " 5 = ADM1025, ADM1030 and ADM1031 evaluation boards\n");
diff --git a/drivers/i2c/busses/i2c-pca-isa.c b/drivers/i2c/busses/i2c-pca-isa.c
new file mode 100644
index 000000000000..9c611134db9c
--- /dev/null
+++ b/drivers/i2c/busses/i2c-pca-isa.c
@@ -0,0 +1,184 @@
+/*
+ *  i2c-pca-isa.c driver for PCA9564 on ISA boards
+ *    Copyright (C) 2004 Arcom Control Systems
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/ioport.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/wait.h>
+
+#include <linux/i2c.h>
+#include <linux/i2c-algo-pca.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+
+#include "../algos/i2c-algo-pca.h"
+
+#define IO_SIZE 4
+
+#undef DEBUG_IO
+//#define DEBUG_IO
+
+static unsigned long base   = 0x330;
+static int irq    = 10;
+
+/* Data sheet recommends 59kHz for 100kHz operation due to variation
+ * in the actual clock rate */
+static int clock  = I2C_PCA_CON_59kHz;
+
+static int own    = 0x55;
+
+static wait_queue_head_t pca_wait;
+
+static int pca_isa_getown(struct i2c_algo_pca_data *adap)
+{
+        return (own);
+}
+
+static int pca_isa_getclock(struct i2c_algo_pca_data *adap)
+{
+        return (clock);
+}
+
+static void
+pca_isa_writebyte(struct i2c_algo_pca_data *adap, int reg, int val)
+{
+#ifdef DEBUG_IO
+        static char *names[] = { "T/O", "DAT", "ADR", "CON" };
+        printk("*** write %s at %#lx <= %#04x\n", names[reg], base+reg, val);
+#endif
+        outb(val, base+reg);
+}
+
+static int
+pca_isa_readbyte(struct i2c_algo_pca_data *adap, int reg)
+{
+        int res = inb(base+reg);
+#ifdef DEBUG_IO
+        {
+                static char *names[] = { "STA", "DAT", "ADR", "CON" };  
+                printk("*** read  %s => %#04x\n", names[reg], res);
+        }
+#endif
+        return res;
+}
+
+static int pca_isa_waitforinterrupt(struct i2c_algo_pca_data *adap)
+{
+        int ret = 0;
+
+        if (irq > -1) {
+                ret = wait_event_interruptible(pca_wait,
+                                               pca_isa_readbyte(adap, I2C_PCA_CON) & I2C_PCA_CON_SI);
+        } else {
+                while ((pca_isa_readbyte(adap, I2C_PCA_CON) & I2C_PCA_CON_SI) == 0) 
+                        udelay(100);
+        }
+        return ret;
+}
+
+static irqreturn_t pca_handler(int this_irq, void *dev_id, struct pt_regs *regs) {
+        wake_up_interruptible(&pca_wait);
+        return IRQ_HANDLED;
+}
+
+static struct i2c_algo_pca_data pca_isa_data = {
+        .get_own                = pca_isa_getown,
+        .get_clock              = pca_isa_getclock,
+        .write_byte             = pca_isa_writebyte,
+        .read_byte              = pca_isa_readbyte,
+        .wait_for_interrupt     = pca_isa_waitforinterrupt,
+};
+
+static struct i2c_adapter pca_isa_ops = {
+        .owner          = THIS_MODULE,
+        .id             = I2C_HW_A_ISA,
+        .algo_data      = &pca_isa_data,
+        .name           = "PCA9564 ISA Adapter",
+};
+
+static int __init pca_isa_init(void)
+{
+
+        init_waitqueue_head(&pca_wait);
+
+        printk(KERN_INFO "i2c-pca-isa: i/o base %#08lx. irq %d\n", base, irq);
+
+        if (!request_region(base, IO_SIZE, "i2c-pca-isa")) {
+                printk(KERN_ERR "i2c-pca-isa: I/O address %#08lx is in use.\n", base);
+                goto out;
+        }
+
+        if (irq > -1) {
+                if (request_irq(irq, pca_handler, 0, "i2c-pca-isa", &pca_isa_ops) < 0) {
+                        printk(KERN_ERR "i2c-pca-isa: Request irq%d failed\n", irq);
+                        goto out_region;
+                }
+        }
+
+        if (i2c_pca_add_bus(&pca_isa_ops) < 0) {
+                printk(KERN_ERR "i2c-pca-isa: Failed to add i2c bus\n");
+                goto out_irq;
+        }
+
+        return 0;
+
+ out_irq:
+        if (irq > -1)
+                free_irq(irq, &pca_isa_ops);
+ out_region:
+        release_region(base, IO_SIZE);
+ out:
+        return -ENODEV;
+}
+
+static void pca_isa_exit(void)
+{
+        i2c_pca_del_bus(&pca_isa_ops);
+
+        if (irq > 0) {
+                disable_irq(irq);
+                free_irq(irq, &pca_isa_ops);
+        }
+        release_region(base, IO_SIZE);
+}
+
+MODULE_AUTHOR("Ian Campbell <icampbell@arcom.com>");
+MODULE_DESCRIPTION("ISA base PCA9564 driver");
+MODULE_LICENSE("GPL");
+
+module_param(base, ulong, 0);
+MODULE_PARM_DESC(base, "I/O base address");
+
+module_param(irq, int, 0);
+MODULE_PARM_DESC(irq, "IRQ");
+module_param(clock, int, 0);
+MODULE_PARM_DESC(clock, "Clock rate as described in table 1 of PCA9564 datasheet");
+
+module_param(own, int, 0); /* the driver can't do slave mode, so there's no real point in this */
+
+module_init(pca_isa_init);
+module_exit(pca_isa_exit);
diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c
new file mode 100644
index 000000000000..646381b6b3bf
--- /dev/null
+++ b/drivers/i2c/busses/i2c-piix4.c
@@ -0,0 +1,490 @@
+/*
+    piix4.c - Part of lm_sensors, Linux kernel modules for hardware
+              monitoring
+    Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and
+    Philip Edelbrock <phil@netroedge.com>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+/*
+   Supports:
+        Intel PIIX4, 440MX
+        Serverworks OSB4, CSB5, CSB6
+        SMSC Victory66
+
+   Note: we assume there can only be one device, with one SMBus interface.
+*/
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/stddef.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <linux/apm_bios.h>
+#include <linux/dmi.h>
+#include <asm/io.h>
+
+
+struct sd {
+        const unsigned short mfr;
+        const unsigned short dev;
+        const unsigned char fn;
+        const char *name;
+};
+
+/* PIIX4 SMBus address offsets */
+#define SMBHSTSTS       (0 + piix4_smba)
+#define SMBHSLVSTS      (1 + piix4_smba)
+#define SMBHSTCNT       (2 + piix4_smba)
+#define SMBHSTCMD       (3 + piix4_smba)
+#define SMBHSTADD       (4 + piix4_smba)
+#define SMBHSTDAT0      (5 + piix4_smba)
+#define SMBHSTDAT1      (6 + piix4_smba)
+#define SMBBLKDAT       (7 + piix4_smba)
+#define SMBSLVCNT       (8 + piix4_smba)
+#define SMBSHDWCMD      (9 + piix4_smba)
+#define SMBSLVEVT       (0xA + piix4_smba)
+#define SMBSLVDAT       (0xC + piix4_smba)
+
+/* count for request_region */
+#define SMBIOSIZE       8
+
+/* PCI Address Constants */
+#define SMBBA           0x090
+#define SMBHSTCFG       0x0D2
+#define SMBSLVC         0x0D3
+#define SMBSHDW1        0x0D4
+#define SMBSHDW2        0x0D5
+#define SMBREV          0x0D6
+
+/* Other settings */
+#define MAX_TIMEOUT     500
+#define  ENABLE_INT9    0
+
+/* PIIX4 constants */
+#define PIIX4_QUICK             0x00
+#define PIIX4_BYTE              0x04
+#define PIIX4_BYTE_DATA         0x08
+#define PIIX4_WORD_DATA         0x0C
+#define PIIX4_BLOCK_DATA        0x14
+
+/* insmod parameters */
+
+/* If force is set to anything different from 0, we forcibly enable the
+   PIIX4. DANGEROUS! */
+static int force = 0;
+module_param (force, int, 0);
+MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!");
+
+/* If force_addr is set to anything different from 0, we forcibly enable
+   the PIIX4 at the given address. VERY DANGEROUS! */
+static int force_addr = 0;
+module_param (force_addr, int, 0);
+MODULE_PARM_DESC(force_addr,
+                 "Forcibly enable the PIIX4 at the given address. "
+                 "EXTREMELY DANGEROUS!");
+
+/* If fix_hstcfg is set to anything different from 0, we reset one of the
+   registers to be a valid value. */
+static int fix_hstcfg = 0;
+module_param (fix_hstcfg, int, 0);
+MODULE_PARM_DESC(fix_hstcfg,
+                "Fix config register. Needed on some boards (Force CPCI735).");
+
+static int piix4_transaction(void);
+
+static unsigned short piix4_smba = 0;
+static struct i2c_adapter piix4_adapter;
+
+static struct dmi_system_id __devinitdata piix4_dmi_table[] = {
+        {
+                .ident = "IBM",
+                .matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), },
+        },
+        { },
+};
+
+static int __devinit piix4_setup(struct pci_dev *PIIX4_dev,
+                                const struct pci_device_id *id)
+{
+        unsigned char temp;
+
+        /* match up the function */
+        if (PCI_FUNC(PIIX4_dev->devfn) != id->driver_data)
+                return -ENODEV;
+
+        dev_info(&PIIX4_dev->dev, "Found %s device\n", pci_name(PIIX4_dev));
+
+        /* Don't access SMBus on IBM systems which get corrupted eeproms */
+        if (dmi_check_system(piix4_dmi_table) &&
+                        PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) {
+                dev_err(&PIIX4_dev->dev, "IBM Laptop detected; this module "
+                        "may corrupt your serial eeprom! Refusing to load "
+                        "module!\n");
+                return -EPERM;
+        }
+
+        /* Determine the address of the SMBus areas */
+        if (force_addr) {
+                piix4_smba = force_addr & 0xfff0;
+                force = 0;
+        } else {
+                pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba);
+                piix4_smba &= 0xfff0;
+                if(piix4_smba == 0) {
+                        dev_err(&PIIX4_dev->dev, "SMB base address "
+                                "uninitialized - upgrade BIOS or use "
+                                "force_addr=0xaddr\n");
+                        return -ENODEV;
+                }
+        }
+
+        if (!request_region(piix4_smba, SMBIOSIZE, "piix4-smbus")) {
+                dev_err(&PIIX4_dev->dev, "SMB region 0x%x already in use!\n",
+                        piix4_smba);
+                return -ENODEV;
+        }
+
+        pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp);
+
+        /* Some BIOS will set up the chipset incorrectly and leave a register
+           in an undefined state (causing I2C to act very strangely). */
+        if (temp & 0x02) {
+                if (fix_hstcfg) {
+                        dev_info(&PIIX4_dev->dev, "Working around buggy BIOS "
+                                        "(I2C)\n");
+                        temp &= 0xfd;
+                        pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp);
+                } else {
+                        dev_info(&PIIX4_dev->dev, "Unusual config register "
+                                        "value\n");
+                        dev_info(&PIIX4_dev->dev, "Try using fix_hstcfg=1 if "
+                                        "you experience problems\n");
+                }
+        }
+ 
+        /* If force_addr is set, we program the new address here. Just to make
+           sure, we disable the PIIX4 first. */
+        if (force_addr) {
+                pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe);
+                pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba);
+                pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01);
+                dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to "
+                        "new address %04x!\n", piix4_smba);
+        } else if ((temp & 1) == 0) {
+                if (force) {
+                        /* This should never need to be done, but has been
+                         * noted that many Dell machines have the SMBus
+                         * interface on the PIIX4 disabled!? NOTE: This assumes
+                         * I/O space and other allocations WERE done by the
+                         * Bios!  Don't complain if your hardware does weird
+                         * things after enabling this. :') Check for Bios
+                         * updates before resorting to this.
+                         */
+                        pci_write_config_byte(PIIX4_dev, SMBHSTCFG,
+                                              temp | 1);
+                        dev_printk(KERN_NOTICE, &PIIX4_dev->dev,
+                                "WARNING: SMBus interface has been "
+                                "FORCEFULLY ENABLED!\n");
+                } else {
+                        dev_err(&PIIX4_dev->dev,
+                                "Host SMBus controller not enabled!\n");
+                        release_region(piix4_smba, SMBIOSIZE);
+                        piix4_smba = 0;
+                        return -ENODEV;
+                }
+        }
+
+        if ((temp & 0x0E) == 8)
+                dev_dbg(&PIIX4_dev->dev, "Using Interrupt 9 for SMBus.\n");
+        else if ((temp & 0x0E) == 0)
+                dev_dbg(&PIIX4_dev->dev, "Using Interrupt SMI# for SMBus.\n");
+        else
+                dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration "
+                        "(or code out of date)!\n");
+
+        pci_read_config_byte(PIIX4_dev, SMBREV, &temp);
+        dev_dbg(&PIIX4_dev->dev, "SMBREV = 0x%X\n", temp);
+        dev_dbg(&PIIX4_dev->dev, "SMBA = 0x%X\n", piix4_smba);
+
+        return 0;
+}
+
+/* Another internally used function */
+static int piix4_transaction(void)
+{
+        int temp;
+        int result = 0;
+        int timeout = 0;
+
+        dev_dbg(&piix4_adapter.dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
+                "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
+                inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
+                inb_p(SMBHSTDAT1));
+
+        /* Make sure the SMBus host is ready to start transmitting */
+        if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
+                dev_dbg(&piix4_adapter.dev, "SMBus busy (%02x). "
+                        "Resetting... \n", temp);
+                outb_p(temp, SMBHSTSTS);
+                if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
+                        dev_err(&piix4_adapter.dev, "Failed! (%02x)\n", temp);
+                        return -1;
+                } else {
+                        dev_dbg(&piix4_adapter.dev, "Successfull!\n");
+                }
+        }
+
+        /* start the transaction by setting bit 6 */
+        outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT);
+
+        /* We will always wait for a fraction of a second! (See PIIX4 docs errata) */
+        do {
+                msleep(1);
+                temp = inb_p(SMBHSTSTS);
+        } while ((temp & 0x01) && (timeout++ < MAX_TIMEOUT));
+
+        /* If the SMBus is still busy, we give up */
+        if (timeout >= MAX_TIMEOUT) {
+                dev_err(&piix4_adapter.dev, "SMBus Timeout!\n");
+                result = -1;
+        }
+
+        if (temp & 0x10) {
+                result = -1;
+                dev_err(&piix4_adapter.dev, "Error: Failed bus transaction\n");
+        }
+
+        if (temp & 0x08) {
+                result = -1;
+                dev_dbg(&piix4_adapter.dev, "Bus collision! SMBus may be "
+                        "locked until next hard reset. (sorry!)\n");
+                /* Clock stops and slave is stuck in mid-transmission */
+        }
+
+        if (temp & 0x04) {
+                result = -1;
+                dev_dbg(&piix4_adapter.dev, "Error: no response!\n");
+        }
+
+        if (inb_p(SMBHSTSTS) != 0x00)
+                outb_p(inb(SMBHSTSTS), SMBHSTSTS);
+
+        if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
+                dev_err(&piix4_adapter.dev, "Failed reset at end of "
+                        "transaction (%02x)\n", temp);
+        }
+        dev_dbg(&piix4_adapter.dev, "Transaction (post): CNT=%02x, CMD=%02x, "
+                "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
+                inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
+                inb_p(SMBHSTDAT1));
+        return result;
+}
+
+/* Return -1 on error. */
+static s32 piix4_access(struct i2c_adapter * adap, u16 addr,
+                 unsigned short flags, char read_write,
+                 u8 command, int size, union i2c_smbus_data * data)
+{
+        int i, len;
+
+        switch (size) {
+        case I2C_SMBUS_PROC_CALL:
+                dev_err(&adap->dev, "I2C_SMBUS_PROC_CALL not supported!\n");
+                return -1;
+        case I2C_SMBUS_QUICK:
+                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
+                       SMBHSTADD);
+                size = PIIX4_QUICK;
+                break;
+        case I2C_SMBUS_BYTE:
+                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
+                       SMBHSTADD);
+                if (read_write == I2C_SMBUS_WRITE)
+                        outb_p(command, SMBHSTCMD);
+                size = PIIX4_BYTE;
+                break;
+        case I2C_SMBUS_BYTE_DATA:
+                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
+                       SMBHSTADD);
+                outb_p(command, SMBHSTCMD);
+                if (read_write == I2C_SMBUS_WRITE)
+                        outb_p(data->byte, SMBHSTDAT0);
+                size = PIIX4_BYTE_DATA;
+                break;
+        case I2C_SMBUS_WORD_DATA:
+                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
+                       SMBHSTADD);
+                outb_p(command, SMBHSTCMD);
+                if (read_write == I2C_SMBUS_WRITE) {
+                        outb_p(data->word & 0xff, SMBHSTDAT0);
+                        outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
+                }
+                size = PIIX4_WORD_DATA;
+                break;
+        case I2C_SMBUS_BLOCK_DATA:
+                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
+                       SMBHSTADD);
+                outb_p(command, SMBHSTCMD);
+                if (read_write == I2C_SMBUS_WRITE) {
+                        len = data->block[0];
+                        if (len < 0)
+                                len = 0;
+                        if (len > 32)
+                                len = 32;
+                        outb_p(len, SMBHSTDAT0);
+                        i = inb_p(SMBHSTCNT);   /* Reset SMBBLKDAT */
+                        for (i = 1; i <= len; i++)
+                                outb_p(data->block[i], SMBBLKDAT);
+                }
+                size = PIIX4_BLOCK_DATA;
+                break;
+        }
+
+        outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT);
+
+        if (piix4_transaction())        /* Error in transaction */
+                return -1;
+
+        if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK))
+                return 0;
+
+
+        switch (size) {
+        case PIIX4_BYTE:        /* Where is the result put? I assume here it is in
+                                   SMBHSTDAT0 but it might just as well be in the
+                                   SMBHSTCMD. No clue in the docs */
+
+                data->byte = inb_p(SMBHSTDAT0);
+                break;
+        case PIIX4_BYTE_DATA:
+                data->byte = inb_p(SMBHSTDAT0);
+                break;
+        case PIIX4_WORD_DATA:
+                data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
+                break;
+        case PIIX4_BLOCK_DATA:
+                data->block[0] = inb_p(SMBHSTDAT0);
+                i = inb_p(SMBHSTCNT);   /* Reset SMBBLKDAT */
+                for (i = 1; i <= data->block[0]; i++)
+                        data->block[i] = inb_p(SMBBLKDAT);
+                break;
+        }
+        return 0;
+}
+
+static u32 piix4_func(struct i2c_adapter *adapter)
+{
+        return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
+            I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
+            I2C_FUNC_SMBUS_BLOCK_DATA;
+}
+
+static struct i2c_algorithm smbus_algorithm = {
+        .name           = "Non-I2C SMBus adapter",
+        .id             = I2C_ALGO_SMBUS,
+        .smbus_xfer     = piix4_access,
+        .functionality  = piix4_func,
+};
+
+static struct i2c_adapter piix4_adapter = {
+        .owner          = THIS_MODULE,
+        .class          = I2C_CLASS_HWMON,
+        .algo           = &smbus_algorithm,
+        .name           = "unset",
+};
+
+static struct pci_device_id piix4_ids[] = {
+        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3),
+          .driver_data = 3 },
+        { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4),
+          .driver_data = 0 },
+        { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5),
+          .driver_data = 0 },
+        { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6),
+          .driver_data = 0 },
+        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3),
+          .driver_data = 3 },
+        { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3),
+          .driver_data = 0 },
+        { 0, }
+};
+
+MODULE_DEVICE_TABLE (pci, piix4_ids);
+
+static int __devinit piix4_probe(struct pci_dev *dev,
+                                const struct pci_device_id *id)
+{
+        int retval;
+
+        retval = piix4_setup(dev, id);
+        if (retval)
+                return retval;
+
+        /* set up the driverfs linkage to our parent device */
+        piix4_adapter.dev.parent = &dev->dev;
+
+        snprintf(piix4_adapter.name, I2C_NAME_SIZE,
+                "SMBus PIIX4 adapter at %04x", piix4_smba);
+
+        if ((retval = i2c_add_adapter(&piix4_adapter))) {
+                dev_err(&dev->dev, "Couldn't register adapter!\n");
+                release_region(piix4_smba, SMBIOSIZE);
+                piix4_smba = 0;
+        }
+
+        return retval;
+}
+
+static void __devexit piix4_remove(struct pci_dev *dev)
+{
+        if (piix4_smba) {
+                i2c_del_adapter(&piix4_adapter);
+                release_region(piix4_smba, SMBIOSIZE);
+                piix4_smba = 0;
+        }
+}
+
+static struct pci_driver piix4_driver = {
+        .name           = "piix4_smbus",
+        .id_table       = piix4_ids,
+        .probe          = piix4_probe,
+        .remove         = __devexit_p(piix4_remove),
+};
+
+static int __init i2c_piix4_init(void)
+{
+        return pci_register_driver(&piix4_driver);
+}
+
+static void __exit i2c_piix4_exit(void)
+{
+        pci_unregister_driver(&piix4_driver);
+}
+
+MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl> and "
+                "Philip Edelbrock <phil@netroedge.com>");
+MODULE_DESCRIPTION("PIIX4 SMBus driver");
+MODULE_LICENSE("GPL");
+
+module_init(i2c_piix4_init);
+module_exit(i2c_piix4_exit);
diff --git a/drivers/i2c/busses/i2c-prosavage.c b/drivers/i2c/busses/i2c-prosavage.c
new file mode 100644
index 000000000000..13d66289933b
--- /dev/null
+++ b/drivers/i2c/busses/i2c-prosavage.c
@@ -0,0 +1,334 @@
+/*
+ *    kernel/busses/i2c-prosavage.c
+ *
+ *    i2c bus driver for S3/VIA 8365/8375 graphics processor.
+ *    Copyright (c) 2003 Henk Vergonet <henk@god.dyndns.org>
+ *    Based on code written by:
+ *      Frodo Looijaard <frodol@dds.nl>,
+ *      Philip Edelbrock <phil@netroedge.com>,
+ *      Ralph Metzler <rjkm@thp.uni-koeln.de>, and
+ *      Mark D. Studebaker <mdsxyz123@yahoo.com>
+ *      Simon Vogl
+ *      and others
+ *
+ *    Please read the lm_sensors documentation for details on use.
+ *
+ *    This program is free software; you can redistribute it and/or modify
+ *    it under the terms of the GNU General Public License as published by
+ *    the Free Software Foundation; either version 2 of the License, or
+ *    (at your option) any later version.
+ *
+ *    This program is distributed in the hope that it will be useful,
+ *    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *    GNU General Public License for more details.
+ *
+ *    You should have received a copy of the GNU General Public License
+ *    along with this program; if not, write to the Free Software
+ *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+/*  18-05-2003 HVE - created
+ *  14-06-2003 HVE - adapted for lm_sensors2
+ *  17-06-2003 HVE - linux 2.5.xx compatible
+ *  18-06-2003 HVE - codingstyle
+ *  21-06-2003 HVE - compatibility lm_sensors2 and linux 2.5.xx
+ *                   codingstyle, mmio enabled
+ *
+ *  This driver interfaces to the I2C bus of the VIA north bridge embedded
+ *  ProSavage4/8 devices. Usefull for gaining access to the TV Encoder chips.
+ *
+ *  Graphics cores:
+ *   S3/VIA KM266/VT8375 aka ProSavage8
+ *   S3/VIA KM133/VT8365 aka Savage4
+ *
+ *  Two serial busses are implemented:
+ *   SERIAL1 - I2C serial communications interface
+ *   SERIAL2 - DDC2 monitor communications interface
+ *
+ *  Tested on a FX41 mainboard, see http://www.shuttle.com
+ * 
+ *
+ *  TODO:
+ *  - integration with prosavage framebuffer device
+ *    (Additional documentation needed :(
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/i2c.h>
+#include <linux/i2c-algo-bit.h>
+#include <asm/io.h>
+
+/*
+ * driver configuration
+ */
+#define MAX_BUSSES      2
+
+struct s_i2c_bus {
+        void __iomem *mmvga;
+        int     i2c_reg;
+        int     adap_ok;
+        struct i2c_adapter              adap;
+        struct i2c_algo_bit_data        algo;
+};
+
+struct s_i2c_chip {
+        void __iomem *mmio;
+        struct s_i2c_bus        i2c_bus[MAX_BUSSES];
+};
+
+
+/*
+ * i2c configuration
+ */
+#ifndef I2C_HW_B_S3VIA
+#define I2C_HW_B_S3VIA  0x18    /* S3VIA ProSavage adapter              */
+#endif
+
+/* delays */
+#define CYCLE_DELAY     10
+#define TIMEOUT         (HZ / 2)
+
+
+/* 
+ * S3/VIA 8365/8375 registers
+ */
+#define VGA_CR_IX       0x3d4
+#define VGA_CR_DATA     0x3d5
+
+#define CR_SERIAL1      0xa0    /* I2C serial communications interface */
+#define MM_SERIAL1      0xff20
+#define CR_SERIAL2      0xb1    /* DDC2 monitor communications interface */
+
+/* based on vt8365 documentation */
+#define I2C_ENAB        0x10
+#define I2C_SCL_OUT     0x01
+#define I2C_SDA_OUT     0x02
+#define I2C_SCL_IN      0x04
+#define I2C_SDA_IN      0x08
+
+#define SET_CR_IX(p, val)       writeb((val), (p)->mmvga + VGA_CR_IX)
+#define SET_CR_DATA(p, val)     writeb((val), (p)->mmvga + VGA_CR_DATA)
+#define GET_CR_DATA(p)          readb((p)->mmvga + VGA_CR_DATA)
+
+
+/*
+ * Serial bus line handling
+ *
+ * serial communications register as parameter in private data
+ *
+ * TODO: locks with other code sections accessing video registers?
+ */
+static void bit_s3via_setscl(void *bus, int val)
+{
+        struct s_i2c_bus *p = (struct s_i2c_bus *)bus;
+        unsigned int r;
+
+        SET_CR_IX(p, p->i2c_reg);
+        r = GET_CR_DATA(p);
+        r |= I2C_ENAB;
+        if (val) {
+                r |= I2C_SCL_OUT;
+        } else {
+                r &= ~I2C_SCL_OUT;
+        }
+        SET_CR_DATA(p, r);
+}
+
+static void bit_s3via_setsda(void *bus, int val)
+{
+        struct s_i2c_bus *p = (struct s_i2c_bus *)bus;
+        unsigned int r;
+        
+        SET_CR_IX(p, p->i2c_reg);
+        r = GET_CR_DATA(p);
+        r |= I2C_ENAB;
+        if (val) {
+                r |= I2C_SDA_OUT;
+        } else {
+                r &= ~I2C_SDA_OUT;
+        }
+        SET_CR_DATA(p, r);
+}
+
+static int bit_s3via_getscl(void *bus)
+{
+        struct s_i2c_bus *p = (struct s_i2c_bus *)bus;
+
+        SET_CR_IX(p, p->i2c_reg);
+        return (0 != (GET_CR_DATA(p) & I2C_SCL_IN));
+}
+
+static int bit_s3via_getsda(void *bus)
+{
+        struct s_i2c_bus *p = (struct s_i2c_bus *)bus;
+
+        SET_CR_IX(p, p->i2c_reg);
+        return (0 != (GET_CR_DATA(p) & I2C_SDA_IN));
+}
+
+
+/*
+ * adapter initialisation
+ */
+static int i2c_register_bus(struct pci_dev *dev, struct s_i2c_bus *p, void __iomem *mmvga, u32 i2c_reg)
+{
+        int ret;
+        p->adap.owner     = THIS_MODULE;
+        p->adap.id        = I2C_HW_B_S3VIA;
+        p->adap.algo_data = &p->algo;
+        p->adap.dev.parent = &dev->dev;
+        p->algo.setsda    = bit_s3via_setsda;
+        p->algo.setscl    = bit_s3via_setscl;
+        p->algo.getsda    = bit_s3via_getsda;
+        p->algo.getscl    = bit_s3via_getscl;
+        p->algo.udelay    = CYCLE_DELAY;
+        p->algo.mdelay    = CYCLE_DELAY;
+        p->algo.timeout   = TIMEOUT;
+        p->algo.data      = p;
+        p->mmvga          = mmvga;
+        p->i2c_reg        = i2c_reg;
+    
+        ret = i2c_bit_add_bus(&p->adap);
+        if (ret) {
+                return ret;
+        }
+
+        p->adap_ok = 1;
+        return 0;
+}
+
+
+/*
+ * Cleanup stuff
+ */
+static void prosavage_remove(struct pci_dev *dev)
+{
+        struct s_i2c_chip *chip;
+        int i, ret;
+
+        chip = (struct s_i2c_chip *)pci_get_drvdata(dev);
+
+        if (!chip) {
+                return;
+        }
+        for (i = MAX_BUSSES - 1; i >= 0; i--) {
+                if (chip->i2c_bus[i].adap_ok == 0)
+                        continue;
+
+                ret = i2c_bit_del_bus(&chip->i2c_bus[i].adap);
+                if (ret) {
+                        dev_err(&dev->dev, "%s not removed\n",
+                                chip->i2c_bus[i].adap.name);
+                }
+        }
+        if (chip->mmio) {
+                iounmap(chip->mmio);
+        }
+        kfree(chip);
+}
+
+
+/*
+ * Detect chip and initialize it
+ */
+static int __devinit prosavage_probe(struct pci_dev *dev, const struct pci_device_id *id)
+{
+        int ret;
+        unsigned long base, len;
+        struct s_i2c_chip *chip;
+        struct s_i2c_bus  *bus;
+
+        pci_set_drvdata(dev, kmalloc(sizeof(struct s_i2c_chip), GFP_KERNEL)); 
+        chip = (struct s_i2c_chip *)pci_get_drvdata(dev);
+        if (chip == NULL) {
+                return -ENOMEM;
+        }
+
+        memset(chip, 0, sizeof(struct s_i2c_chip));
+
+        base = dev->resource[0].start & PCI_BASE_ADDRESS_MEM_MASK;
+        len  = dev->resource[0].end - base + 1;
+        chip->mmio = ioremap_nocache(base, len);
+
+        if (chip->mmio == NULL) {
+                dev_err(&dev->dev, "ioremap failed\n");
+                prosavage_remove(dev);
+                return -ENODEV;
+        }
+
+
+        /*
+         * Chip initialisation
+         */
+        /* Unlock Extended IO Space ??? */
+
+
+        /*
+         * i2c bus registration
+         */
+        bus = &chip->i2c_bus[0];
+        snprintf(bus->adap.name, sizeof(bus->adap.name),
+                "ProSavage I2C bus at %02x:%02x.%x",
+                dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
+        ret = i2c_register_bus(dev, bus, chip->mmio + 0x8000, CR_SERIAL1);
+        if (ret) {
+                goto err_adap;
+        }
+        /*
+         * ddc bus registration
+         */
+        bus = &chip->i2c_bus[1];
+        snprintf(bus->adap.name, sizeof(bus->adap.name),
+                "ProSavage DDC bus at %02x:%02x.%x",
+                dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
+        ret = i2c_register_bus(dev, bus, chip->mmio + 0x8000, CR_SERIAL2);
+        if (ret) {
+                goto err_adap;
+        }
+        return 0;
+err_adap:
+        dev_err(&dev->dev, "%s failed\n", bus->adap.name);
+        prosavage_remove(dev);
+        return ret;
+}
+
+
+/*
+ * Data for PCI driver interface
+ */
+static struct pci_device_id prosavage_pci_tbl[] = {
+        { PCI_DEVICE(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_SAVAGE4) },
+        { PCI_DEVICE(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_PROSAVAGE8) },
+        { 0, },
+};
+
+MODULE_DEVICE_TABLE (pci, prosavage_pci_tbl);
+
+static struct pci_driver prosavage_driver = {
+        .name           =       "prosavage_smbus",
+        .id_table       =       prosavage_pci_tbl,
+        .probe          =       prosavage_probe,
+        .remove         =       prosavage_remove,
+};
+
+static int __init i2c_prosavage_init(void)
+{
+        return pci_register_driver(&prosavage_driver);
+}
+
+static void __exit i2c_prosavage_exit(void)
+{
+        pci_unregister_driver(&prosavage_driver);
+}
+
+MODULE_DEVICE_TABLE(pci, prosavage_pci_tbl);
+MODULE_AUTHOR("Henk Vergonet");
+MODULE_DESCRIPTION("ProSavage VIA 8365/8375 smbus driver");
+MODULE_LICENSE("GPL");
+
+module_init (i2c_prosavage_init);
+module_exit (i2c_prosavage_exit);
diff --git a/drivers/i2c/busses/i2c-rpx.c b/drivers/i2c/busses/i2c-rpx.c
new file mode 100644
index 000000000000..9497b1b6852f
--- /dev/null
+++ b/drivers/i2c/busses/i2c-rpx.c
@@ -0,0 +1,102 @@
+/*
+ * Embedded Planet RPX Lite MPC8xx CPM I2C interface.
+ * Copyright (c) 1999 Dan Malek (dmalek@jlc.net).
+ *
+ * moved into proper i2c interface;
+ * Brad Parker (brad@heeltoe.com)
+ *
+ * RPX lite specific parts of the i2c interface
+ * Update:  There actually isn't anything RPXLite-specific about this module.
+ * This should work for most any 8xx board.  The console messages have been 
+ * changed to eliminate RPXLite references.
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/stddef.h>
+#include <linux/i2c.h>
+#include <linux/i2c-algo-8xx.h>
+#include <asm/mpc8xx.h>
+#include <asm/commproc.h>
+
+
+static void
+rpx_iic_init(struct i2c_algo_8xx_data *data)
+{
+        volatile cpm8xx_t *cp;
+        volatile immap_t *immap;
+
+        cp = cpmp;      /* Get pointer to Communication Processor */
+        immap = (immap_t *)IMAP_ADDR;   /* and to internal registers */
+
+        data->iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
+
+        /* Check for and use a microcode relocation patch.
+        */
+        if ((data->reloc = data->iip->iic_rpbase))
+                data->iip = (iic_t *)&cp->cp_dpmem[data->iip->iic_rpbase];
+                
+        data->i2c = (i2c8xx_t *)&(immap->im_i2c);
+        data->cp = cp;
+
+        /* Initialize Port B IIC pins.
+        */
+        cp->cp_pbpar |= 0x00000030;
+        cp->cp_pbdir |= 0x00000030;
+        cp->cp_pbodr |= 0x00000030;
+
+        /* Allocate space for two transmit and two receive buffer
+         * descriptors in the DP ram.
+         */
+        data->dp_addr = cpm_dpalloc(sizeof(cbd_t) * 4, 8);
+                
+        /* ptr to i2c area */
+        data->i2c = (i2c8xx_t *)&(((immap_t *)IMAP_ADDR)->im_i2c);
+}
+
+static int rpx_install_isr(int irq, void (*func)(void *, void *), void *data)
+{
+        /* install interrupt handler */
+        cpm_install_handler(irq, (void (*)(void *, struct pt_regs *)) func, data);
+
+        return 0;
+}
+
+static struct i2c_algo_8xx_data rpx_data = {
+        .setisr = rpx_install_isr
+};
+
+static struct i2c_adapter rpx_ops = {
+        .owner          = THIS_MODULE,
+        .name           = "m8xx",
+        .id             = I2C_HW_MPC8XX_EPON,
+        .algo_data      = &rpx_data,
+};
+
+int __init i2c_rpx_init(void)
+{
+        printk(KERN_INFO "i2c-rpx: i2c MPC8xx driver\n");
+
+        /* reset hardware to sane state */
+        rpx_iic_init(&rpx_data);
+
+        if (i2c_8xx_add_bus(&rpx_ops) < 0) {
+                printk(KERN_ERR "i2c-rpx: Unable to register with I2C\n");
+                return -ENODEV;
+        }
+
+        return 0;
+}
+
+void __exit i2c_rpx_exit(void)
+{
+        i2c_8xx_del_bus(&rpx_ops);
+}
+
+MODULE_AUTHOR("Dan Malek <dmalek@jlc.net>");
+MODULE_DESCRIPTION("I2C-Bus adapter routines for MPC8xx boards");
+
+module_init(i2c_rpx_init);
+module_exit(i2c_rpx_exit);
diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c
new file mode 100644
index 000000000000..fcfa51c1436b
--- /dev/null
+++ b/drivers/i2c/busses/i2c-s3c2410.c
@@ -0,0 +1,938 @@
+/* linux/drivers/i2c/busses/i2c-s3c2410.c
+ *
+ * Copyright (C) 2004,2005 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 I2C Controller
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include <linux/i2c.h>
+#include <linux/i2c-id.h>
+#include <linux/init.h>
+#include <linux/time.h>
+#include <linux/interrupt.h>
+#include <linux/sched.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/device.h>
+
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/io.h>
+
+#include <asm/hardware/clock.h>
+#include <asm/arch/regs-gpio.h>
+#include <asm/arch/regs-iic.h>
+#include <asm/arch/iic.h>
+
+/* i2c controller state */
+
+enum s3c24xx_i2c_state {
+        STATE_IDLE,
+        STATE_START,
+        STATE_READ,
+        STATE_WRITE,
+        STATE_STOP
+};
+
+struct s3c24xx_i2c {
+        spinlock_t              lock;
+        wait_queue_head_t       wait;
+
+        struct i2c_msg          *msg;
+        unsigned int            msg_num;
+        unsigned int            msg_idx;
+        unsigned int            msg_ptr;
+
+        enum s3c24xx_i2c_state  state;
+
+        void __iomem            *regs;
+        struct clk              *clk;
+        struct device           *dev;
+        struct resource         *irq;
+        struct resource         *ioarea;
+        struct i2c_adapter      adap;
+};
+
+/* default platform data to use if not supplied in the platform_device
+*/
+
+static struct s3c2410_platform_i2c s3c24xx_i2c_default_platform = {
+        .flags          = 0,
+        .slave_addr     = 0x10,
+        .bus_freq       = 100*1000,
+        .max_freq       = 400*1000,
+        .sda_delay      = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
+};
+
+/* s3c24xx_i2c_is2440()
+ *
+ * return true is this is an s3c2440
+*/
+
+static inline int s3c24xx_i2c_is2440(struct s3c24xx_i2c *i2c)
+{
+        struct platform_device *pdev = to_platform_device(i2c->dev);
+
+        return !strcmp(pdev->name, "s3c2440-i2c");
+}
+
+
+/* s3c24xx_i2c_get_platformdata
+ *
+ * get the platform data associated with the given device, or return
+ * the default if there is none
+*/
+
+static inline struct s3c2410_platform_i2c *s3c24xx_i2c_get_platformdata(struct device *dev)
+{
+        if (dev->platform_data != NULL)
+                return (struct s3c2410_platform_i2c *)dev->platform_data;
+
+        return &s3c24xx_i2c_default_platform;
+}
+
+/* s3c24xx_i2c_master_complete
+ *
+ * complete the message and wake up the caller, using the given return code,
+ * or zero to mean ok.
+*/
+
+static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
+{
+        dev_dbg(i2c->dev, "master_complete %d\n", ret);
+
+        i2c->msg_ptr = 0;
+        i2c->msg = NULL;
+        i2c->msg_idx ++;
+        i2c->msg_num = 0;
+        if (ret)
+                i2c->msg_idx = ret;
+
+        wake_up(&i2c->wait);
+}
+
+static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
+{
+        unsigned long tmp;
+        
+        tmp = readl(i2c->regs + S3C2410_IICCON);
+        writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
+
+}
+
+static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
+{
+        unsigned long tmp;
+        
+        tmp = readl(i2c->regs + S3C2410_IICCON);
+        writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
+
+}
+
+/* irq enable/disable functions */
+
+static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
+{
+        unsigned long tmp;
+        
+        tmp = readl(i2c->regs + S3C2410_IICCON);
+        writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
+}
+
+static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
+{
+        unsigned long tmp;
+        
+        tmp = readl(i2c->regs + S3C2410_IICCON);
+        writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
+}
+
+
+/* s3c24xx_i2c_message_start
+ *
+ * put the start of a message onto the bus 
+*/
+
+static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c, 
+                                      struct i2c_msg *msg)
+{
+        unsigned int addr = (msg->addr & 0x7f) << 1;
+        unsigned long stat;
+        unsigned long iiccon;
+
+        stat = 0;
+        stat |=  S3C2410_IICSTAT_TXRXEN;
+
+        if (msg->flags & I2C_M_RD) {
+                stat |= S3C2410_IICSTAT_MASTER_RX;
+                addr |= 1;
+        } else
+                stat |= S3C2410_IICSTAT_MASTER_TX;
+
+        if (msg->flags & I2C_M_REV_DIR_ADDR)
+                addr ^= 1;
+
+        // todo - check for wether ack wanted or not
+        s3c24xx_i2c_enable_ack(i2c);
+
+        iiccon = readl(i2c->regs + S3C2410_IICCON);
+        writel(stat, i2c->regs + S3C2410_IICSTAT);
+        
+        dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
+        writeb(addr, i2c->regs + S3C2410_IICDS);
+        
+        // delay a bit and reset iiccon before setting start (per samsung)
+        udelay(1);
+        dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
+        writel(iiccon, i2c->regs + S3C2410_IICCON);
+        
+        stat |=  S3C2410_IICSTAT_START;
+        writel(stat, i2c->regs + S3C2410_IICSTAT);
+}
+
+static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
+{
+        unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
+
+        dev_dbg(i2c->dev, "STOP\n");
+
+        /* stop the transfer */
+        iicstat &= ~ S3C2410_IICSTAT_START;
+        writel(iicstat, i2c->regs + S3C2410_IICSTAT);
+        
+        i2c->state = STATE_STOP;
+        
+        s3c24xx_i2c_master_complete(i2c, ret);
+        s3c24xx_i2c_disable_irq(i2c);
+}
+
+/* helper functions to determine the current state in the set of
+ * messages we are sending */
+
+/* is_lastmsg()
+ *
+ * returns TRUE if the current message is the last in the set 
+*/
+
+static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
+{
+        return i2c->msg_idx >= (i2c->msg_num - 1);
+}
+
+/* is_msglast
+ *
+ * returns TRUE if we this is the last byte in the current message
+*/
+
+static inline int is_msglast(struct s3c24xx_i2c *i2c)
+{
+        return i2c->msg_ptr == i2c->msg->len-1;
+}
+
+/* is_msgend
+ *
+ * returns TRUE if we reached the end of the current message
+*/
+
+static inline int is_msgend(struct s3c24xx_i2c *i2c)
+{
+        return i2c->msg_ptr >= i2c->msg->len;
+}
+
+/* i2s_s3c_irq_nextbyte
+ *
+ * process an interrupt and work out what to do
+ */
+
+static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
+{
+        unsigned long tmp;
+        unsigned char byte;
+        int ret = 0;
+
+        switch (i2c->state) {
+
+        case STATE_IDLE:
+                dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __FUNCTION__);
+                goto out;
+                break;
+
+        case STATE_STOP:
+                dev_err(i2c->dev, "%s: called in STATE_STOP\n", __FUNCTION__);
+                s3c24xx_i2c_disable_irq(i2c);           
+                goto out_ack;
+
+        case STATE_START:
+                /* last thing we did was send a start condition on the
+                 * bus, or started a new i2c message
+                 */
+                
+                if (iicstat  & S3C2410_IICSTAT_LASTBIT &&
+                    !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
+                        /* ack was not received... */
+
+                        dev_dbg(i2c->dev, "ack was not received\n");
+                        s3c24xx_i2c_stop(i2c, -EREMOTEIO);
+                        goto out_ack;
+                }
+
+                if (i2c->msg->flags & I2C_M_RD)
+                        i2c->state = STATE_READ;
+                else
+                        i2c->state = STATE_WRITE;
+
+                /* terminate the transfer if there is nothing to do
+                 * (used by the i2c probe to find devices */
+
+                if (is_lastmsg(i2c) && i2c->msg->len == 0) {
+                        s3c24xx_i2c_stop(i2c, 0);
+                        goto out_ack;
+                }
+
+                if (i2c->state == STATE_READ)
+                        goto prepare_read;
+
+                /* fall through to the write state, as we will need to 
+                 * send a byte as well */
+
+        case STATE_WRITE:
+                /* we are writing data to the device... check for the
+                 * end of the message, and if so, work out what to do
+                 */
+
+        retry_write:
+                if (!is_msgend(i2c)) {
+                        byte = i2c->msg->buf[i2c->msg_ptr++];
+                        writeb(byte, i2c->regs + S3C2410_IICDS);
+                        
+                } else if (!is_lastmsg(i2c)) {
+                        /* we need to go to the next i2c message */
+
+                        dev_dbg(i2c->dev, "WRITE: Next Message\n");
+
+                        i2c->msg_ptr = 0;
+                        i2c->msg_idx ++;
+                        i2c->msg++;
+                        
+                        /* check to see if we need to do another message */
+                        if (i2c->msg->flags & I2C_M_NOSTART) {
+
+                                if (i2c->msg->flags & I2C_M_RD) {
+                                        /* cannot do this, the controller
+                                         * forces us to send a new START
+                                         * when we change direction */
+
+                                        s3c24xx_i2c_stop(i2c, -EINVAL);
+                                }
+
+                                goto retry_write;
+                        } else {
+                        
+                                /* send the new start */
+                                s3c24xx_i2c_message_start(i2c, i2c->msg);
+                                i2c->state = STATE_START;
+                        }
+
+                } else {
+                        /* send stop */
+
+                        s3c24xx_i2c_stop(i2c, 0);
+                }
+                break;
+
+        case STATE_READ:
+                /* we have a byte of data in the data register, do 
+                 * something with it, and then work out wether we are
+                 * going to do any more read/write
+                 */
+
+                if (!(i2c->msg->flags & I2C_M_IGNORE_NAK) &&
+                    !(is_msglast(i2c) && is_lastmsg(i2c))) {
+
+                        if (iicstat & S3C2410_IICSTAT_LASTBIT) {
+                                dev_dbg(i2c->dev, "READ: No Ack\n");
+
+                                s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
+                                goto out_ack;
+                        }
+                }
+
+                byte = readb(i2c->regs + S3C2410_IICDS);
+                i2c->msg->buf[i2c->msg_ptr++] = byte;
+
+        prepare_read:
+                if (is_msglast(i2c)) {
+                        /* last byte of buffer */
+
+                        if (is_lastmsg(i2c))
+                                s3c24xx_i2c_disable_ack(i2c);
+                        
+                } else if (is_msgend(i2c)) {
+                        /* ok, we've read the entire buffer, see if there
+                         * is anything else we need to do */
+
+                        if (is_lastmsg(i2c)) {
+                                /* last message, send stop and complete */
+                                dev_dbg(i2c->dev, "READ: Send Stop\n");
+
+                                s3c24xx_i2c_stop(i2c, 0);
+                        } else {
+                                /* go to the next transfer */
+                                dev_dbg(i2c->dev, "READ: Next Transfer\n");
+
+                                i2c->msg_ptr = 0;
+                                i2c->msg_idx++;
+                                i2c->msg++;
+                        }
+                }
+
+                break;
+        }
+
+        /* acknowlegde the IRQ and get back on with the work */
+
+ out_ack:
+        tmp = readl(i2c->regs + S3C2410_IICCON);        
+        tmp &= ~S3C2410_IICCON_IRQPEND;
+        writel(tmp, i2c->regs + S3C2410_IICCON);
+ out:
+        return ret;
+}
+
+/* s3c24xx_i2c_irq
+ *
+ * top level IRQ servicing routine
+*/
+
+static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id,
+                                   struct pt_regs *regs)
+{
+        struct s3c24xx_i2c *i2c = dev_id;
+        unsigned long status;
+        unsigned long tmp;
+
+        status = readl(i2c->regs + S3C2410_IICSTAT);
+
+        if (status & S3C2410_IICSTAT_ARBITR) {
+                // deal with arbitration loss
+                dev_err(i2c->dev, "deal with arbitration loss\n");
+        }
+
+        if (i2c->state == STATE_IDLE) {
+                dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
+
+                tmp = readl(i2c->regs + S3C2410_IICCON);        
+                tmp &= ~S3C2410_IICCON_IRQPEND;
+                writel(tmp, i2c->regs +  S3C2410_IICCON);
+                goto out;
+        }
+        
+        /* pretty much this leaves us with the fact that we've
+         * transmitted or received whatever byte we last sent */
+
+        i2s_s3c_irq_nextbyte(i2c, status);
+
+ out:
+        return IRQ_HANDLED;
+}
+
+
+/* s3c24xx_i2c_set_master
+ *
+ * get the i2c bus for a master transaction
+*/
+
+static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
+{
+        unsigned long iicstat;
+        int timeout = 400;
+
+        while (timeout-- > 0) {
+                iicstat = readl(i2c->regs + S3C2410_IICSTAT);
+                
+                if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
+                        return 0;
+
+                msleep(1);
+        }
+
+        dev_dbg(i2c->dev, "timeout: GPEDAT is %08x\n",
+                __raw_readl(S3C2410_GPEDAT));
+
+        return -ETIMEDOUT;
+}
+
+/* s3c24xx_i2c_doxfer
+ *
+ * this starts an i2c transfer
+*/
+
+static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, struct i2c_msg *msgs, int num)
+{
+        unsigned long timeout;
+        int ret;
+
+        ret = s3c24xx_i2c_set_master(i2c);
+        if (ret != 0) {
+                dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
+                ret = -EAGAIN;
+                goto out;
+        }
+
+        spin_lock_irq(&i2c->lock);
+
+        i2c->msg     = msgs;
+        i2c->msg_num = num;
+        i2c->msg_ptr = 0;
+        i2c->msg_idx = 0;
+        i2c->state   = STATE_START;
+
+        s3c24xx_i2c_enable_irq(i2c);
+        s3c24xx_i2c_message_start(i2c, msgs);
+        spin_unlock_irq(&i2c->lock);
+        
+        timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
+
+        ret = i2c->msg_idx;
+
+        /* having these next two as dev_err() makes life very 
+         * noisy when doing an i2cdetect */
+
+        if (timeout == 0)
+                dev_dbg(i2c->dev, "timeout\n");
+        else if (ret != num)
+                dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
+
+        /* ensure the stop has been through the bus */
+
+        msleep(1);
+
+ out:
+        return ret;
+}
+
+/* s3c24xx_i2c_xfer
+ *
+ * first port of call from the i2c bus code when an message needs
+ * transfering across the i2c bus.
+*/
+
+static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
+                        struct i2c_msg *msgs, int num)
+{
+        struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
+        int retry;
+        int ret;
+
+        for (retry = 0; retry < adap->retries; retry++) {
+
+                ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
+
+                if (ret != -EAGAIN)
+                        return ret;
+
+                dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
+
+                udelay(100);
+        }
+
+        return -EREMOTEIO;
+}
+
+/* declare our i2c functionality */
+static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
+{
+        return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
+}
+
+/* i2c bus registration info */
+
+static struct i2c_algorithm s3c24xx_i2c_algorithm = {
+        .name                   = "S3C2410-I2C-Algorithm",
+        .master_xfer            = s3c24xx_i2c_xfer,
+        .functionality          = s3c24xx_i2c_func,
+};
+
+static struct s3c24xx_i2c s3c24xx_i2c = {
+        .lock   = SPIN_LOCK_UNLOCKED,
+        .wait   = __WAIT_QUEUE_HEAD_INITIALIZER(s3c24xx_i2c.wait),
+        .adap   = {
+                .name                   = "s3c2410-i2c",
+                .owner                  = THIS_MODULE,
+                .algo                   = &s3c24xx_i2c_algorithm,
+                .retries                = 2,
+                .class                  = I2C_CLASS_HWMON,
+        },
+};
+
+/* s3c24xx_i2c_calcdivisor
+ *
+ * return the divisor settings for a given frequency
+*/
+
+static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
+                                   unsigned int *div1, unsigned int *divs)
+{
+        unsigned int calc_divs = clkin / wanted;
+        unsigned int calc_div1;
+
+        if (calc_divs > (16*16))
+                calc_div1 = 512;
+        else
+                calc_div1 = 16;
+
+        calc_divs += calc_div1-1;
+        calc_divs /= calc_div1;
+
+        if (calc_divs == 0)
+                calc_divs = 1;
+        if (calc_divs > 17)
+                calc_divs = 17;
+
+        *divs = calc_divs;
+        *div1 = calc_div1;
+
+        return clkin / (calc_divs * calc_div1);
+}
+
+/* freq_acceptable
+ *
+ * test wether a frequency is within the acceptable range of error
+*/
+
+static inline int freq_acceptable(unsigned int freq, unsigned int wanted)
+{
+        int diff = freq - wanted;
+
+        return (diff >= -2 && diff <= 2);
+}
+
+/* s3c24xx_i2c_getdivisor
+ *
+ * work out a divisor for the user requested frequency setting,
+ * either by the requested frequency, or scanning the acceptable
+ * range of frequencies until something is found
+*/
+
+static int s3c24xx_i2c_getdivisor(struct s3c24xx_i2c *i2c,
+                                  struct s3c2410_platform_i2c *pdata,
+                                  unsigned long *iicon,
+                                  unsigned int *got)
+{
+        unsigned long clkin = clk_get_rate(i2c->clk);
+        
+        unsigned int divs, div1;
+        int freq;
+        int start, end;
+
+        clkin /= 1000;          /* clkin now in KHz */
+     
+        dev_dbg(i2c->dev,  "pdata %p, freq %lu %lu..%lu\n",
+                 pdata, pdata->bus_freq, pdata->min_freq, pdata->max_freq);
+
+        if (pdata->bus_freq != 0) {
+                freq = s3c24xx_i2c_calcdivisor(clkin, pdata->bus_freq/1000,
+                                               &div1, &divs);
+                if (freq_acceptable(freq, pdata->bus_freq/1000))
+                        goto found;
+        }
+
+        /* ok, we may have to search for something suitable... */
+
+        start = (pdata->max_freq == 0) ? pdata->bus_freq : pdata->max_freq;
+        end = pdata->min_freq;
+
+        start /= 1000;
+        end /= 1000;
+
+        /* search loop... */
+
+        for (; start > end; start--) {
+                freq = s3c24xx_i2c_calcdivisor(clkin, start, &div1, &divs);
+                if (freq_acceptable(freq, start))
+                        goto found;
+        }
+
+        /* cannot find frequency spec */
+
+        return -EINVAL;
+
+ found:
+        *got = freq;
+        *iicon |= (divs-1);
+        *iicon |= (div1 == 512) ? S3C2410_IICCON_TXDIV_512 : 0;
+        return 0;
+}
+
+/* s3c24xx_i2c_init
+ *
+ * initialise the controller, set the IO lines and frequency 
+*/
+
+static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
+{
+        unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN;
+        struct s3c2410_platform_i2c *pdata;
+        unsigned int freq;
+
+        /* get the plafrom data */
+
+        pdata = s3c24xx_i2c_get_platformdata(i2c->adap.dev.parent);
+
+        /* inititalise the gpio */
+
+        s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA);
+        s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL);
+
+        /* write slave address */
+        
+        writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
+
+        dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
+
+        /* we need to work out the divisors for the clock... */
+
+        if (s3c24xx_i2c_getdivisor(i2c, pdata, &iicon, &freq) != 0) {
+                dev_err(i2c->dev, "cannot meet bus frequency required\n");
+                return -EINVAL;
+        }
+
+        /* todo - check that the i2c lines aren't being dragged anywhere */
+
+        dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
+        dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon);
+        
+        writel(iicon, i2c->regs + S3C2410_IICCON);
+
+        /* check for s3c2440 i2c controller  */
+
+        if (s3c24xx_i2c_is2440(i2c)) {
+                dev_dbg(i2c->dev, "S3C2440_IICLC=%08x\n", pdata->sda_delay);
+
+                writel(pdata->sda_delay, i2c->regs + S3C2440_IICLC);
+        }
+
+        return 0;
+}
+
+static void s3c24xx_i2c_free(struct s3c24xx_i2c *i2c)
+{
+        if (i2c->clk != NULL && !IS_ERR(i2c->clk)) {
+                clk_disable(i2c->clk);
+                clk_unuse(i2c->clk);
+                clk_put(i2c->clk);
+                i2c->clk = NULL;
+        }
+
+        if (i2c->regs != NULL) {
+                iounmap(i2c->regs);
+                i2c->regs = NULL;
+        }
+
+        if (i2c->ioarea != NULL) {
+                release_resource(i2c->ioarea);
+                kfree(i2c->ioarea);
+                i2c->ioarea = NULL;
+        }
+}
+
+/* s3c24xx_i2c_probe
+ *
+ * called by the bus driver when a suitable device is found
+*/
+
+static int s3c24xx_i2c_probe(struct device *dev)
+{
+        struct platform_device *pdev = to_platform_device(dev);
+        struct s3c24xx_i2c *i2c = &s3c24xx_i2c;
+        struct resource *res;
+        int ret;
+
+        /* find the clock and enable it */
+
+        i2c->dev = dev;
+        i2c->clk = clk_get(dev, "i2c");
+        if (IS_ERR(i2c->clk)) {
+                dev_err(dev, "cannot get clock\n");
+                ret = -ENOENT;
+                goto out;
+        }
+
+        dev_dbg(dev, "clock source %p\n", i2c->clk);
+
+        clk_use(i2c->clk);
+        clk_enable(i2c->clk);
+
+        /* map the registers */
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (res == NULL) {
+                dev_err(dev, "cannot find IO resource\n");
+                ret = -ENOENT;
+                goto out;
+        }
+
+        i2c->ioarea = request_mem_region(res->start, (res->end-res->start)+1,
+                                         pdev->name);
+
+        if (i2c->ioarea == NULL) {
+                dev_err(dev, "cannot request IO\n");
+                ret = -ENXIO;
+                goto out;
+        }
+
+        i2c->regs = ioremap(res->start, (res->end-res->start)+1);
+
+        if (i2c->regs == NULL) {
+                dev_err(dev, "cannot map IO\n");
+                ret = -ENXIO;
+                goto out;
+        }
+
+        dev_dbg(dev, "registers %p (%p, %p)\n", i2c->regs, i2c->ioarea, res);
+
+        /* setup info block for the i2c core */
+
+        i2c->adap.algo_data = i2c;
+        i2c->adap.dev.parent = dev;
+
+        /* initialise the i2c controller */
+
+        ret = s3c24xx_i2c_init(i2c);
+        if (ret != 0)
+                goto out;
+
+        /* find the IRQ for this unit (note, this relies on the init call to
+         * ensure no current IRQs pending 
+         */
+
+        res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+        if (res == NULL) {
+                dev_err(dev, "cannot find IRQ\n");
+                ret = -ENOENT;
+                goto out;
+        }
+
+        ret = request_irq(res->start, s3c24xx_i2c_irq, SA_INTERRUPT,
+                          pdev->name, i2c);
+
+        if (ret != 0) {
+                dev_err(dev, "cannot claim IRQ\n");
+                goto out;
+        }
+
+        i2c->irq = res;
+                
+        dev_dbg(dev, "irq resource %p (%ld)\n", res, res->start);
+
+        ret = i2c_add_adapter(&i2c->adap);
+        if (ret < 0) {
+                dev_err(dev, "failed to add bus to i2c core\n");
+                goto out;
+        }
+
+        dev_set_drvdata(dev, i2c);
+
+        dev_info(dev, "%s: S3C I2C adapter\n", i2c->adap.dev.bus_id);
+
+ out:
+        if (ret < 0)
+                s3c24xx_i2c_free(i2c);
+
+        return ret;
+}
+
+/* s3c24xx_i2c_remove
+ *
+ * called when device is removed from the bus
+*/
+
+static int s3c24xx_i2c_remove(struct device *dev)
+{
+        struct s3c24xx_i2c *i2c = dev_get_drvdata(dev);
+        
+        if (i2c != NULL) {
+                s3c24xx_i2c_free(i2c);
+                dev_set_drvdata(dev, NULL);
+        }
+
+        return 0;
+}
+
+#ifdef CONFIG_PM
+static int s3c24xx_i2c_resume(struct device *dev, u32 level)
+{
+        struct s3c24xx_i2c *i2c = dev_get_drvdata(dev);
+        
+        if (i2c != NULL && level == RESUME_ENABLE) {
+                dev_dbg(dev, "resume: level %d\n", level);
+                s3c24xx_i2c_init(i2c);
+        }
+
+        return 0;
+}
+
+#else
+#define s3c24xx_i2c_resume NULL
+#endif
+
+/* device driver for platform bus bits */
+
+static struct device_driver s3c2410_i2c_driver = {
+        .name           = "s3c2410-i2c",
+        .bus            = &platform_bus_type,
+        .probe          = s3c24xx_i2c_probe,
+        .remove         = s3c24xx_i2c_remove,
+        .resume         = s3c24xx_i2c_resume,
+};
+
+static struct device_driver s3c2440_i2c_driver = {
+        .name           = "s3c2440-i2c",
+        .bus            = &platform_bus_type,
+        .probe          = s3c24xx_i2c_probe,
+        .remove         = s3c24xx_i2c_remove,
+        .resume         = s3c24xx_i2c_resume,
+};
+
+static int __init i2c_adap_s3c_init(void)
+{
+        int ret;
+
+        ret = driver_register(&s3c2410_i2c_driver);
+        if (ret == 0)
+                ret = driver_register(&s3c2440_i2c_driver); 
+
+        return ret;
+}
+
+static void __exit i2c_adap_s3c_exit(void)
+{
+        driver_unregister(&s3c2410_i2c_driver);
+        driver_unregister(&s3c2440_i2c_driver);
+}
+
+module_init(i2c_adap_s3c_init);
+module_exit(i2c_adap_s3c_exit);
+
+MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
+MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/i2c/busses/i2c-savage4.c b/drivers/i2c/busses/i2c-savage4.c
new file mode 100644
index 000000000000..092d0323c6c6
--- /dev/null
+++ b/drivers/i2c/busses/i2c-savage4.c
@@ -0,0 +1,205 @@
+/*
+    i2c-savage4.c - Part of lm_sensors, Linux kernel modules for hardware
+              monitoring
+    Copyright (C) 1998-2003  The LM Sensors Team
+    Alexander Wold <awold@bigfoot.com>
+    Mark D. Studebaker <mdsxyz123@yahoo.com>
+    
+    Based on i2c-voodoo3.c.
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+/* This interfaces to the I2C bus of the Savage4 to gain access to
+   the BT869 and possibly other I2C devices. The DDC bus is not
+   yet supported because its register is not memory-mapped.
+   However we leave the DDC code here, commented out, to make
+   it easier to add later.
+*/
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/i2c.h>
+#include <linux/i2c-algo-bit.h>
+#include <asm/io.h>
+
+/* 3DFX defines */
+#define PCI_CHIP_SAVAGE3D       0x8A20
+#define PCI_CHIP_SAVAGE3D_MV    0x8A21
+#define PCI_CHIP_SAVAGE4        0x8A22
+#define PCI_CHIP_SAVAGE2000     0x9102
+#define PCI_CHIP_PROSAVAGE_PM   0x8A25
+#define PCI_CHIP_PROSAVAGE_KM   0x8A26
+#define PCI_CHIP_SAVAGE_MX_MV   0x8c10
+#define PCI_CHIP_SAVAGE_MX      0x8c11
+#define PCI_CHIP_SAVAGE_IX_MV   0x8c12
+#define PCI_CHIP_SAVAGE_IX      0x8c13
+
+#define REG                     0xff20  /* Serial Port 1 Register */
+
+/* bit locations in the register */
+#define DDC_ENAB                0x00040000
+#define DDC_SCL_OUT             0x00080000
+#define DDC_SDA_OUT             0x00100000
+#define DDC_SCL_IN              0x00200000
+#define DDC_SDA_IN              0x00400000
+#define I2C_ENAB                0x00000020
+#define I2C_SCL_OUT             0x00000001
+#define I2C_SDA_OUT             0x00000002
+#define I2C_SCL_IN              0x00000008
+#define I2C_SDA_IN              0x00000010
+
+/* initialization states */
+#define INIT2                   0x20
+#define INIT3                   0x04
+
+/* delays */
+#define CYCLE_DELAY             10
+#define TIMEOUT                 (HZ / 2)
+
+
+static void __iomem *ioaddr;
+
+/* The sav GPIO registers don't have individual masks for each bit
+   so we always have to read before writing. */
+
+static void bit_savi2c_setscl(void *data, int val)
+{
+        unsigned int r;
+        r = readl(ioaddr + REG);
+        if(val)
+                r |= I2C_SCL_OUT;
+        else
+                r &= ~I2C_SCL_OUT;
+        writel(r, ioaddr + REG);
+        readl(ioaddr + REG);    /* flush posted write */
+}
+
+static void bit_savi2c_setsda(void *data, int val)
+{
+        unsigned int r;
+        r = readl(ioaddr + REG);
+        if(val)
+                r |= I2C_SDA_OUT;
+        else
+                r &= ~I2C_SDA_OUT;
+        writel(r, ioaddr + REG);
+        readl(ioaddr + REG);    /* flush posted write */
+}
+
+/* The GPIO pins are open drain, so the pins always remain outputs.
+   We rely on the i2c-algo-bit routines to set the pins high before
+   reading the input from other chips. */
+
+static int bit_savi2c_getscl(void *data)
+{
+        return (0 != (readl(ioaddr + REG) & I2C_SCL_IN));
+}
+
+static int bit_savi2c_getsda(void *data)
+{
+        return (0 != (readl(ioaddr + REG) & I2C_SDA_IN));
+}
+
+/* Configures the chip */
+
+static int config_s4(struct pci_dev *dev)
+{
+        unsigned long cadr;
+
+        /* map memory */
+        cadr = dev->resource[0].start;
+        cadr &= PCI_BASE_ADDRESS_MEM_MASK;
+        ioaddr = ioremap_nocache(cadr, 0x0080000);
+        if (ioaddr) {
+                /* writel(0x8160, ioaddr + REG2); */
+                writel(0x00000020, ioaddr + REG);
+                dev_info(&dev->dev, "Using Savage4 at %p\n", ioaddr);
+                return 0;
+        }
+        return -ENODEV;
+}
+
+static struct i2c_algo_bit_data sav_i2c_bit_data = {
+        .setsda         = bit_savi2c_setsda,
+        .setscl         = bit_savi2c_setscl,
+        .getsda         = bit_savi2c_getsda,
+        .getscl         = bit_savi2c_getscl,
+        .udelay         = CYCLE_DELAY,
+        .mdelay         = CYCLE_DELAY,
+        .timeout        = TIMEOUT
+};
+
+static struct i2c_adapter savage4_i2c_adapter = {
+        .owner          = THIS_MODULE,
+        .name           = "I2C Savage4 adapter",
+        .algo_data      = &sav_i2c_bit_data,
+};
+
+static struct pci_device_id savage4_ids[] __devinitdata = {
+        { PCI_DEVICE(PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE4) },
+        { PCI_DEVICE(PCI_VENDOR_ID_S3, PCI_CHIP_SAVAGE2000) },
+        { 0, }
+};
+
+MODULE_DEVICE_TABLE (pci, savage4_ids);
+
+static int __devinit savage4_probe(struct pci_dev *dev, const struct pci_device_id *id)
+{
+        int retval;
+
+        retval = config_s4(dev);
+        if (retval)
+                return retval;
+
+        /* set up the sysfs linkage to our parent device */
+        savage4_i2c_adapter.dev.parent = &dev->dev;
+
+        return i2c_bit_add_bus(&savage4_i2c_adapter);
+}
+
+static void __devexit savage4_remove(struct pci_dev *dev)
+{
+        i2c_bit_del_bus(&savage4_i2c_adapter);
+        iounmap(ioaddr);
+}
+
+static struct pci_driver savage4_driver = {
+        .name           = "savage4_smbus",
+        .id_table       = savage4_ids,
+        .probe          = savage4_probe,
+        .remove         = __devexit_p(savage4_remove),
+};
+
+static int __init i2c_savage4_init(void)
+{
+        return pci_register_driver(&savage4_driver);
+}
+
+static void __exit i2c_savage4_exit(void)
+{
+        pci_unregister_driver(&savage4_driver);
+}
+
+MODULE_AUTHOR("Alexander Wold <awold@bigfoot.com> "
+                "and Mark D. Studebaker <mdsxyz123@yahoo.com>");
+MODULE_DESCRIPTION("Savage4 I2C/SMBus driver");
+MODULE_LICENSE("GPL");
+
+module_init(i2c_savage4_init);
+module_exit(i2c_savage4_exit);
diff --git a/drivers/i2c/busses/i2c-sibyte.c b/drivers/i2c/busses/i2c-sibyte.c
new file mode 100644
index 000000000000..e5dd90bdb04a
--- /dev/null
+++ b/drivers/i2c/busses/i2c-sibyte.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2004 Steven J. Hill
+ * Copyright (C) 2001,2002,2003 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/i2c-algo-sibyte.h>
+#include <asm/sibyte/sb1250_regs.h>
+#include <asm/sibyte/sb1250_smbus.h>
+
+static struct i2c_algo_sibyte_data sibyte_board_data[2] = {
+        { NULL, 0, (void *) (KSEG1+A_SMB_BASE(0)) },
+        { NULL, 1, (void *) (KSEG1+A_SMB_BASE(1)) }
+};
+
+static struct i2c_adapter sibyte_board_adapter[2] = {
+        {
+                .owner          = THIS_MODULE,
+                .id             = I2C_HW_SIBYTE,
+                .class          = I2C_CLASS_HWMON,
+                .algo           = NULL,
+                .algo_data      = &sibyte_board_data[0],
+                .name           = "SiByte SMBus 0",
+        },
+        {
+                .owner          = THIS_MODULE,
+                .id             = I2C_HW_SIBYTE,
+                .class          = I2C_CLASS_HWMON,
+                .algo           = NULL,
+                .algo_data      = &sibyte_board_data[1],
+                .name           = "SiByte SMBus 1",
+        },
+};
+
+static int __init i2c_sibyte_init(void)
+{
+        printk("i2c-swarm.o: i2c SMBus adapter module for SiByte board\n");
+        if (i2c_sibyte_add_bus(&sibyte_board_adapter[0], K_SMB_FREQ_100KHZ) < 0)
+                return -ENODEV;
+        if (i2c_sibyte_add_bus(&sibyte_board_adapter[1], K_SMB_FREQ_400KHZ) < 0)
+                return -ENODEV;
+        return 0;
+}
+
+static void __exit i2c_sibyte_exit(void)
+{
+        i2c_sibyte_del_bus(&sibyte_board_adapter[0]);
+        i2c_sibyte_del_bus(&sibyte_board_adapter[1]);
+}
+
+module_init(i2c_sibyte_init);
+module_exit(i2c_sibyte_exit);
+
+MODULE_AUTHOR("Kip Walker <kwalker@broadcom.com>, Steven J. Hill <sjhill@realitydiluted.com>");
+MODULE_DESCRIPTION("SMBus adapter routines for SiByte boards");
+MODULE_LICENSE("GPL");
diff --git a/drivers/i2c/busses/i2c-sis5595.c b/drivers/i2c/busses/i2c-sis5595.c
new file mode 100644
index 000000000000..425733b019b6
--- /dev/null
+++ b/drivers/i2c/busses/i2c-sis5595.c
@@ -0,0 +1,424 @@
+/*
+    sis5595.c - Part of lm_sensors, Linux kernel modules for hardware
+              monitoring
+    Copyright (c) 1998, 1999  Frodo Looijaard <frodol@dds.nl> and
+    Philip Edelbrock <phil@netroedge.com>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+/* Note: we assume there can only be one SIS5595 with one SMBus interface */
+
+/*
+   Note: all have mfr. ID 0x1039.
+   SUPPORTED            PCI ID          
+        5595            0008
+
+   Note: these chips contain a 0008 device which is incompatible with the
+         5595. We recognize these by the presence of the listed
+         "blacklist" PCI ID and refuse to load.
+
+   NOT SUPPORTED        PCI ID          BLACKLIST PCI ID        
+         540            0008            0540
+         550            0008            0550
+        5513            0008            5511
+        5581            0008            5597
+        5582            0008            5597
+        5597            0008            5597
+        5598            0008            5597/5598
+         630            0008            0630
+         645            0008            0645
+         646            0008            0646
+         648            0008            0648
+         650            0008            0650
+         651            0008            0651
+         730            0008            0730
+         735            0008            0735
+         745            0008            0745
+         746            0008            0746
+*/
+
+/* TO DO: 
+ * Add Block Transfers (ugly, but supported by the adapter)
+ * Add adapter resets
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <linux/ioport.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+#include <asm/io.h>
+
+static int blacklist[] = {
+        PCI_DEVICE_ID_SI_540,
+        PCI_DEVICE_ID_SI_550,
+        PCI_DEVICE_ID_SI_630,
+        PCI_DEVICE_ID_SI_645,
+        PCI_DEVICE_ID_SI_646,
+        PCI_DEVICE_ID_SI_648,
+        PCI_DEVICE_ID_SI_650,
+        PCI_DEVICE_ID_SI_651,
+        PCI_DEVICE_ID_SI_730,
+        PCI_DEVICE_ID_SI_735,
+        PCI_DEVICE_ID_SI_745,
+        PCI_DEVICE_ID_SI_746,
+        PCI_DEVICE_ID_SI_5511,  /* 5513 chip has the 0008 device but that ID
+                                   shows up in other chips so we use the 5511
+                                   ID for recognition */
+        PCI_DEVICE_ID_SI_5597,
+        PCI_DEVICE_ID_SI_5598,
+        0,                      /* terminates the list */
+};
+
+/* Length of ISA address segment */
+#define SIS5595_EXTENT          8
+/* SIS5595 SMBus registers */
+#define SMB_STS_LO              0x00
+#define SMB_STS_HI              0x01
+#define SMB_CTL_LO              0x02
+#define SMB_CTL_HI              0x03
+#define SMB_ADDR                0x04
+#define SMB_CMD                 0x05
+#define SMB_PCNT                0x06
+#define SMB_CNT                 0x07
+#define SMB_BYTE                0x08
+#define SMB_DEV                 0x10
+#define SMB_DB0                 0x11
+#define SMB_DB1                 0x12
+#define SMB_HAA                 0x13
+
+/* PCI Address Constants */
+#define SMB_INDEX               0x38
+#define SMB_DAT                 0x39
+#define SIS5595_ENABLE_REG      0x40
+#define ACPI_BASE               0x90
+
+/* Other settings */
+#define MAX_TIMEOUT             500
+
+/* SIS5595 constants */
+#define SIS5595_QUICK           0x00
+#define SIS5595_BYTE            0x02
+#define SIS5595_BYTE_DATA       0x04
+#define SIS5595_WORD_DATA       0x06
+#define SIS5595_PROC_CALL       0x08
+#define SIS5595_BLOCK_DATA      0x0A
+
+/* insmod parameters */
+
+/* If force_addr is set to anything different from 0, we forcibly enable
+   the device at the given address. */
+static u16 force_addr = 0;
+module_param(force_addr, ushort, 0);
+MODULE_PARM_DESC(force_addr, "Initialize the base address of the i2c controller");
+
+static unsigned short sis5595_base = 0;
+
+static u8 sis5595_read(u8 reg)
+{
+        outb(reg, sis5595_base + SMB_INDEX);
+        return inb(sis5595_base + SMB_DAT);
+}
+
+static void sis5595_write(u8 reg, u8 data)
+{
+        outb(reg, sis5595_base + SMB_INDEX);
+        outb(data, sis5595_base + SMB_DAT);
+}
+
+static int sis5595_setup(struct pci_dev *SIS5595_dev)
+{
+        u16 a;
+        u8 val;
+        int *i;
+        int retval = -ENODEV;
+
+        /* Look for imposters */
+        for (i = blacklist; *i != 0; i++) {
+                struct pci_dev *dev;
+                dev = pci_get_device(PCI_VENDOR_ID_SI, *i, NULL);
+                if (dev) {
+                        dev_err(&SIS5595_dev->dev, "Looked for SIS5595 but found unsupported device %.4x\n", *i);
+                        pci_dev_put(dev);
+                        return -ENODEV;
+                }
+        }
+
+        /* Determine the address of the SMBus areas */
+        pci_read_config_word(SIS5595_dev, ACPI_BASE, &sis5595_base);
+        if (sis5595_base == 0 && force_addr == 0) {
+                dev_err(&SIS5595_dev->dev, "ACPI base address uninitialized - upgrade BIOS or use force_addr=0xaddr\n");
+                return -ENODEV;
+        }
+
+        if (force_addr)
+                sis5595_base = force_addr & ~(SIS5595_EXTENT - 1);
+        dev_dbg(&SIS5595_dev->dev, "ACPI Base address: %04x\n", sis5595_base);
+
+        /* NB: We grab just the two SMBus registers here, but this may still
+         * interfere with ACPI :-(  */
+        if (!request_region(sis5595_base + SMB_INDEX, 2, "sis5595-smbus")) {
+                dev_err(&SIS5595_dev->dev, "SMBus registers 0x%04x-0x%04x already in use!\n",
+                        sis5595_base + SMB_INDEX, sis5595_base + SMB_INDEX + 1);
+                return -ENODEV;
+        }
+
+        if (force_addr) {
+                dev_info(&SIS5595_dev->dev, "forcing ISA address 0x%04X\n", sis5595_base);
+                if (pci_write_config_word(SIS5595_dev, ACPI_BASE, sis5595_base)
+                    != PCIBIOS_SUCCESSFUL)
+                        goto error;
+                if (pci_read_config_word(SIS5595_dev, ACPI_BASE, &a)
+                    != PCIBIOS_SUCCESSFUL)
+                        goto error;
+                if ((a & ~(SIS5595_EXTENT - 1)) != sis5595_base) {
+                        /* doesn't work for some chips! */
+                        dev_err(&SIS5595_dev->dev, "force address failed - not supported?\n");
+                        goto error;
+                }
+        }
+
+        if (pci_read_config_byte(SIS5595_dev, SIS5595_ENABLE_REG, &val)
+            != PCIBIOS_SUCCESSFUL)
+                goto error;
+        if ((val & 0x80) == 0) {
+                dev_info(&SIS5595_dev->dev, "enabling ACPI\n");
+                if (pci_write_config_byte(SIS5595_dev, SIS5595_ENABLE_REG, val | 0x80)
+                    != PCIBIOS_SUCCESSFUL)
+                        goto error;
+                if (pci_read_config_byte(SIS5595_dev, SIS5595_ENABLE_REG, &val)
+                    != PCIBIOS_SUCCESSFUL)
+                        goto error;
+                if ((val & 0x80) == 0) {
+                        /* doesn't work for some chips? */
+                        dev_err(&SIS5595_dev->dev, "ACPI enable failed - not supported?\n");
+                        goto error;
+                }
+        }
+
+        /* Everything is happy */
+        return 0;
+
+error:
+        release_region(sis5595_base + SMB_INDEX, 2);
+        return retval;
+}
+
+static int sis5595_transaction(struct i2c_adapter *adap)
+{
+        int temp;
+        int result = 0;
+        int timeout = 0;
+
+        /* Make sure the SMBus host is ready to start transmitting */
+        temp = sis5595_read(SMB_STS_LO) + (sis5595_read(SMB_STS_HI) << 8);
+        if (temp != 0x00) {
+                dev_dbg(&adap->dev, "SMBus busy (%04x). Resetting... \n", temp);
+                sis5595_write(SMB_STS_LO, temp & 0xff);
+                sis5595_write(SMB_STS_HI, temp >> 8);
+                if ((temp = sis5595_read(SMB_STS_LO) + (sis5595_read(SMB_STS_HI) << 8)) != 0x00) {
+                        dev_dbg(&adap->dev, "Failed! (%02x)\n", temp);
+                        return -1;
+                } else {
+                        dev_dbg(&adap->dev, "Successfull!\n");
+                }
+        }
+
+        /* start the transaction by setting bit 4 */
+        sis5595_write(SMB_CTL_LO, sis5595_read(SMB_CTL_LO) | 0x10);
+
+        /* We will always wait for a fraction of a second! */
+        do {
+                msleep(1);
+                temp = sis5595_read(SMB_STS_LO);
+        } while (!(temp & 0x40) && (timeout++ < MAX_TIMEOUT));
+
+        /* If the SMBus is still busy, we give up */
+        if (timeout >= MAX_TIMEOUT) {
+                dev_dbg(&adap->dev, "SMBus Timeout!\n");
+                result = -1;
+        }
+
+        if (temp & 0x10) {
+                dev_dbg(&adap->dev, "Error: Failed bus transaction\n");
+                result = -1;
+        }
+
+        if (temp & 0x20) {
+                dev_err(&adap->dev, "Bus collision! SMBus may be locked until "
+                        "next hard reset (or not...)\n");
+                /* Clock stops and slave is stuck in mid-transmission */
+                result = -1;
+        }
+
+        temp = sis5595_read(SMB_STS_LO) + (sis5595_read(SMB_STS_HI) << 8);
+        if (temp != 0x00) {
+                sis5595_write(SMB_STS_LO, temp & 0xff);
+                sis5595_write(SMB_STS_HI, temp >> 8);
+        }
+
+        temp = sis5595_read(SMB_STS_LO) + (sis5595_read(SMB_STS_HI) << 8);
+        if (temp != 0x00)
+                dev_dbg(&adap->dev, "Failed reset at end of transaction (%02x)\n", temp);
+
+        return result;
+}
+
+/* Return -1 on error. */
+static s32 sis5595_access(struct i2c_adapter *adap, u16 addr,
+                          unsigned short flags, char read_write,
+                          u8 command, int size, union i2c_smbus_data *data)
+{
+        switch (size) {
+        case I2C_SMBUS_QUICK:
+                sis5595_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01));
+                size = SIS5595_QUICK;
+                break;
+        case I2C_SMBUS_BYTE:
+                sis5595_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01));
+                if (read_write == I2C_SMBUS_WRITE)
+                        sis5595_write(SMB_CMD, command);
+                size = SIS5595_BYTE;
+                break;
+        case I2C_SMBUS_BYTE_DATA:
+                sis5595_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01));
+                sis5595_write(SMB_CMD, command);
+                if (read_write == I2C_SMBUS_WRITE)
+                        sis5595_write(SMB_BYTE, data->byte);
+                size = SIS5595_BYTE_DATA;
+                break;
+        case I2C_SMBUS_PROC_CALL:
+        case I2C_SMBUS_WORD_DATA:
+                sis5595_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01));
+                sis5595_write(SMB_CMD, command);
+                if (read_write == I2C_SMBUS_WRITE) {
+                        sis5595_write(SMB_BYTE, data->word & 0xff);
+                        sis5595_write(SMB_BYTE + 1,
+                                      (data->word & 0xff00) >> 8);
+                }
+                size = (size == I2C_SMBUS_PROC_CALL) ? SIS5595_PROC_CALL : SIS5595_WORD_DATA;
+                break;
+/*
+        case I2C_SMBUS_BLOCK_DATA:
+                printk(KERN_WARNING "sis5595.o: Block data not yet implemented!\n");
+                return -1;
+                break;
+*/
+        default:
+                printk(KERN_WARNING "sis5595.o: Unsupported transaction %d\n", size);
+                return -1;
+        }
+
+        sis5595_write(SMB_CTL_LO, ((size & 0x0E)));
+
+        if (sis5595_transaction(adap))
+                return -1;
+
+        if ((size != SIS5595_PROC_CALL) &&
+            ((read_write == I2C_SMBUS_WRITE) || (size == SIS5595_QUICK)))
+                return 0;
+
+
+        switch (size) {
+        case SIS5595_BYTE:      /* Where is the result put? I assume here it is in
+                                   SMB_DATA but it might just as well be in the
+                                   SMB_CMD. No clue in the docs */
+        case SIS5595_BYTE_DATA:
+                data->byte = sis5595_read(SMB_BYTE);
+                break;
+        case SIS5595_WORD_DATA:
+        case SIS5595_PROC_CALL:
+                data->word = sis5595_read(SMB_BYTE) + (sis5595_read(SMB_BYTE + 1) << 8);
+                break;
+        }
+        return 0;
+}
+
+static u32 sis5595_func(struct i2c_adapter *adapter)
+{
+        return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
+            I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
+            I2C_FUNC_SMBUS_PROC_CALL;
+}
+
+static struct i2c_algorithm smbus_algorithm = {
+        .name           = "Non-I2C SMBus adapter",
+        .id             = I2C_ALGO_SMBUS,
+        .smbus_xfer     = sis5595_access,
+        .functionality  = sis5595_func,
+};
+
+static struct i2c_adapter sis5595_adapter = {
+        .owner          = THIS_MODULE,
+        .class          = I2C_CLASS_HWMON,
+        .name           = "unset",
+        .algo           = &smbus_algorithm,
+};
+
+static struct pci_device_id sis5595_ids[] __devinitdata = {
+        { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503) }, 
+        { 0, }
+};
+
+MODULE_DEVICE_TABLE (pci, sis5595_ids);
+
+static int __devinit sis5595_probe(struct pci_dev *dev, const struct pci_device_id *id)
+{
+        if (sis5595_setup(dev)) {
+                dev_err(&dev->dev, "SIS5595 not detected, module not inserted.\n");
+                return -ENODEV;
+        }
+
+        /* set up the driverfs linkage to our parent device */
+        sis5595_adapter.dev.parent = &dev->dev;
+
+        sprintf(sis5595_adapter.name, "SMBus SIS5595 adapter at %04x",
+                sis5595_base + SMB_INDEX);
+        return i2c_add_adapter(&sis5595_adapter);
+}
+
+static void __devexit sis5595_remove(struct pci_dev *dev)
+{
+        i2c_del_adapter(&sis5595_adapter);
+        release_region(sis5595_base + SMB_INDEX, 2);
+}
+
+static struct pci_driver sis5595_driver = {
+        .name           = "sis5595_smbus",
+        .id_table       = sis5595_ids,
+        .probe          = sis5595_probe,
+        .remove         = __devexit_p(sis5595_remove),
+};
+
+static int __init i2c_sis5595_init(void)
+{
+        return pci_register_driver(&sis5595_driver);
+}
+
+static void __exit i2c_sis5595_exit(void)
+{
+        pci_unregister_driver(&sis5595_driver);
+}
+
+MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl>");
+MODULE_DESCRIPTION("SIS5595 SMBus driver");
+MODULE_LICENSE("GPL");
+
+module_init(i2c_sis5595_init);
+module_exit(i2c_sis5595_exit);
diff --git a/drivers/i2c/busses/i2c-sis630.c b/drivers/i2c/busses/i2c-sis630.c
new file mode 100644
index 000000000000..58df63df1540
--- /dev/null
+++ b/drivers/i2c/busses/i2c-sis630.c
@@ -0,0 +1,523 @@
+/*
+    i2c-sis630.c - Part of lm_sensors, Linux kernel modules for hardware
+              monitoring
+
+    Copyright (c) 2002,2003 Alexander Malysh <amalysh@web.de>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+/*
+   Changes:
+   24.08.2002
+        Fixed the typo in sis630_access (Thanks to Mark M. Hoffman)
+        Changed sis630_transaction.(Thanks to Mark M. Hoffman)
+   18.09.2002
+        Added SIS730 as supported.
+   21.09.2002
+        Added high_clock module option.If this option is set
+        used Host Master Clock 56KHz (default 14KHz).For now we save old Host
+        Master Clock and after transaction completed restore (otherwise
+        it's confuse BIOS and hung Machine).
+   24.09.2002
+        Fixed typo in sis630_access
+        Fixed logical error by restoring of Host Master Clock
+   31.07.2003
+        Added block data read/write support.
+*/
+
+/*
+   Status: beta
+
+   Supports:
+        SIS 630
+        SIS 730
+
+   Note: we assume there can only be one device, with one SMBus interface.
+*/
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <linux/ioport.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+#include <asm/io.h>
+
+/* SIS630 SMBus registers */
+#define SMB_STS                 0x80    /* status */
+#define SMB_EN                  0x81    /* status enable */
+#define SMB_CNT                 0x82
+#define SMBHOST_CNT             0x83
+#define SMB_ADDR                0x84
+#define SMB_CMD                 0x85
+#define SMB_PCOUNT              0x86    /* processed count */
+#define SMB_COUNT               0x87
+#define SMB_BYTE                0x88    /* ~0x8F data byte field */
+#define SMBDEV_ADDR             0x90
+#define SMB_DB0                 0x91
+#define SMB_DB1                 0x92
+#define SMB_SAA                 0x93
+
+/* register count for request_region */
+#define SIS630_SMB_IOREGION     20
+
+/* PCI address constants */
+/* acpi base address register  */
+#define SIS630_ACPI_BASE_REG    0x74
+/* bios control register */
+#define SIS630_BIOS_CTL_REG     0x40
+
+/* Other settings */
+#define MAX_TIMEOUT             500
+
+/* SIS630 constants */
+#define SIS630_QUICK            0x00
+#define SIS630_BYTE             0x01
+#define SIS630_BYTE_DATA        0x02
+#define SIS630_WORD_DATA        0x03
+#define SIS630_PCALL            0x04
+#define SIS630_BLOCK_DATA       0x05
+
+/* insmod parameters */
+static int high_clock;
+static int force;
+module_param(high_clock, bool, 0);
+MODULE_PARM_DESC(high_clock, "Set Host Master Clock to 56KHz (default 14KHz).");
+module_param(force, bool, 0);
+MODULE_PARM_DESC(force, "Forcibly enable the SIS630. DANGEROUS!");
+
+/* acpi base address */
+static unsigned short acpi_base = 0;
+
+/* supported chips */
+static int supported[] = {
+        PCI_DEVICE_ID_SI_630,
+        PCI_DEVICE_ID_SI_730,
+        0 /* terminates the list */
+};
+
+static inline u8 sis630_read(u8 reg)
+{
+        return inb(acpi_base + reg);
+}
+
+static inline void sis630_write(u8 reg, u8 data)
+{
+        outb(data, acpi_base + reg);
+}
+
+static int sis630_transaction_start(struct i2c_adapter *adap, int size, u8 *oldclock)
+{
+        int temp;
+
+        /* Make sure the SMBus host is ready to start transmitting. */
+        if ((temp = sis630_read(SMB_CNT) & 0x03) != 0x00) {
+                dev_dbg(&adap->dev, "SMBus busy (%02x).Resetting...\n",temp);
+                /* kill smbus transaction */
+                sis630_write(SMBHOST_CNT, 0x20);
+
+                if ((temp = sis630_read(SMB_CNT) & 0x03) != 0x00) {
+                        dev_dbg(&adap->dev, "Failed! (%02x)\n", temp);
+                        return -1;
+                } else {
+                        dev_dbg(&adap->dev, "Successfull!\n");
+                }
+        }
+
+        /* save old clock, so we can prevent machine for hung */
+        *oldclock = sis630_read(SMB_CNT);
+
+        dev_dbg(&adap->dev, "saved clock 0x%02x\n", *oldclock);
+
+        /* disable timeout interrupt , set Host Master Clock to 56KHz if requested */
+        if (high_clock)
+                sis630_write(SMB_CNT, 0x20);
+        else
+                sis630_write(SMB_CNT, (*oldclock & ~0x40));
+
+        /* clear all sticky bits */
+        temp = sis630_read(SMB_STS);
+        sis630_write(SMB_STS, temp & 0x1e);
+
+        /* start the transaction by setting bit 4 and size */
+        sis630_write(SMBHOST_CNT,0x10 | (size & 0x07));
+
+        return 0;
+}
+
+static int sis630_transaction_wait(struct i2c_adapter *adap, int size)
+{
+        int temp, result = 0, timeout = 0;
+
+        /* We will always wait for a fraction of a second! */
+        do {
+                msleep(1);
+                temp = sis630_read(SMB_STS);
+                /* check if block transmitted */
+                if (size == SIS630_BLOCK_DATA && (temp & 0x10))
+                        break;
+        } while (!(temp & 0x0e) && (timeout++ < MAX_TIMEOUT));
+
+        /* If the SMBus is still busy, we give up */
+        if (timeout >= MAX_TIMEOUT) {
+                dev_dbg(&adap->dev, "SMBus Timeout!\n");
+                result = -1;
+        }
+
+        if (temp & 0x02) {
+                dev_dbg(&adap->dev, "Error: Failed bus transaction\n");
+                result = -1;
+        }
+
+        if (temp & 0x04) {
+                dev_err(&adap->dev, "Bus collision!\n");
+                result = -1;
+                /*
+                  TBD: Datasheet say:
+                  the software should clear this bit and restart SMBUS operation.
+                  Should we do it or user start request again?
+                */
+        }
+
+        return result;
+}
+
+static void sis630_transaction_end(struct i2c_adapter *adap, u8 oldclock)
+{
+        int temp = 0;
+
+        /* clear all status "sticky" bits */
+        sis630_write(SMB_STS, temp);
+
+        dev_dbg(&adap->dev, "SMB_CNT before clock restore 0x%02x\n", sis630_read(SMB_CNT));
+
+        /*
+         * restore old Host Master Clock if high_clock is set
+         * and oldclock was not 56KHz
+         */
+        if (high_clock && !(oldclock & 0x20))
+                sis630_write(SMB_CNT,(sis630_read(SMB_CNT) & ~0x20));
+
+        dev_dbg(&adap->dev, "SMB_CNT after clock restore 0x%02x\n", sis630_read(SMB_CNT));
+}
+
+static int sis630_transaction(struct i2c_adapter *adap, int size)
+{
+        int result = 0;
+        u8 oldclock = 0;
+
+        result = sis630_transaction_start(adap, size, &oldclock);
+        if (!result) {
+                result = sis630_transaction_wait(adap, size);
+                sis630_transaction_end(adap, oldclock);
+        }
+
+        return result;
+}
+
+static int sis630_block_data(struct i2c_adapter *adap, union i2c_smbus_data *data, int read_write)
+{
+        int i, len = 0, rc = 0;
+        u8 oldclock = 0;
+
+        if (read_write == I2C_SMBUS_WRITE) {
+                len = data->block[0];
+                if (len < 0)
+                        len = 0;
+                else if (len > 32)
+                        len = 32;
+                sis630_write(SMB_COUNT, len);
+                for (i=1; i <= len; i++) {
+                        dev_dbg(&adap->dev, "set data 0x%02x\n", data->block[i]);
+                        /* set data */
+                        sis630_write(SMB_BYTE+(i-1)%8, data->block[i]);
+                        if (i==8 || (len<8 && i==len)) {
+                                dev_dbg(&adap->dev, "start trans len=%d i=%d\n",len ,i);
+                                /* first transaction */
+                                if (sis630_transaction_start(adap, SIS630_BLOCK_DATA, &oldclock))
+                                        return -1;
+                        }
+                        else if ((i-1)%8 == 7 || i==len) {
+                                dev_dbg(&adap->dev, "trans_wait len=%d i=%d\n",len,i);
+                                if (i>8) {
+                                        dev_dbg(&adap->dev, "clear smbary_sts len=%d i=%d\n",len,i);
+                                        /*
+                                           If this is not first transaction,
+                                           we must clear sticky bit.
+                                           clear SMBARY_STS
+                                        */
+                                        sis630_write(SMB_STS,0x10);
+                                }
+                                if (sis630_transaction_wait(adap, SIS630_BLOCK_DATA)) {
+                                        dev_dbg(&adap->dev, "trans_wait failed\n");
+                                        rc = -1;
+                                        break;
+                                }
+                        }
+                }
+        }
+        else {
+                /* read request */
+                data->block[0] = len = 0;
+                if (sis630_transaction_start(adap, SIS630_BLOCK_DATA, &oldclock)) {
+                        return -1;
+                }
+                do {
+                        if (sis630_transaction_wait(adap, SIS630_BLOCK_DATA)) {
+                                dev_dbg(&adap->dev, "trans_wait failed\n");
+                                rc = -1;
+                                break;
+                        }
+                        /* if this first transaction then read byte count */
+                        if (len == 0)
+                                data->block[0] = sis630_read(SMB_COUNT);
+
+                        /* just to be sure */
+                        if (data->block[0] > 32)
+                                data->block[0] = 32;
+
+                        dev_dbg(&adap->dev, "block data read len=0x%x\n", data->block[0]);
+
+                        for (i=0; i < 8 && len < data->block[0]; i++,len++) {
+                                dev_dbg(&adap->dev, "read i=%d len=%d\n", i, len);
+                                data->block[len+1] = sis630_read(SMB_BYTE+i);
+                        }
+
+                        dev_dbg(&adap->dev, "clear smbary_sts len=%d i=%d\n",len,i);
+
+                        /* clear SMBARY_STS */
+                        sis630_write(SMB_STS,0x10);
+                } while(len < data->block[0]);
+        }
+
+        sis630_transaction_end(adap, oldclock);
+
+        return rc;
+}
+
+/* Return -1 on error. */
+static s32 sis630_access(struct i2c_adapter *adap, u16 addr,
+                         unsigned short flags, char read_write,
+                         u8 command, int size, union i2c_smbus_data *data)
+{
+        switch (size) {
+                case I2C_SMBUS_QUICK:
+                        sis630_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01));
+                        size = SIS630_QUICK;
+                        break;
+                case I2C_SMBUS_BYTE:
+                        sis630_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01));
+                        if (read_write == I2C_SMBUS_WRITE)
+                                sis630_write(SMB_CMD, command);
+                        size = SIS630_BYTE;
+                        break;
+                case I2C_SMBUS_BYTE_DATA:
+                        sis630_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01));
+                        sis630_write(SMB_CMD, command);
+                        if (read_write == I2C_SMBUS_WRITE)
+                                sis630_write(SMB_BYTE, data->byte);
+                        size = SIS630_BYTE_DATA;
+                        break;
+                case I2C_SMBUS_PROC_CALL:
+                case I2C_SMBUS_WORD_DATA:
+                        sis630_write(SMB_ADDR,((addr & 0x7f) << 1) | (read_write & 0x01));
+                        sis630_write(SMB_CMD, command);
+                        if (read_write == I2C_SMBUS_WRITE) {
+                                sis630_write(SMB_BYTE, data->word & 0xff);
+                                sis630_write(SMB_BYTE + 1,(data->word & 0xff00) >> 8);
+                        }
+                        size = (size == I2C_SMBUS_PROC_CALL ? SIS630_PCALL : SIS630_WORD_DATA);
+                        break;
+                case I2C_SMBUS_BLOCK_DATA:
+                        sis630_write(SMB_ADDR,((addr & 0x7f) << 1) | (read_write & 0x01));
+                        sis630_write(SMB_CMD, command);
+                        size = SIS630_BLOCK_DATA;
+                        return sis630_block_data(adap, data, read_write);
+                default:
+                        printk("Unsupported I2C size\n");
+                        return -1;
+                        break;
+        }
+
+        if (sis630_transaction(adap, size))
+                return -1;
+
+        if ((size != SIS630_PCALL) &&
+                ((read_write == I2C_SMBUS_WRITE) || (size == SIS630_QUICK))) {
+                return 0;
+        }
+
+        switch(size) {
+                case SIS630_BYTE:
+                case SIS630_BYTE_DATA:
+                        data->byte = sis630_read(SMB_BYTE);
+                        break;
+                case SIS630_PCALL:
+                case SIS630_WORD_DATA:
+                        data->word = sis630_read(SMB_BYTE) + (sis630_read(SMB_BYTE + 1) << 8);
+                        break;
+                default:
+                        return -1;
+                        break;
+        }
+
+        return 0;
+}
+
+static u32 sis630_func(struct i2c_adapter *adapter)
+{
+        return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA |
+                I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_PROC_CALL |
+                I2C_FUNC_SMBUS_BLOCK_DATA;
+}
+
+static int sis630_setup(struct pci_dev *sis630_dev)
+{
+        unsigned char b;
+        struct pci_dev *dummy = NULL;
+        int retval = -ENODEV, i;
+
+        /* check for supported SiS devices */
+        for (i=0; supported[i] > 0 ; i++) {
+                if ((dummy = pci_get_device(PCI_VENDOR_ID_SI, supported[i], dummy)))
+                        break; /* found */
+        }
+
+        if (dummy) {
+                pci_dev_put(dummy);
+        }
+        else if (force) {
+                dev_err(&sis630_dev->dev, "WARNING: Can't detect SIS630 compatible device, but "
+                        "loading because of force option enabled\n");
+        }
+        else {
+                return -ENODEV;
+        }
+
+        /*
+           Enable ACPI first , so we can accsess reg 74-75
+           in acpi io space and read acpi base addr
+        */
+        if (pci_read_config_byte(sis630_dev, SIS630_BIOS_CTL_REG,&b)) {
+                dev_err(&sis630_dev->dev, "Error: Can't read bios ctl reg\n");
+                goto exit;
+        }
+        /* if ACPI already enabled , do nothing */
+        if (!(b & 0x80) &&
+            pci_write_config_byte(sis630_dev, SIS630_BIOS_CTL_REG, b | 0x80)) {
+                dev_err(&sis630_dev->dev, "Error: Can't enable ACPI\n");
+                goto exit;
+        }
+
+        /* Determine the ACPI base address */
+        if (pci_read_config_word(sis630_dev,SIS630_ACPI_BASE_REG,&acpi_base)) {
+                dev_err(&sis630_dev->dev, "Error: Can't determine ACPI base address\n");
+                goto exit;
+        }
+
+        dev_dbg(&sis630_dev->dev, "ACPI base at 0x%04x\n", acpi_base);
+
+        /* Everything is happy, let's grab the memory and set things up. */
+        if (!request_region(acpi_base + SMB_STS, SIS630_SMB_IOREGION, "sis630-smbus")) {
+                dev_err(&sis630_dev->dev, "SMBus registers 0x%04x-0x%04x already "
+                        "in use!\n", acpi_base + SMB_STS, acpi_base + SMB_SAA);
+                goto exit;
+        }
+
+        retval = 0;
+
+exit:
+        if (retval)
+                acpi_base = 0;
+        return retval;
+}
+
+
+static struct i2c_algorithm smbus_algorithm = {
+        .name           = "Non-I2C SMBus adapter",
+        .id             = I2C_ALGO_SMBUS,
+        .smbus_xfer     = sis630_access,
+        .functionality  = sis630_func,
+};
+
+static struct i2c_adapter sis630_adapter = {
+        .owner          = THIS_MODULE,
+        .class          = I2C_CLASS_HWMON,
+        .name           = "unset",
+        .algo           = &smbus_algorithm,
+};
+
+static struct pci_device_id sis630_ids[] __devinitdata = {
+        { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503) },
+        { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC) },
+        { 0, }
+};
+
+MODULE_DEVICE_TABLE (pci, sis630_ids);
+
+static int __devinit sis630_probe(struct pci_dev *dev, const struct pci_device_id *id)
+{
+        if (sis630_setup(dev)) {
+                dev_err(&dev->dev, "SIS630 comp. bus not detected, module not inserted.\n");
+                return -ENODEV;
+        }
+
+        /* set up the driverfs linkage to our parent device */
+        sis630_adapter.dev.parent = &dev->dev;
+
+        sprintf(sis630_adapter.name, "SMBus SIS630 adapter at %04x",
+                acpi_base + SMB_STS);
+
+        return i2c_add_adapter(&sis630_adapter);
+}
+
+static void __devexit sis630_remove(struct pci_dev *dev)
+{
+        if (acpi_base) {
+                i2c_del_adapter(&sis630_adapter);
+                release_region(acpi_base + SMB_STS, SIS630_SMB_IOREGION);
+                acpi_base = 0;
+        }
+}
+
+
+static struct pci_driver sis630_driver = {
+        .name           = "sis630_smbus",
+        .id_table       = sis630_ids,
+        .probe          = sis630_probe,
+        .remove         = __devexit_p(sis630_remove),
+};
+
+static int __init i2c_sis630_init(void)
+{
+        return pci_register_driver(&sis630_driver);
+}
+
+
+static void __exit i2c_sis630_exit(void)
+{
+        pci_unregister_driver(&sis630_driver);
+}
+
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Alexander Malysh <amalysh@web.de>");
+MODULE_DESCRIPTION("SIS630 SMBus driver");
+
+module_init(i2c_sis630_init);
+module_exit(i2c_sis630_exit);
diff --git a/drivers/i2c/busses/i2c-sis96x.c b/drivers/i2c/busses/i2c-sis96x.c
new file mode 100644
index 000000000000..3cac6d43bce5
--- /dev/null
+++ b/drivers/i2c/busses/i2c-sis96x.c
@@ -0,0 +1,358 @@
+/*
+    sis96x.c - Part of lm_sensors, Linux kernel modules for hardware
+              monitoring
+
+    Copyright (c) 2003 Mark M. Hoffman <mhoffman@lightlink.com>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+/*
+    This module must be considered BETA unless and until
+    the chipset manufacturer releases a datasheet.
+    The register definitions are based on the SiS630.
+
+    This module relies on quirk_sis_96x_smbus (drivers/pci/quirks.c)
+    for just about every machine for which users have reported.
+    If this module isn't detecting your 96x south bridge, have a 
+    look there.
+
+    We assume there can only be one SiS96x with one SMBus interface.
+*/
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/stddef.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <asm/io.h>
+
+/*
+        HISTORY:
+        2003-05-11      1.0.0   Updated from lm_sensors project for kernel 2.5
+                                (was i2c-sis645.c from lm_sensors 2.7.0)
+*/
+#define SIS96x_VERSION "1.0.0"
+
+/* base address register in PCI config space */
+#define SIS96x_BAR 0x04
+
+/* SiS96x SMBus registers */
+#define SMB_STS      0x00
+#define SMB_EN       0x01
+#define SMB_CNT      0x02
+#define SMB_HOST_CNT 0x03
+#define SMB_ADDR     0x04
+#define SMB_CMD      0x05
+#define SMB_PCOUNT   0x06
+#define SMB_COUNT    0x07
+#define SMB_BYTE     0x08
+#define SMB_DEV_ADDR 0x10
+#define SMB_DB0      0x11
+#define SMB_DB1      0x12
+#define SMB_SAA      0x13
+
+/* register count for request_region */
+#define SMB_IOSIZE 0x20
+
+/* Other settings */
+#define MAX_TIMEOUT 500
+
+/* SiS96x SMBus constants */
+#define SIS96x_QUICK      0x00
+#define SIS96x_BYTE       0x01
+#define SIS96x_BYTE_DATA  0x02
+#define SIS96x_WORD_DATA  0x03
+#define SIS96x_PROC_CALL  0x04
+#define SIS96x_BLOCK_DATA 0x05
+
+static struct i2c_adapter sis96x_adapter;
+static u16 sis96x_smbus_base = 0;
+
+static inline u8 sis96x_read(u8 reg)
+{
+        return inb(sis96x_smbus_base + reg) ;
+}
+
+static inline void sis96x_write(u8 reg, u8 data)
+{
+        outb(data, sis96x_smbus_base + reg) ;
+}
+
+/* Execute a SMBus transaction.
+   int size is from SIS96x_QUICK to SIS96x_BLOCK_DATA
+ */
+static int sis96x_transaction(int size)
+{
+        int temp;
+        int result = 0;
+        int timeout = 0;
+
+        dev_dbg(&sis96x_adapter.dev, "SMBus transaction %d\n", size);
+
+        /* Make sure the SMBus host is ready to start transmitting */
+        if (((temp = sis96x_read(SMB_CNT)) & 0x03) != 0x00) {
+
+                dev_dbg(&sis96x_adapter.dev, "SMBus busy (0x%02x). "
+                        "Resetting...\n", temp);
+
+                /* kill the transaction */
+                sis96x_write(SMB_HOST_CNT, 0x20);
+
+                /* check it again */
+                if (((temp = sis96x_read(SMB_CNT)) & 0x03) != 0x00) {
+                        dev_dbg(&sis96x_adapter.dev, "Failed (0x%02x)\n", temp);
+                        return -1;
+                } else {
+                        dev_dbg(&sis96x_adapter.dev, "Successful\n");
+                }
+        }
+
+        /* Turn off timeout interrupts, set fast host clock */
+        sis96x_write(SMB_CNT, 0x20);
+
+        /* clear all (sticky) status flags */
+        temp = sis96x_read(SMB_STS);
+        sis96x_write(SMB_STS, temp & 0x1e);
+
+        /* start the transaction by setting bit 4 and size bits */
+        sis96x_write(SMB_HOST_CNT, 0x10 | (size & 0x07));
+
+        /* We will always wait for a fraction of a second! */
+        do {
+                msleep(1);
+                temp = sis96x_read(SMB_STS);
+        } while (!(temp & 0x0e) && (timeout++ < MAX_TIMEOUT));
+
+        /* If the SMBus is still busy, we give up */
+        if (timeout >= MAX_TIMEOUT) {
+                dev_dbg(&sis96x_adapter.dev, "SMBus Timeout! (0x%02x)\n", temp);
+                result = -1;
+        }
+
+        /* device error - probably missing ACK */
+        if (temp & 0x02) {
+                dev_dbg(&sis96x_adapter.dev, "Failed bus transaction!\n");
+                result = -1;
+        }
+
+        /* bus collision */
+        if (temp & 0x04) {
+                dev_dbg(&sis96x_adapter.dev, "Bus collision!\n");
+                result = -1;
+        }
+
+        /* Finish up by resetting the bus */
+        sis96x_write(SMB_STS, temp);
+        if ((temp = sis96x_read(SMB_STS))) {
+                dev_dbg(&sis96x_adapter.dev, "Failed reset at "
+                        "end of transaction! (0x%02x)\n", temp);
+        }
+
+        return result;
+}
+
+/* Return -1 on error. */
+static s32 sis96x_access(struct i2c_adapter * adap, u16 addr,
+                         unsigned short flags, char read_write,
+                         u8 command, int size, union i2c_smbus_data * data)
+{
+
+        switch (size) {
+        case I2C_SMBUS_QUICK:
+                sis96x_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01));
+                size = SIS96x_QUICK;
+                break;
+
+        case I2C_SMBUS_BYTE:
+                sis96x_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01));
+                if (read_write == I2C_SMBUS_WRITE)
+                        sis96x_write(SMB_CMD, command);
+                size = SIS96x_BYTE;
+                break;
+
+        case I2C_SMBUS_BYTE_DATA:
+                sis96x_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01));
+                sis96x_write(SMB_CMD, command);
+                if (read_write == I2C_SMBUS_WRITE)
+                        sis96x_write(SMB_BYTE, data->byte);
+                size = SIS96x_BYTE_DATA;
+                break;
+
+        case I2C_SMBUS_PROC_CALL:
+        case I2C_SMBUS_WORD_DATA:
+                sis96x_write(SMB_ADDR, ((addr & 0x7f) << 1) | (read_write & 0x01));
+                sis96x_write(SMB_CMD, command);
+                if (read_write == I2C_SMBUS_WRITE) {
+                        sis96x_write(SMB_BYTE, data->word & 0xff);
+                        sis96x_write(SMB_BYTE + 1, (data->word & 0xff00) >> 8);
+                }
+                size = (size == I2C_SMBUS_PROC_CALL ? 
+                        SIS96x_PROC_CALL : SIS96x_WORD_DATA);
+                break;
+
+        case I2C_SMBUS_BLOCK_DATA:
+                /* TO DO: */
+                dev_info(&adap->dev, "SMBus block not implemented!\n");
+                return -1;
+                break;
+
+        default:
+                dev_info(&adap->dev, "Unsupported I2C size\n");
+                return -1;
+                break;
+        }
+
+        if (sis96x_transaction(size))
+                return -1;
+
+        if ((size != SIS96x_PROC_CALL) &&
+                ((read_write == I2C_SMBUS_WRITE) || (size == SIS96x_QUICK)))
+                return 0;
+
+        switch (size) {
+        case SIS96x_BYTE:
+        case SIS96x_BYTE_DATA:
+                data->byte = sis96x_read(SMB_BYTE);
+                break;
+
+        case SIS96x_WORD_DATA:
+        case SIS96x_PROC_CALL:
+                data->word = sis96x_read(SMB_BYTE) +
+                                (sis96x_read(SMB_BYTE + 1) << 8);
+                break;
+        }
+        return 0;
+}
+
+static u32 sis96x_func(struct i2c_adapter *adapter)
+{
+        return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
+            I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
+            I2C_FUNC_SMBUS_PROC_CALL;
+}
+
+static struct i2c_algorithm smbus_algorithm = {
+        .name           = "Non-I2C SMBus adapter",
+        .id             = I2C_ALGO_SMBUS,
+        .smbus_xfer     = sis96x_access,
+        .functionality  = sis96x_func,
+};
+
+static struct i2c_adapter sis96x_adapter = {
+        .owner          = THIS_MODULE,
+        .class          = I2C_CLASS_HWMON,
+        .algo           = &smbus_algorithm,
+        .name           = "unset",
+};
+
+static struct pci_device_id sis96x_ids[] = {
+        { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_SMBUS) },
+        { 0, }
+};
+
+MODULE_DEVICE_TABLE (pci, sis96x_ids);
+
+static int __devinit sis96x_probe(struct pci_dev *dev,
+                                const struct pci_device_id *id)
+{
+        u16 ww = 0;
+        int retval;
+
+        if (sis96x_smbus_base) {
+                dev_err(&dev->dev, "Only one device supported.\n");
+                return -EBUSY;
+        }
+
+        pci_read_config_word(dev, PCI_CLASS_DEVICE, &ww);
+        if (PCI_CLASS_SERIAL_SMBUS != ww) {
+                dev_err(&dev->dev, "Unsupported device class 0x%04x!\n", ww);
+                return -ENODEV;
+        }
+
+        sis96x_smbus_base = pci_resource_start(dev, SIS96x_BAR);
+        if (!sis96x_smbus_base) {
+                dev_err(&dev->dev, "SiS96x SMBus base address "
+                        "not initialized!\n");
+                return -EINVAL;
+        }
+        dev_info(&dev->dev, "SiS96x SMBus base address: 0x%04x\n",
+                        sis96x_smbus_base);
+
+        /* Everything is happy, let's grab the memory and set things up. */
+        if (!request_region(sis96x_smbus_base, SMB_IOSIZE, "sis96x-smbus")) {
+                dev_err(&dev->dev, "SMBus registers 0x%04x-0x%04x "
+                        "already in use!\n", sis96x_smbus_base,
+                        sis96x_smbus_base + SMB_IOSIZE - 1);
+
+                sis96x_smbus_base = 0;
+                return -EINVAL;
+        }
+
+        /* set up the driverfs linkage to our parent device */
+        sis96x_adapter.dev.parent = &dev->dev;
+
+        snprintf(sis96x_adapter.name, I2C_NAME_SIZE,
+                "SiS96x SMBus adapter at 0x%04x", sis96x_smbus_base);
+
+        if ((retval = i2c_add_adapter(&sis96x_adapter))) {
+                dev_err(&dev->dev, "Couldn't register adapter!\n");
+                release_region(sis96x_smbus_base, SMB_IOSIZE);
+                sis96x_smbus_base = 0;
+        }
+
+        return retval;
+}
+
+static void __devexit sis96x_remove(struct pci_dev *dev)
+{
+        if (sis96x_smbus_base) {
+                i2c_del_adapter(&sis96x_adapter);
+                release_region(sis96x_smbus_base, SMB_IOSIZE);
+                sis96x_smbus_base = 0;
+        }
+}
+
+static struct pci_driver sis96x_driver = {
+        .name           = "sis96x_smbus",
+        .id_table       = sis96x_ids,
+        .probe          = sis96x_probe,
+        .remove         = __devexit_p(sis96x_remove),
+};
+
+static int __init i2c_sis96x_init(void)
+{
+        printk(KERN_INFO "i2c-sis96x version %s\n", SIS96x_VERSION);
+        return pci_register_driver(&sis96x_driver);
+}
+
+static void __exit i2c_sis96x_exit(void)
+{
+        pci_unregister_driver(&sis96x_driver);
+}
+
+MODULE_AUTHOR("Mark M. Hoffman <mhoffman@lightlink.com>");
+MODULE_DESCRIPTION("SiS96x SMBus driver");
+MODULE_LICENSE("GPL");
+
+/* Register initialization functions using helper macros */
+module_init(i2c_sis96x_init);
+module_exit(i2c_sis96x_exit);
+
diff --git a/drivers/i2c/busses/i2c-stub.c b/drivers/i2c/busses/i2c-stub.c
new file mode 100644
index 000000000000..19c805ead4d8
--- /dev/null
+++ b/drivers/i2c/busses/i2c-stub.c
@@ -0,0 +1,143 @@
+/*
+    i2c-stub.c - Part of lm_sensors, Linux kernel modules for hardware
+              monitoring
+
+    Copyright (c) 2004 Mark M. Hoffman <mhoffman@lightlink.com>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#define DEBUG 1
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/i2c.h>
+
+static u8  stub_pointer;
+static u8  stub_bytes[256];
+static u16 stub_words[256];
+
+/* Return -1 on error. */
+static s32 stub_xfer(struct i2c_adapter * adap, u16 addr, unsigned short flags,
+        char read_write, u8 command, int size, union i2c_smbus_data * data)
+{
+        s32 ret;
+
+        switch (size) {
+
+        case I2C_SMBUS_QUICK:
+                dev_dbg(&adap->dev, "smbus quick - addr 0x%02x\n", addr);
+                ret = 0;
+                break;
+
+        case I2C_SMBUS_BYTE:
+                if (read_write == I2C_SMBUS_WRITE) {
+                        stub_pointer = command;
+                        dev_dbg(&adap->dev, "smbus byte - addr 0x%02x, "
+                                        "wrote 0x%02x.\n",
+                                        addr, command);
+                } else {
+                        data->byte = stub_bytes[stub_pointer++];
+                        dev_dbg(&adap->dev, "smbus byte - addr 0x%02x, "
+                                        "read  0x%02x.\n",
+                                        addr, data->byte);
+                }
+
+                ret = 0;
+                break;
+
+        case I2C_SMBUS_BYTE_DATA:
+                if (read_write == I2C_SMBUS_WRITE) {
+                        stub_bytes[command] = data->byte;
+                        dev_dbg(&adap->dev, "smbus byte data - addr 0x%02x, "
+                                        "wrote 0x%02x at 0x%02x.\n",
+                                        addr, data->byte, command);
+                } else {
+                        data->byte = stub_bytes[command];
+                        dev_dbg(&adap->dev, "smbus byte data - addr 0x%02x, "
+                                        "read  0x%02x at 0x%02x.\n",
+                                        addr, data->byte, command);
+                }
+                stub_pointer = command + 1;
+
+                ret = 0;
+                break;
+
+        case I2C_SMBUS_WORD_DATA:
+                if (read_write == I2C_SMBUS_WRITE) {
+                        stub_words[command] = data->word;
+                        dev_dbg(&adap->dev, "smbus word data - addr 0x%02x, "
+                                        "wrote 0x%04x at 0x%02x.\n",
+                                        addr, data->word, command);
+                } else {
+                        data->word = stub_words[command];
+                        dev_dbg(&adap->dev, "smbus word data - addr 0x%02x, "
+                                        "read  0x%04x at 0x%02x.\n",
+                                        addr, data->word, command);
+                }
+
+                ret = 0;
+                break;
+
+        default:
+                dev_dbg(&adap->dev, "Unsupported I2C/SMBus command\n");
+                ret = -1;
+                break;
+        } /* switch (size) */
+
+        return ret;
+}
+
+static u32 stub_func(struct i2c_adapter *adapter)
+{
+        return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
+                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA;
+}
+
+static struct i2c_algorithm smbus_algorithm = {
+        .name           = "Non-I2C SMBus adapter",
+        .id             = I2C_ALGO_SMBUS,
+        .functionality  = stub_func,
+        .smbus_xfer     = stub_xfer,
+};
+
+static struct i2c_adapter stub_adapter = {
+        .owner          = THIS_MODULE,
+        .class          = I2C_CLASS_HWMON,
+        .algo           = &smbus_algorithm,
+        .name           = "SMBus stub driver",
+};
+
+static int __init i2c_stub_init(void)
+{
+        printk(KERN_INFO "i2c-stub loaded\n");
+        return i2c_add_adapter(&stub_adapter);
+}
+
+static void __exit i2c_stub_exit(void)
+{
+        i2c_del_adapter(&stub_adapter);
+}
+
+MODULE_AUTHOR("Mark M. Hoffman <mhoffman@lightlink.com>");
+MODULE_DESCRIPTION("I2C stub driver");
+MODULE_LICENSE("GPL");
+
+module_init(i2c_stub_init);
+module_exit(i2c_stub_exit);
+
diff --git a/drivers/i2c/busses/i2c-via.c b/drivers/i2c/busses/i2c-via.c
new file mode 100644
index 000000000000..2cbc4cd22366
--- /dev/null
+++ b/drivers/i2c/busses/i2c-via.c
@@ -0,0 +1,185 @@
+/*
+    i2c-via.c - Part of lm_sensors,  Linux kernel modules
+                for hardware monitoring
+
+    i2c Support for Via Technologies 82C586B South Bridge
+
+    Copyright (c) 1998, 1999 Kyösti Mälkki <kmalkki@cc.hut.fi>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/ioport.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+#include <linux/i2c-algo-bit.h>
+#include <asm/io.h>
+
+/* Power management registers */
+#define PM_CFG_REVID    0x08    /* silicon revision code */
+#define PM_CFG_IOBASE0  0x20
+#define PM_CFG_IOBASE1  0x48
+
+#define I2C_DIR         (pm_io_base+0x40)
+#define I2C_OUT         (pm_io_base+0x42)
+#define I2C_IN          (pm_io_base+0x44)
+#define I2C_SCL         0x02    /* clock bit in DIR/OUT/IN register */
+#define I2C_SDA         0x04
+
+/* io-region reservation */
+#define IOSPACE         0x06
+#define IOTEXT          "via-i2c"
+
+static u16 pm_io_base = 0;
+
+/*
+   It does not appear from the datasheet that the GPIO pins are
+   open drain. So a we set a low value by setting the direction to
+   output and a high value by setting the direction to input and
+   relying on the required I2C pullup. The data value is initialized
+   to 0 in via_init() and never changed.
+*/
+static void bit_via_setscl(void *data, int state)
+{
+        outb(state ? inb(I2C_DIR) & ~I2C_SCL : inb(I2C_DIR) | I2C_SCL, I2C_DIR);
+}
+
+static void bit_via_setsda(void *data, int state)
+{
+        outb(state ? inb(I2C_DIR) & ~I2C_SDA : inb(I2C_DIR) | I2C_SDA, I2C_DIR);
+}
+
+static int bit_via_getscl(void *data)
+{
+        return (0 != (inb(I2C_IN) & I2C_SCL));
+}
+
+static int bit_via_getsda(void *data)
+{
+        return (0 != (inb(I2C_IN) & I2C_SDA));
+}
+
+
+static struct i2c_algo_bit_data bit_data = {
+        .setsda         = bit_via_setsda,
+        .setscl         = bit_via_setscl,
+        .getsda         = bit_via_getsda,
+        .getscl         = bit_via_getscl,
+        .udelay         = 5,
+        .mdelay         = 5,
+        .timeout        = HZ
+};
+
+static struct i2c_adapter vt586b_adapter = {
+        .owner          = THIS_MODULE,
+        .class          = I2C_CLASS_HWMON,
+        .name           = "VIA i2c",
+        .algo_data      = &bit_data,
+};
+
+
+static struct pci_device_id vt586b_ids[] __devinitdata = {
+        { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3) },
+        { 0, }
+};
+
+MODULE_DEVICE_TABLE (pci, vt586b_ids);
+
+static int __devinit vt586b_probe(struct pci_dev *dev, const struct pci_device_id *id)
+{
+        u16 base;
+        u8 rev;
+        int res;
+
+        if (pm_io_base) {
+                dev_err(&dev->dev, "i2c-via: Will only support one host\n");
+                return -ENODEV;
+        }
+
+        pci_read_config_byte(dev, PM_CFG_REVID, &rev);
+
+        switch (rev) {
+        case 0x00:
+                base = PM_CFG_IOBASE0;
+                break;
+        case 0x01:
+        case 0x10:
+                base = PM_CFG_IOBASE1;
+                break;
+
+        default:
+                base = PM_CFG_IOBASE1;
+                /* later revision */
+        }
+
+        pci_read_config_word(dev, base, &pm_io_base);
+        pm_io_base &= (0xff << 8);
+
+        if (!request_region(I2C_DIR, IOSPACE, IOTEXT)) {
+                dev_err(&dev->dev, "IO 0x%x-0x%x already in use\n", I2C_DIR, I2C_DIR + IOSPACE);
+                return -ENODEV;
+        }
+
+        outb(inb(I2C_DIR) & ~(I2C_SDA | I2C_SCL), I2C_DIR);
+        outb(inb(I2C_OUT) & ~(I2C_SDA | I2C_SCL), I2C_OUT);
+
+        /* set up the driverfs linkage to our parent device */
+        vt586b_adapter.dev.parent = &dev->dev;
+
+        res = i2c_bit_add_bus(&vt586b_adapter);
+        if ( res < 0 ) {
+                release_region(I2C_DIR, IOSPACE);
+                pm_io_base = 0;
+                return res;
+        }
+        return 0;
+}
+
+static void __devexit vt586b_remove(struct pci_dev *dev)
+{
+        i2c_bit_del_bus(&vt586b_adapter);
+        release_region(I2C_DIR, IOSPACE);
+        pm_io_base = 0;
+}
+
+
+static struct pci_driver vt586b_driver = {
+        .name           = "vt586b_smbus",
+        .id_table       = vt586b_ids,
+        .probe          = vt586b_probe,
+        .remove         = __devexit_p(vt586b_remove),
+};
+
+static int __init i2c_vt586b_init(void)
+{
+        return pci_register_driver(&vt586b_driver);
+}
+
+static void __exit i2c_vt586b_exit(void)
+{
+        pci_unregister_driver(&vt586b_driver);
+}
+
+
+MODULE_AUTHOR("Kyösti Mälkki <kmalkki@cc.hut.fi>");
+MODULE_DESCRIPTION("i2c for Via vt82c586b southbridge");
+MODULE_LICENSE("GPL");
+
+module_init(i2c_vt586b_init);
+module_exit(i2c_vt586b_exit);
diff --git a/drivers/i2c/busses/i2c-viapro.c b/drivers/i2c/busses/i2c-viapro.c
new file mode 100644
index 000000000000..0bb60a636e16
--- /dev/null
+++ b/drivers/i2c/busses/i2c-viapro.c
@@ -0,0 +1,458 @@
+/*
+    i2c-viapro.c - Part of lm_sensors, Linux kernel modules for hardware
+              monitoring
+    Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>, 
+    Philip Edelbrock <phil@netroedge.com>, Kyösti Mälkki <kmalkki@cc.hut.fi>,
+    Mark D. Studebaker <mdsxyz123@yahoo.com>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+/*
+   Supports Via devices:
+        82C596A/B (0x3050)
+        82C596B (0x3051)
+        82C686A/B
+        8231
+        8233
+        8233A (0x3147 and 0x3177)
+        8235
+        8237
+   Note: we assume there can only be one device, with one SMBus interface.
+*/
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/stddef.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <asm/io.h>
+
+static struct pci_dev *vt596_pdev;
+
+#define SMBBA1           0x90
+#define SMBBA2           0x80
+#define SMBBA3           0xD0
+
+/* SMBus address offsets */
+static unsigned short vt596_smba;
+#define SMBHSTSTS       (vt596_smba + 0)
+#define SMBHSLVSTS      (vt596_smba + 1)
+#define SMBHSTCNT       (vt596_smba + 2)
+#define SMBHSTCMD       (vt596_smba + 3)
+#define SMBHSTADD       (vt596_smba + 4)
+#define SMBHSTDAT0      (vt596_smba + 5)
+#define SMBHSTDAT1      (vt596_smba + 6)
+#define SMBBLKDAT       (vt596_smba + 7)
+#define SMBSLVCNT       (vt596_smba + 8)
+#define SMBSHDWCMD      (vt596_smba + 9)
+#define SMBSLVEVT       (vt596_smba + 0xA)
+#define SMBSLVDAT       (vt596_smba + 0xC)
+
+/* PCI Address Constants */
+
+/* SMBus data in configuration space can be found in two places,
+   We try to select the better one*/
+
+static unsigned short smb_cf_hstcfg = 0xD2;
+
+#define SMBHSTCFG   (smb_cf_hstcfg)
+#define SMBSLVC     (smb_cf_hstcfg + 1)
+#define SMBSHDW1    (smb_cf_hstcfg + 2)
+#define SMBSHDW2    (smb_cf_hstcfg + 3)
+#define SMBREV      (smb_cf_hstcfg + 4)
+
+/* Other settings */
+#define MAX_TIMEOUT     500
+#define ENABLE_INT9     0
+
+/* VT82C596 constants */
+#define VT596_QUICK      0x00
+#define VT596_BYTE       0x04
+#define VT596_BYTE_DATA  0x08
+#define VT596_WORD_DATA  0x0C
+#define VT596_BLOCK_DATA 0x14
+
+
+/* If force is set to anything different from 0, we forcibly enable the
+   VT596. DANGEROUS! */
+static int force;
+module_param(force, bool, 0);
+MODULE_PARM_DESC(force, "Forcibly enable the SMBus. DANGEROUS!");
+
+/* If force_addr is set to anything different from 0, we forcibly enable
+   the VT596 at the given address. VERY DANGEROUS! */
+static u16 force_addr;
+module_param(force_addr, ushort, 0);
+MODULE_PARM_DESC(force_addr,
+                 "Forcibly enable the SMBus at the given address. "
+                 "EXTREMELY DANGEROUS!");
+
+
+static struct i2c_adapter vt596_adapter;
+
+/* Another internally used function */
+static int vt596_transaction(void)
+{
+        int temp;
+        int result = 0;
+        int timeout = 0;
+
+        dev_dbg(&vt596_adapter.dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
+                "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT), 
+                inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), 
+                inb_p(SMBHSTDAT1));
+
+        /* Make sure the SMBus host is ready to start transmitting */
+        if ((temp = inb_p(SMBHSTSTS)) & 0x1F) {
+                dev_dbg(&vt596_adapter.dev, "SMBus busy (0x%02x). "
+                                "Resetting...\n", temp);
+                
+                outb_p(temp, SMBHSTSTS);
+                if ((temp = inb_p(SMBHSTSTS)) & 0x1F) {
+                        dev_dbg(&vt596_adapter.dev, "Failed! (0x%02x)\n", temp);
+                        
+                        return -1;
+                } else {
+                        dev_dbg(&vt596_adapter.dev, "Successfull!\n");
+                }
+        }
+
+        /* start the transaction by setting bit 6 */
+        outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT);
+
+        /* We will always wait for a fraction of a second! 
+           I don't know if VIA needs this, Intel did  */
+        do {
+                msleep(1);
+                temp = inb_p(SMBHSTSTS);
+        } while ((temp & 0x01) && (timeout++ < MAX_TIMEOUT));
+
+        /* If the SMBus is still busy, we give up */
+        if (timeout >= MAX_TIMEOUT) {
+                result = -1;
+                dev_dbg(&vt596_adapter.dev, "SMBus Timeout!\n");
+        }
+
+        if (temp & 0x10) {
+                result = -1;
+                dev_dbg(&vt596_adapter.dev, "Error: Failed bus transaction\n");
+        }
+
+        if (temp & 0x08) {
+                result = -1;
+                dev_info(&vt596_adapter.dev, "Bus collision! SMBus may be "
+                        "locked until next hard\nreset. (sorry!)\n");
+                /* Clock stops and slave is stuck in mid-transmission */
+        }
+
+        if (temp & 0x04) {
+                result = -1;
+                dev_dbg(&vt596_adapter.dev, "Error: no response!\n");
+        }
+
+        if ((temp = inb_p(SMBHSTSTS)) & 0x1F) {
+                outb_p(temp, SMBHSTSTS);
+                if ((temp = inb_p(SMBHSTSTS)) & 0x1F) {
+                        dev_warn(&vt596_adapter.dev, "Failed reset at end "
+                                 "of transaction (%02x)\n", temp);
+                }
+        }
+
+        dev_dbg(&vt596_adapter.dev, "Transaction (post): CNT=%02x, CMD=%02x, "
+                "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
+                inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), 
+                inb_p(SMBHSTDAT1));
+        
+        return result;
+}
+
+/* Return -1 on error. */
+static s32 vt596_access(struct i2c_adapter *adap, u16 addr,
+                unsigned short flags,  char read_write, u8 command,
+                int size,  union i2c_smbus_data *data)
+{
+        int i, len;
+
+        switch (size) {
+        case I2C_SMBUS_PROC_CALL:
+                dev_info(&vt596_adapter.dev,
+                         "I2C_SMBUS_PROC_CALL not supported!\n");
+                return -1;
+        case I2C_SMBUS_QUICK:
+                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
+                       SMBHSTADD);
+                size = VT596_QUICK;
+                break;
+        case I2C_SMBUS_BYTE:
+                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
+                       SMBHSTADD);
+                if (read_write == I2C_SMBUS_WRITE)
+                        outb_p(command, SMBHSTCMD);
+                size = VT596_BYTE;
+                break;
+        case I2C_SMBUS_BYTE_DATA:
+                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
+                       SMBHSTADD);
+                outb_p(command, SMBHSTCMD);
+                if (read_write == I2C_SMBUS_WRITE)
+                        outb_p(data->byte, SMBHSTDAT0);
+                size = VT596_BYTE_DATA;
+                break;
+        case I2C_SMBUS_WORD_DATA:
+                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
+                       SMBHSTADD);
+                outb_p(command, SMBHSTCMD);
+                if (read_write == I2C_SMBUS_WRITE) {
+                        outb_p(data->word & 0xff, SMBHSTDAT0);
+                        outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
+                }
+                size = VT596_WORD_DATA;
+                break;
+        case I2C_SMBUS_BLOCK_DATA:
+                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
+                       SMBHSTADD);
+                outb_p(command, SMBHSTCMD);
+                if (read_write == I2C_SMBUS_WRITE) {
+                        len = data->block[0];
+                        if (len < 0)
+                                len = 0;
+                        if (len > I2C_SMBUS_BLOCK_MAX)
+                                len = I2C_SMBUS_BLOCK_MAX;
+                        outb_p(len, SMBHSTDAT0);
+                        i = inb_p(SMBHSTCNT);   /* Reset SMBBLKDAT */
+                        for (i = 1; i <= len; i++)
+                                outb_p(data->block[i], SMBBLKDAT);
+                }
+                size = VT596_BLOCK_DATA;
+                break;
+        }
+
+        outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT);
+
+        if (vt596_transaction()) /* Error in transaction */
+                return -1;
+
+        if ((read_write == I2C_SMBUS_WRITE) || (size == VT596_QUICK))
+                return 0;
+
+        switch (size) {
+        case VT596_BYTE:
+                /* Where is the result put? I assume here it is in
+                 * SMBHSTDAT0 but it might just as well be in the
+                 * SMBHSTCMD. No clue in the docs 
+                 */
+                data->byte = inb_p(SMBHSTDAT0);
+                break;
+        case VT596_BYTE_DATA:
+                data->byte = inb_p(SMBHSTDAT0);
+                break;
+        case VT596_WORD_DATA:
+                data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
+                break;
+        case VT596_BLOCK_DATA:
+                data->block[0] = inb_p(SMBHSTDAT0);
+                if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
+                        data->block[0] = I2C_SMBUS_BLOCK_MAX;
+                i = inb_p(SMBHSTCNT);   /* Reset SMBBLKDAT */
+                for (i = 1; i <= data->block[0]; i++)
+                        data->block[i] = inb_p(SMBBLKDAT);
+                break;
+        }
+        return 0;
+}
+
+static u32 vt596_func(struct i2c_adapter *adapter)
+{
+        return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
+            I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
+            I2C_FUNC_SMBUS_BLOCK_DATA;
+}
+
+static struct i2c_algorithm smbus_algorithm = {
+        .name           = "Non-I2C SMBus adapter",
+        .id             = I2C_ALGO_SMBUS,
+        .smbus_xfer     = vt596_access,
+        .functionality  = vt596_func,
+};
+
+static struct i2c_adapter vt596_adapter = {
+        .owner          = THIS_MODULE,
+        .class          = I2C_CLASS_HWMON,
+        .algo           = &smbus_algorithm,
+        .name           = "unset",
+};
+
+static int __devinit vt596_probe(struct pci_dev *pdev,
+                                 const struct pci_device_id *id)
+{
+        unsigned char temp;
+        int error = -ENODEV;
+        
+        /* Determine the address of the SMBus areas */
+        if (force_addr) {
+                vt596_smba = force_addr & 0xfff0;
+                force = 0;
+                goto found;
+        }
+
+        if ((pci_read_config_word(pdev, id->driver_data, &vt596_smba)) ||
+            !(vt596_smba & 0x1)) {
+                /* try 2nd address and config reg. for 596 */
+                if (id->device == PCI_DEVICE_ID_VIA_82C596_3 &&
+                    !pci_read_config_word(pdev, SMBBA2, &vt596_smba) &&
+                    (vt596_smba & 0x1)) {
+                        smb_cf_hstcfg = 0x84;
+                } else {
+                        /* no matches at all */
+                        dev_err(&pdev->dev, "Cannot configure "
+                                "SMBus I/O Base address\n");
+                        return -ENODEV;
+                }
+        }
+
+        vt596_smba &= 0xfff0;
+        if (vt596_smba == 0) {
+                dev_err(&pdev->dev, "SMBus base address "
+                        "uninitialized - upgrade BIOS or use "
+                        "force_addr=0xaddr\n");
+                return -ENODEV;
+        }
+
+ found:
+        if (!request_region(vt596_smba, 8, "viapro-smbus")) {
+                dev_err(&pdev->dev, "SMBus region 0x%x already in use!\n",
+                        vt596_smba);
+                return -ENODEV;
+        }
+
+        pci_read_config_byte(pdev, SMBHSTCFG, &temp);
+        /* If force_addr is set, we program the new address here. Just to make
+           sure, we disable the VT596 first. */
+        if (force_addr) {
+                pci_write_config_byte(pdev, SMBHSTCFG, temp & 0xfe);
+                pci_write_config_word(pdev, id->driver_data, vt596_smba);
+                pci_write_config_byte(pdev, SMBHSTCFG, temp | 0x01);
+                dev_warn(&pdev->dev, "WARNING: SMBus interface set to new "
+                     "address 0x%04x!\n", vt596_smba);
+        } else if ((temp & 1) == 0) {
+                if (force) {
+                        /* NOTE: This assumes I/O space and other allocations 
+                         * WERE done by the Bios!  Don't complain if your 
+                         * hardware does weird things after enabling this. 
+                         * :') Check for Bios updates before resorting to 
+                         * this.
+                         */
+                        pci_write_config_byte(pdev, SMBHSTCFG, temp | 1);
+                        dev_info(&pdev->dev, "Enabling SMBus device\n");
+                } else {
+                        dev_err(&pdev->dev, "SMBUS: Error: Host SMBus "
+                                "controller not enabled! - upgrade BIOS or "
+                                "use force=1\n");
+                        goto release_region;
+                }
+        }
+
+        if ((temp & 0x0E) == 8)
+                dev_dbg(&pdev->dev, "using Interrupt 9 for SMBus.\n");
+        else if ((temp & 0x0E) == 0)
+                dev_dbg(&pdev->dev, "using Interrupt SMI# for SMBus.\n");
+        else
+                dev_dbg(&pdev->dev, "Illegal Interrupt configuration "
+                        "(or code out of date)!\n");
+
+        pci_read_config_byte(pdev, SMBREV, &temp);
+        dev_dbg(&pdev->dev, "SMBREV = 0x%X\n", temp);
+        dev_dbg(&pdev->dev, "VT596_smba = 0x%X\n", vt596_smba);
+
+        vt596_adapter.dev.parent = &pdev->dev;
+        snprintf(vt596_adapter.name, I2C_NAME_SIZE,
+                        "SMBus Via Pro adapter at %04x", vt596_smba);
+        
+        vt596_pdev = pci_dev_get(pdev);
+        if (i2c_add_adapter(&vt596_adapter)) {
+                pci_dev_put(vt596_pdev);
+                vt596_pdev = NULL;
+        }
+
+        /* Always return failure here.  This is to allow other drivers to bind
+         * to this pci device.  We don't really want to have control over the
+         * pci device, we only wanted to read as few register values from it.
+         */
+        return -ENODEV;
+
+ release_region:
+        release_region(vt596_smba, 8);
+        return error;
+}
+
+static struct pci_device_id vt596_ids[] = {
+        { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596_3),
+          .driver_data = SMBBA1 },
+        { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596B_3),
+          .driver_data = SMBBA1 },
+        { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4),
+          .driver_data = SMBBA1 },
+        { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0),
+          .driver_data = SMBBA3 },
+        { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A),
+          .driver_data = SMBBA3 },
+        { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235),
+          .driver_data = SMBBA3 },
+        { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237),
+          .driver_data = SMBBA3 },
+        { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231_4),
+          .driver_data = SMBBA1 },
+        { 0, }
+};
+
+MODULE_DEVICE_TABLE (pci, vt596_ids);
+
+static struct pci_driver vt596_driver = {
+        .name           = "vt596_smbus",
+        .id_table       = vt596_ids,
+        .probe          = vt596_probe,
+};
+
+static int __init i2c_vt596_init(void)
+{
+        return pci_register_driver(&vt596_driver);
+}
+
+
+static void __exit i2c_vt596_exit(void)
+{
+        pci_unregister_driver(&vt596_driver);
+        if (vt596_pdev != NULL) {
+                i2c_del_adapter(&vt596_adapter);
+                release_region(vt596_smba, 8);
+                pci_dev_put(vt596_pdev);
+                vt596_pdev = NULL;
+        }
+}
+
+MODULE_AUTHOR(
+    "Frodo Looijaard <frodol@dds.nl> and "
+    "Philip Edelbrock <phil@netroedge.com>");
+MODULE_DESCRIPTION("vt82c596 SMBus driver");
+MODULE_LICENSE("GPL");
+
+module_init(i2c_vt596_init);
+module_exit(i2c_vt596_exit);
diff --git a/drivers/i2c/busses/i2c-voodoo3.c b/drivers/i2c/busses/i2c-voodoo3.c
new file mode 100644
index 000000000000..3edf0e34155e
--- /dev/null
+++ b/drivers/i2c/busses/i2c-voodoo3.c
@@ -0,0 +1,254 @@
+/*
+    voodoo3.c - Part of lm_sensors, Linux kernel modules for hardware
+              monitoring
+    Copyright (c) 1998, 1999  Frodo Looijaard <frodol@dds.nl>,
+    Philip Edelbrock <phil@netroedge.com>,
+    Ralph Metzler <rjkm@thp.uni-koeln.de>, and
+    Mark D. Studebaker <mdsxyz123@yahoo.com>
+    
+    Based on code written by Ralph Metzler <rjkm@thp.uni-koeln.de> and
+    Simon Vogl
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+/* This interfaces to the I2C bus of the Voodoo3 to gain access to
+    the BT869 and possibly other I2C devices. */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/i2c.h>
+#include <linux/i2c-algo-bit.h>
+#include <asm/io.h>
+
+/* the only registers we use */
+#define REG             0x78
+#define REG2            0x70
+
+/* bit locations in the register */
+#define DDC_ENAB        0x00040000
+#define DDC_SCL_OUT     0x00080000
+#define DDC_SDA_OUT     0x00100000
+#define DDC_SCL_IN      0x00200000
+#define DDC_SDA_IN      0x00400000
+#define I2C_ENAB        0x00800000
+#define I2C_SCL_OUT     0x01000000
+#define I2C_SDA_OUT     0x02000000
+#define I2C_SCL_IN      0x04000000
+#define I2C_SDA_IN      0x08000000
+
+/* initialization states */
+#define INIT2           0x2
+#define INIT3           0x4
+
+/* delays */
+#define CYCLE_DELAY     10
+#define TIMEOUT         (HZ / 2)
+
+
+static void __iomem *ioaddr;
+
+/* The voo GPIO registers don't have individual masks for each bit
+   so we always have to read before writing. */
+
+static void bit_vooi2c_setscl(void *data, int val)
+{
+        unsigned int r;
+        r = readl(ioaddr + REG);
+        if (val)
+                r |= I2C_SCL_OUT;
+        else
+                r &= ~I2C_SCL_OUT;
+        writel(r, ioaddr + REG);
+        readl(ioaddr + REG);    /* flush posted write */
+}
+
+static void bit_vooi2c_setsda(void *data, int val)
+{
+        unsigned int r;
+        r = readl(ioaddr + REG);
+        if (val)
+                r |= I2C_SDA_OUT;
+        else
+                r &= ~I2C_SDA_OUT;
+        writel(r, ioaddr + REG);
+        readl(ioaddr + REG);    /* flush posted write */
+}
+
+/* The GPIO pins are open drain, so the pins always remain outputs.
+   We rely on the i2c-algo-bit routines to set the pins high before
+   reading the input from other chips. */
+
+static int bit_vooi2c_getscl(void *data)
+{
+        return (0 != (readl(ioaddr + REG) & I2C_SCL_IN));
+}
+
+static int bit_vooi2c_getsda(void *data)
+{
+        return (0 != (readl(ioaddr + REG) & I2C_SDA_IN));
+}
+
+static void bit_vooddc_setscl(void *data, int val)
+{
+        unsigned int r;
+        r = readl(ioaddr + REG);
+        if (val)
+                r |= DDC_SCL_OUT;
+        else
+                r &= ~DDC_SCL_OUT;
+        writel(r, ioaddr + REG);
+        readl(ioaddr + REG);    /* flush posted write */
+}
+
+static void bit_vooddc_setsda(void *data, int val)
+{
+        unsigned int r;
+        r = readl(ioaddr + REG);
+        if (val)
+                r |= DDC_SDA_OUT;
+        else
+                r &= ~DDC_SDA_OUT;
+        writel(r, ioaddr + REG);
+        readl(ioaddr + REG);    /* flush posted write */
+}
+
+static int bit_vooddc_getscl(void *data)
+{
+        return (0 != (readl(ioaddr + REG) & DDC_SCL_IN));
+}
+
+static int bit_vooddc_getsda(void *data)
+{
+        return (0 != (readl(ioaddr + REG) & DDC_SDA_IN));
+}
+
+static int config_v3(struct pci_dev *dev)
+{
+        unsigned long cadr;
+
+        /* map Voodoo3 memory */
+        cadr = dev->resource[0].start;
+        cadr &= PCI_BASE_ADDRESS_MEM_MASK;
+        ioaddr = ioremap_nocache(cadr, 0x1000);
+        if (ioaddr) {
+                writel(0x8160, ioaddr + REG2);
+                writel(0xcffc0020, ioaddr + REG);
+                dev_info(&dev->dev, "Using Banshee/Voodoo3 I2C device at %p\n", ioaddr);
+                return 0;
+        }
+        return -ENODEV;
+}
+
+static struct i2c_algo_bit_data voo_i2c_bit_data = {
+        .setsda         = bit_vooi2c_setsda,
+        .setscl         = bit_vooi2c_setscl,
+        .getsda         = bit_vooi2c_getsda,
+        .getscl         = bit_vooi2c_getscl,
+        .udelay         = CYCLE_DELAY,
+        .mdelay         = CYCLE_DELAY,
+        .timeout        = TIMEOUT
+};
+
+static struct i2c_adapter voodoo3_i2c_adapter = {
+        .owner          = THIS_MODULE,
+        .class          = I2C_CLASS_TV_ANALOG, 
+        .name           = "I2C Voodoo3/Banshee adapter",
+        .algo_data      = &voo_i2c_bit_data,
+};
+
+static struct i2c_algo_bit_data voo_ddc_bit_data = {
+        .setsda         = bit_vooddc_setsda,
+        .setscl         = bit_vooddc_setscl,
+        .getsda         = bit_vooddc_getsda,
+        .getscl         = bit_vooddc_getscl,
+        .udelay         = CYCLE_DELAY,
+        .mdelay         = CYCLE_DELAY,
+        .timeout        = TIMEOUT
+};
+
+static struct i2c_adapter voodoo3_ddc_adapter = {
+        .owner          = THIS_MODULE,
+        .class          = I2C_CLASS_DDC, 
+        .name           = "DDC Voodoo3/Banshee adapter",
+        .algo_data      = &voo_ddc_bit_data,
+};
+
+static struct pci_device_id voodoo3_ids[] __devinitdata = {
+        { PCI_DEVICE(PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO3) },
+        { PCI_DEVICE(PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_BANSHEE) },
+        { 0, }
+};
+
+MODULE_DEVICE_TABLE (pci, voodoo3_ids);
+
+static int __devinit voodoo3_probe(struct pci_dev *dev, const struct pci_device_id *id)
+{
+        int retval;
+
+        retval = config_v3(dev);
+        if (retval)
+                return retval;
+
+        /* set up the sysfs linkage to our parent device */
+        voodoo3_i2c_adapter.dev.parent = &dev->dev;
+        voodoo3_ddc_adapter.dev.parent = &dev->dev;
+
+        retval = i2c_bit_add_bus(&voodoo3_i2c_adapter);
+        if (retval)
+                return retval;
+        retval = i2c_bit_add_bus(&voodoo3_ddc_adapter);
+        if (retval)
+                i2c_bit_del_bus(&voodoo3_i2c_adapter);
+        return retval;
+}
+
+static void __devexit voodoo3_remove(struct pci_dev *dev)
+{
+        i2c_bit_del_bus(&voodoo3_i2c_adapter);
+        i2c_bit_del_bus(&voodoo3_ddc_adapter);
+        iounmap(ioaddr);
+}
+
+static struct pci_driver voodoo3_driver = {
+        .name           = "voodoo3_smbus",
+        .id_table       = voodoo3_ids,
+        .probe          = voodoo3_probe,
+        .remove         = __devexit_p(voodoo3_remove),
+};
+
+static int __init i2c_voodoo3_init(void)
+{
+        return pci_register_driver(&voodoo3_driver);
+}
+
+static void __exit i2c_voodoo3_exit(void)
+{
+        pci_unregister_driver(&voodoo3_driver);
+}
+
+
+MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl>, "
+                "Philip Edelbrock <phil@netroedge.com>, "
+                "Ralph Metzler <rjkm@thp.uni-koeln.de>, "
+                "and Mark D. Studebaker <mdsxyz123@yahoo.com>");
+MODULE_DESCRIPTION("Voodoo3 I2C/SMBus driver");
+MODULE_LICENSE("GPL");
+
+module_init(i2c_voodoo3_init);
+module_exit(i2c_voodoo3_exit);
diff --git a/drivers/i2c/busses/scx200_acb.c b/drivers/i2c/busses/scx200_acb.c
new file mode 100644
index 000000000000..1c4159a93623
--- /dev/null
+++ b/drivers/i2c/busses/scx200_acb.c
@@ -0,0 +1,557 @@
+/*  linux/drivers/i2c/scx200_acb.c 
+
+    Copyright (c) 2001,2002 Christer Weinigel <wingel@nano-system.com>
+
+    National Semiconductor SCx200 ACCESS.bus support
+    
+    Based on i2c-keywest.c which is:
+        Copyright (c) 2001 Benjamin Herrenschmidt <benh@kernel.crashing.org>
+        Copyright (c) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
+    
+    This program is free software; you can redistribute it and/or
+    modify it under the terms of the GNU General Public License as
+    published by the Free Software Foundation; either version 2 of the
+    License, or (at your option) any later version.
+   
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+    General Public License for more details.
+   
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+*/
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+#include <linux/smp_lock.h>
+#include <linux/pci.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+
+#include <linux/scx200.h>
+
+#define NAME "scx200_acb"
+
+MODULE_AUTHOR("Christer Weinigel <wingel@nano-system.com>");
+MODULE_DESCRIPTION("NatSemi SCx200 ACCESS.bus Driver");
+MODULE_LICENSE("GPL");
+
+#define MAX_DEVICES 4
+static int base[MAX_DEVICES] = { 0x820, 0x840 };
+module_param_array(base, int, NULL, 0);
+MODULE_PARM_DESC(base, "Base addresses for the ACCESS.bus controllers");
+
+#ifdef DEBUG
+#define DBG(x...) printk(KERN_DEBUG NAME ": " x)
+#else
+#define DBG(x...)
+#endif
+
+/* The hardware supports interrupt driven mode too, but I haven't
+   implemented that. */
+#define POLLED_MODE 1
+#define POLL_TIMEOUT (HZ)
+
+enum scx200_acb_state {
+        state_idle,
+        state_address,
+        state_command,
+        state_repeat_start,
+        state_quick,
+        state_read,
+        state_write,
+};
+
+static const char *scx200_acb_state_name[] = {
+        "idle",
+        "address",
+        "command",
+        "repeat_start",
+        "quick",
+        "read",
+        "write",
+};
+
+/* Physical interface */
+struct scx200_acb_iface
+{
+        struct scx200_acb_iface *next;
+        struct i2c_adapter adapter;
+        unsigned base;
+        struct semaphore sem;
+
+        /* State machine data */
+        enum scx200_acb_state state;
+        int result;
+        u8 address_byte;
+        u8 command;
+        u8 *ptr;
+        char needs_reset;
+        unsigned len;
+};
+
+/* Register Definitions */
+#define ACBSDA          (iface->base + 0)
+#define ACBST           (iface->base + 1)
+#define    ACBST_SDAST          0x40 /* SDA Status */
+#define    ACBST_BER            0x20 
+#define    ACBST_NEGACK         0x10 /* Negative Acknowledge */
+#define    ACBST_STASTR         0x08 /* Stall After Start */
+#define    ACBST_MASTER         0x02
+#define ACBCST          (iface->base + 2)
+#define    ACBCST_BB            0x02
+#define ACBCTL1         (iface->base + 3)
+#define    ACBCTL1_STASTRE      0x80
+#define    ACBCTL1_NMINTE       0x40
+#define    ACBCTL1_ACK          0x10
+#define    ACBCTL1_STOP         0x02
+#define    ACBCTL1_START        0x01
+#define ACBADDR         (iface->base + 4)
+#define ACBCTL2         (iface->base + 5)
+#define    ACBCTL2_ENABLE       0x01
+
+/************************************************************************/
+
+static void scx200_acb_machine(struct scx200_acb_iface *iface, u8 status)
+{
+        const char *errmsg;
+
+        DBG("state %s, status = 0x%02x\n", 
+            scx200_acb_state_name[iface->state], status);
+
+        if (status & ACBST_BER) {
+                errmsg = "bus error";
+                goto error;
+        }
+        if (!(status & ACBST_MASTER)) {
+                errmsg = "not master";
+                goto error;
+        }
+        if (status & ACBST_NEGACK)
+                goto negack;
+
+        switch (iface->state) {
+        case state_idle:
+                dev_warn(&iface->adapter.dev, "interrupt in idle state\n");
+                break;
+
+        case state_address:
+                /* Do a pointer write first */
+                outb(iface->address_byte & ~1, ACBSDA);
+
+                iface->state = state_command;
+                break;
+
+        case state_command:
+                outb(iface->command, ACBSDA);
+
+                if (iface->address_byte & 1)
+                        iface->state = state_repeat_start;
+                else
+                        iface->state = state_write;
+                break;
+
+        case state_repeat_start:
+                outb(inb(ACBCTL1) | ACBCTL1_START, ACBCTL1);
+                /* fallthrough */
+                
+        case state_quick:
+                if (iface->address_byte & 1) {
+                        if (iface->len == 1) 
+                                outb(inb(ACBCTL1) | ACBCTL1_ACK, ACBCTL1);
+                        else
+                                outb(inb(ACBCTL1) & ~ACBCTL1_ACK, ACBCTL1);
+                        outb(iface->address_byte, ACBSDA);
+
+                        iface->state = state_read;
+                } else {
+                        outb(iface->address_byte, ACBSDA);
+
+                        iface->state = state_write;
+                }
+                break;
+
+        case state_read:
+                /* Set ACK if receiving the last byte */
+                if (iface->len == 1)
+                        outb(inb(ACBCTL1) | ACBCTL1_ACK, ACBCTL1);
+                else
+                        outb(inb(ACBCTL1) & ~ACBCTL1_ACK, ACBCTL1);
+
+                *iface->ptr++ = inb(ACBSDA);
+                --iface->len;
+
+                if (iface->len == 0) {
+                        iface->result = 0;
+                        iface->state = state_idle;
+                        outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
+                }
+
+                break;
+
+        case state_write:
+                if (iface->len == 0) {
+                        iface->result = 0;
+                        iface->state = state_idle;
+                        outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
+                        break;
+                }
+                
+                outb(*iface->ptr++, ACBSDA);
+                --iface->len;
+                
+                break;
+        }
+
+        return;
+
+ negack:
+        DBG("negative acknowledge in state %s\n", 
+            scx200_acb_state_name[iface->state]);
+
+        iface->state = state_idle;
+        iface->result = -ENXIO;
+
+        outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
+        outb(ACBST_STASTR | ACBST_NEGACK, ACBST);
+        return;
+
+ error:
+        dev_err(&iface->adapter.dev, "%s in state %s\n", errmsg,
+                scx200_acb_state_name[iface->state]);
+
+        iface->state = state_idle;
+        iface->result = -EIO;
+        iface->needs_reset = 1;
+}
+
+static void scx200_acb_timeout(struct scx200_acb_iface *iface) 
+{
+        dev_err(&iface->adapter.dev, "timeout in state %s\n",
+                scx200_acb_state_name[iface->state]);
+
+        iface->state = state_idle;
+        iface->result = -EIO;
+        iface->needs_reset = 1;
+}
+
+#ifdef POLLED_MODE
+static void scx200_acb_poll(struct scx200_acb_iface *iface)
+{
+        u8 status = 0;
+        unsigned long timeout;
+
+        timeout = jiffies + POLL_TIMEOUT;
+        while (time_before(jiffies, timeout)) {
+                status = inb(ACBST);
+                if ((status & (ACBST_SDAST|ACBST_BER|ACBST_NEGACK)) != 0) {
+                        scx200_acb_machine(iface, status);
+                        return;
+                }
+                msleep(10);
+        }
+
+        scx200_acb_timeout(iface);
+}
+#endif /* POLLED_MODE */
+
+static void scx200_acb_reset(struct scx200_acb_iface *iface)
+{
+        /* Disable the ACCESS.bus device and Configure the SCL
+           frequency: 16 clock cycles */
+        outb(0x70, ACBCTL2);
+        /* Polling mode */
+        outb(0, ACBCTL1);
+        /* Disable slave address */
+        outb(0, ACBADDR);
+        /* Enable the ACCESS.bus device */
+        outb(inb(ACBCTL2) | ACBCTL2_ENABLE, ACBCTL2);
+        /* Free STALL after START */
+        outb(inb(ACBCTL1) & ~(ACBCTL1_STASTRE | ACBCTL1_NMINTE), ACBCTL1);
+        /* Send a STOP */
+        outb(inb(ACBCTL1) | ACBCTL1_STOP, ACBCTL1);
+        /* Clear BER, NEGACK and STASTR bits */
+        outb(ACBST_BER | ACBST_NEGACK | ACBST_STASTR, ACBST);
+        /* Clear BB bit */
+        outb(inb(ACBCST) | ACBCST_BB, ACBCST);
+}
+
+static s32 scx200_acb_smbus_xfer(struct i2c_adapter *adapter,
+                                u16 address, unsigned short flags,      
+                                char rw, u8 command, int size, 
+                                union i2c_smbus_data *data)
+{
+        struct scx200_acb_iface *iface = i2c_get_adapdata(adapter);
+        int len;
+        u8 *buffer;
+        u16 cur_word;
+        int rc;
+
+        switch (size) {
+        case I2C_SMBUS_QUICK:
+                len = 0;
+                buffer = NULL;
+                break;
+        case I2C_SMBUS_BYTE:
+                if (rw == I2C_SMBUS_READ) {
+                        len = 1;
+                        buffer = &data->byte;
+                } else {
+                        len = 1;
+                        buffer = &command;
+                }
+                break;
+        case I2C_SMBUS_BYTE_DATA:
+                len = 1;
+                buffer = &data->byte;
+                break;
+        case I2C_SMBUS_WORD_DATA:
+                len = 2;
+                cur_word = cpu_to_le16(data->word);
+                buffer = (u8 *)&cur_word;
+                break;
+        case I2C_SMBUS_BLOCK_DATA:
+                len = data->block[0];
+                buffer = &data->block[1];
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        DBG("size=%d, address=0x%x, command=0x%x, len=%d, read=%d\n",
+            size, address, command, len, rw == I2C_SMBUS_READ);
+
+        if (!len && rw == I2C_SMBUS_READ) {
+                dev_warn(&adapter->dev, "zero length read\n");
+                return -EINVAL;
+        }
+
+        if (len && !buffer) {
+                dev_warn(&adapter->dev, "nonzero length but no buffer\n");
+                return -EFAULT;
+        }
+
+        down(&iface->sem);
+
+        iface->address_byte = address<<1;
+        if (rw == I2C_SMBUS_READ)
+                iface->address_byte |= 1;
+        iface->command = command;
+        iface->ptr = buffer;
+        iface->len = len;
+        iface->result = -EINVAL;
+        iface->needs_reset = 0;
+
+        outb(inb(ACBCTL1) | ACBCTL1_START, ACBCTL1);
+
+        if (size == I2C_SMBUS_QUICK || size == I2C_SMBUS_BYTE)
+                iface->state = state_quick;
+        else
+                iface->state = state_address;
+
+#ifdef POLLED_MODE
+        while (iface->state != state_idle)
+                scx200_acb_poll(iface);
+#else /* POLLED_MODE */
+#error Interrupt driven mode not implemented
+#endif /* POLLED_MODE */        
+
+        if (iface->needs_reset)
+                scx200_acb_reset(iface);
+
+        rc = iface->result;
+
+        up(&iface->sem);
+
+        if (rc == 0 && size == I2C_SMBUS_WORD_DATA && rw == I2C_SMBUS_READ)
+                data->word = le16_to_cpu(cur_word);
+
+#ifdef DEBUG
+        DBG(": transfer done, result: %d", rc);
+        if (buffer) {
+                int i;
+                printk(" data:");
+                for (i = 0; i < len; ++i)
+                        printk(" %02x", buffer[i]);
+        }
+        printk("\n");
+#endif
+
+        return rc;
+}
+
+static u32 scx200_acb_func(struct i2c_adapter *adapter)
+{
+        return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
+               I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
+               I2C_FUNC_SMBUS_BLOCK_DATA;
+}
+
+/* For now, we only handle combined mode (smbus) */
+static struct i2c_algorithm scx200_acb_algorithm = {
+        .name           = "NatSemi SCx200 ACCESS.bus",
+        .id             = I2C_ALGO_SMBUS,
+        .smbus_xfer     = scx200_acb_smbus_xfer,
+        .functionality  = scx200_acb_func,
+};
+
+static struct scx200_acb_iface *scx200_acb_list;
+
+static int scx200_acb_probe(struct scx200_acb_iface *iface)
+{
+        u8 val;
+
+        /* Disable the ACCESS.bus device and Configure the SCL
+           frequency: 16 clock cycles */
+        outb(0x70, ACBCTL2);
+
+        if (inb(ACBCTL2) != 0x70) {
+                DBG("ACBCTL2 readback failed\n");
+                return -ENXIO;
+        }
+
+        outb(inb(ACBCTL1) | ACBCTL1_NMINTE, ACBCTL1);
+
+        val = inb(ACBCTL1);
+        if (val) {
+                DBG("disabled, but ACBCTL1=0x%02x\n", val);
+                return -ENXIO;
+        }
+
+        outb(inb(ACBCTL2) | ACBCTL2_ENABLE, ACBCTL2);
+
+        outb(inb(ACBCTL1) | ACBCTL1_NMINTE, ACBCTL1);
+
+        val = inb(ACBCTL1);
+        if ((val & ACBCTL1_NMINTE) != ACBCTL1_NMINTE) {
+                DBG("enabled, but NMINTE won't be set, ACBCTL1=0x%02x\n", val);
+                return -ENXIO;
+        }
+
+        return 0;
+}
+
+static int  __init scx200_acb_create(int base, int index)
+{
+        struct scx200_acb_iface *iface;
+        struct i2c_adapter *adapter;
+        int rc = 0;
+        char description[64];
+
+        iface = kmalloc(sizeof(*iface), GFP_KERNEL);
+        if (!iface) {
+                printk(KERN_ERR NAME ": can't allocate memory\n");
+                rc = -ENOMEM;
+                goto errout;
+        }
+
+        memset(iface, 0, sizeof(*iface));
+        adapter = &iface->adapter;
+        i2c_set_adapdata(adapter, iface);
+        snprintf(adapter->name, I2C_NAME_SIZE, "SCx200 ACB%d", index);
+        adapter->owner = THIS_MODULE;
+        adapter->id = I2C_ALGO_SMBUS;
+        adapter->algo = &scx200_acb_algorithm;
+        adapter->class = I2C_CLASS_HWMON;
+
+        init_MUTEX(&iface->sem);
+
+        snprintf(description, sizeof(description), "NatSemi SCx200 ACCESS.bus [%s]", adapter->name);
+        if (request_region(base, 8, description) == 0) {
+                dev_err(&adapter->dev, "can't allocate io 0x%x-0x%x\n",
+                        base, base + 8-1);
+                rc = -EBUSY;
+                goto errout;
+        }
+        iface->base = base;
+
+        rc = scx200_acb_probe(iface);
+        if (rc) {
+                dev_warn(&adapter->dev, "probe failed\n");
+                goto errout;
+        }
+
+        scx200_acb_reset(iface);
+
+        if (i2c_add_adapter(adapter) < 0) {
+                dev_err(&adapter->dev, "failed to register\n");
+                rc = -ENODEV;
+                goto errout;
+        }
+
+        lock_kernel();
+        iface->next = scx200_acb_list;
+        scx200_acb_list = iface;
+        unlock_kernel();
+
+        return 0;
+
+ errout:
+        if (iface) {
+                if (iface->base)
+                        release_region(iface->base, 8);
+                kfree(iface);
+        }
+        return rc;
+}
+
+static struct pci_device_id scx200[] = {
+        { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SCx200_BRIDGE) },
+        { PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SC1100_BRIDGE) },
+        { },
+};
+
+static int __init scx200_acb_init(void)
+{
+        int i;
+        int rc;
+
+        pr_debug(NAME ": NatSemi SCx200 ACCESS.bus Driver\n");
+
+        /* Verify that this really is a SCx200 processor */
+        if (pci_dev_present(scx200) == 0)
+                return -ENODEV;
+
+        rc = -ENXIO;
+        for (i = 0; i < MAX_DEVICES; ++i) {
+                if (base[i] > 0)
+                        rc = scx200_acb_create(base[i], i);
+        }
+        if (scx200_acb_list)
+                return 0;
+        return rc;
+}
+
+static void __exit scx200_acb_cleanup(void)
+{
+        struct scx200_acb_iface *iface;
+        lock_kernel();
+        while ((iface = scx200_acb_list) != NULL) {
+                scx200_acb_list = iface->next;
+                unlock_kernel();
+
+                i2c_del_adapter(&iface->adapter);
+                release_region(iface->base, 8);
+                kfree(iface);
+                lock_kernel();
+        }
+        unlock_kernel();
+}
+
+module_init(scx200_acb_init);
+module_exit(scx200_acb_cleanup);
+
+/*
+    Local variables:
+        compile-command: "make -k -C ../.. SUBDIRS=drivers/i2c modules"
+        c-basic-offset: 8
+    End:
+*/
+
diff --git a/drivers/i2c/busses/scx200_i2c.c b/drivers/i2c/busses/scx200_i2c.c
new file mode 100644
index 000000000000..27fbfecc414f
--- /dev/null
+++ b/drivers/i2c/busses/scx200_i2c.c
@@ -0,0 +1,131 @@
+/* linux/drivers/i2c/scx200_i2c.c 
+
+   Copyright (c) 2001,2002 Christer Weinigel <wingel@nano-system.com>
+
+   National Semiconductor SCx200 I2C bus on GPIO pins
+
+   Based on i2c-velleman.c Copyright (C) 1995-96, 2000 Simon G. Vogl
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+   
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+   
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.                 
+*/
+
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+#include <linux/i2c-algo-bit.h>
+#include <asm/io.h>
+
+#include <linux/scx200_gpio.h>
+
+#define NAME "scx200_i2c"
+
+MODULE_AUTHOR("Christer Weinigel <wingel@nano-system.com>");
+MODULE_DESCRIPTION("NatSemi SCx200 I2C Driver");
+MODULE_LICENSE("GPL");
+
+static int scl = CONFIG_SCx200_I2C_SCL;
+static int sda = CONFIG_SCx200_I2C_SDA;
+
+module_param(scl, int, 0);
+MODULE_PARM_DESC(scl, "GPIO line for SCL");
+module_param(sda, int, 0);
+MODULE_PARM_DESC(sda, "GPIO line for SDA");
+
+static void scx200_i2c_setscl(void *data, int state)
+{
+        scx200_gpio_set(scl, state);
+}
+
+static void scx200_i2c_setsda(void *data, int state)
+{
+        scx200_gpio_set(sda, state);
+} 
+
+static int scx200_i2c_getscl(void *data)
+{
+        return scx200_gpio_get(scl);
+}
+
+static int scx200_i2c_getsda(void *data)
+{
+        return scx200_gpio_get(sda);
+}
+
+/* ------------------------------------------------------------------------
+ * Encapsulate the above functions in the correct operations structure.
+ * This is only done when more than one hardware adapter is supported.
+ */
+
+static struct i2c_algo_bit_data scx200_i2c_data = {
+        NULL,
+        scx200_i2c_setsda,
+        scx200_i2c_setscl,
+        scx200_i2c_getsda,
+        scx200_i2c_getscl,
+        10, 10, 100,            /* waits, timeout */
+};
+
+static struct i2c_adapter scx200_i2c_ops = {
+        .owner             = THIS_MODULE,
+        .algo_data         = &scx200_i2c_data,
+        .name   = "NatSemi SCx200 I2C",
+};
+
+static int scx200_i2c_init(void)
+{
+        pr_debug(NAME ": NatSemi SCx200 I2C Driver\n");
+
+        if (!scx200_gpio_present()) {
+                printk(KERN_ERR NAME ": no SCx200 gpio pins available\n");
+                return -ENODEV;
+        }
+
+        pr_debug(NAME ": SCL=GPIO%02u, SDA=GPIO%02u\n", scl, sda);
+
+        if (scl == -1 || sda == -1 || scl == sda) {
+                printk(KERN_ERR NAME ": scl and sda must be specified\n");
+                return -EINVAL;
+        }
+
+        /* Configure GPIOs as open collector outputs */
+        scx200_gpio_configure(scl, ~2, 5);
+        scx200_gpio_configure(sda, ~2, 5);
+
+        if (i2c_bit_add_bus(&scx200_i2c_ops) < 0) {
+                printk(KERN_ERR NAME ": adapter %s registration failed\n", 
+                       scx200_i2c_ops.name);
+                return -ENODEV;
+        }
+        
+        return 0;
+}
+
+static void scx200_i2c_cleanup(void)
+{
+        i2c_bit_del_bus(&scx200_i2c_ops);
+}
+
+module_init(scx200_i2c_init);
+module_exit(scx200_i2c_cleanup);
+
+/*
+    Local variables:
+        compile-command: "make -k -C ../.. SUBDIRS=drivers/i2c modules"
+        c-basic-offset: 8
+    End:
+*/