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authorRussell King <rmk+kernel@arm.linux.org.uk>2013-05-16 16:39:12 -0400
committerWolfram Sang <wsa@the-dreams.de>2013-06-05 17:06:48 -0400
commit4243fa0bad551b8c8d4ff7104e8fd557ae848845 (patch)
tree0c1ed68b9ed3963663dc71ba093d83b47318e3ba /drivers/i2c/busses
parent3420afbc06058c9c13f7d69cf48b9d5429db6bd9 (diff)
I2C: mv64xxx: fix race between FSM/interrupt and process context
Asking for a multi-part message to be handled by this driver is racy; it has been observed that the following sequence is possible with this driver: - send start - send address + write - send data - send (repeated) start - send address + write - send (repeated) start - send address + read - unrecoverable bus hang (except by system reset) The problem is that the interrupt handling sees the next event after the first repeated start is sent - the IFLG bit is set in the register even though INTEN is disabled. Let's fix this by moving all of the message processing into interrupt context, rather than having it partly in IRQ and partly in process context. This allows us to move immediately to the next message in the interrupt handler and get on with the transfer, rather than incuring a couple of scheduling switches to get the next message. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Mark A. Greer <mgreer@animalcreek.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Diffstat (limited to 'drivers/i2c/busses')
-rw-r--r--drivers/i2c/busses/i2c-mv64xxx.c54
1 files changed, 34 insertions, 20 deletions
diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c
index bb37e14f3fbd..6356439454ee 100644
--- a/drivers/i2c/busses/i2c-mv64xxx.c
+++ b/drivers/i2c/busses/i2c-mv64xxx.c
@@ -86,6 +86,8 @@ enum {
86}; 86};
87 87
88struct mv64xxx_i2c_data { 88struct mv64xxx_i2c_data {
89 struct i2c_msg *msgs;
90 int num_msgs;
89 int irq; 91 int irq;
90 u32 state; 92 u32 state;
91 u32 action; 93 u32 action;
@@ -194,7 +196,7 @@ mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
194 if ((drv_data->bytes_left == 0) 196 if ((drv_data->bytes_left == 0)
195 || (drv_data->aborting 197 || (drv_data->aborting
196 && (drv_data->byte_posn != 0))) { 198 && (drv_data->byte_posn != 0))) {
197 if (drv_data->send_stop) { 199 if (drv_data->send_stop || drv_data->aborting) {
198 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP; 200 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
199 drv_data->state = MV64XXX_I2C_STATE_IDLE; 201 drv_data->state = MV64XXX_I2C_STATE_IDLE;
200 } else { 202 } else {
@@ -271,12 +273,25 @@ mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
271{ 273{
272 switch(drv_data->action) { 274 switch(drv_data->action) {
273 case MV64XXX_I2C_ACTION_SEND_RESTART: 275 case MV64XXX_I2C_ACTION_SEND_RESTART:
276 /* We should only get here if we have further messages */
277 BUG_ON(drv_data->num_msgs == 0);
278
274 drv_data->cntl_bits |= MV64XXX_I2C_REG_CONTROL_START; 279 drv_data->cntl_bits |= MV64XXX_I2C_REG_CONTROL_START;
275 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
276 writel(drv_data->cntl_bits, 280 writel(drv_data->cntl_bits,
277 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL); 281 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
278 drv_data->block = 0; 282
279 wake_up(&drv_data->waitq); 283 drv_data->msgs++;
284 drv_data->num_msgs--;
285
286 /* Setup for the next message */
287 mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs);
288
289 /*
290 * We're never at the start of the message here, and by this
291 * time it's already too late to do any protocol mangling.
292 * Thankfully, do not advertise support for that feature.
293 */
294 drv_data->send_stop = drv_data->num_msgs == 1;
280 break; 295 break;
281 296
282 case MV64XXX_I2C_ACTION_CONTINUE: 297 case MV64XXX_I2C_ACTION_CONTINUE:
@@ -412,20 +427,15 @@ mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
412 427
413static int 428static int
414mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg, 429mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg,
415 int is_first, int is_last) 430 int is_last)
416{ 431{
417 unsigned long flags; 432 unsigned long flags;
418 433
419 spin_lock_irqsave(&drv_data->lock, flags); 434 spin_lock_irqsave(&drv_data->lock, flags);
420 mv64xxx_i2c_prepare_for_io(drv_data, msg); 435 mv64xxx_i2c_prepare_for_io(drv_data, msg);
421 436
422 if (is_first) { 437 drv_data->action = MV64XXX_I2C_ACTION_SEND_START;
423 drv_data->action = MV64XXX_I2C_ACTION_SEND_START; 438 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
424 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
425 } else {
426 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
427 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
428 }
429 439
430 drv_data->send_stop = is_last; 440 drv_data->send_stop = is_last;
431 drv_data->block = 1; 441 drv_data->block = 1;
@@ -453,16 +463,20 @@ static int
453mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 463mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
454{ 464{
455 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap); 465 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
456 int i, rc; 466 int rc, ret = num;
457 467
458 for (i = 0; i < num; i++) { 468 BUG_ON(drv_data->msgs != NULL);
459 rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[i], 469 drv_data->msgs = msgs;
460 i == 0, i + 1 == num); 470 drv_data->num_msgs = num;
461 if (rc < 0) 471
462 return rc; 472 rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[0], num == 1);
463 } 473 if (rc < 0)
474 ret = rc;
475
476 drv_data->num_msgs = 0;
477 drv_data->msgs = NULL;
464 478
465 return num; 479 return ret;
466} 480}
467 481
468static const struct i2c_algorithm mv64xxx_i2c_algo = { 482static const struct i2c_algorithm mv64xxx_i2c_algo = {