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authoraddy ke <addy.ke@rock-chips.com>2014-10-14 02:09:21 -0400
committerWolfram Sang <wsa@the-dreams.de>2014-11-10 09:56:26 -0500
commit0285f8f5fd7cf7f458e13d9189eb735dacc244b5 (patch)
treea987fb295469a367b9ae1753a5101eec33a2c425 /drivers/i2c/busses/i2c-tegra.c
parent900ef800a2a4c08aa28af4785a5b2d5d7e199103 (diff)
i2c: rk3x: adjust the LOW divison based on characteristics of SCL
As show in I2C specification: - Standard-mode: the minimum HIGH period of the scl clock is 4.0us the minimum LOW period of the scl clock is 4.7us - Fast-mode: the minimum HIGH period of the scl clock is 0.6us the minimum LOW period of the scl clock is 1.3us I have measured i2c SCL waveforms in fast-mode by oscilloscope on rk3288-pinky board. the LOW period of the scl clock is 1.3us. It is so critical that we must adjust LOW division to increase the LOW period of the scl clock. Thanks Doug for the suggestion about division formulas. Signed-off-by: Addy Ke <addy.ke@rock-chips.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Max Schwarz <max.schwarz@online.de> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
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