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authorMagnus Damm <damm@igel.co.jp>2008-08-27 05:33:56 -0400
committerPaul Mundt <lethal@linux-sh.org>2008-09-05 01:54:13 -0400
commit4eb00c9f92202a759aadbce73ea4a947b639b5e6 (patch)
treeb1c94bcc53924b6a90c3ed82ea645bfa482c923f /drivers/i2c/busses/i2c-sh_mobile.c
parentdbce1f649e3d22aa7ddc0fdbfa6a7470047b61bd (diff)
i2c: fix i2c-sh_mobile timing issues
This patch teaches the i2c-sh_mobile driver to make use of wait irqs. Without this patch only dte irqs are used which may lead to overruns and cases of missing stop and extra bytes being read on the i2c bus. Use of wait irqs forces the hardware to pause and wait until the cpu is ready. Polling is also reworked in this patch to fix ms delay issues. Verified with bus analyzer and tested on MigoR and AP325RXA boards. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'drivers/i2c/busses/i2c-sh_mobile.c')
-rw-r--r--drivers/i2c/busses/i2c-sh_mobile.c271
1 files changed, 208 insertions, 63 deletions
diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
index 840e634fa31f..640cbb237328 100644
--- a/drivers/i2c/busses/i2c-sh_mobile.c
+++ b/drivers/i2c/busses/i2c-sh_mobile.c
@@ -31,13 +31,84 @@
31#include <linux/clk.h> 31#include <linux/clk.h>
32#include <linux/io.h> 32#include <linux/io.h>
33 33
34/* Transmit operation: */
35/* */
36/* 0 byte transmit */
37/* BUS: S A8 ACK P */
38/* IRQ: DTE WAIT */
39/* ICIC: */
40/* ICCR: 0x94 0x90 */
41/* ICDR: A8 */
42/* */
43/* 1 byte transmit */
44/* BUS: S A8 ACK D8(1) ACK P */
45/* IRQ: DTE WAIT WAIT */
46/* ICIC: -DTE */
47/* ICCR: 0x94 0x90 */
48/* ICDR: A8 D8(1) */
49/* */
50/* 2 byte transmit */
51/* BUS: S A8 ACK D8(1) ACK D8(2) ACK P */
52/* IRQ: DTE WAIT WAIT WAIT */
53/* ICIC: -DTE */
54/* ICCR: 0x94 0x90 */
55/* ICDR: A8 D8(1) D8(2) */
56/* */
57/* 3 bytes or more, +---------+ gets repeated */
58/* */
59/* */
60/* Receive operation: */
61/* */
62/* 0 byte receive - not supported since slave may hold SDA low */
63/* */
64/* 1 byte receive [TX] | [RX] */
65/* BUS: S A8 ACK | D8(1) ACK P */
66/* IRQ: DTE WAIT | WAIT DTE */
67/* ICIC: -DTE | +DTE */
68/* ICCR: 0x94 0x81 | 0xc0 */
69/* ICDR: A8 | D8(1) */
70/* */
71/* 2 byte receive [TX]| [RX] */
72/* BUS: S A8 ACK | D8(1) ACK D8(2) ACK P */
73/* IRQ: DTE WAIT | WAIT WAIT DTE */
74/* ICIC: -DTE | +DTE */
75/* ICCR: 0x94 0x81 | 0xc0 */
76/* ICDR: A8 | D8(1) D8(2) */
77/* */
78/* 3 byte receive [TX] | [RX] */
79/* BUS: S A8 ACK | D8(1) ACK D8(2) ACK D8(3) ACK P */
80/* IRQ: DTE WAIT | WAIT WAIT WAIT DTE */
81/* ICIC: -DTE | +DTE */
82/* ICCR: 0x94 0x81 | 0xc0 */
83/* ICDR: A8 | D8(1) D8(2) D8(3) */
84/* */
85/* 4 bytes or more, this part is repeated +---------+ */
86/* */
87/* */
88/* Interrupt order and BUSY flag */
89/* ___ _ */
90/* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/ */
91/* SCL \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/ */
92/* */
93/* S D7 D6 D5 D4 D3 D2 D1 D0 P */
94/* ___ */
95/* WAIT IRQ ________________________________/ \___________ */
96/* TACK IRQ ____________________________________/ \_______ */
97/* DTE IRQ __________________________________________/ \_ */
98/* AL IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */
99/* _______________________________________________ */
100/* BUSY __/ \_ */
101/* */
102
34enum sh_mobile_i2c_op { 103enum sh_mobile_i2c_op {
35 OP_START = 0, 104 OP_START = 0,
36 OP_TX_ONLY, 105 OP_TX_FIRST,
106 OP_TX,
37 OP_TX_STOP, 107 OP_TX_STOP,
38 OP_TX_TO_RX, 108 OP_TX_TO_RX,
39 OP_RX_ONLY, 109 OP_RX,
40 OP_RX_STOP, 110 OP_RX_STOP,
111 OP_RX_STOP_DATA,
41}; 112};
42 113
43struct sh_mobile_i2c_data { 114struct sh_mobile_i2c_data {
@@ -127,25 +198,34 @@ static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
127 spin_lock_irqsave(&pd->lock, flags); 198 spin_lock_irqsave(&pd->lock, flags);
128 199
129 switch (op) { 200 switch (op) {
130 case OP_START: 201 case OP_START: /* issue start and trigger DTE interrupt */
131 iowrite8(0x94, ICCR(pd)); 202 iowrite8(0x94, ICCR(pd));
132 break; 203 break;
133 case OP_TX_ONLY: 204 case OP_TX_FIRST: /* disable DTE interrupt and write data */
205 iowrite8(ICIC_WAITE | ICIC_ALE | ICIC_TACKE, ICIC(pd));
134 iowrite8(data, ICDR(pd)); 206 iowrite8(data, ICDR(pd));
135 break; 207 break;
136 case OP_TX_STOP: 208 case OP_TX: /* write data */
137 iowrite8(data, ICDR(pd)); 209 iowrite8(data, ICDR(pd));
138 iowrite8(0x90, ICCR(pd));
139 iowrite8(ICIC_ALE | ICIC_TACKE, ICIC(pd));
140 break; 210 break;
141 case OP_TX_TO_RX: 211 case OP_TX_STOP: /* write data and issue a stop afterwards */
142 iowrite8(data, ICDR(pd)); 212 iowrite8(data, ICDR(pd));
213 iowrite8(0x90, ICCR(pd));
214 break;
215 case OP_TX_TO_RX: /* select read mode */
143 iowrite8(0x81, ICCR(pd)); 216 iowrite8(0x81, ICCR(pd));
144 break; 217 break;
145 case OP_RX_ONLY: 218 case OP_RX: /* just read data */
146 ret = ioread8(ICDR(pd)); 219 ret = ioread8(ICDR(pd));
147 break; 220 break;
148 case OP_RX_STOP: 221 case OP_RX_STOP: /* enable DTE interrupt, issue stop */
222 iowrite8(ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE,
223 ICIC(pd));
224 iowrite8(0xc0, ICCR(pd));
225 break;
226 case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
227 iowrite8(ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE,
228 ICIC(pd));
149 ret = ioread8(ICDR(pd)); 229 ret = ioread8(ICDR(pd));
150 iowrite8(0xc0, ICCR(pd)); 230 iowrite8(0xc0, ICCR(pd));
151 break; 231 break;
@@ -157,58 +237,120 @@ static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
157 return ret; 237 return ret;
158} 238}
159 239
240static int sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd)
241{
242 if (pd->pos == -1)
243 return 1;
244
245 return 0;
246}
247
248static int sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd)
249{
250 if (pd->pos == (pd->msg->len - 1))
251 return 1;
252
253 return 0;
254}
255
256static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd,
257 unsigned char *buf)
258{
259 switch (pd->pos) {
260 case -1:
261 *buf = (pd->msg->addr & 0x7f) << 1;
262 *buf |= (pd->msg->flags & I2C_M_RD) ? 1 : 0;
263 break;
264 default:
265 *buf = pd->msg->buf[pd->pos];
266 }
267}
268
269static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd)
270{
271 unsigned char data;
272
273 if (pd->pos == pd->msg->len)
274 return 1;
275
276 sh_mobile_i2c_get_data(pd, &data);
277
278 if (sh_mobile_i2c_is_last_byte(pd))
279 i2c_op(pd, OP_TX_STOP, data);
280 else if (sh_mobile_i2c_is_first_byte(pd))
281 i2c_op(pd, OP_TX_FIRST, data);
282 else
283 i2c_op(pd, OP_TX, data);
284
285 pd->pos++;
286 return 0;
287}
288
289static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
290{
291 unsigned char data;
292 int real_pos;
293
294 do {
295 if (pd->pos <= -1) {
296 sh_mobile_i2c_get_data(pd, &data);
297
298 if (sh_mobile_i2c_is_first_byte(pd))
299 i2c_op(pd, OP_TX_FIRST, data);
300 else
301 i2c_op(pd, OP_TX, data);
302 break;
303 }
304
305 if (pd->pos == 0) {
306 i2c_op(pd, OP_TX_TO_RX, 0);
307 break;
308 }
309
310 real_pos = pd->pos - 2;
311
312 if (pd->pos == pd->msg->len) {
313 if (real_pos < 0) {
314 i2c_op(pd, OP_RX_STOP, 0);
315 break;
316 }
317 data = i2c_op(pd, OP_RX_STOP_DATA, 0);
318 } else
319 data = i2c_op(pd, OP_RX, 0);
320
321 pd->msg->buf[real_pos] = data;
322 } while (0);
323
324 pd->pos++;
325 return pd->pos == (pd->msg->len + 2);
326}
327
160static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id) 328static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
161{ 329{
162 struct platform_device *dev = dev_id; 330 struct platform_device *dev = dev_id;
163 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev); 331 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
164 struct i2c_msg *msg = pd->msg; 332 unsigned char sr;
165 unsigned char data, sr; 333 int wakeup;
166 int wakeup = 0;
167 334
168 sr = ioread8(ICSR(pd)); 335 sr = ioread8(ICSR(pd));
169 pd->sr |= sr; 336 pd->sr |= sr; /* remember state */
170 337
171 dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr, 338 dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
172 (msg->flags & I2C_M_RD) ? "read" : "write", 339 (pd->msg->flags & I2C_M_RD) ? "read" : "write",
173 pd->pos, msg->len); 340 pd->pos, pd->msg->len);
174 341
175 if (sr & (ICSR_AL | ICSR_TACK)) { 342 if (sr & (ICSR_AL | ICSR_TACK)) {
176 iowrite8(0, ICIC(pd)); /* disable interrupts */ 343 /* don't interrupt transaction - continue to issue stop */
177 wakeup = 1; 344 iowrite8(sr & ~(ICSR_AL | ICSR_TACK), ICSR(pd));
178 goto do_wakeup; 345 wakeup = 0;
179 } 346 } else if (pd->msg->flags & I2C_M_RD)
347 wakeup = sh_mobile_i2c_isr_rx(pd);
348 else
349 wakeup = sh_mobile_i2c_isr_tx(pd);
180 350
181 if (pd->pos == msg->len) { 351 if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
182 i2c_op(pd, OP_RX_ONLY, 0); 352 iowrite8(sr & ~ICSR_WAIT, ICSR(pd));
183 wakeup = 1;
184 goto do_wakeup;
185 }
186 353
187 if (pd->pos == -1) {
188 data = (msg->addr & 0x7f) << 1;
189 data |= (msg->flags & I2C_M_RD) ? 1 : 0;
190 } else
191 data = msg->buf[pd->pos];
192
193 if ((pd->pos == -1) || !(msg->flags & I2C_M_RD)) {
194 if (msg->flags & I2C_M_RD)
195 i2c_op(pd, OP_TX_TO_RX, data);
196 else if (pd->pos == (msg->len - 1)) {
197 i2c_op(pd, OP_TX_STOP, data);
198 wakeup = 1;
199 } else
200 i2c_op(pd, OP_TX_ONLY, data);
201 } else {
202 if (pd->pos == (msg->len - 1))
203 data = i2c_op(pd, OP_RX_STOP, 0);
204 else
205 data = i2c_op(pd, OP_RX_ONLY, 0);
206
207 msg->buf[pd->pos] = data;
208 }
209 pd->pos++;
210
211 do_wakeup:
212 if (wakeup) { 354 if (wakeup) {
213 pd->sr |= SW_DONE; 355 pd->sr |= SW_DONE;
214 wake_up(&pd->wait); 356 wake_up(&pd->wait);
@@ -219,6 +361,11 @@ static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
219 361
220static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg) 362static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg)
221{ 363{
364 if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) {
365 dev_err(pd->dev, "Unsupported zero length i2c read\n");
366 return -EIO;
367 }
368
222 /* Initialize channel registers */ 369 /* Initialize channel registers */
223 iowrite8(ioread8(ICCR(pd)) & ~ICCR_ICE, ICCR(pd)); 370 iowrite8(ioread8(ICCR(pd)) & ~ICCR_ICE, ICCR(pd));
224 371
@@ -233,9 +380,8 @@ static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg)
233 pd->pos = -1; 380 pd->pos = -1;
234 pd->sr = 0; 381 pd->sr = 0;
235 382
236 /* Enable all interrupts except wait */ 383 /* Enable all interrupts to begin with */
237 iowrite8(ioread8(ICIC(pd)) | ICIC_ALE | ICIC_TACKE | ICIC_DTEE, 384 iowrite8(ICIC_WAITE | ICIC_ALE | ICIC_TACKE | ICIC_DTEE, ICIC(pd));
238 ICIC(pd));
239 return 0; 385 return 0;
240} 386}
241 387
@@ -268,25 +414,18 @@ static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
268 if (!k) 414 if (!k)
269 dev_err(pd->dev, "Transfer request timed out\n"); 415 dev_err(pd->dev, "Transfer request timed out\n");
270 416
271 retry_count = 10; 417 retry_count = 1000;
272again: 418again:
273 val = ioread8(ICSR(pd)); 419 val = ioread8(ICSR(pd));
274 420
275 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr); 421 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
276 422
277 if ((val | pd->sr) & (ICSR_TACK | ICSR_AL)) {
278 err = -EIO;
279 break;
280 }
281
282 /* the interrupt handler may wake us up before the 423 /* the interrupt handler may wake us up before the
283 * transfer is finished, so poll the hardware 424 * transfer is finished, so poll the hardware
284 * until we're done. 425 * until we're done.
285 */ 426 */
286 427 if (val & ICSR_BUSY) {
287 if (!(!(val & ICSR_BUSY) && (val & ICSR_SCLM) && 428 udelay(10);
288 (val & ICSR_SDAM))) {
289 msleep(1);
290 if (retry_count--) 429 if (retry_count--)
291 goto again; 430 goto again;
292 431
@@ -294,6 +433,12 @@ again:
294 dev_err(pd->dev, "Polling timed out\n"); 433 dev_err(pd->dev, "Polling timed out\n");
295 break; 434 break;
296 } 435 }
436
437 /* handle missing acknowledge and arbitration lost */
438 if ((val | pd->sr) & (ICSR_TACK | ICSR_AL)) {
439 err = -EIO;
440 break;
441 }
297 } 442 }
298 443
299 deactivate_ch(pd); 444 deactivate_ch(pd);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-15 15:57:44 -0500