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authorLinus Torvalds <torvalds@woody.linux-foundation.org>2007-02-19 16:18:39 -0500
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-02-19 16:18:39 -0500
commit59b8175c771040afcd4ad67022b0cc80c216b866 (patch)
tree4ef5935bee1e342716d49b9d4b99e3fa835526e6 /drivers/i2c/busses/i2c-pxa.c
parent920841d8d1d61bc12b43f95a579a5374f6d98f81 (diff)
parent3b0eb4a195a124567cd0dd6f700f8388def542c6 (diff)
Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (117 commits) [ARM] 4058/2: iop32x: set ->broken_parity_status on n2100 onboard r8169 ports [ARM] 4140/1: AACI stability add ac97 timeout and retries [ARM] 4139/1: AACI record support [ARM] 4138/1: AACI: multiple channel support for IRQ handling [ARM] 4211/1: Provide a defconfig for ns9xxx [ARM] 4210/1: base for new machine type "NetSilicon NS9360" [ARM] 4222/1: S3C2443: Remove reference to missing S3C2443_PM [ARM] 4221/1: S3C2443: DMA support [ARM] 4220/1: S3C24XX: DMA system initialised from sysdev [ARM] 4219/1: S3C2443: DMA source definitions [ARM] 4218/1: S3C2412: fix CONFIG_CPU_S3C2412_ONLY wrt to S3C2443 [ARM] 4217/1: S3C24XX: remove the dma channel show at startup [ARM] 4090/2: avoid clash between PXA and SA1111 defines [ARM] 4216/1: add .gitignore entries for ARM specific files [ARM] 4214/2: S3C2410: Add Armzone QT2410 [ARM] 4215/1: s3c2410 usb device: per-platform vbus_draw [ARM] 4213/1: S3C2410 - Update definition of ADCTSC_XY_PST [ARM] 4098/1: ARM: rtc_lock only used with rtc_cmos [ARM] 4137/1: Add kexec support [ARM] 4201/1: SMP barriers pair needed for the secondary boot process ... Fix up conflict due to typedef removal in sound/arm/aaci.h
Diffstat (limited to 'drivers/i2c/busses/i2c-pxa.c')
-rw-r--r--drivers/i2c/busses/i2c-pxa.c241
1 files changed, 164 insertions, 77 deletions
diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c
index c3b1567c852a..14e83d0aac8c 100644
--- a/drivers/i2c/busses/i2c-pxa.c
+++ b/drivers/i2c/busses/i2c-pxa.c
@@ -34,6 +34,7 @@
34 34
35#include <asm/hardware.h> 35#include <asm/hardware.h>
36#include <asm/irq.h> 36#include <asm/irq.h>
37#include <asm/io.h>
37#include <asm/arch/i2c.h> 38#include <asm/arch/i2c.h>
38#include <asm/arch/pxa-regs.h> 39#include <asm/arch/pxa-regs.h>
39 40
@@ -54,8 +55,21 @@ struct pxa_i2c {
54 unsigned int irqlogidx; 55 unsigned int irqlogidx;
55 u32 isrlog[32]; 56 u32 isrlog[32];
56 u32 icrlog[32]; 57 u32 icrlog[32];
58
59 void __iomem *reg_base;
60
61 unsigned long iobase;
62 unsigned long iosize;
63
64 int irq;
57}; 65};
58 66
67#define _IBMR(i2c) ((i2c)->reg_base + 0)
68#define _IDBR(i2c) ((i2c)->reg_base + 8)
69#define _ICR(i2c) ((i2c)->reg_base + 0x10)
70#define _ISR(i2c) ((i2c)->reg_base + 0x18)
71#define _ISAR(i2c) ((i2c)->reg_base + 0x20)
72
59/* 73/*
60 * I2C Slave mode address 74 * I2C Slave mode address
61 */ 75 */
@@ -130,7 +144,8 @@ static unsigned int i2c_debug = DEBUG;
130 144
131static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname) 145static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
132{ 146{
133 dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno, ISR, ICR, IBMR); 147 dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno,
148 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
134} 149}
135 150
136#define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __FUNCTION__) 151#define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __FUNCTION__)
@@ -153,7 +168,7 @@ static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
153 printk("i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n", 168 printk("i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n",
154 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr); 169 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
155 printk("i2c: ICR: %08x ISR: %08x\n" 170 printk("i2c: ICR: %08x ISR: %08x\n"
156 "i2c: log: ", ICR, ISR); 171 "i2c: log: ", readl(_ICR(i2c)), readl(_ISR(i2c)));
157 for (i = 0; i < i2c->irqlogidx; i++) 172 for (i = 0; i < i2c->irqlogidx; i++)
158 printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]); 173 printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
159 printk("\n"); 174 printk("\n");
@@ -161,7 +176,7 @@ static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
161 176
162static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c) 177static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
163{ 178{
164 return !(ICR & ICR_SCLE); 179 return !(readl(_ICR(i2c)) & ICR_SCLE);
165} 180}
166 181
167static void i2c_pxa_abort(struct pxa_i2c *i2c) 182static void i2c_pxa_abort(struct pxa_i2c *i2c)
@@ -173,28 +188,29 @@ static void i2c_pxa_abort(struct pxa_i2c *i2c)
173 return; 188 return;
174 } 189 }
175 190
176 while (time_before(jiffies, timeout) && (IBMR & 0x1) == 0) { 191 while (time_before(jiffies, timeout) && (readl(_IBMR(i2c)) & 0x1) == 0) {
177 unsigned long icr = ICR; 192 unsigned long icr = readl(_ICR(i2c));
178 193
179 icr &= ~ICR_START; 194 icr &= ~ICR_START;
180 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB; 195 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
181 196
182 ICR = icr; 197 writel(icr, _ICR(i2c));
183 198
184 show_state(i2c); 199 show_state(i2c);
185 200
186 msleep(1); 201 msleep(1);
187 } 202 }
188 203
189 ICR &= ~(ICR_MA | ICR_START | ICR_STOP); 204 writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
205 _ICR(i2c));
190} 206}
191 207
192static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c) 208static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
193{ 209{
194 int timeout = DEF_TIMEOUT; 210 int timeout = DEF_TIMEOUT;
195 211
196 while (timeout-- && ISR & (ISR_IBB | ISR_UB)) { 212 while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
197 if ((ISR & ISR_SAD) != 0) 213 if ((readl(_ISR(i2c)) & ISR_SAD) != 0)
198 timeout += 4; 214 timeout += 4;
199 215
200 msleep(2); 216 msleep(2);
@@ -214,9 +230,9 @@ static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
214 while (time_before(jiffies, timeout)) { 230 while (time_before(jiffies, timeout)) {
215 if (i2c_debug > 1) 231 if (i2c_debug > 1)
216 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n", 232 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
217 __func__, (long)jiffies, ISR, ICR, IBMR); 233 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
218 234
219 if (ISR & ISR_SAD) { 235 if (readl(_ISR(i2c)) & ISR_SAD) {
220 if (i2c_debug > 0) 236 if (i2c_debug > 0)
221 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__); 237 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
222 goto out; 238 goto out;
@@ -226,7 +242,7 @@ static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
226 * quick check of the i2c lines themselves to ensure they've 242 * quick check of the i2c lines themselves to ensure they've
227 * gone high... 243 * gone high...
228 */ 244 */
229 if ((ISR & (ISR_UB | ISR_IBB)) == 0 && IBMR == 3) { 245 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) {
230 if (i2c_debug > 0) 246 if (i2c_debug > 0)
231 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__); 247 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
232 return 1; 248 return 1;
@@ -246,7 +262,7 @@ static int i2c_pxa_set_master(struct pxa_i2c *i2c)
246 if (i2c_debug) 262 if (i2c_debug)
247 dev_dbg(&i2c->adap.dev, "setting to bus master\n"); 263 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
248 264
249 if ((ISR & (ISR_UB | ISR_IBB)) != 0) { 265 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) {
250 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__); 266 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
251 if (!i2c_pxa_wait_master(i2c)) { 267 if (!i2c_pxa_wait_master(i2c)) {
252 dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__); 268 dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
@@ -254,7 +270,7 @@ static int i2c_pxa_set_master(struct pxa_i2c *i2c)
254 } 270 }
255 } 271 }
256 272
257 ICR |= ICR_SCLE; 273 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
258 return 0; 274 return 0;
259} 275}
260 276
@@ -270,11 +286,11 @@ static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
270 while (time_before(jiffies, timeout)) { 286 while (time_before(jiffies, timeout)) {
271 if (i2c_debug > 1) 287 if (i2c_debug > 1)
272 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n", 288 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
273 __func__, (long)jiffies, ISR, ICR, IBMR); 289 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
274 290
275 if ((ISR & (ISR_UB|ISR_IBB)) == 0 || 291 if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 ||
276 (ISR & ISR_SAD) != 0 || 292 (readl(_ISR(i2c)) & ISR_SAD) != 0 ||
277 (ICR & ICR_SCLE) == 0) { 293 (readl(_ICR(i2c)) & ICR_SCLE) == 0) {
278 if (i2c_debug > 1) 294 if (i2c_debug > 1)
279 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__); 295 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
280 return 1; 296 return 1;
@@ -302,9 +318,9 @@ static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
302 /* we need to wait for the stop condition to end */ 318 /* we need to wait for the stop condition to end */
303 319
304 /* if we where in stop, then clear... */ 320 /* if we where in stop, then clear... */
305 if (ICR & ICR_STOP) { 321 if (readl(_ICR(i2c)) & ICR_STOP) {
306 udelay(100); 322 udelay(100);
307 ICR &= ~ICR_STOP; 323 writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
308 } 324 }
309 325
310 if (!i2c_pxa_wait_slave(i2c)) { 326 if (!i2c_pxa_wait_slave(i2c)) {
@@ -314,12 +330,12 @@ static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
314 } 330 }
315 } 331 }
316 332
317 ICR &= ~(ICR_STOP|ICR_ACKNAK|ICR_MA); 333 writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
318 ICR &= ~ICR_SCLE; 334 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
319 335
320 if (i2c_debug) { 336 if (i2c_debug) {
321 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", ICR, ISR); 337 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c)));
322 decode_ICR(ICR); 338 decode_ICR(readl(_ICR(i2c)));
323 } 339 }
324} 340}
325#else 341#else
@@ -334,24 +350,24 @@ static void i2c_pxa_reset(struct pxa_i2c *i2c)
334 i2c_pxa_abort(i2c); 350 i2c_pxa_abort(i2c);
335 351
336 /* reset according to 9.8 */ 352 /* reset according to 9.8 */
337 ICR = ICR_UR; 353 writel(ICR_UR, _ICR(i2c));
338 ISR = I2C_ISR_INIT; 354 writel(I2C_ISR_INIT, _ISR(i2c));
339 ICR &= ~ICR_UR; 355 writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
340 356
341 ISAR = i2c->slave_addr; 357 writel(i2c->slave_addr, _ISAR(i2c));
342 358
343 /* set control register values */ 359 /* set control register values */
344 ICR = I2C_ICR_INIT; 360 writel(I2C_ICR_INIT, _ICR(i2c));
345 361
346#ifdef CONFIG_I2C_PXA_SLAVE 362#ifdef CONFIG_I2C_PXA_SLAVE
347 dev_info(&i2c->adap.dev, "Enabling slave mode\n"); 363 dev_info(&i2c->adap.dev, "Enabling slave mode\n");
348 ICR |= ICR_SADIE | ICR_ALDIE | ICR_SSDIE; 364 writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
349#endif 365#endif
350 366
351 i2c_pxa_set_slave(i2c, 0); 367 i2c_pxa_set_slave(i2c, 0);
352 368
353 /* enable unit */ 369 /* enable unit */
354 ICR |= ICR_IUE; 370 writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
355 udelay(100); 371 udelay(100);
356} 372}
357 373
@@ -371,19 +387,19 @@ static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
371 if (i2c->slave != NULL) 387 if (i2c->slave != NULL)
372 ret = i2c->slave->read(i2c->slave->data); 388 ret = i2c->slave->read(i2c->slave->data);
373 389
374 IDBR = ret; 390 writel(ret, _IDBR(i2c));
375 ICR |= ICR_TB; /* allow next byte */ 391 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); /* allow next byte */
376 } 392 }
377} 393}
378 394
379static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr) 395static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
380{ 396{
381 unsigned int byte = IDBR; 397 unsigned int byte = readl(_IDBR(i2c));
382 398
383 if (i2c->slave != NULL) 399 if (i2c->slave != NULL)
384 i2c->slave->write(i2c->slave->data, byte); 400 i2c->slave->write(i2c->slave->data, byte);
385 401
386 ICR |= ICR_TB; 402 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
387} 403}
388 404
389static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr) 405static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
@@ -403,13 +419,13 @@ static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
403 * start condition... if this happens, we'd better back off 419 * start condition... if this happens, we'd better back off
404 * and stop holding the poor thing up 420 * and stop holding the poor thing up
405 */ 421 */
406 ICR &= ~(ICR_START|ICR_STOP); 422 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
407 ICR |= ICR_TB; 423 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
408 424
409 timeout = 0x10000; 425 timeout = 0x10000;
410 426
411 while (1) { 427 while (1) {
412 if ((IBMR & 2) == 2) 428 if ((readl(_IBMR(i2c)) & 2) == 2)
413 break; 429 break;
414 430
415 timeout--; 431 timeout--;
@@ -420,7 +436,7 @@ static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
420 } 436 }
421 } 437 }
422 438
423 ICR &= ~ICR_SCLE; 439 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
424} 440}
425 441
426static void i2c_pxa_slave_stop(struct pxa_i2c *i2c) 442static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
@@ -447,14 +463,14 @@ static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
447 if (isr & ISR_BED) { 463 if (isr & ISR_BED) {
448 /* what should we do here? */ 464 /* what should we do here? */
449 } else { 465 } else {
450 IDBR = 0; 466 writel(0, _IDBR(i2c));
451 ICR |= ICR_TB; 467 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
452 } 468 }
453} 469}
454 470
455static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr) 471static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
456{ 472{
457 ICR |= ICR_TB | ICR_ACKNAK; 473 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
458} 474}
459 475
460static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr) 476static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
@@ -466,13 +482,13 @@ static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
466 * start condition... if this happens, we'd better back off 482 * start condition... if this happens, we'd better back off
467 * and stop holding the poor thing up 483 * and stop holding the poor thing up
468 */ 484 */
469 ICR &= ~(ICR_START|ICR_STOP); 485 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
470 ICR |= ICR_TB | ICR_ACKNAK; 486 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
471 487
472 timeout = 0x10000; 488 timeout = 0x10000;
473 489
474 while (1) { 490 while (1) {
475 if ((IBMR & 2) == 2) 491 if ((readl(_IBMR(i2c)) & 2) == 2)
476 break; 492 break;
477 493
478 timeout--; 494 timeout--;
@@ -483,7 +499,7 @@ static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
483 } 499 }
484 } 500 }
485 501
486 ICR &= ~ICR_SCLE; 502 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
487} 503}
488 504
489static void i2c_pxa_slave_stop(struct pxa_i2c *i2c) 505static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
@@ -514,13 +530,13 @@ static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
514 /* 530 /*
515 * Step 1: target slave address into IDBR 531 * Step 1: target slave address into IDBR
516 */ 532 */
517 IDBR = i2c_pxa_addr_byte(i2c->msg); 533 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
518 534
519 /* 535 /*
520 * Step 2: initiate the write. 536 * Step 2: initiate the write.
521 */ 537 */
522 icr = ICR & ~(ICR_STOP | ICR_ALDIE); 538 icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
523 ICR = icr | ICR_START | ICR_TB; 539 writel(icr | ICR_START | ICR_TB, _ICR(i2c));
524} 540}
525 541
526/* 542/*
@@ -594,7 +610,7 @@ static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
594 610
595static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr) 611static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
596{ 612{
597 u32 icr = ICR & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB); 613 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
598 614
599 again: 615 again:
600 /* 616 /*
@@ -645,7 +661,7 @@ static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
645 /* 661 /*
646 * Write mode. Write the next data byte. 662 * Write mode. Write the next data byte.
647 */ 663 */
648 IDBR = i2c->msg->buf[i2c->msg_ptr++]; 664 writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));
649 665
650 icr |= ICR_ALDIE | ICR_TB; 666 icr |= ICR_ALDIE | ICR_TB;
651 667
@@ -675,7 +691,7 @@ static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
675 /* 691 /*
676 * Write the next address. 692 * Write the next address.
677 */ 693 */
678 IDBR = i2c_pxa_addr_byte(i2c->msg); 694 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
679 695
680 /* 696 /*
681 * And trigger a repeated start, and send the byte. 697 * And trigger a repeated start, and send the byte.
@@ -696,18 +712,18 @@ static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
696 712
697 i2c->icrlog[i2c->irqlogidx-1] = icr; 713 i2c->icrlog[i2c->irqlogidx-1] = icr;
698 714
699 ICR = icr; 715 writel(icr, _ICR(i2c));
700 show_state(i2c); 716 show_state(i2c);
701} 717}
702 718
703static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr) 719static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
704{ 720{
705 u32 icr = ICR & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB); 721 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
706 722
707 /* 723 /*
708 * Read the byte. 724 * Read the byte.
709 */ 725 */
710 i2c->msg->buf[i2c->msg_ptr++] = IDBR; 726 i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c));
711 727
712 if (i2c->msg_ptr < i2c->msg->len) { 728 if (i2c->msg_ptr < i2c->msg->len) {
713 /* 729 /*
@@ -724,17 +740,17 @@ static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
724 740
725 i2c->icrlog[i2c->irqlogidx-1] = icr; 741 i2c->icrlog[i2c->irqlogidx-1] = icr;
726 742
727 ICR = icr; 743 writel(icr, _ICR(i2c));
728} 744}
729 745
730static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id) 746static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
731{ 747{
732 struct pxa_i2c *i2c = dev_id; 748 struct pxa_i2c *i2c = dev_id;
733 u32 isr = ISR; 749 u32 isr = readl(_ISR(i2c));
734 750
735 if (i2c_debug > 2 && 0) { 751 if (i2c_debug > 2 && 0) {
736 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n", 752 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
737 __func__, isr, ICR, IBMR); 753 __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));
738 decode_ISR(isr); 754 decode_ISR(isr);
739 } 755 }
740 756
@@ -746,7 +762,7 @@ static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
746 /* 762 /*
747 * Always clear all pending IRQs. 763 * Always clear all pending IRQs.
748 */ 764 */
749 ISR = isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED); 765 writel(isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED), _ISR(i2c));
750 766
751 if (isr & ISR_SAD) 767 if (isr & ISR_SAD)
752 i2c_pxa_slave_start(i2c, isr); 768 i2c_pxa_slave_start(i2c, isr);
@@ -779,7 +795,7 @@ static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num
779 /* If the I2C controller is disabled we need to reset it (probably due 795 /* If the I2C controller is disabled we need to reset it (probably due
780 to a suspend/resume destroying state). We do this here as we can then 796 to a suspend/resume destroying state). We do this here as we can then
781 avoid worrying about resuming the controller before its users. */ 797 avoid worrying about resuming the controller before its users. */
782 if (!(ICR & ICR_IUE)) 798 if (!(readl(_ICR(i2c)) & ICR_IUE))
783 i2c_pxa_reset(i2c); 799 i2c_pxa_reset(i2c);
784 800
785 for (i = adap->retries; i >= 0; i--) { 801 for (i = adap->retries; i >= 0; i--) {
@@ -810,28 +826,53 @@ static const struct i2c_algorithm i2c_pxa_algorithm = {
810 826
811static struct pxa_i2c i2c_pxa = { 827static struct pxa_i2c i2c_pxa = {
812 .lock = SPIN_LOCK_UNLOCKED, 828 .lock = SPIN_LOCK_UNLOCKED,
813 .wait = __WAIT_QUEUE_HEAD_INITIALIZER(i2c_pxa.wait),
814 .adap = { 829 .adap = {
815 .owner = THIS_MODULE, 830 .owner = THIS_MODULE,
816 .algo = &i2c_pxa_algorithm, 831 .algo = &i2c_pxa_algorithm,
817 .name = "pxa2xx-i2c", 832 .name = "pxa2xx-i2c.0",
818 .retries = 5, 833 .retries = 5,
819 }, 834 },
820}; 835};
821 836
837#define res_len(r) ((r)->end - (r)->start + 1)
822static int i2c_pxa_probe(struct platform_device *dev) 838static int i2c_pxa_probe(struct platform_device *dev)
823{ 839{
824 struct pxa_i2c *i2c = &i2c_pxa; 840 struct pxa_i2c *i2c = &i2c_pxa;
841 struct resource *res;
825#ifdef CONFIG_I2C_PXA_SLAVE 842#ifdef CONFIG_I2C_PXA_SLAVE
826 struct i2c_pxa_platform_data *plat = dev->dev.platform_data; 843 struct i2c_pxa_platform_data *plat = dev->dev.platform_data;
827#endif 844#endif
828 int ret; 845 int ret;
846 int irq;
829 847
830#ifdef CONFIG_PXA27x 848 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
831 pxa_gpio_mode(GPIO117_I2CSCL_MD); 849 irq = platform_get_irq(dev, 0);
832 pxa_gpio_mode(GPIO118_I2CSDA_MD); 850 if (res == NULL || irq < 0)
833 udelay(100); 851 return -ENODEV;
834#endif 852
853 if (!request_mem_region(res->start, res_len(res), res->name))
854 return -ENOMEM;
855
856 i2c = kmalloc(sizeof(struct pxa_i2c), GFP_KERNEL);
857 if (!i2c) {
858 ret = -ENOMEM;
859 goto emalloc;
860 }
861
862 memcpy(i2c, &i2c_pxa, sizeof(struct pxa_i2c));
863 init_waitqueue_head(&i2c->wait);
864 i2c->adap.name[strlen(i2c->adap.name) - 1] = '0' + dev->id % 10;
865
866 i2c->reg_base = ioremap(res->start, res_len(res));
867 if (!i2c->reg_base) {
868 ret = -EIO;
869 goto eremap;
870 }
871
872 i2c->iobase = res->start;
873 i2c->iosize = res_len(res);
874
875 i2c->irq = irq;
835 876
836 i2c->slave_addr = I2C_PXA_SLAVE_ADDR; 877 i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
837 878
@@ -842,11 +883,28 @@ static int i2c_pxa_probe(struct platform_device *dev)
842 } 883 }
843#endif 884#endif
844 885
845 pxa_set_cken(CKEN14_I2C, 1); 886 switch (dev->id) {
846 ret = request_irq(IRQ_I2C, i2c_pxa_handler, IRQF_DISABLED, 887 case 0:
847 "pxa2xx-i2c", i2c); 888#ifdef CONFIG_PXA27x
889 pxa_gpio_mode(GPIO117_I2CSCL_MD);
890 pxa_gpio_mode(GPIO118_I2CSDA_MD);
891#endif
892 pxa_set_cken(CKEN14_I2C, 1);
893 break;
894#ifdef CONFIG_PXA27x
895 case 1:
896 local_irq_disable();
897 PCFR |= PCFR_PI2CEN;
898 local_irq_enable();
899 pxa_set_cken(CKEN15_PWRI2C, 1);
900#endif
901 }
902
903 ret = request_irq(irq, i2c_pxa_handler, IRQF_DISABLED,
904 i2c->adap.name, i2c);
848 if (ret) 905 if (ret)
849 goto out; 906 goto ereqirq;
907
850 908
851 i2c_pxa_reset(i2c); 909 i2c_pxa_reset(i2c);
852 910
@@ -856,7 +914,7 @@ static int i2c_pxa_probe(struct platform_device *dev)
856 ret = i2c_add_adapter(&i2c->adap); 914 ret = i2c_add_adapter(&i2c->adap);
857 if (ret < 0) { 915 if (ret < 0) {
858 printk(KERN_INFO "I2C: Failed to add bus\n"); 916 printk(KERN_INFO "I2C: Failed to add bus\n");
859 goto err_irq; 917 goto eadapt;
860 } 918 }
861 919
862 platform_set_drvdata(dev, i2c); 920 platform_set_drvdata(dev, i2c);
@@ -870,9 +928,25 @@ static int i2c_pxa_probe(struct platform_device *dev)
870#endif 928#endif
871 return 0; 929 return 0;
872 930
873 err_irq: 931eadapt:
874 free_irq(IRQ_I2C, i2c); 932 free_irq(irq, i2c);
875 out: 933ereqirq:
934 switch (dev->id) {
935 case 0:
936 pxa_set_cken(CKEN14_I2C, 0);
937 break;
938#ifdef CONFIG_PXA27x
939 case 1:
940 pxa_set_cken(CKEN15_PWRI2C, 0);
941 local_irq_disable();
942 PCFR &= ~PCFR_PI2CEN;
943 local_irq_enable();
944#endif
945 }
946eremap:
947 kfree(i2c);
948emalloc:
949 release_mem_region(res->start, res_len(res));
876 return ret; 950 return ret;
877} 951}
878 952
@@ -883,8 +957,21 @@ static int i2c_pxa_remove(struct platform_device *dev)
883 platform_set_drvdata(dev, NULL); 957 platform_set_drvdata(dev, NULL);
884 958
885 i2c_del_adapter(&i2c->adap); 959 i2c_del_adapter(&i2c->adap);
886 free_irq(IRQ_I2C, i2c); 960 free_irq(i2c->irq, i2c);
887 pxa_set_cken(CKEN14_I2C, 0); 961 switch (dev->id) {
962 case 0:
963 pxa_set_cken(CKEN14_I2C, 0);
964 break;
965#ifdef CONFIG_PXA27x
966 case 1:
967 pxa_set_cken(CKEN15_PWRI2C, 0);
968 local_irq_disable();
969 PCFR &= ~PCFR_PI2CEN;
970 local_irq_enable();
971#endif
972 }
973 release_mem_region(i2c->iobase, i2c->iosize);
974 kfree(i2c);
888 975
889 return 0; 976 return 0;
890} 977}