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authorEric Miao <eric.miao@marvell.com>2008-09-08 02:15:08 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-10-07 14:12:55 -0400
commit283afa06619ed3e4dd7b5431f862fe23625c452f (patch)
tree331abfcd109219dbb9962bcdb086e356a2cae1f8 /drivers/i2c/busses/i2c-pxa.c
parente7f3c60037fcad0edc0b79b8d285418246bcef40 (diff)
[ARM] pxa: move i2c register and bit definitions into i2c-pxa.c
Signed-off-by: Eric Miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'drivers/i2c/busses/i2c-pxa.c')
-rw-r--r--drivers/i2c/busses/i2c-pxa.c39
1 files changed, 38 insertions, 1 deletions
diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c
index 8b38ed0379d5..906f9b9d715d 100644
--- a/drivers/i2c/busses/i2c-pxa.c
+++ b/drivers/i2c/busses/i2c-pxa.c
@@ -38,7 +38,44 @@
38#include <asm/irq.h> 38#include <asm/irq.h>
39#include <asm/io.h> 39#include <asm/io.h>
40#include <mach/i2c.h> 40#include <mach/i2c.h>
41#include <mach/pxa-regs.h> 41
42/*
43 * I2C registers and bit definitions
44 */
45#define IBMR (0x00)
46#define IDBR (0x08)
47#define ICR (0x10)
48#define ISR (0x18)
49#define ISAR (0x20)
50
51#define ICR_START (1 << 0) /* start bit */
52#define ICR_STOP (1 << 1) /* stop bit */
53#define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
54#define ICR_TB (1 << 3) /* transfer byte bit */
55#define ICR_MA (1 << 4) /* master abort */
56#define ICR_SCLE (1 << 5) /* master clock enable */
57#define ICR_IUE (1 << 6) /* unit enable */
58#define ICR_GCD (1 << 7) /* general call disable */
59#define ICR_ITEIE (1 << 8) /* enable tx interrupts */
60#define ICR_IRFIE (1 << 9) /* enable rx interrupts */
61#define ICR_BEIE (1 << 10) /* enable bus error ints */
62#define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
63#define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
64#define ICR_SADIE (1 << 13) /* slave address detected int enable */
65#define ICR_UR (1 << 14) /* unit reset */
66#define ICR_FM (1 << 15) /* fast mode */
67
68#define ISR_RWM (1 << 0) /* read/write mode */
69#define ISR_ACKNAK (1 << 1) /* ack/nak status */
70#define ISR_UB (1 << 2) /* unit busy */
71#define ISR_IBB (1 << 3) /* bus busy */
72#define ISR_SSD (1 << 4) /* slave stop detected */
73#define ISR_ALD (1 << 5) /* arbitration loss detected */
74#define ISR_ITE (1 << 6) /* tx buffer empty */
75#define ISR_IRF (1 << 7) /* rx buffer full */
76#define ISR_GCAD (1 << 8) /* general call address detected */
77#define ISR_SAD (1 << 9) /* slave address detected */
78#define ISR_BED (1 << 10) /* bus error no ACK/NAK */
42 79
43struct pxa_i2c { 80struct pxa_i2c {
44 spinlock_t lock; 81 spinlock_t lock;