diff options
author | Jean Delvare <khali@linux-fr.org> | 2008-07-14 16:38:25 -0400 |
---|---|---|
committer | Jean Delvare <khali@mahadeva.delvare> | 2008-07-14 16:38:25 -0400 |
commit | ac7fc4fb2b6a126af8d07f46500440c9641976cf (patch) | |
tree | 1ba7a6b229699f6d69cfe3f1bd74c020e952e16b /drivers/i2c/busses/i2c-piix4.c | |
parent | fa63cd56d2f09806169307d761e8f430e23bc09b (diff) |
i2c: Consistently reject unsupported transactions
Many PC SMBus host controller drivers don't properly handle the case
where they are requested to achieve a transaction they do not support.
Update them so that the consistently print a warning message and
return a single error value in this case.
Signed-off-by: Jean Delvare <khali@linux-fr.org>
Diffstat (limited to 'drivers/i2c/busses/i2c-piix4.c')
-rw-r--r-- | drivers/i2c/busses/i2c-piix4.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c index 77aaa5fe5e38..2bde47509e1a 100644 --- a/drivers/i2c/busses/i2c-piix4.c +++ b/drivers/i2c/busses/i2c-piix4.c | |||
@@ -307,9 +307,6 @@ static s32 piix4_access(struct i2c_adapter * adap, u16 addr, | |||
307 | int status; | 307 | int status; |
308 | 308 | ||
309 | switch (size) { | 309 | switch (size) { |
310 | case I2C_SMBUS_PROC_CALL: | ||
311 | dev_err(&adap->dev, "I2C_SMBUS_PROC_CALL not supported!\n"); | ||
312 | return -EOPNOTSUPP; | ||
313 | case I2C_SMBUS_QUICK: | 310 | case I2C_SMBUS_QUICK: |
314 | outb_p((addr << 1) | read_write, | 311 | outb_p((addr << 1) | read_write, |
315 | SMBHSTADD); | 312 | SMBHSTADD); |
@@ -355,6 +352,9 @@ static s32 piix4_access(struct i2c_adapter * adap, u16 addr, | |||
355 | } | 352 | } |
356 | size = PIIX4_BLOCK_DATA; | 353 | size = PIIX4_BLOCK_DATA; |
357 | break; | 354 | break; |
355 | default: | ||
356 | dev_warn(&adap->dev, "Unsupported transaction %d\n", size); | ||
357 | return -EOPNOTSUPP; | ||
358 | } | 358 | } |
359 | 359 | ||
360 | outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT); | 360 | outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT); |