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authorMarek Vasut <marex@denx.de>2012-11-30 12:48:35 -0500
committerWolfram Sang <wolfram@the-dreams.de>2013-02-10 13:55:14 -0500
commit626f0a2ff6bc9820b17c17958d5862262556892f (patch)
treebb2e4a827e8eafc14f42bf7e4a1cb7ab16dd404d /drivers/i2c/busses/i2c-mxs.c
parentc2db409cbc8751ccc7e6d2cc2e41af0d12ea637f (diff)
i2c: mxs: Implement arbitrary clock speed derivation algorithm
This patch drops the i2c timing tables from this driver and instead derives the timing based from the requested clock sleep. The timing tables were completely wrong anyway when observed on a scope. This new algorithm is also only derived by using a scope, but it seems to produce much more accurate result. Signed-off-by: Marek Vasut <marex@denx.de> Tested-by: Shawn Guo <shawn.guo@linaro.org> [wsa: changed messages from dev_err to dev_warn] Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
Diffstat (limited to 'drivers/i2c/busses/i2c-mxs.c')
-rw-r--r--drivers/i2c/busses/i2c-mxs.c94
1 files changed, 55 insertions, 39 deletions
diff --git a/drivers/i2c/busses/i2c-mxs.c b/drivers/i2c/busses/i2c-mxs.c
index e55736077d23..22d8ad353409 100644
--- a/drivers/i2c/busses/i2c-mxs.c
+++ b/drivers/i2c/busses/i2c-mxs.c
@@ -93,35 +93,6 @@
93#define MXS_CMD_I2C_READ (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \ 93#define MXS_CMD_I2C_READ (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \
94 MXS_I2C_CTRL0_MASTER_MODE) 94 MXS_I2C_CTRL0_MASTER_MODE)
95 95
96struct mxs_i2c_speed_config {
97 uint32_t timing0;
98 uint32_t timing1;
99 uint32_t timing2;
100};
101
102/*
103 * Timing values for the default 24MHz clock supplied into the i2c block.
104 *
105 * The bus can operate at 95kHz or at 400kHz with the following timing
106 * register configurations. The 100kHz mode isn't present because it's
107 * values are not stated in the i.MX233/i.MX28 datasheet. The 95kHz mode
108 * shall be close enough replacement. Therefore when the bus is configured
109 * for 100kHz operation, 95kHz timing settings are actually loaded.
110 *
111 * For details, see i.MX233 [25.4.2 - 25.4.4] and i.MX28 [27.5.2 - 27.5.4].
112 */
113static const struct mxs_i2c_speed_config mxs_i2c_95kHz_config = {
114 .timing0 = 0x00780030,
115 .timing1 = 0x00800030,
116 .timing2 = 0x00300030,
117};
118
119static const struct mxs_i2c_speed_config mxs_i2c_400kHz_config = {
120 .timing0 = 0x000f0007,
121 .timing1 = 0x001f000f,
122 .timing2 = 0x00300030,
123};
124
125/** 96/**
126 * struct mxs_i2c_dev - per device, private MXS-I2C data 97 * struct mxs_i2c_dev - per device, private MXS-I2C data
127 * 98 *
@@ -137,7 +108,9 @@ struct mxs_i2c_dev {
137 struct completion cmd_complete; 108 struct completion cmd_complete;
138 int cmd_err; 109 int cmd_err;
139 struct i2c_adapter adapter; 110 struct i2c_adapter adapter;
140 const struct mxs_i2c_speed_config *speed; 111
112 uint32_t timing0;
113 uint32_t timing1;
141 114
142 /* DMA support components */ 115 /* DMA support components */
143 int dma_channel; 116 int dma_channel;
@@ -153,9 +126,16 @@ static void mxs_i2c_reset(struct mxs_i2c_dev *i2c)
153{ 126{
154 stmp_reset_block(i2c->regs); 127 stmp_reset_block(i2c->regs);
155 128
156 writel(i2c->speed->timing0, i2c->regs + MXS_I2C_TIMING0); 129 /*
157 writel(i2c->speed->timing1, i2c->regs + MXS_I2C_TIMING1); 130 * Configure timing for the I2C block. The I2C TIMING2 register has to
158 writel(i2c->speed->timing2, i2c->regs + MXS_I2C_TIMING2); 131 * be programmed with this particular magic number. The rest is derived
132 * from the XTAL speed and requested I2C speed.
133 *
134 * For details, see i.MX233 [25.4.2 - 25.4.4] and i.MX28 [27.5.2 - 27.5.4].
135 */
136 writel(i2c->timing0, i2c->regs + MXS_I2C_TIMING0);
137 writel(i2c->timing1, i2c->regs + MXS_I2C_TIMING1);
138 writel(0x00300030, i2c->regs + MXS_I2C_TIMING2);
159 139
160 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET); 140 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
161} 141}
@@ -553,6 +533,43 @@ static bool mxs_i2c_dma_filter(struct dma_chan *chan, void *param)
553 return true; 533 return true;
554} 534}
555 535
536static void mxs_i2c_derive_timing(struct mxs_i2c_dev *i2c, int speed)
537{
538 /* The I2C block clock run at 24MHz */
539 const uint32_t clk = 24000000;
540 uint32_t base;
541 uint16_t high_count, low_count, rcv_count, xmit_count;
542 struct device *dev = i2c->dev;
543
544 if (speed > 540000) {
545 dev_warn(dev, "Speed too high (%d Hz), using 540 kHz\n", speed);
546 speed = 540000;
547 } else if (speed < 12000) {
548 dev_warn(dev, "Speed too low (%d Hz), using 12 kHz\n", speed);
549 speed = 12000;
550 }
551
552 /*
553 * The timing derivation algorithm. There is no documentation for this
554 * algorithm available, it was derived by using the scope and fiddling
555 * with constants until the result observed on the scope was good enough
556 * for 20kHz, 50kHz, 100kHz, 200kHz, 300kHz and 400kHz. It should be
557 * possible to assume the algorithm works for other frequencies as well.
558 *
559 * Note it was necessary to cap the frequency on both ends as it's not
560 * possible to configure completely arbitrary frequency for the I2C bus
561 * clock.
562 */
563 base = ((clk / speed) - 38) / 2;
564 high_count = base + 3;
565 low_count = base - 3;
566 rcv_count = (high_count * 3) / 4;
567 xmit_count = low_count / 4;
568
569 i2c->timing0 = (high_count << 16) | rcv_count;
570 i2c->timing1 = (low_count << 16) | xmit_count;
571}
572
556static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c) 573static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c)
557{ 574{
558 uint32_t speed; 575 uint32_t speed;
@@ -572,12 +589,12 @@ static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c)
572 } 589 }
573 590
574 ret = of_property_read_u32(node, "clock-frequency", &speed); 591 ret = of_property_read_u32(node, "clock-frequency", &speed);
575 if (ret) 592 if (ret) {
576 dev_warn(dev, "No I2C speed selected, using 100kHz\n"); 593 dev_warn(dev, "No I2C speed selected, using 100kHz\n");
577 else if (speed == 400000) 594 speed = 100000;
578 i2c->speed = &mxs_i2c_400kHz_config; 595 }
579 else if (speed != 100000) 596
580 dev_warn(dev, "Unsupported I2C speed selected, using 100kHz\n"); 597 mxs_i2c_derive_timing(i2c, speed);
581 598
582 return 0; 599 return 0;
583} 600}
@@ -621,7 +638,6 @@ static int mxs_i2c_probe(struct platform_device *pdev)
621 return err; 638 return err;
622 639
623 i2c->dev = dev; 640 i2c->dev = dev;
624 i2c->speed = &mxs_i2c_95kHz_config;
625 641
626 init_completion(&i2c->cmd_complete); 642 init_completion(&i2c->cmd_complete);
627 643