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authorMathieu J. Poirier <mathieu.poirier@linaro.org>2011-09-08 15:47:40 -0400
committerOhad Ben-Cohen <ohad@wizery.com>2011-09-21 12:57:45 -0400
commitf84a8ecfca9229e9227c6ec84123b114ee634959 (patch)
treec5b519c7a10af21434a892c690ad9759fde80d11 /drivers/hwspinlock
parent300bab9770e2bd10262bcc78e7249fdce2c74b38 (diff)
hwspinlock/u8500: add hwspinlock driver
Add hwspinlock driver for U8500's Hsem hardware. At this point only HSem's protocol 1 is used (i.e. no interrupts). Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> [ohad@wizery.com: adopt recent hwspin_lock_{un}register API changes] [ohad@wizery.com: set the owner member of the driver] [ohad@wizery.com: mark ->remove() function as __devexit] [ohad@wizery.com: write commit log] [ohad@wizery.com: small cleanups] Signed-off-by: Ohad Ben-Cohen <ohad@wizery.com>
Diffstat (limited to 'drivers/hwspinlock')
-rw-r--r--drivers/hwspinlock/Kconfig11
-rw-r--r--drivers/hwspinlock/Makefile1
-rw-r--r--drivers/hwspinlock/u8500_hsem.c198
3 files changed, 210 insertions, 0 deletions
diff --git a/drivers/hwspinlock/Kconfig b/drivers/hwspinlock/Kconfig
index c8e7bdac1404..c7c3128393d1 100644
--- a/drivers/hwspinlock/Kconfig
+++ b/drivers/hwspinlock/Kconfig
@@ -18,4 +18,15 @@ config HWSPINLOCK_OMAP
18 18
19 If unsure, say N. 19 If unsure, say N.
20 20
21config HSEM_U8500
22 tristate "STE Hardware Semaphore functionality"
23 depends on ARCH_U8500
24 select HWSPINLOCK
25 help
26 Say y here to support the STE Hardware Semaphore functionality, which
27 provides a synchronisation mechanism for the various processor on the
28 SoC.
29
30 If unsure, say N.
31
21endmenu 32endmenu
diff --git a/drivers/hwspinlock/Makefile b/drivers/hwspinlock/Makefile
index 5729a3f7ed3d..93eb64b66486 100644
--- a/drivers/hwspinlock/Makefile
+++ b/drivers/hwspinlock/Makefile
@@ -4,3 +4,4 @@
4 4
5obj-$(CONFIG_HWSPINLOCK) += hwspinlock_core.o 5obj-$(CONFIG_HWSPINLOCK) += hwspinlock_core.o
6obj-$(CONFIG_HWSPINLOCK_OMAP) += omap_hwspinlock.o 6obj-$(CONFIG_HWSPINLOCK_OMAP) += omap_hwspinlock.o
7obj-$(CONFIG_HSEM_U8500) += u8500_hsem.o
diff --git a/drivers/hwspinlock/u8500_hsem.c b/drivers/hwspinlock/u8500_hsem.c
new file mode 100644
index 000000000000..143461a95ae4
--- /dev/null
+++ b/drivers/hwspinlock/u8500_hsem.c
@@ -0,0 +1,198 @@
1/*
2 * u8500 HWSEM driver
3 *
4 * Copyright (C) 2010-2011 ST-Ericsson
5 *
6 * Implements u8500 semaphore handling for protocol 1, no interrupts.
7 *
8 * Author: Mathieu Poirier <mathieu.poirier@linaro.org>
9 * Heavily borrowed from the work of :
10 * Simon Que <sque@ti.com>
11 * Hari Kanigeri <h-kanigeri2@ti.com>
12 * Ohad Ben-Cohen <ohad@wizery.com>
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * version 2 as published by the Free Software Foundation.
17 *
18 * This program is distributed in the hope that it will be useful, but
19 * WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21 * General Public License for more details.
22 */
23
24#include <linux/delay.h>
25#include <linux/io.h>
26#include <linux/pm_runtime.h>
27#include <linux/slab.h>
28#include <linux/spinlock.h>
29#include <linux/hwspinlock.h>
30#include <linux/platform_device.h>
31
32#include "hwspinlock_internal.h"
33
34/*
35 * Implementation of STE's HSem protocol 1 without interrutps.
36 * The only masterID we allow is '0x01' to force people to use
37 * HSems for synchronisation between processors rather than processes
38 * on the ARM core.
39 */
40
41#define U8500_MAX_SEMAPHORE 32 /* a total of 32 semaphore */
42#define RESET_SEMAPHORE (0) /* free */
43
44/*
45 * CPU ID for master running u8500 kernel.
46 * Hswpinlocks should only be used to synchonise operations
47 * between the Cortex A9 core and the other CPUs. Hence
48 * forcing the masterID to a preset value.
49 */
50#define HSEM_MASTER_ID 0x01
51
52#define HSEM_REGISTER_OFFSET 0x08
53
54#define HSEM_CTRL_REG 0x00
55#define HSEM_ICRALL 0x90
56#define HSEM_PROTOCOL_1 0x01
57
58static int u8500_hsem_trylock(struct hwspinlock *lock)
59{
60 void __iomem *lock_addr = lock->priv;
61
62 writel(HSEM_MASTER_ID, lock_addr);
63
64 /* get only first 4 bit and compare to masterID.
65 * if equal, we have the semaphore, otherwise
66 * someone else has it.
67 */
68 return (HSEM_MASTER_ID == (0x0F & readl(lock_addr)));
69}
70
71static void u8500_hsem_unlock(struct hwspinlock *lock)
72{
73 void __iomem *lock_addr = lock->priv;
74
75 /* release the lock by writing 0 to it */
76 writel(RESET_SEMAPHORE, lock_addr);
77}
78
79/*
80 * u8500: what value is recommended here ?
81 */
82static void u8500_hsem_relax(struct hwspinlock *lock)
83{
84 ndelay(50);
85}
86
87static const struct hwspinlock_ops u8500_hwspinlock_ops = {
88 .trylock = u8500_hsem_trylock,
89 .unlock = u8500_hsem_unlock,
90 .relax = u8500_hsem_relax,
91};
92
93static int __devinit u8500_hsem_probe(struct platform_device *pdev)
94{
95 struct hwspinlock_pdata *pdata = pdev->dev.platform_data;
96 struct hwspinlock_device *bank;
97 struct hwspinlock *hwlock;
98 struct resource *res;
99 void __iomem *io_base;
100 int i, ret, num_locks = U8500_MAX_SEMAPHORE;
101 ulong val;
102
103 if (!pdata)
104 return -ENODEV;
105
106 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
107 if (!res)
108 return -ENODEV;
109
110 io_base = ioremap(res->start, resource_size(res));
111 if (!io_base) {
112 ret = -ENOMEM;
113 goto free_state;
114 }
115
116 /* make sure protocol 1 is selected */
117 val = readl(io_base + HSEM_CTRL_REG);
118 writel((val & ~HSEM_PROTOCOL_1), io_base + HSEM_CTRL_REG);
119
120 /* clear all interrupts */
121 writel(0xFFFF, io_base + HSEM_ICRALL);
122
123 bank = kzalloc(sizeof(*bank) + num_locks * sizeof(*hwlock), GFP_KERNEL);
124 if (!bank) {
125 ret = -ENOMEM;
126 goto iounmap_base;
127 }
128
129 platform_set_drvdata(pdev, bank);
130
131 for (i = 0, hwlock = &bank->lock[0]; i < num_locks; i++, hwlock++)
132 hwlock->priv = io_base + HSEM_REGISTER_OFFSET + sizeof(u32) * i;
133
134 /* no pm needed for HSem but required to comply with hwspilock core */
135 pm_runtime_enable(&pdev->dev);
136
137 ret = hwspin_lock_register(bank, &pdev->dev, &u8500_hwspinlock_ops,
138 pdata->base_id, num_locks);
139 if (ret)
140 goto reg_fail;
141
142 return 0;
143
144reg_fail:
145 pm_runtime_disable(&pdev->dev);
146 kfree(bank);
147iounmap_base:
148 iounmap(io_base);
149 return ret;
150}
151
152static int __devexit u8500_hsem_remove(struct platform_device *pdev)
153{
154 struct hwspinlock_device *bank = platform_get_drvdata(pdev);
155 void __iomem *io_base = bank->lock[0].priv - HSEM_REGISTER_OFFSET;
156 int ret;
157
158 /* clear all interrupts */
159 writel(0xFFFF, io_base + HSEM_ICRALL);
160
161 ret = hwspin_lock_unregister(bank);
162 if (ret) {
163 dev_err(&pdev->dev, "%s failed: %d\n", __func__, ret);
164 return ret;
165 }
166
167 pm_runtime_disable(&pdev->dev);
168 iounmap(io_base);
169 kfree(bank);
170
171 return 0;
172}
173
174static struct platform_driver u8500_hsem_driver = {
175 .probe = u8500_hsem_probe,
176 .remove = __devexit_p(u8500_hsem_remove),
177 .driver = {
178 .name = "u8500_hsem",
179 .owner = THIS_MODULE,
180 },
181};
182
183static int __init u8500_hsem_init(void)
184{
185 return platform_driver_register(&u8500_hsem_driver);
186}
187/* board init code might need to reserve hwspinlocks for predefined purposes */
188postcore_initcall(u8500_hsem_init);
189
190static void __exit u8500_hsem_exit(void)
191{
192 platform_driver_unregister(&u8500_hsem_driver);
193}
194module_exit(u8500_hsem_exit);
195
196MODULE_LICENSE("GPL v2");
197MODULE_DESCRIPTION("Hardware Spinlock driver for u8500");
198MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>");