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authorJesse Barnes <jbarnes@virtuousgeek.org>2010-07-21 16:57:47 -0400
committerEric Anholt <eric@anholt.net>2010-08-01 22:35:15 -0400
commit4f444071702bf0b76cfb381150cf0fc8cacdc931 (patch)
treee85f0e9b900c2c7be5c6d74e2bf039be2afefb1e /drivers/gpu
parent831cd4453598b2c8e193f077023910c6b0c39558 (diff)
drm/i915: apply DP bandwidth workaround for PCH eDP as well
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=29141 though the workaround itself is still a bit of a mystery. Tested-by: Adam Hill <sidepipeuk@yahoo.co.uk> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c612981e6195..5a11a2bada37 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -534,7 +534,7 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
534 } 534 }
535 } 535 }
536 536
537 if (IS_eDP(intel_encoder)) { 537 if (IS_eDP(intel_encoder) || IS_PCH_eDP(dp_priv)) {
538 /* okay we failed just pick the highest */ 538 /* okay we failed just pick the highest */
539 dp_priv->lane_count = max_lane_count; 539 dp_priv->lane_count = max_lane_count;
540 dp_priv->link_bw = bws[max_clock]; 540 dp_priv->link_bw = bws[max_clock];